Semiconductor device

Abstract

A semiconductor device according to the present invention includes: a semiconductor layer that is of a first conductivity type and has a principal surface; a body region that is of a second conductivity type and is formed at a surface layer portion of the principal surface; a trench-type gate structure that is formed at the principal surface so as to pass through the body region and extends in a first direction along the principal surface; a first pillar region that is of the first conductivity type and extends in a second direction along the principal surface within the semiconductor layer so as to intersect the gate structure; a second pillar region that is of the second conductivity type, is adjacent to the first pillar region in the first direction, and forms a pn junction with the first pillar region; and a plurality of contact regions that are of the second conductivity type and are arranged at intervals along the first direction, each of the contact regions being selectively provided at a surface layer portion of the body region in a region that is directly above the second pillar region in the thickness direction of the semiconductor layer so as to be opposite the second pillar region in the thickness direction of the semiconductor layer.

Description

Semiconductor device Related application

[0001] This application corresponds to Japanese Patent Application No. 2025-019229 filed with the Japan Patent Office on February 7, 2025, and the entire disclosure of this application is hereby incorporated by reference.

[0002] This disclosure relates to a semiconductor device.

[0003] Patent Document 1 (US2021 / 036116A1) discloses a field effect transistor including a silicon carbide layer, a superjunction structure, and a gate electrode. The superjunction structure includes p-type regions and n-type regions alternately formed in the silicon carbide layer. The gate electrode is embedded in a gate trench formed in the p-type region.

[0004] United States Patent Application Publication No. 2021 / 036116

[0005] [Summary] One embodiment of this disclosure provides a semiconductor device capable of improving the efficiency of manufacturing processes.

[0006] Figure 1 is a plan view showing a semiconductor device according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface shown in Figure 2. Figure 4 is an enlarged plan view showing the inner part of the active region shown in Figure 3. Figure 5 is an enlarged plan view showing the peripheral part of the active region shown in Figure 3. Figure 6 is a cross-sectional view taken along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view taken along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view taken along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view taken along the line IX-IX shown in Figure 4. Figure 10 is a cross-sectional view taken along the line XX shown in Figure 5. Figure 11 is an enlarged cross-sectional view of the gate structure shown in Figure 6. Figure 12 is an enlarged cross-sectional view of the gate structure shown in Figure 7. Figure 13 is a further enlarged cross-sectional view of the source opening shown in Figure 11. Figure 14 is a cross-sectional perspective view showing the first main part of the active region. Figure 15 is a cross-sectional perspective view showing the second main part of the active region. Figure 16 is a cross-sectional perspective view showing the third main part of the active region. Figure 17 is a cross-sectional perspective view showing the fourth main part of the active region. Figure 18 is a horizontal cross-sectional view along the line XVIII-XVIII shown in Figure 6. Figure 19 is a horizontal cross-sectional view along the line XIX-XIX shown in Figure 6. Figure 20 is a schematic diagram showing a wafer used in the manufacture of a semiconductor device. Figure 21A is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21B is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21C is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21D is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21E is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21F is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21G is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21H is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21I is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21J is a cross-sectional view showing one step in an example of a semiconductor device manufacturing method. Figure 21K is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21L is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21M is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21N is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21O is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process.Figure 21P is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21Q is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 21R is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 22 is a plan view showing a modified well region. Figure 23 is a cross-sectional view showing a modified well region. Figure 24 is a cross-sectional view showing a first modified well region. Figure 25 is a cross-sectional view showing a second modified well region. Figure 26 is a cross-sectional view showing a third modified well region. Figure 27 is a cross-sectional view showing a fourth modified well region. Figure 28 is a cross-sectional view showing a fifth modified well region. Figure 29 is a cross-sectional view showing a sixth modified well region. Figure 30 is a cross-sectional view showing a seventh modified well region.

[0007] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0008] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0009] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0010] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0011] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] (1) Figure 1, an overall explanatory diagram of the semiconductor device 1, is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface 3 shown in Figure 2. Figure 4 is an enlarged plan view showing the inner part of the active region 8 shown in Figure 3. Figure 5 is an enlarged plan view showing the peripheral part of the active region 8 shown in Figure 3.

[0013] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 4. Figure 10 is a cross-sectional view along the line XX shown in Figure 5.

[0014] Figure 11 is an enlarged cross-sectional view of the gate structure 15 shown in Figure 6. Figure 12 is an enlarged cross-sectional view of the gate structure 15 shown in Figure 7. Figure 13 is a further enlarged cross-sectional view of the source opening 56 shown in Figure 11. Figures 14 to 17 are cross-sectional perspective views showing the first to fourth main parts of the active region 8. Figure 18 is a horizontal cross-sectional view along the line XVIII-XVIII shown in Figure 6. Figure 19 is a horizontal cross-sectional view along the line XIX-XIX shown in Figure 6.

[0015] Referring to Figures 1 to 19, semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate type vertical structure.

[0016] The semiconductor device 1 includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1 is a "wide-bandgap semiconductor device." The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0017] A wide-bandgap semiconductor is a semiconductor that has a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1 is a "SiC semiconductor device".

[0018] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0019] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") taken from the thickness direction Z of the chip 2. The thickness direction Z is also the normal direction (vertical direction) to the first main surface 3 and the second main surface 4.

[0020] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0021] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0022] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction and the second direction Y may be the m-axis direction. Alternatively, the first direction X may be a direction that intersects both the a-axis and m-axis directions, and the second direction Y may be a direction that intersects both the a-axis and m-axis directions.

[0023] In the following, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is the direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the thickness direction Z.

[0024] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0025] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0026] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0027] The semiconductor device 1 includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0028] The first semiconductor layer 6 is 1 × 10 １８ cm －３ The above 1 x 10 ２１ cm －３ The n-type impurity concentration may be as follows. The n-type impurity concentration of the first semiconductor layer 6 may be approximately constant in the thickness direction Z. The n-type impurity concentration of the first semiconductor layer 6 may be adjusted by a single pentavalent element. Preferably, the first semiconductor layer 6 contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the first semiconductor layer 6 is adjusted by nitrogen as the pentavalent element.

[0029] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0030] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0031] The semiconductor device 1 includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)," "drain layer (region)," "drift layer (region)," etc. The second semiconductor layer 7 has an n-type impurity concentration lower than that of the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z.

[0032] The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0033] The second semiconductor layer 7 contains a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a semiconductor layer (SiC layer) containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0034] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, 17.5 μm or more and 20 μm or less, 20 μm or more and 22.5 μm or less, and 22.5 μm or more and 25 μm or less.

[0035] The semiconductor device 1 includes an active region 8 set on the first main surface 3. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is set as a polygon (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0036] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, 0.9 or more and 0.95 or less, and 0.95 or more and less than 1.

[0037] The semiconductor device 1 includes an outer region 9 set outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include the device structure (transistor structure Tr). The outer region 9 is set at the periphery of the first main surface 3. The outer region 9 is provided in the region between the periphery of the first main surface 3 and the active region 8. In a plan view, the outer region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this embodiment) that surrounds the active region 8.

[0038] The semiconductor device 1 includes a p-type body region 10 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The body region 10 may also be referred to as the "impurity region," "surface region," etc. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as the basis for circuit operation. The reference potential may also be the ground potential.

[0039] The body region 10 is formed in the active region 8, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer region 9. In this configuration, the body region 10 is formed across the entire area of ​​the active region 8. The body region 10 is formed on the surface layer of the first main surface 3 and extends in layers along the first main surface 3. The body region 10 replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0040] The body region 10 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3 side, and faces the first semiconductor layer 6 with a part of the second semiconductor layer 7 interposed therebetween. The body region 10 may be formed at a distance from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3 side.

[0041] The body region 10 forms a pn junction with the second semiconductor layer 7. As a result, a bipolar diode (body diode) including the second semiconductor layer 7 as a cathode region and the body region 10 as an anode region is formed.

[0042] The semiconductor device 1 includes a plurality of trench-type (trench electrode type) gate structures 15 formed in the inner part (active region 8) of the first main surface 3. The gate structure 15 may be referred to as a "trench structure", a "trench gate structure", or the like. A gate potential (gate signal) as a control potential is applied to the plurality of gate structures 15.

[0043] The plurality of gate structures 15 are formed in the active region 8 at a distance from the periphery of the first main surface 3 and are not formed in the outer region 9. The plurality of gate structures 15 each extend in a strip shape in the first direction X (= m-axis direction) in plan view and are arranged at intervals in the second direction Y (= a-axis direction). The plurality of gate structures 15 are arranged in a stripe shape extending in the first direction X in plan view. The extending direction of the plurality of gate structures 15 intersects (specifically, is orthogonal to) the off-direction of the SiC single crystal.

[0044] The long sides of the plurality of gate structures 15 are formed by the a-plane ((11 - 20) plane) of the SiC single crystal, and the short sides of the plurality of gate structures 15 are formed by the m-plane ((1 - 100) plane) of the SiC single crystal. Depending on the extending direction of the plurality of gate structures 15, the long sides may be formed by the m-plane and the short sides may be formed by the a-plane.

[0045] The bottom walls of the plurality of gate structures 15 are formed by the c-plane (Si plane) of the SiC single crystal. The bottom walls of the plurality of gate structures 15 may extend substantially flat along the horizontal direction. The bottom walls of the plurality of gate structures 15 may be curved in an arc shape toward the second main surface 4 side.

[0046] The gate structure 15 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. The width of the gate structure 15 is preferably 1.5 μm or less.

[0047] In this embodiment, the multiple gate structures 15 are arranged with a spacing greater than the width of the gate structure 15. Of course, the spacing between the gate structures 15 may be less than the width of the gate structure 15. The spacing between the gate structures 15 may be greater than 0 μm and 3 μm or less.

[0048] The spacing of the gate structures 15 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the spacing of the gate structures 15 is 2 μm or less.

[0049] The multiple gate structures 15 penetrate the body region 10 and are formed at intervals from the bottom of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3. The side walls of the multiple gate structures 15, together with the first main surface 3, define the obliquely inclined open ends. The open ends of the multiple gate structures 15 may be curved in an arc shape (circular arc shape).

[0050] The multiple gate structures 15 are formed substantially perpendicular to the first main surface 3. The multiple gate structures 15 may be formed in a tapered shape toward the bottom of the second semiconductor layer 7. The inclination angle (absolute value) of the side walls (long sides) of the gate structures 15 with respect to the horizontal plane may be 85° or more and 95° or less.

[0051] The inclination angle may have a value that falls within at least one of the following ranges: 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. Preferably, the inclination angle is 87° to 93°.

[0052] The gate structure 15 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. Preferably, the depth of the gate structure 15 is 2 μm or less.

[0053] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0054] The multiple gate structures 15 each include a trench 16, an insulating film 17, and an embedded electrode 18. The trench 16 may be referred to as a "gate trench," the insulating film 17 as a "gate insulating film," and the embedded electrode 18 as a "gate embedded electrode." The trench 16 is formed on the first main surface 3 and demarcates the wall surfaces (side walls and bottom walls) of the gate structure 15.

[0055] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 17 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 17 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0056] The insulating film 17 coats the walls (side walls and bottom walls) of the trench 16 in a film-like manner. The thickness of the insulating film 17 covering the bottom wall of the trench 16 may be greater than the thickness of the insulating film 17 covering the side walls of the trench 16.

[0057] The thickness of the insulating film 17 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 17 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0058] The embedded electrode 18 includes either a metal conductor or a non-metallic conductor, or both. The embedded electrode 18 may also include conductive polysilicon. In this case, the embedded electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. It is preferable that the embedded electrode 18 is made of n-type conductive polysilicon.

[0059] The embedded electrode 18 is embedded in the trench 16 via an insulating film 17. The embedded electrode 18 has an electrode surface located on the bottom wall side of the trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 16. The electrode surface may also be located on the bottom wall side of the trench 16 with respect to the depth position of the middle part of the trench 16. The electrode surface may have a recess facing the bottom wall side.

[0060] The semiconductor device 1 includes a plurality of p-type well regions 20 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The well regions 20 may also be referred to as "impurity regions," "gate well regions," etc. The well regions 20 have a p-type impurity concentration higher than that of the body region 10. Source potentials are applied to the plurality of well regions 20.

[0061] Multiple well regions 20 are formed in the active region 8, spaced apart from the periphery of the first main surface 3, but not in the outer region 9. Multiple well regions 20 are formed within the second semiconductor layer 7, spaced apart from the first main surface 3 and the bottom of the second semiconductor layer 7, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7. Multiple well regions 20 replace the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0062] The multiple well regions 20 each extend in a strip-like manner in the first direction X when viewed from above, and are arranged with gaps in the second direction Y. The multiple well regions 20 are arranged in a stripe-like manner extending in the first direction X when viewed from above. The extension directions of the multiple well regions 20 intersect (specifically orthogonal to) the off-direction of the SiC single crystal.

[0063] Multiple well regions 20 are formed in the regions below (specifically directly beneath) the multiple gate structures 15, and overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z. In other words, the multiple well regions 20 extend in a strip-like manner in the first direction X, following the extension direction of the corresponding gate structure 15 in a plan view. The multiple well regions 20 mitigate the electric field for the multiple gate structures 15 from the bottom wall side.

[0064] With respect to the first direction X, the ends of the multiple well regions 20 may be located inward or outward from the ends of the multiple gate structures 15. Of course, the multiple well regions 20 may be formed at intervals in the first direction X in a one-to-many correspondence with respect to one gate structure 15. In this case, the multiple well regions 20 may extend in a strip-like shape in the first direction X.

[0065] With respect to the second direction Y, in this embodiment, each of the multiple well regions 20 is formed to be wider than the corresponding gate structure 15. That is, each of the multiple well regions 20 has a width greater than the width of the corresponding gate structure 15 and protrudes from the side walls of the corresponding gate structure 15 to both sides in the second direction Y.

[0066] The amount of overhang of the well region 20 relative to the side wall of the gate structure 15 may be greater than 0 μm and 0.5 μm or less. The amount of overhang may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, and 0.4 μm or more and 0.5 μm or less.

[0067] Each of the multiple well regions 20 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor layer 7. The upper ends of the multiple well regions 20 are formed with a gap between the bottom of the body region 10 and the bottom wall side of the corresponding gate structure 15.

[0068] The upper ends of the multiple well regions 20 are located on the bottom wall side of the corresponding gate structure 15 with respect to the depth position of the intermediate part of the corresponding gate structure 15. The upper ends of the multiple well regions 20 are connected to the bottom wall of the corresponding gate structure 15 and face the embedded electrode 18 via the insulating film 17. The upper ends of the multiple well regions 20 are located near the corners of the bottom wall of the corresponding gate structure 15.

[0069] The upper ends of the multiple well regions 20 may have portions that run along the lower end of the side wall of the corresponding gate structure 15 via the vicinity of the corner of the bottom wall of the corresponding gate structure 15. In other words, the multiple well regions 20 may face the embedded electrode 18 via the insulating film 17 at the side wall of the corresponding gate structure 15.

[0070] The depth of the well region 20 relative to the bottom wall of the gate structure 15 is less than the depth of the gate structure 15 relative to the first main surface 3. The ratio of the depth of the well region 20 to the depth of the gate structure 15 may be greater than 0 and 0.5 or less.

[0071] The depth ratio may be greater than 0 and less than or equal to 0.1, between 0.1 and 0.2, between 0.2 and 0.3, between 0.3 and 0.4, or between 0.4 and 0.5. Of course, the depth of the well region 20 may be greater than the depth of the gate structure 15.

[0072] The depth of the well region 20 may be greater than 0 μm and less than or equal to 1 μm. The depth of the well region 20 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, between 0.1 μm and 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, and between 0.75 μm and 1 μm.

[0073] The semiconductor device 1 includes a plurality of n-type first pillar regions 21 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The first pillar regions 21 may also be referred to as "first regions," "first impurity regions," "first column regions," etc. The plurality of first pillar regions 21 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The plurality of first pillar regions 21 may be considered as a part (a component) of the second semiconductor layer 7 as a high-concentration portion of the second semiconductor layer 7.

[0074] The n-type impurity concentrations in the multiple first pillar regions 21 are lower than the p-type impurity concentrations in the multiple well regions 20. The n-type impurity concentrations in the multiple first pillar regions 21 may be higher or lower than the p-type impurity concentrations in the body region 10.

[0075] Multiple first pillar regions 21 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but not in the outer region 9. Of course, multiple first pillar regions 21 may also be formed in the outer region 9 within the second semiconductor layer 7. In a plan view, the multiple first pillar regions 21 are arranged at intervals in the first direction X (= m-axis direction) and each extends in a strip shape in the second direction Y (= a-axis direction).

[0076] In other words, the multiple first pillar regions 21 are arranged in a stripe-like pattern extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 15. The direction of extension of the multiple first pillar regions 21 coincides with the off-direction of the SiC single crystal.

[0077] Multiple first pillar regions 21 may be formed at intervals greater than 0 μm and 3 μm or less. The spacing between the first pillar regions 21 may be greater than or less than the width of the first pillar regions 21. The spacing between the first pillar regions 21 may be greater than or less than the width of the gate structure 15. The spacing between the first pillar regions 21 may be greater than or less than the spacing of the gate structure 15.

[0078] The spacing of the first pillar region 21 may have a value greater than 0 μm and belonging to at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0079] Multiple first pillar regions 21 are formed in a region below the bottom of the body region 10 and extend in a vertical columnar shape along the thickness direction Z. Multiple first pillar regions 21 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0080] In this configuration, each of the multiple first pillar regions 21 is formed by a single n-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). The axial channel is a region (channel) with relatively wide interatomic distances in the SiC single crystal and is surrounded by rows of atoms that constitute the crystal axis extending in the stacking direction. In other words, the axial channel is a region in which a region with sparse interatomic distances (atomic density) in the horizontal direction extends in the thickness direction Z.

[0081] The axial channel is preferably a region surrounded by atomic rows along the low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all between 0 and 2 (preferably 1) with respect to Miller indices (a1, a2, a3, c).

[0082] In this configuration, the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. In other words, the multiple first pillar regions 21 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. In other words, the multiple first pillar regions 21 are tilted by the off-angle from the vertical axis in the off-direction.

[0083] In this configuration, the extension direction (a-axis direction) of the multiple first pillar regions 21 coincides with the off-direction of the off-angle. Therefore, the multiple first pillar regions 21 extend almost perpendicularly in a cross-sectional view along the direction perpendicular to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0084] The first pillar region 21 has a depth greater than the depth of the gate structure 15. The depth of the first pillar region 21 is less than the thickness of the second semiconductor layer 7. The depth of the first pillar region 21 may be greater than 0 μm and 5 μm or less.

[0085] The depth of the first pillar region 21 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the first pillar region 21 is 1 μm or more.

[0086] The first pillar region 21 may have an aspect ratio of 1 or more and 10 or less. The aspect ratio of the first pillar region 21 is the ratio of the depth of the first pillar region 21 to the width of the first pillar region 21.

[0087] The aspect ratio of the first pillar region 21 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0088] Each of the multiple first pillar regions 21 has a first upper region 21U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 15, and a first lower region 21L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 15. The n-type impurity concentration in the multiple first pillar regions 21 is lower than the p-type impurity concentration in the multiple well regions 20 in both the first upper region 21U and the first lower region 21L.

[0089] The first upper region 21U is interposed in the region between the multiple gate structures 15 and extends in the second direction Y. The first upper region 21U is connected to the side walls of the multiple gate structures 15 and faces the embedded electrode 18 via the insulating film 17 of the multiple gate structures 15. The first upper region 21U has a first upper end connected to the body region 10.

[0090] Referring to Figures 8 and 14 to 17, the first upper region 21U in this configuration has a first base portion 67 with a substantially constant width in the thickness direction Z, a first constricted portion 68 constricted in the first direction X, and a first bulge portion 69 that expands in the first direction X.

[0091] The first base portion 67 is continuously connected to the first lower region 21L and is the portion that maintains the width W1 of the first lower region 21L in the thickness direction Z. For example, the width W2 of the first base portion 67 may be 90% or more and 110% or less of the width W1 of the first lower region 21L. The width W2 of the first base portion 67 may have a value that falls within at least one of the following ranges of 90% or more and 95%, 95% or more and 100%, 100% or more and 105%, or 105% or more and 110% or less of the width W1 of the first lower region 21L. In this embodiment, the first base portion 67 is formed in a tapered shape in cross-sectional view, with its width slightly narrowing toward the first main surface 3.

[0092] The widths W1 and W2 may specifically be greater than 0 μm and 3 μm or less. The widths W1 and W2 may be greater than or less than the width of the gate structure 15. The widths W1 and W2 may be greater than or less than the spacing of the gate structure 15. The widths W1 and W2 may have values ​​that fall within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0093] The first constriction 68 is formed in the thickness range between the bottom walls of the multiple gate structures 15 and the bottom of the body region 10, and is a portion in which the width in the first direction X gradually decreases toward the body region 10. The width W3 of the first constriction 68 is narrower than the width W2 of the first base portion 67. The width W3 of the first constriction 68 may be 50% or more and 80% or less of the width W2 of the first base portion 67. The width W3 of the first constriction 68 may have a value that falls within at least one of the following ranges: 50% or more and 55%, 55% or more and 60%, 60% or more and 65%, 65% or more and 70%, 70% or more and 75%, and 75% or more and 80% or less of the width W2 of the first base portion 67.

[0094] Specifically, the width W3 may be greater than 0 μm and 3 μm or less. The width W3 may be greater than or less than the spacing of the gate structure 15. The width W3 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0095] The first bulge 69 is formed in a thickness range between the bottom of the body region 10 and the first constriction 68, and is a portion whose width in the first direction X gradually increases toward the bottom of the body region 10. In this embodiment, the first bulge 69 forms a first upper end connected to the body region 10. The width W4 of the first bulge 69 is wider than the width W3 of the first constriction 68. The width W4 of the first bulge 69 may be greater than 100% and less than or equal to 130% of the width W3 of the first constriction 68. The width W4 of the first bulge 69 may have a value that falls within at least one of the following ranges: greater than 100% and less than or equal to 105%, 105% or more and less than or equal to 110%, 110% or more and less than or equal to 115%, 115% or more and less than or equal to 120%, 120% or more and less than or equal to 125%, and 125% or more and less than or equal to 130% of the width W3 of the first constriction 68. The width W4 of the first bulge 69 may be approximately the same as the width W2 of the first base 67.

[0096] Of course, the width W4 of the first bulge 69 may be narrower or wider than the width W2 of the first base 67. If the width W4 is narrower than the width W2, the width W4 may be 50% or more and 80% or less of the width W2. The width W4 may have a value that falls within at least one of the following ranges: 50% or more and 55% or less, 55% or more and 60% or less, 60% or more and 65% or less, 65% or more and 70% or less, 70% or more and 75% or less, and 75% or more and 80% or less of the width W2. If the width W4 is wider than the width W2, the width W4 may exceed 100% of the width W2 and not exceed 130%. The width W4 may have a value that falls within at least one of the following ranges of width W2: greater than 100% and 105% or less, 105% or more and 110% or less, 110% or more and 115% or less, 115% or more and 120% or less, 120% or more and 125% or less, and 125% or more and 130% or less.

[0097] The width W4 may be greater than 0 μm and 3 μm or less. The width W4 may be greater than or less than the spacing of the gate structure 15. The width W4 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0098] The first upper region 21U has a first pillar side portion 76, which includes a first side portion 73, a second side portion 74, and a third side portion 75, in order from the first lower region 21L toward the first main surface 3. The first pillar side portion 76 forms a boundary with the second pillar region 22 in the first direction X. The first side portion 73 is the side portion corresponding to the first base portion 67. The first side portion 73 may also be called the "first pillar side first side portion," the "n-type first side portion," the "first base side portion," the "first main body side portion," etc. The second side portion 74 is the side portion corresponding to the first constriction portion 68. The second side portion 74 may also be called the "first pillar side second side portion," the "n-type second side portion," the "first constriction side portion," the "first concave side portion," etc. The third side portion 75 is the side portion corresponding to the first bulge portion 69. The third side portion 75 may also be referred to as the "first pillar side third side portion," the "n-type third side portion," the "first bulging side portion," the "first convex side portion," etc.

[0099] The first lower region 21L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 15, and intersects with the multiple gate structures 15 in three dimensions. In other words, the multiple first pillar regions 21 (first lower region 21L) are formed in the region directly below the gate structures 15, spaced apart in the first direction X following the direction of extension of the gate structures 15.

[0100] In this configuration, the first lower region 21L intersects with and connects to multiple well regions 20 in the region directly below the multiple gate structures 15. At the first intersection Cr1 of the well region 20 and the first lower region 21L (see Figure 18), the p-type impurity concentration in the well region 20 is offset (reduced) by the amount of the n-type impurity concentration (pentavalent element concentration) in the first lower region 21L.

[0101] The first lower region 21L has a first bottom portion 21B located below the depth position of the bottom walls of the multiple gate structures 15. The first bottom portion 21B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 15, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 15.

[0102] The first bottom portion 21B is located below the bottoms of the multiple well regions 20. The first bottom portion 21B has a portion that extends in the second direction Y in the region directly below the multiple well regions 20, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 20. The first bottom portion 21B faces the bottom walls of the multiple gate structures 15 via the multiple well regions 20.

[0103] The distance between the bottom of the well region 20 and the first bottom 21B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 21B. The distance between the bottom wall of the gate structure 15 and the first bottom 21B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 21B.

[0104] In this embodiment, the distance between the bottom wall of the gate structure 15 and the first bottom 21B is smaller than the depth of the gate structure 15. The distance between the bottom wall of the gate structure 15 and the first bottom 21B may be larger than the depth of the gate structure 15.

[0105] The first pillar region 21 does not necessarily have to include both the first constriction 68 and the first bulge 69 at the same time. The first pillar region 21 may have the first constriction 68 but not the first bulge 69. In this case, the first constriction 68 may be connected to the body region 10 as the first upper end. The first pillar region 21 may not have the first constriction 68 but may have the first bulge 69. In this case, the first bulge 69 may be connected to the body region 10 as the first upper end.

[0106] The first pillar region 21 does not necessarily have both the first constriction 68 and the first bulge 69. In this case, the first pillar region 21 may extend perpendicularly in the thickness direction Z. Of course, the first pillar region 21 may be formed in a tapered or tapered shape in the thickness direction Z. In other words, the first pillar region 21 may have only the first base portion 67.

[0107] The semiconductor device 1 includes a plurality of p-type second pillar regions 22 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The second pillar regions 22 may also be referred to as "second regions," "second impurity regions," "second column regions," etc.

[0108] Multiple second pillar regions 22 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the multiple second pillar regions 22 is lower than the p-type impurity concentration of the multiple well regions 20. The p-type impurity concentration of the multiple second pillar regions 22 may be higher or lower than the p-type impurity concentration of the body region 10.

[0109] Multiple second pillar regions 22 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 9. Of course, multiple second pillar regions 22 may also be formed in the outer region 9 within the second semiconductor layer 7. In a plan view, the multiple second pillar regions 22 are arranged at intervals in the first direction X (= m-axis direction) and each extends in a strip shape in the second direction Y (= a-axis direction).

[0110] In other words, the multiple second pillar regions 22 are arranged in a stripe-like pattern extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 15. The direction of extension of the multiple second pillar regions 22 coincides with the off-direction of the SiC single crystal.

[0111] Multiple second pillar regions 22 are formed alternately with multiple first pillar regions 21 in the first direction X, and form pn junctions with the multiple first pillar regions 21. As a result, a bipolar diode is formed that includes multiple first pillar regions 21 as cathode regions and multiple second pillar regions 22 as anode regions.

[0112] The multiple second pillar regions 22 have a charge balance with respect to the multiple first pillar regions 21 and constitute a superjunction structure with the multiple first pillar regions 21. Charge balance refers to a state in which the depletion layers extending from the multiple second pillar regions 22 are connected within the multiple first pillar regions 21.

[0113] Multiple second pillar regions 22 are formed at intervals corresponding to the width of the first pillar region 21. The spacing of the second pillar regions 22 may be approximately equal to the width of the second pillar region 22. The spacing of the second pillar regions 22 may be greater than or less than the width of the second pillar region 22.

[0114] The spacing of the second pillar region 22 may be approximately equal to the spacing of the first pillar region 21. The spacing of the second pillar region 22 may be larger or smaller than the spacing of the first pillar region 21. The spacing of the second pillar region 22 may be larger or smaller than the width of the gate structure 15. The spacing of the second pillar region 22 may be larger or smaller than the spacing of the gate structure 15.

[0115] The spacing of the second pillar region 22 may be greater than 0 μm and less than or equal to 3 μm. The spacing of the second pillar region 22 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0116] Multiple second pillar regions 22 are formed in a region below the bottom of the body region 10 and extend in a vertical columnar shape along the thickness direction Z. Multiple second pillar regions 22 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0117] In this configuration, each of the multiple second pillar regions 22 is formed by a single p-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). In other words, the multiple second pillar regions 22 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. In other words, the multiple second pillar regions 22 are inclined by the off-angle from the vertical axis in the off-direction.

[0118] In this configuration, the extension direction (a-axis direction) of the multiple second pillar regions 22 coincides with the off-direction of the off-angle. Therefore, the multiple second pillar regions 22 extend almost perpendicularly in a cross-sectional view along the direction orthogonal to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0119] The second pillar region 22 has a depth greater than the depth of the gate structure 15. The depth of the second pillar region 22 is less than the thickness of the second semiconductor layer 7. The depth of the second pillar region 22 may be approximately equal to the depth of the first pillar region 21.

[0120] The depth of the second pillar region 22 may be greater than the depth of the first pillar region 21. The depth of the second pillar region 22 may be less than the depth of the first pillar region 21. The depth of the second pillar region 22 may be greater than 0 μm and 5 μm or less.

[0121] The depth of the second pillar region 22 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or more and 5 μm or less. Preferably, the depth of the second pillar region 22 is 1 μm or more.

[0122] The aspect ratio of the second pillar region 22 may be approximately equal to that of the first pillar region 21. The aspect ratio of the second pillar region 22 is the ratio of the depth of the second pillar region 22 to its width. The aspect ratio of the second pillar region 22 may be greater than or less than that of the first pillar region 21.

[0123] The aspect ratio of the second pillar region 22 may be between 1 and 10. The aspect ratio of the second pillar region 22 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0124] Each of the multiple second pillar regions 22 has a second upper region 22U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 15, and a second lower region 22L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 15. The p-type impurity concentration in the multiple second pillar regions 22 is lower than the p-type impurity concentration in the multiple well regions 20 in both the second upper region 22U and the second lower region 22L.

[0125] The second upper region 22U is interposed in the region between the multiple gate structures 15 and extends in the second direction Y. The second upper region 22U is connected to the side walls of the multiple gate structures 15 and faces the embedded electrode 18 via the insulating film 17 of the multiple gate structures 15. The second upper region 22U has a second upper end connected to the body region 10.

[0126] The second upper region 22U is located between the multiple gate structures 15 and forms a pn junction with the first upper region 21U of the multiple first pillar regions 21. The second upper region 22U has a charge balance with the first upper region 21U in the region between the multiple gate structures 15 and forms a superjunction structure with the first upper region 21U.

[0127] Referring to Figures 8 and 14 to 17, the second upper region 22U in this configuration has a second base portion 70 with a substantially constant width in the thickness direction Z, a second bulge portion 71 that bulges in the first direction X, and a second constriction portion 72 that is narrowed in the first direction X.

[0128] The second base portion 70 is continuously connected to the second lower region 22L and is the portion that maintains the width W5 of the second lower region 22L in the thickness direction Z. For example, the width W6 of the second base portion 70 may be 90% or more and 110% or less of the width W5 of the second lower region 22L. The width W6 of the second base portion 70 may have a value that falls within at least one of the following ranges of 90% or more and 95%, 95% or more and 100%, 100% or more and 105%, or 105% or more and 110% of the width W5 of the second lower region 22L. In this embodiment, the second base portion 70 is formed in a tapered shape that widens slightly toward the first main surface 3 in cross-sectional view.

[0129] Widths W5 and W6 have widths corresponding to the spacing of the first pillar region 21. Widths W5 and W6 may be approximately equal to the width W2 of the first base portion 67. Widths W5 and W6 may be larger or smaller than width W2. Widths W5 and W6 may be larger or smaller than the width of the gate structure 15. Widths W5 and W6 may be larger or smaller than the spacing of the gate structure 15.

[0130] The widths W5 and W6 may specifically be greater than 0 μm and 3 μm or less. The widths W5 and W6 may have values ​​that fall within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0131] The second bulge 71 is formed along the first constriction 68 of the first pillar region 21 within a thickness range between the bottom walls of the multiple gate structures 15 and the bottom of the body region 10, and is a portion in which the width in the first direction X gradually increases toward the body region 10.

[0132] The width W7 of the second bulge 71 is wider than the width W8 of the second constriction 72 (described later). The width W7 of the second bulge 71 may be greater than 100% of the width W8 of the second constriction 72 and less than or equal to 130%. The width W7 of the second bulge 71 may have a value that falls within at least one of the following ranges: greater than 100% of the width W8 of the second constriction 72 and less than or equal to 105%, 105% or more and less than or equal to 110%, 110% or more and less than or equal to 115%, 115% or more and less than or equal to 120%, 120% or more and less than or equal to 125%, and 125% or more and less than or equal to 130%.

[0133] Specifically, the width W7 may be greater than 0 μm and 3 μm or less. The width W7 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0134] The second constriction 72 is formed along the first bulge 69 of the first pillar region 21 in the region between the body region 10 and the second bulge 71, and is a portion in which the width in the first direction X gradually decreases toward the bottom of the body region 10. In other words, the irregularities of the second upper region 22U interlock with the irregularities of the first upper region 21U. In this embodiment, the second constriction 72 forms a second upper end connected to the body region 10.

[0135] The width W8 of the second constriction 72 is narrower than the width W7 of the second bulge 71. The width W8 of the second constriction 72 may be 50% or more and 80% or less of the width W7 of the second bulge 71. The width W8 of the second constriction 72 may have a value that falls within at least one of the following ranges: 50% or more and 55%, 55% or more and 60%, 60% or more and 65%, 65% or more and 70%, 70% or more and 75%, or 75% or more and 80% of the width W7 of the second bulge 71.

[0136] The width W8 may specifically be greater than 0 μm and 3 μm or less. The width W8 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0137] Of course, the width W8 of the second constricted portion 72 may be narrower or wider than the width W6 of the second base portion 70. If the width W8 is narrower than the width W6, the width W8 may be 50% or more and 80% or less of the width W2. The width W8 may have a value that falls within at least one of the following ranges of width W6: 50% or more and 55%, 55% or more and 60%, 60% or more and 65%, 65% or more and 70%, 70% or more and 75%, or 75% or more and 80%. If the width W8 is wider than the width W6, the width W8 may be greater than 100% of the width W6 and 130% or less. The width W8 may have a value that falls within at least one of the following ranges of width W6: greater than 100% and 105% or less, 105% or more and 110% or less, 110% or more and 115% or less, 115% or more and 120% or less, 120% or more and 125% or less, and 125% or more and 130% or less.

[0138] The second upper region 22U has a second pillar side portion 96, which includes a first side portion 93, a second side portion 94, and a third side portion 95, in order from the second lower region 22L toward the first main surface 3. The second pillar side portion 96 forms a boundary with the first pillar region 21 in the first direction X. The first side portion 93 is the side portion corresponding to the second base portion 70. The first side portion 93 may also be called the "second pillar side first side portion," the "p-type first side portion," the "second base side portion," the "second main body side portion," etc. The second side portion 94 is the side portion corresponding to the second bulge portion 71. The second side portion 94 may also be called the "second pillar side second side portion," the "p-type second side portion," the "second bulge side portion," the "second convex side portion," etc. The third side portion 95 is the side portion corresponding to the second constriction portion 72. The third side portion 95 may also be referred to as the "second pillar side third side portion," the "p-type third side portion," the "second constricted side portion," the "second concave side portion," etc.

[0139] The second lower region 22L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 15 and intersects with the multiple gate structures 15 in three dimensions. In other words, the multiple second pillar regions 22 (second lower region 22L) are formed in the region directly below the gate structures 15, spaced apart in the first direction X following the direction of extension of the gate structures 15. The multiple second pillar regions 22 are formed alternately with the multiple first pillar regions 21 in the region directly below the gate structures 15 in the first direction X.

[0140] In this configuration, the second lower region 22L intersects with and connects to the multiple well regions 20 in the region directly below the multiple gate structures 15. In other words, the multiple second pillar regions 22 are interposed between the body region 10 and the multiple well regions 20, electrically connecting the multiple well regions 20 to the body region 10. The multiple second pillar regions 22 are electrically interlocked with the body region 10 and the multiple well regions 20.

[0141] In the second intersection Cr2 of the well region 20 and the second lower region 22L (see Figure 18), the p-type impurity concentration in the well region 20 is increased by the amount of the p-type impurity concentration (trivalent element concentration) in the second lower region 22L. In other words, the p-type impurity concentration in the second intersection Cr2 is higher than the p-type impurity concentration in the first intersection Cr1.

[0142] The second lower region 22L forms a pn joint with the first lower region 21L of the multiple first pillar regions 21. Specifically, the second lower region 22L has a portion that forms a pn joint with the first lower region 21L in the region directly below the multiple gate structures 15, and a portion that forms a pn joint with the first lower region 21L outside the region directly below the multiple gate structures 15.

[0143] The second lower region 22L has a portion that forms a pn junction with the first lower region 21L in the region directly below the multiple well regions 20, and a portion that forms a pn junction with the first lower region 21L outside the region directly below the multiple well regions 20. The second lower region 22L has a charge balance with the first lower region 21L and constitutes a superjunction structure with the first lower region 21L.

[0144] The second lower region 22L has a second bottom portion 22B located below the depth position of the bottom walls of the multiple gate structures 15. The second bottom portion 22B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 15, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 15.

[0145] The second bottom portion 22B is located below the bottoms of the multiple well regions 20. The second bottom portion 22B has a portion that extends in the second direction Y in the region directly below the multiple well regions 20, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 20. The second bottom portion 22B faces the bottom walls of the multiple gate structures 15 via the multiple well regions 20.

[0146] The second bottom 22B may be located in the region directly beneath the multiple gate structures 15 at approximately the same depth as the first bottom 21B of the first pillar region 21. The second bottom 22B may be located below the first bottom 21B (towards the bottom of the second semiconductor layer 7) in the region directly beneath the multiple gate structures 15. The second bottom 22B may be located above the first bottom 21B (towards the bottom wall of the multiple gate structures 15 / towards the bottom of the multiple well regions 20) in the region directly beneath the multiple gate structures 15.

[0147] The distance between the bottom of the well region 20 and the second bottom 22B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 22B. The distance between the bottom wall of the gate structure 15 and the second bottom 22B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 22B.

[0148] In this embodiment, the distance between the bottom wall of the gate structure 15 and the second bottom 22B is smaller than the depth of the gate structure 15. The distance between the bottom wall of the gate structure 15 and the second bottom 22B may be larger than the depth of the gate structure 15.

[0149] The second pillar region 22 does not necessarily have to include both the second bulge 71 and the second constriction 72 at the same time. The second pillar region 22 may have the second bulge 71 but not the second constriction 72. In this case, the second bulge 71 may be connected to the body region 10 as the second upper end. The second pillar region 22 may not have the second bulge 71 but may have the second constriction 72. In this case, the second constriction 72 may be connected to the body region 10 as the second upper end.

[0150] The second pillar region 22 does not necessarily have both the second bulge 71 and the second constriction 72. In this case, the second pillar region 22 may extend perpendicularly in the thickness direction Z. Of course, the second pillar region 22 may be formed in a tapered or tapered shape in the thickness direction Z. In other words, the second pillar region 22 may have only the second base portion 70.

[0151] Referring to Figures 18 and 19, the semiconductor device 1 includes a p-type mesh region 25 formed within the second semiconductor layer 7 in a horizontal cross-sectional view. The mesh region 25 extends in a mesh-like manner in the first direction X (m-axis direction) and the second direction Y (a-axis direction) along the first main surface 3 at a thickness position spaced apart from the first main surface 3 within the second semiconductor layer 7.

[0152] The mesh region 25 divides the second semiconductor layer 7 into multiple n-type inter-mesh regions 26, which serve as multiple current paths. The mesh region 25 narrows the current when the device is on and improves short-circuit withstand capability. The mesh region 25 is formed in a region below the depth position of the bottom of the body region 10. The mesh region 25 is formed in a region below the bottom walls of the multiple gate structures 15 (trenches 16).

[0153] The mesh region 25 integrally includes a plurality of p-shaped well regions 20 as a plurality of first regions (first stripe regions) extending in a strip shape in the first direction X, and a plurality of p-shaped second pillar regions 22 as a plurality of second regions (second stripe regions) extending in a strip shape in the second direction Y.

[0154] Multiple well regions 20 extend in a stripe-like pattern in the first direction X at thickness positions spaced apart from the first main surface 3 within the second semiconductor layer 7. Each of the multiple well regions 20 is formed in the region below (specifically directly beneath) the multiple gate structures 15, and overlaps with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z.

[0155] Each of the multiple second pillar regions 22 has a p-type impurity concentration lower than that of the multiple well regions 20. The multiple second pillar regions 22 extend in a stripe pattern in the second direction Y within the second semiconductor layer 7 so as to be connected to the multiple well regions 20 in a mesh-like manner, and demarcate the multiple well regions 20 and the multiple inter-mesh regions 26.

[0156] Multiple second pillar regions 22 are connected to multiple well regions 20 in a cross shape. Of course, multiple second pillar regions 22 may also be connected to multiple well regions 20 in a T shape. The second pillar regions 22 may have a width greater than the width of the well regions 20. The width of the second pillar regions 22 may be less than the width of the well regions 20. The width of the second pillar regions 22 may be approximately equal to the width of the well regions 20.

[0157] The multiple second pillar regions 22 extend vertically in the thickness direction Z of the second semiconductor layer 7 in a cross-sectional view, and each has a second upper region 22U (first portion) located above the multiple well regions 20, and a second lower region 22L (second portion) located below the multiple well regions 20. The second bottom portion 22B of the second lower region 22L is located below the bottom portion of the multiple well regions 20.

[0158] Multiple second upper regions 22U are connected to the body region 10, and multiple second lower regions 22L are connected to multiple well regions 20. In other words, the multiple second lower regions 22L form a mesh region 25 with the multiple well regions 20 and simultaneously partition multiple intermesh regions 26. Furthermore, the multiple second upper regions 22U are formed as connection parts that electrically connect the mesh region 25 to the body region 10.

[0159] The multiple intermesh regions 26 are partitioned in a row along the first direction X, following the direction of extension of the multiple well regions 20 (multiple gate structures 15) in a plan view. The multiple intermesh regions 26 are partitioned in a row along the second direction Y, following the direction of extension of the multiple second pillar regions 22 (multiple first pillar regions 21) in a plan view. In other words, the multiple intermesh regions 26 are partitioned in a matrix with spacing in the first direction X and the second direction Y in a plan view.

[0160] In this configuration, the multiple intermesh regions 26 are formed by multiple n-type first pillar regions 21 having an n-type impurity concentration higher than that of the second semiconductor layer 7, and extend in a vertically elongated columnar shape along the thickness direction Z. The multiple intermesh regions 26 form low-resistance current paths having a resistance value lower than that of the second semiconductor layer 7.

[0161] Each of the multiple mesh regions 26 comprises a first upper region 21U (first part) partitioned above the bottom walls of the multiple gate structures 15, and a first lower region 21L (second part) partitioned below the bottom walls of the multiple gate structures 15.

[0162] The first upper region 21U is partitioned by a plurality of gate structures 15 and a plurality of second pillar regions 22 (second upper region 22U). The first lower region 21L is partitioned by a mesh region 25. In other words, the first lower region 21L is partitioned by a plurality of well regions 20 and a plurality of second pillar regions 22 (second lower region 22L).

[0163] The semiconductor device 1 includes a plurality of n-type source regions 40 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The source regions 40 may also be referred to as "impurity regions," "high-concentration regions," etc. The source regions 40 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0164] The n-type impurity concentration in the source region 40 is higher than the p-type impurity concentration in the body region 10. The n-type impurity concentration in the source region 40 is higher than the n-type impurity concentration in the first pillar region 21. The n-type impurity concentration in the source region 40 is higher than the p-type impurity concentration in the second pillar region 22.

[0165] Multiple source regions 40 are formed on the surface of the body region 10, spaced apart from the bottom of the body region 10 towards the first main surface 3, in the region between the multiple gate structures 15. Referring to Figures 4 and 5, the multiple source regions 40 are strip-shaped and extend along the second direction Y, following the intersecting direction of the extending direction of the multiple gate structures 15, so as to cross the multiple gate structures 15. Each of the strip-shaped multiple source regions 40 is arranged spaced apart in the first direction X, following the extending direction of the multiple gate structures 15.

[0166] From another perspective, with respect to the multiple source regions 40 formed on one side and the other side of the second direction Y with respect to a single gate structure 15, the multiple source regions 40 on the other side are opposite the source region 40 on the one side in the second direction Y when viewed from above. In other words, the multiple source regions 40 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0167] Referring to Figures 14 to 16, the multiple source regions 40 are formed in a region that overlaps with the multiple second pillar regions 22 in the thickness direction Z via a portion of the body region 10 (i.e., a region that overlaps with the multiple first pillar regions 21). In this embodiment, the multiple source regions 40 overlap both the multiple first pillar regions 21 and the multiple second pillar regions 22 in the thickness direction Z via a portion of the body region 10.

[0168] The multiple source regions 40 may be arranged, for example, in a first direction X at approximately the same pitch as the first pillar region 21, and may form stripes that cross the multiple gate structures 15. As shown in Figures 4 and 5, in a plan view, the first pillar region 21 and the source regions 40 provide a first stripe region 101 that is spaced apart in the first direction X. That is, the multiple source regions 40 are located away from the region directly above the second pillar region 22 in the thickness direction Z.

[0169] More specifically, the first side portion 93 (second base side portion) of the second pillar region 22 is located in the region directly below the boundary portion 77 between the contact region 41 (described later) and the source region 40. "Located in the region directly below the boundary portion 77" may be defined as the first side portion 93 extending in the thickness direction Z along an imaginary extension line 78 (shown as a dashed line in Figures 14 to 16) of the boundary portion 77 which extends in the thickness direction Z. In other words, the first side portion 93 may be located substantially on the extension line 78 of the boundary portion 77 in the thickness direction Z. Of course, the first side portion 93 may be slightly offset (for example, by about 100 nm or less) on both sides of the extension line 78 in the first direction X.

[0170] The ends 97 of the multiple source regions 40 in a first direction X may face the first side portion 93 of the second pillar region 22 in the thickness direction Z. The ends 97 of the multiple source regions 40 in a first direction X may overlap the first side portion 93 of the second pillar region 22 in the thickness direction Z. As a result, most of the multiple source regions 40 overlap the multiple first pillar regions 21 in the thickness direction Z via a part of the body region 10.

[0171] The second side portion 94 (second bulging side portion) of the second pillar region 22 is located in the region directly below the inner portion 98 of the source region 40. The inner portion 98 of the source region 40 is, for example, the entire region that is separated from the source region 40 in the first direction X by more than 100 nm from the boundary portion 77, and may be referred to as the central portion of the source region 40. In this embodiment, since the second pillar region 22 has a second bulging portion 71, the source region 40 (inner portion 98) overlaps with a plurality of second pillar regions 22 in the thickness direction Z via a part of the body region 10.

[0172] Each of the multiple source regions 40 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 18, and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the embedded electrode 18. The multiple source regions 40 are connected to the multiple gate structures 15 in the second direction Y and face the embedded electrode 18 via an insulating film 17.

[0173] The multiple source regions 40 are formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3. The multiple source regions 40 may also have portions located toward the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15.

[0174] In this embodiment, the width W9 of the multiple source regions 40 in the first direction X is approximately equal to the width W2 of the first base portion 67. W9 may be greater than 0 μm and 3 μm or less. The width W9 may be greater than or less than the width of the gate structure 15. The width W9 may be greater than or less than the spacing of the gate structure 15. The width W9 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0175] The semiconductor device 1 includes a plurality of p-type contact regions 41 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The contact regions 41 may also be referred to as "impurity regions," "high-concentration regions," etc.

[0176] The contact region 41 has a higher p-type impurity concentration than the body region 10. The contact region 41 may be considered a high-concentration area of ​​the body region 10. The p-type impurity concentration in the contact region 41 is higher than the n-type impurity concentration in the first pillar region 21. The p-type impurity concentration in the contact region 41 is higher than the p-type impurity concentration in the second pillar region 22.

[0177] Multiple contact regions 41 are formed on the surface of the body region 10, spaced apart from the bottom of the body region 10 toward the first main surface 3, in the region between the multiple gate structures 15. Referring to Figures 4 and 5, the multiple contact regions 41 are strip-shaped, extending along the second direction Y, following the intersecting direction of the extending direction of the multiple gate structures 15, so as to cross the multiple gate structures 15. Each of the strip-shaped multiple contact regions 41 is arranged spaced apart in the first direction X, following the extending direction of the multiple gate structures 15. In this configuration, the multiple contact regions 41 are arranged alternately with the multiple source regions 40 in a stripe pattern along the first direction X.

[0178] From another perspective, with respect to the multiple contact regions 41 formed on one side and the other side in the second direction Y with respect to a single gate structure 15, the multiple contact regions 41 on the other side are opposite the contact regions 41 on the one side in the second direction Y when viewed from above. In other words, the multiple contact regions 41 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0179] Referring to Figures 14 to 16, the multiple contact regions 41 are selectively positioned in the region directly above the second pillar region 22 in the thickness direction Z. In this configuration, "selectively positioned in the region directly above the second pillar region 22" means that the multiple contact regions 41 are formed in a region that overlaps with the multiple second pillar regions 22 via a part of the body region 10 in the thickness direction Z (a region that overlaps outside the first pillar region 21). In this configuration, the multiple contact regions 41 selectively overlap with the multiple second pillar regions 22 in the thickness direction Z via a part of the body region 10, while not overlapping with the multiple first pillar regions 21 in the thickness direction Z.

[0180] The multiple contact regions 41 may be arranged, for example, in a stripe pattern across the multiple gate structures 15, with approximately the same pitch as the second pillar regions 22 in the first direction X. As shown in Figures 4 and 5, in a plan view, the second pillar regions 22 and the contact regions 41 provide a second stripe region 102 that is spaced apart in the first direction X.

[0181] More specifically, as described above, the first side portion 93 (second base side portion) of the second pillar region 22 is positioned in the region directly below the boundary portion 77. As a result, the ends 99 of the multiple contact regions 41 in the first direction X may face the first side portion 93 of the second pillar region 22 in the thickness direction Z. The ends 99 of the multiple contact regions 41 in the first direction X may overlap the first side portion 93 of the second pillar region 22 in the thickness direction Z.

[0182] The second side portion 94 (second bulging side portion) of the second pillar region 22 bulges out in a direction away from the region directly below the boundary portion 77 in the first direction X. Therefore, the entire contact region 41, including the end portion 99 and the inner portion 100, overlaps with a plurality of second pillar regions 22 in the thickness direction Z via a part of the body region 10, but does not overlap with the first pillar region 21. The inner portion 100 of the contact region 41 is, for example, the entire region that is separated from the boundary portion 77 by more than 100 nm in the first direction X and is located inside the contact region 41, and may be referred to as the central portion of the contact region 41.

[0183] Referring to Figure 8, the end 99 of the contact region 41 may extend in a first direction X along the bottom of the source region 40 and support the end 97 of the source region 40 from the second main surface 4 side. The end 97 of the source region 40 is sandwiched between the end 99 of the contact region 41 and the source electrode 60 in the thickness direction Z.

[0184] In this embodiment, the multiple contact regions 41 are formed at intervals in the first direction X from the multiple first pillar regions 21 in a plan view, and do not overlap with the first pillar regions 21 in the thickness direction Z. Of course, the multiple contact regions 41 may have portions that overlap with the first pillar regions 21 in the thickness direction Z.

[0185] In this configuration, the multiple contact regions 41 overlap with the multiple second pillar regions 22 in a one-to-one correspondence in the thickness direction Z. The multiple contact regions 41 are electrically connected to the multiple second pillar regions 22 via the body region 10. In other words, the multiple contact regions 41 are electrically connected to the multiple well regions 20 via the multiple second pillar regions 22.

[0186] In this configuration, the multiple contact regions 41 are in contact with the insulating film 17 of the multiple gate structures 15 and face the embedded electrode 18 in the second direction Y through a portion of the insulating film 17.

[0187] The multiple contact regions 41 are formed deeper than the multiple source regions 40 and have bottoms located closer to the bottom of the body region 10 than the bottoms of the multiple source regions 40. The multiple contact regions 41 may be formed shallower than the multiple source regions 40.

[0188] Multiple contact regions 41 are formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3. The multiple contact regions 41 may also have portions located toward the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15.

[0189] The width W10 of the multiple contact regions 41 in the first direction X is narrower than the width W9 of the multiple source regions 40. W10 may be greater than 0 μm and 3 μm or less. The width W10 may be greater than or less than the width of the gate structure 15. The width W10 may be greater than or less than the spacing between the gate structures 15. The width W10 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Although not shown in the figures, the width W10 of the multiple contact regions 41 in the first direction X may be wider than the width W9 of the multiple source regions 40.

[0190] The width W10 of the multiple contact regions 41 in the first direction X is narrower than the width W8 of the second constriction 72. As a result, the end portion 99 of the contact region 41 is positioned inside the second constriction 72 in the first direction X. Of course, the width W10 of the multiple contact regions 41 in the first direction X is narrower than the width W6 of the second base portion 70 and the width W7 of the second bulge portion.

[0191] The semiconductor device 1 includes a plurality of n-type cap regions 42 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The cap regions 42 may also be referred to as "impurity regions," "high-concentration regions," etc.

[0192] The cap region 42 has an n-type impurity concentration higher than that of the second semiconductor layer 7. The n-type impurity concentration of the cap region 42 is higher than that of the p-type impurity concentration of the body region 10. The n-type impurity concentration of the cap region 42 may be higher or lower than that of the p-type impurity concentration of the well region 20.

[0193] The n-type impurity concentration in the cap region 42 is higher than the n-type impurity concentration in the first pillar region 21. The n-type impurity concentration in the cap region 42 is higher than the p-type impurity concentration in the second pillar region 22. The n-type impurity concentration in the cap region 42 may be higher or lower than the n-type impurity concentration in the source region 40.

[0194] The multiple cap regions 42 are each formed in the region between the multiple gate structures 15, in the region below the body region 10. The multiple cap regions 42 are formed with a gap between them and the first main surface 3 from the depth position of the bottom wall of the multiple gate structures 15. The multiple cap regions 42 include a plurality of first cap regions 42A and a plurality of second cap regions 42B.

[0195] The multiple first cap regions 42A are formed at intervals in the first direction X, following the extending direction of the multiple gate structures 15, and are adjacent to the multiple gate structures 15 in the second direction Y. Each of the multiple first cap regions 42A is formed in a one-to-one correspondence with each of the multiple first pillar regions 21. The multiple first cap regions 42A are connected to the first upper regions 21U of the multiple first pillar regions 21, thereby increasing the n-type impurity concentration in the first upper regions 21U.

[0196] The multiple first cap regions 42A are positioned on the bottom wall side of the trench 16 with respect to the electrode surface of the embedded electrode 18 and face the embedded electrode 18 via the insulating film 17. The multiple first cap regions 42A face the multiple source regions 40 in the thickness direction Z via a part of the body region 10. As a result, the multiple first cap regions 42A, together with the multiple source regions 40, form a first channel Ch1 along the multiple gate structures 15 within the body region 10.

[0197] Referring to Figures 14 to 16, in this configuration, the multiple first cap regions 42A provide the first bulge 69 (third side portion 75) of the first upper region 21U. As a result, the multiple first cap regions 42A adjacent to each other in the first direction X sandwich the second constriction 72 of the second upper region 22U. On the other hand, the second bulge 71 of the second upper region 22U bulges in the first direction X along the bottom of the first cap region 42A and supports the first cap region 42A from the second main surface 4 side. The first cap region 42A is sandwiched between the second bulge 71 and the body region 10 in the thickness direction Z.

[0198] The multiple second cap regions 42B are interposed in the regions between the multiple gate structures 15, in the regions between the multiple first cap regions 42A that are adjacent in the first direction X. The multiple second cap regions 42B extend in a strip shape in the first direction X along the side walls of the corresponding gate structures 15.

[0199] Multiple second cap regions 42B are formed at intervals from each other in the second direction Y when viewed in cross-section along the second direction Y, and face each other in the second direction Y via a portion of the corresponding second pillar region 22 (see Figure 7).

[0200] In other words, the multiple second cap regions 42B are interposed in the region between the side wall of the corresponding gate structure 15 and the corresponding second pillar region 22 in a cross-sectional view along the second direction Y (see Figure 7). Furthermore, the multiple second cap regions 42B are interposed in the thickness direction Z between the body region 10 and the corresponding second pillar region 22 in a cross-sectional view along the second direction Y (see Figure 7).

[0201] The multiple second cap regions 42B are each formed in the portion of the second upper region 22U of the multiple second pillar regions 22 that is interposed between the multiple first cap regions 42A. In this embodiment, the multiple second cap regions 42B are drawn out in a strip shape in the first direction X along the side walls of the multiple gate structures 15 from the multiple first cap regions 42A, and replace the conductivity type of a part of the second upper region 22U of the multiple second pillar regions 22 from p type to n type.

[0202] The multiple second cap regions 42B face the multiple contact regions 41 in the thickness direction Z via a portion of the body region 10. The portion of the body region 10 directly above the multiple second cap regions 42B forms a second channel Ch2. The second channel Ch2 is a portion drawn out on both sides in the first direction X from the body region 10 (first channel Ch1) directly below the multiple source regions 40. The multiple second cap regions 42B may have portions facing the multiple source regions 40 in the thickness direction Z via a portion of the body region 10.

[0203] In this way, the multiple cap regions 42 extend the current path connecting the multiple first pillar regions 21 and the multiple source regions 40 through the first channel Ch1 originating from the first cap region 42A and the second channel Ch2 originating from the second cap region 42B.

[0204] The semiconductor device 1 includes a p-type outer well region 45 formed within the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The outer well region 45 may also be referred to as the "impurity region." The outer well region 45 has a p-type impurity concentration lower than that of the well region 20. The p-type impurity concentration of the outer well region 45 may be higher or lower than that of the body region 10.

[0205] The p-type impurity concentration in the outer well region 45 may be approximately equal to that of the second pillar region 22. The p-type impurity concentration in the outer well region 45 may be higher or lower than that of the second pillar region 22. The p-type impurity concentration in the outer well region 45 is lower than that of the contact region 41. A source potential is applied to the outer well region 45.

[0206] The outer well region 45 is formed on the surface of the first main surface 3 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The outer well region 45 is formed at intervals from the periphery of the first main surface 3 to the inward side of the first main surface 3 (towards the active region 8) and extends in layers along the first main surface 3. In a plan view, the outer well region 45 extends in a band shape along the active region 8.

[0207] In this embodiment, the outer well region 45 is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The outer well region 45 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0208] The outer well region 45 has a width greater than the width of the gate structure 15. The width of the outer well region 45 is greater than the width of the well region 20. The width of the outer well region 45 is greater than the width of the first pillar region 21. The width of the outer well region 45 is greater than the width of the second pillar region 22.

[0209] The ratio of the width of the outer well region 45 to the width of the second pillar region 22 (width of the first pillar region 21) may be greater than 1 and 100 or less. The width ratio may have at least one thickness range among those greater than 1 and 10 or less, 10 to 20, 20 to 30, 30 to 40, 40 to 50, 50 to 60, 60 to 70, 70 to 80, 80 to 90, and 90 to 100.

[0210] The outer well region 45 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer well region 45 demarcates the boundary between the active region 8 and the outer region 9.

[0211] The inner edge of the outer well region 45 may be connected to either or both of the body region 10 and the plurality of second pillar regions 22. The inner edge of the outer well region 45 may be connected to the ends of the plurality of gate structures 15. The outer edge of the outer well region 45 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 45.

[0212] The outer well region 45 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The outer well region 45 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0213] In this embodiment, the outer well region 45 has a depth greater than the depth of the multiple gate structures 15. In this embodiment, the depth of the outer well region 45 is approximately equal to the depth of the multiple second pillar regions 22. The depth of the outer well region 45 may be greater or less than the depth of the multiple second pillar regions 22.

[0214] The depth of the outer well region 45 may be greater than or less than the depth of the multiple first pillar regions 21. The depth of the outer well region 45 may be less than the depth of the multiple gate structures 15. The depth of the outer well region 45 may be approximately equal to the depth of the body region 10. The depth of the outer well region 45 may be greater than or less than the depth of the body region 10.

[0215] The outer well region 45 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode including the second semiconductor layer 7 as the cathode region and the outer well region 45 as the anode region. The outer well region 45 together with the body region 10 forms a bipolar diode.

[0216] When the gate is off and a drain voltage is applied, the depletion layer expands from the outer well region 45 into the second semiconductor layer 7. The depletion layer expanding from the outer well region 45 extends the depletion layer expanding from the body region 10 (active region 8) towards the periphery of the first main surface 3, thereby mitigating the electric field (electric field concentration) at the periphery of the active region 8.

[0217] The semiconductor device 1 includes a p-type outer contact region 46 formed on the surface of the outer well region 45. The outer contact region 46 may also be referred to as the "impurity region," "high-concentration region," etc. The outer contact region 46 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 45. The outer contact region 46 may also be considered as the high-concentration portion of the outer well region 45.

[0218] The p-type impurity concentration in the outer contact region 46 is higher than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the outer contact region 46 may be approximately equal to the p-type impurity concentration in the well region 20. The p-type impurity concentration in the outer contact region 46 may be greater or less than the p-type impurity concentration in the well region 20.

[0219] The p-type impurity concentration in the outer contact region 46 is higher than the p-type impurity concentration in the second pillar region 22. The p-type impurity concentration in the outer contact region 46 may be approximately equal to the p-type impurity concentration in the contact region 41. The p-type impurity concentration in the outer contact region 46 may be greater or less than the p-type impurity concentration in the contact region 41.

[0220] The outer contact region 46 extends in a band shape along the outer well region 45 in a plan view. In this configuration, the outer contact region 46 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0221] The outer contact region 46 may have an edge portion that connects a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y in an arc shape (preferably a quarter-circular arc shape). The semiconductor device 1 may include a plurality of outer contact regions 46. In this case, the plurality of outer contact regions 46 may be formed with spacing between them following the extending direction of the outer well region 45.

[0222] The outer contact region 46 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer contact region 46 may be connected to a plurality of gate structures 15. In this case, the inner edge of the outer contact region 46 may be connected to the body region 10. The inner edge of the outer contact region 46 may be formed at a distance from the plurality of gate structures 15 on the peripheral side of the first main surface 3.

[0223] The outer edge of the outer contact region 46 is formed with a gap between the periphery of the first main surface 3 and the inward side of the first main surface 3. In this configuration, the outer edge of the outer contact region 46 is formed with a gap between the outer edge of the outer well region 45 and the inward side of the first main surface 3, and extends substantially parallel to the inner edge of the outer contact region 46.

[0224] The outer contact region 46 is formed with a gap from the bottom of the outer well region 45 toward the first main surface 3, and faces the second semiconductor layer 7 via a portion of the outer well region 45. The outer contact region 46 has a depth less than the depth of the multiple gate structures 15.

[0225] The depth of the outer contact region 46 is less than the depth of the body region 10. The depth of the outer contact region 46 may be approximately equal to the depth of the contact region 41. The depth of the outer contact region 46 may be greater than or less than the depth of the contact region 41.

[0226] The semiconductor device 1 includes at least one (or more in this embodiment) p-type field regions 47 formed within the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The field regions 47 may also be referred to as "impurity regions," etc. The multiple field regions 47 may be formed in an electrically floating state. The multiple field regions 47 may be fixed to the source potential.

[0227] The number of field regions 47 may be between 1 and 20. The number of field regions 47 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 47 is between 1 and 8. In this embodiment, the semiconductor device 1 includes 4 field regions 47.

[0228] The multiple field regions 47 have a p-type impurity concentration lower than the p-type impurity concentration of the well region 20. The p-type impurity concentration of the multiple field regions 47 may be higher or lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the multiple field regions 47 may be higher or lower than the n-type impurity concentration of the first pillar region 21.

[0229] The p-type impurity concentrations in the multiple field regions 47 may be approximately equal to the p-type impurity concentration in the second pillar region 22. The p-type impurity concentrations in the multiple field regions 47 may be higher or lower than the p-type impurity concentration in the second pillar region 22. The p-type impurity concentrations in the multiple field regions 47 may be lower than the p-type impurity concentration in the contact region 41.

[0230] The p-type impurity concentrations in multiple field regions 47 may be approximately equal to the p-type impurity concentrations in the outer well region 45. The p-type impurity concentrations in multiple field regions 47 may be higher or lower than the p-type impurity concentrations in the outer well region 45. The p-type impurity concentrations in multiple field regions 47 may be lower than the p-type impurity concentrations in the outer contact region 46.

[0231] Multiple field regions 47 are formed at intervals from each other on the surface of the second semiconductor layer 7 at the periphery of the first main surface 3, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Multiple field regions 47 are formed at intervals from the periphery of the first main surface 3 and the active region 8, in the region between the periphery of the first main surface 3 and the active region 8.

[0232] Multiple field regions 47 are formed at intervals from the outer well region 45 towards the periphery of the first main surface 3. In a plan view, the multiple field regions 47 extend in a band shape along the outer well region 45.

[0233] In this embodiment, the multiple field regions 47 are formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple field regions 47 may have edge portions that connect the portions extending in a strip shape in the first direction X and the portions extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0234] The field region 47 has a width less than the width of the outer well region 45. The width of the field region 47 may be greater than or less than the width of the gate structure 15. The width of the field region 47 may be greater than or less than the width of the well region 20. The width of the field region 47 may be greater than or less than the width of the first pillar region 21. The width of the field region 47 may be greater than or less than the width of the second pillar region 22.

[0235] Multiple field regions 47 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 through a portion of the second semiconductor layer 7. The multiple field regions 47 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0236] In this configuration, the multiple field regions 47 have a depth greater than the depth of the multiple gate structures 15. In this configuration, the depth of the multiple field regions 47 is approximately equal to the depth of the multiple second pillar regions 22. The depth of the multiple field regions 47 may be greater or less than the depth of the multiple second pillar regions 22.

[0237] In this configuration, the depth of the multiple field regions 47 is approximately equal to the depth of the outer well region 45. The depth of the multiple field regions 47 may be greater or less than the depth of the outer well region 45.

[0238] The depths of the multiple field regions 47 may be greater than or less than the depths of the multiple first pillar regions 21. The depths of the multiple field regions 47 may be less than the depths of the multiple gate structures 15. The depths of the multiple field regions 47 may be approximately equal to the depth of the body region 10. The depths of the multiple field regions 47 may be greater than or less than the depth of the body region 10.

[0239] Multiple field regions 47 form a pn junction with the second semiconductor layer 7. When the gate is off and a drain voltage is applied, multiple depletion layers spread from the multiple field regions 47 to the second semiconductor layer 7. The depletion layers spreading from the multiple field regions 47 extend the depletion layer spreading from the outer well region 45 (active region 8) toward the periphery of the first main surface 3, thereby mitigating the electric field (electric field concentration) at the periphery of the first main surface 3.

[0240] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 47 may be approximately constant or non-uniform. The width of the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3.

[0241] The depths of the multiple field regions 47 may be approximately constant or non-uniform. The depths of the multiple field regions 47 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 47 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0242] The spacing between the multiple field regions 47 may be approximately constant or non-uniform. The spacing between the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 47 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3.

[0243] The semiconductor device 1 includes an insulating interlayer film 50 that selectively covers the first main surface 3. In this embodiment, the interlayer film 50 has a laminated structure including a first interlayer film 51 and a second interlayer film 52. The first interlayer film 51 may be referred to as the "main surface insulating film," "lower insulating film," etc., and the second interlayer film 52 may be referred to as the "upper insulating film," etc.

[0244] The first interlayer film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 51 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The first interlayer film 51 may include a silicon oxide film containing oxides other than the oxide of the chip 2. The first interlayer film 51 may include an insulator of the same type as the insulating film 17.

[0245] The first interlayer film 51 selectively coats the first main surface 3 in an active region 8 and an outer region 9. The first interlayer film 51 covers the first main surface 3 in the active region 8, exposing multiple gate structures 15. Specifically, the first interlayer film 51 is connected to multiple insulating films 17, exposing multiple embedded electrodes 18. In this configuration, the first interlayer film 51 forms a single insulating film integral with the multiple insulating films 17.

[0246] The first interlayer membrane 51 covers the outer well region 45, the outer contact region 46, and multiple field regions 47 in the outer region 9. The first interlayer membrane 51 is continuous with the first to fourth side surfaces 5A to 5D. The first interlayer membrane 51 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0247] The first interlayer film 51 may have a thickness approximately equal to the thickness of the insulating film 17. The thickness of the first interlayer film 51 may be greater than 0 nm and 250 nm or less. The thickness of the first interlayer film 51 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0248] The second interlayer film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 52 may have a single-layer structure or a multilayer structure including at least one of an NSG film (Nondoped Silicate Glass film), a PSG film (Phosphorus Silicon Glass film), and a BPSG film (Boron Phosphorus Silicon Glass film).

[0249] The NSG film is a silicon oxide film without impurities, the PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron. The second interlayer film 52 preferably has a single-layer structure or a multilayer structure including at least an NSG film.

[0250] The second interlayer film 52 may have a laminated structure including an NSG film and a PSG film (or BPSG film) stacked in this order from the chip 2 side.

[0251] The second interlayer membrane 52 covers the first interlayer membrane 51 in a film-like manner in the active region 8 and the outer region 9. The second interlayer membrane 52 covers multiple gate structures 15 in the active region 8. Specifically, the second interlayer membrane 52 penetrates into multiple trenches 16 from above the first interlayer membrane 51 and covers multiple embedded electrodes 18 within the multiple trenches 16.

[0252] The second interlayer membrane 52 covers the first main surface 3 via the first interlayer membrane 51 in the outer region 9. Specifically, the second interlayer membrane 52 covers the outer well region 45, the outer contact region 46, and multiple field regions 47 via the first interlayer membrane 51.

[0253] The second interlayer membrane 52 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the second interlayer membrane 52 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the first interlayer membrane 51.

[0254] The second interlayer membrane 52 has a thickness greater than the thickness of the first interlayer membrane 51. The thickness of the second interlayer membrane 52 may be greater than 0 μm and 5 μm or less. The thickness of the second interlayer membrane 52 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0255] Referring to Figure 10, the semiconductor device 1 includes one or more (one in this embodiment) gate wirings 55 selectively routed along the periphery (outer region 9) of the first main surface 3. The gate wirings 55 are electrically connected to a plurality of gate structures 15 and provide gate potentials to the plurality of gate structures 15.

[0256] The gate wiring 55 may contain a non-metallic conductor. The gate wiring 55 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 55 contains the same conductive material as the conductive material of the embedded electrode 18.

[0257] The gate wiring 55 is located within the interlayer film 50. Specifically, the gate wiring 55 is located on the first interlayer film 51 and covered by the second interlayer film 52. The gate wiring 55 is spaced apart from the periphery of the first main surface 3 towards the active region 8. The gate wiring 55 is spaced apart from the multiple field regions 47 (the innermost field region 47).

[0258] The gate wiring 55 is positioned at a distance from the outer edge of the outer well region 45. The gate wiring 55 is positioned at a distance from the outer edge of the outer contact region 46. In a plan view, the gate wiring 55 extends in a strip shape along the active region 8.

[0259] In this embodiment, the gate wiring 55 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The gate wiring 55 may also be formed in the shape of an ended strip. The gate wiring 55 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0260] The gate wiring 55 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the gate wiring 55 is mechanically and electrically connected to the ends of the multiple gate structures 15. Specifically, the inner edge of the gate wiring 55 enters into the multiple trenches 16 from above the first interlayer membrane 51 and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16.

[0261] In this configuration, the gate wiring 55 is formed integrally with the multiple buried electrodes 18 as the lead-out portion of the multiple buried electrodes 18. The connection portion of the gate wiring 55 to the multiple buried electrodes 18 may be considered as part of the multiple buried electrodes 18, or as part of the gate wiring 55.

[0262] The inner edge of the gate wiring 55 covers the first main surface 3 via the first interlayer film 51 in the region between the multiple gate structures 15. The inner edge of the gate wiring 55 may overlap either or both of the body region 10 and the outer well region 45 in the region between the multiple gate structures 15.

[0263] The semiconductor device 1 includes one or more (in this embodiment, more than one) source openings 56 formed in the interlayer film 50 in the active region 8. The multiple source openings 56 are each formed in the region between the multiple gate structures 15, spaced apart from the multiple gate structures 15, and penetrate the interlayer film 50. In other words, the multiple source openings 56 each expose multiple mesa regions partitioned by the multiple gate structures 15 in the chip 2 (second semiconductor layer 7).

[0264] Multiple source openings 56 are formed at intervals in the second direction Y and each extends in a strip shape in the first direction X, following the direction of extension of the multiple gate structures 15. Multiple source openings 56 expose multiple source regions 40 and multiple contact regions 41.

[0265] The multiple source openings 56 may be formed at intervals in the first direction X in the region between two adjacent gate structures 15 in the second direction Y. In this case, the multiple source openings 56 may each extend in a strip shape in the first direction X, exposing either or both of the source region 40 and the contact region 41.

[0266] Each of the multiple source apertures 56 has an aperture width less than or equal to the spacing between the multiple gate structures 15. The aperture width may be greater than 0 μm and 3 μm or less. The aperture width may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less.

[0267] The aperture width may be 1.5 μm or less. The aperture width may be 1.2 μm or less. The aperture width may be 1 μm or less. The aperture width may be 0.8 μm or less. The aperture width may be 0.6 μm or less. The aperture width may be 0.4 μm or less.

[0268] Referring to Figures 11 to 17, the semiconductor device 1 includes one or more (in this embodiment, more) source recesses 57 formed on the first main surface 3 in the active region 8. The source recesses 57 may also be called "recesses," "mesa recesses," etc. The source recesses 57 may be considered as part of (a component of) the first main surface 3. The semiconductor device 1 is not necessarily required to have source recesses 57, and a configuration without source recesses 57 may be adopted.

[0269] Multiple source recesses 57 are formed in the portion of the first main surface 3 that is exposed from multiple source openings 56. Each of the multiple source recesses 57 has a planar shape that matches the planar shape of the multiple source openings 56 and is excavated toward the second main surface 4.

[0270] Multiple source recesses 57 are formed at intervals toward the first main surface 3 from the depth positions of the bottom of the multiple source regions 40 and the depth positions of the bottom of the multiple contact regions 41, exposing the multiple source regions 40 and the multiple contact regions 41. The multiple source recesses 57 are located toward the first main surface 3 than the depth positions of the electrode surfaces of the multiple embedded electrodes 18.

[0271] Referring to Figures 5 and 10, the semiconductor device 1 includes one or more (in this embodiment, more) gate openings 58 formed in the interlayer film 50 in the outer region 9. The multiple gate openings 58 penetrate the interlayer film 50 and selectively expose gate wiring 55.

[0272] In this configuration, the multiple gate openings 58 extend in a strip-like shape following the direction of extension of the gate wiring 55. The multiple gate openings 58 may be formed at intervals in the direction of extension of the gate wiring 55. The multiple gate openings 58 may be formed in a polygonal or circular shape in plan view. The multiple gate structures 15 may be formed in a square or hexagonal shape in plan view.

[0273] The multiple gate openings 58 may have portions that extend in a strip shape in a first direction X and portions that extend in a strip shape in a second direction Y when viewed from above. The multiple gate openings 58 may have edge portions that connect the portions that extend in the first direction X and the portions that extend in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above. The semiconductor device 1 may include one gate opening 58 that extends in a strip shape along the gate wiring 55.

[0274] Referring to Figure 2, the semiconductor device 1 includes one or more (one in this embodiment) outer openings 59 formed in the interlayer film 50. The outer openings 59 are formed with a gap from the gate wiring 55 toward the periphery of the first main surface 3 and with a gap from the periphery of the first main surface 3 toward the inward side of the first main surface 3. The outer openings 59 are formed with a gap from a plurality of field regions 47 (the innermost field region 47) toward the inward side of the first main surface 3.

[0275] The outer opening 59 penetrates the interlayer film 50 and exposes the outer contact region 46. In this embodiment, the outer opening 59 has a width less than the width of the outer contact region 46 and exposes the inner portion of the outer contact region 46 at a distance from its inner and outer edges. The outer opening 59 may also expose the outer well region 45.

[0276] The outer opening 59 extends in a strip shape following the direction of extension of the outer well region 45. The outer opening 59 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the outer opening 59 is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0277] The outer opening 59 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape) when viewed from above. The outer opening 59 may be formed in the shape of an end-band.

[0278] The semiconductor device 1 may include a plurality of outer openings 59. In this case, the plurality of outer openings 59 may be formed at intervals in the extending direction of the outer well region 45. The plurality of outer openings 59 may be formed in a polygonal or circular shape in plan view. The plurality of outer openings 59 may be formed in a square or hexagonal shape in plan view.

[0279] The semiconductor device 1 includes a source electrode 60 positioned in the inner portion (active region 8) of the first main surface 3. The source electrode 60 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source pad electrode," etc. The source electrode 60 is made of metal and is positioned on the interlayer film 50.

[0280] In this embodiment, the source electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large surface area and forms the main body of the source electrode 60. In this embodiment, the first pad portion 60a is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the third side surface 5C relative to the central part of the first main surface 3.

[0281] The second pad portion 60b has a flat area less than that of the first pad portion 60a, and extends in a strip-like (square-shaped) manner from one end of the first direction X (the end on the second side surface 5B side) toward the first side surface 5A.

[0282] The third pad portion 60c has a flat area less than the flat area of ​​the first pad portion 60a, extends in a strip shape (square shape) from the other end of the first pad portion 60a in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A, and faces the second pad portion 60b in the first direction X. The flat area of ​​the third pad portion 60c may be approximately equal to the flat area of ​​the second pad portion 60b. The flat area of ​​the third pad portion 60c may be larger or smaller than the flat area of ​​the second pad portion 60b.

[0283] Either the second pad portion 60b or the third pad portion 60c, or both, may be used as terminal portions for current monitoring. The source electrode 60 may have only one of the second pad portion 60b or the third pad portion 60c. The source electrode 60 may consist only of the first pad portion 60a and may not have both the second pad portion 60b and the third pad portion 60c.

[0284] The source electrode 60 enters a plurality of source openings 56 from above the interlayer film 50 and is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within the plurality of source openings 56. In this embodiment, the source electrode 60 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within a plurality of source recesses 57.

[0285] The source electrode 60 is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the source electrode 60 is formed with a gap between it and the active region 8 from the multiple field regions 47. The peripheral edge of the source electrode 60 is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the source electrode 60 is formed with a gap between it and the outer edge of the outer contact region 46.

[0286] The peripheral edge of the source electrode 60 is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the source electrode 60 faces the outer well region 45 in the thickness direction Z. The peripheral edge of the source electrode 60 may also face the outer contact region 46 in the thickness direction Z.

[0287] The source electrode 60 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source electrode 60 may contain a metal film comprising at least one of the following: aluminum (Al)-based metals, titanium (Ti)-based metals, nickel (Ni)-based metals, copper (Cu)-based metals, molybdenum (Mo)-based metals, palladium (Pd)-based metals, silver (Ag)-based metals, tungsten (W)-based metals, and gold (Au)-based metals.

[0288] The source electrode 60 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The source electrode 60 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0289] In this embodiment, the source electrode 60 has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 is formed as a barrier electrode for the chip 2 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0290] In this embodiment, the base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b. The first electrode 61a consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 61a consists of a titanium-based metal film (titanium film).

[0291] The first electrode 61a penetrates the interlayer film 50 through a plurality of source openings 56. The first electrode 61a has a portion that covers the interlayer film 50 in a film-like manner, a portion that covers the walls of the plurality of source openings 56 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner.

[0292] The first electrode 61a is electrically connected to multiple source regions 40 and multiple contact regions 41 within multiple source openings 56. In this embodiment, the first electrode 61a is electrically connected to multiple source regions 40 and multiple contact regions 41 within multiple source recesses 57.

[0293] The first electrode 61a is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the first electrode 61a is formed with a gap between it and the multiple field regions 47 towards the active region 8. The peripheral edge of the first electrode 61a is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the first electrode 61a is formed with a gap between it and the outer edge of the outer contact region 46.

[0294] The peripheral edge of the first electrode 61a is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the first electrode 61a faces the outer well region 45 in the thickness direction Z. The peripheral edge of the first electrode 61a may also face the outer contact region 46 in the thickness direction Z.

[0295] The first electrode 61a has a thickness less than the thickness of the interlayer film 50. The thickness of the first electrode 61a may be greater than 0 nm and 100 nm or less. The thickness of the first electrode 61a may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0296] The second electrode 61b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second electrode 61b consists of a different metal film or alloy film than the first electrode 61a. In this embodiment, the second electrode 61b consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0297] The second electrode 61b covers the first electrode 61a in a film-like manner and penetrates the multiple source openings 56 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the wall surfaces of the multiple source openings 56 in a film-like manner via the first electrode 61a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 61a.

[0298] The second electrode 61b is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via the first electrode 61a. In this embodiment, the second electrode 61b is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via the first electrode 61a over a plurality of source recesses 57.

[0299] The second electrode 61b is drawn out into the outer region 9 and has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral portion of the second electrode 61b is formed with a gap between it and the multiple field regions 47 towards the active region 8. The peripheral portion of the second electrode 61b is formed with a gap between it and the outer edge of the outer well region 45. The peripheral portion of the second electrode 61b is formed with a gap between it and the outer edge of the outer contact region 46.

[0300] The peripheral edge of the second electrode 61b is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the second electrode 61b faces the outer well region 45 in the thickness direction Z. The peripheral edge of the second electrode 61b may also face the outer contact region 46 in the thickness direction Z.

[0301] The second electrode 61b has a thickness less than the thickness of the interlayer film 50. In this embodiment, the thickness of the second electrode 61b is greater than the thickness of the first electrode 61a. The thickness of the second electrode 61b may be less than the thickness of the first electrode 61a. The thickness of the second electrode 61b may be greater than 0 nm and 300 nm or less.

[0302] The thickness of the second electrode 61b may be greater than 0 nm and fall within at least one of the following ranges: 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0303] The main electrode 62 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The main electrode 62 is made of a different conductor than the first electrode 61a and the second electrode 61b. In this embodiment, the main electrode 62 is made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may contain at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0304] The main electrode 62 covers the base electrode 61 in a film-like manner and penetrates the multiple source openings 56 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surfaces of the multiple source openings 56 in a film-like manner via the base electrode 61, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 61.

[0305] The main electrode 62 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via a base electrode 61. In this embodiment, the main electrode 62 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via a base electrode 61 over a plurality of source recesses 57.

[0306] The main electrode 62 is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the main electrode 62 is formed with a gap between it and the active region 8 from the multiple field regions 47. The peripheral edge of the main electrode 62 is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the main electrode 62 is formed with a gap between it and the outer edge of the outer contact region 46.

[0307] The peripheral edge of the main electrode 62 is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the main electrode 62 faces the outer well region 45 in the thickness direction Z. The peripheral edge of the main electrode 62 may also face the outer contact region 46 in the thickness direction Z.

[0308] The main electrode 62 has a thickness greater than the thickness of the base electrode 61 (the total thickness of the first electrode 61a and the second electrode 61b). In this embodiment, the thickness of the main electrode 62 is greater than the thickness of the interlayer film 50. The thickness of the main electrode 62 may be less than the thickness of the interlayer film 50. The thickness of the main electrode 62 may be greater than 0 μm and 5 μm or less.

[0309] The thickness of the main electrode 62 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0310] The semiconductor device 1 includes a source finger 63 arranged on the peripheral edge (outer region 9) of the first main surface 3. The source finger 63 may also be called a "source electrode," "source wiring," or "source finger electrode." The source finger 63 is made of metal. The source finger 63 transmits the source potential applied to the source electrode 60 to other regions.

[0311] The source finger 63 is drawn out from the source electrode 60 onto the interlayer film 50. The source finger 63 is routed around the periphery of the first main surface 3 and the region between the source electrode 60, extending in a band shape along the active region 8. In this embodiment, the source finger 63 is drawn out from the side of the first pad portion 60a on the third side surface 5C side onto the outer opening 59.

[0312] The source finger 63 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y when viewed from above. In this embodiment, the source finger 63 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8. The source finger 63 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0313] The source finger 63 enters the outer opening 59 from above the interlayer film 50 and is electrically connected to the outer contact region 46 within the outer opening 59. As a result, the source potential applied to the source electrode 60 is applied to the outer well region 45 via the outer contact region 46.

[0314] The source finger 63 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source finger 63 is spaced apart from the plurality of gate structures 15 on the peripheral side of the first main surface 3 and faces the outer well region 45 in the thickness direction Z.

[0315] The inner edge of the source finger 63 is positioned at a distance from the gate wiring 55 toward the periphery of the first main surface 3. The inner edge of the source finger 63 may also be formed at a distance from the middle of the outer well region 45 toward the periphery of the first main surface 3. The inner edge of the source finger 63 may face the outer contact region 46 in the thickness direction Z.

[0316] The outer edge of the source finger 63 is formed at intervals from multiple field regions 47 (the innermost field region 47) toward the inward side of the first main surface 3 and extends substantially parallel to the inner edge of the source finger 63. This suppresses the shielding of the electric field dispersion path by the source finger 63, and the electric field (electric field lines) is appropriately dispersed by the multiple field regions 47.

[0317] In this embodiment, the outer edge of the source finger 63 is formed at a distance from the outer edge of the outer well region 45 toward the inward side of the first main surface 3 and is located on the outer well region 45. The outer edge of the source finger 63 may also be located on the outer contact region 46. The outer edge of the source finger 63 may also be located on the second semiconductor layer 7.

[0318] The source finger 63, like the source electrode 60, has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b.

[0319] The first electrode 61a extends from above the interlayer film 50 into the outer opening 59. The first electrode 61a has a portion that covers the insulating surface of the interlayer film 50 in a film-like manner, a portion that covers the wall surface of the outer opening 59 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner. The first electrode 61a is electrically connected to the outer contact region 46 within the outer opening 59.

[0320] The second electrode 61b covers the first electrode 61a in a film-like manner and extends into the outer opening 59 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the wall surface of the outer opening 59 in a film-like manner via the first electrode 61a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 61a. The second electrode 61b is electrically connected to the outer contact region 46 via the first electrode 61a within the outer opening 59.

[0321] The main electrode 62 covers the base electrode 61 in a film-like manner and enters the outer opening 59 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surface of the outer opening 59 in a film-like manner via the base electrode 61, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 61. The main electrode 62 is electrically connected to the outer contact region 46 within the outer opening 59 via the base electrode 61.

[0322] Referring to Figures 1 and 2, the semiconductor device 1 includes a gate electrode 64 disposed on the first main surface 3. The gate electrode 64 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "gate pad electrode," etc. The gate electrode 64 is made of metal. The gate electrode 64 is disposed on the interlayer film 50 at a distance from the source electrode 60 and source finger 63.

[0323] The gate electrode 64 is positioned in the region on the first side surface 5A side relative to the first pad portion 60a, and faces the central portion of the first side surface 5A and the first pad portion 60a in the second direction Y. The gate electrode 64 is interposed in the region between the second pad portion 60b and the third pad portion 60c, and faces both the second pad portion 60b and the third pad portion 60c in the first direction X.

[0324] The gate electrode 64 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 64 has a planar area less than the planar area of ​​the source electrode 60. The planar area of ​​the gate electrode 64 is less than the planar area of ​​the first pad portion 60a. The planar area of ​​the gate electrode 64 may be larger or smaller than the planar area of ​​the second pad portion 60b (third pad portion 60c).

[0325] In this embodiment, the gate electrode 64 faces the first main surface 3 via the interlayer film 50 and does not have a direct electrical connection to the gate wiring 55. The gate electrode 64 may be electrically connected to the gate wiring 55 via one or more gate openings 58, and electrically connected to a plurality of gate structures 15 via the gate wiring 55.

[0326] In this embodiment, the gate electrode 64 faces the outer well region 45 via the interlayer film 50. The gate electrode 64 may have portions that face multiple gate structures 15 via the interlayer film 50. The gate electrode 64 may be formed at a distance from the multiple gate structures 15 and may not face multiple gate structures 15 in the thickness direction Z.

[0327] Although not shown in the illustration, the gate electrode 64, like the source electrode 60, includes a base electrode 61 and a main electrode 62 stacked in this order from the interlayer film 50 side. The base electrode 61 has a stacked structure including a first electrode 61a and a second electrode 61b.

[0328] Referring to Figures 1, 5, and 10, the semiconductor device 1 includes a gate finger 65 positioned on the periphery (outer region 9) of the first main surface 3. The gate finger 65 may also be referred to as a "gate electrode," "gate wiring," or "gate finger electrode." The gate finger 65 is made of metal. The gate finger 65 transmits the gate potential applied to the gate electrode 64 to other regions.

[0329] The gate finger 65 is drawn out from the gate electrode 64 onto the interlayer film 50. The gate finger 65 is routed in a strip-like manner in the region between the source electrode 60 and the source finger 63. The gate finger 65 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y when viewed in plan.

[0330] In this embodiment, the gate finger 65 is formed in the shape of an ended band having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 60. The gate finger 65 is positioned closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 15. The gate finger 65 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0331] The gate finger 65 enters a plurality of gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 55 within the plurality of gate openings 58. As a result, the gate potential applied to the gate electrode 64 is applied to the plurality of gate structures 15 via the gate wiring 55 and the gate finger 65.

[0332] The gate finger 65 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger 65 is formed at a distance from the plurality of gate structures 15 on the peripheral side of the first main surface 3. In other words, the gate finger 65 does not face the plurality of gate structures 15 in the thickness direction Z.

[0333] The inner edge of the gate finger 65 is positioned on the gate wiring 55. The inner edge of the gate finger 65 is horizontally opposed to the peripheral edge of the source electrode 60 on the gate wiring 55. The inner edge of the gate finger 65 may be located on the peripheral side of the first main surface 3 relative to the middle portion of the gate wiring 55. The inner edge of the gate finger 65 may be located on the inward side of the first main surface 3 relative to the middle portion of the gate wiring 55.

[0334] The outer edge of the gate finger 65 extends substantially parallel to the inner edge of the gate finger 65. The outer edge of the gate finger 65 is drawn out from above the gate wiring 55 towards the peripheral edge of the first main surface 3 and does not face the gate wiring 55 in the thickness direction Z. The outer edge of the gate finger 65 is formed with a gap between multiple field regions 47 (the innermost field region 47) on the inward side of the first main surface 3.

[0335] The outer edge of the gate finger 65 is formed with a gap between it and the outer edge of the outer well region 45, on the inward side of the first main surface 3. In this configuration, the outer edge of the gate finger 65 is formed with a gap between it and the inner edge of the outer contact region 46, on the inward side of the first main surface 3, and faces the outer well region 45.

[0336] The outer edge of the gate finger 65 is horizontally opposed to the inner edge of the source finger 63. The outer edge of the gate finger 65 may be located on the outer contact region 46. The outer edge of the gate finger 65 may be located on the second semiconductor layer 7.

[0337] The gate finger 65, like the source electrode 60 (gate electrode 64), has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b.

[0338] The first electrode 61a penetrates the interlayer film 50 through a plurality of gate openings 58. The first electrode 61a has a portion that covers the insulating surface of the interlayer film 50 in a film-like manner, a portion that covers the walls of the plurality of gate openings 58 in a film-like manner, and a portion that covers the gate wiring 55 in a film-like manner. The first electrode 61a is electrically connected to the gate wiring 55 within the plurality of gate openings 58.

[0339] The second electrode 61b covers the first electrode 61a in a film-like manner and penetrates the multiple gate openings 58 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the walls of the multiple gate openings 58 in a film-like manner via the first electrode 61a, and a portion that covers the gate wiring 55 in a film-like manner via the first electrode 61a. The second electrode 61b is electrically connected to the gate wiring 55 via the first electrode 61a within the multiple gate openings 58.

[0340] The main electrode 62 covers the base electrode 61 in a film-like manner and penetrates the multiple gate openings 58 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner via the base electrode 61, and a portion that covers the gate wiring 55 in a film-like manner via the base electrode 61. The main electrode 62 is electrically connected to the gate wiring 55 via the base electrode 61 within the multiple gate openings 58.

[0341] The semiconductor device 1 includes a drain electrode 66 that covers the second main surface 4. The drain electrode 66 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," "drain pad electrode," etc. The drain electrode 66 is mechanically and electrically connected to the first semiconductor layer 6. The drain electrode 66 forms ohmic contact with the first semiconductor layer 6.

[0342] The drain electrode 66 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 66 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0343] The breakdown voltage that can be applied between the source electrode 60 and the drain electrode 66 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0344] (2) Method for Manufacturing the Semiconductor Device 1 The method for manufacturing the semiconductor device 1 will be described below. Figure 20 is a schematic diagram showing a wafer 80 used in the manufacturing method of the semiconductor device 1. Referring to Figure 20, the wafer 80 is cut from a semiconductor single crystal (SiC single crystal) ingot as a substrate for the chip 2 and formed into a flat disc shape. The wafer 80 may also be formed into a flat rectangular plate shape.

[0345] The wafer 80 has a first wafer main surface 81 on one side, a second wafer main surface 82 on the other side, and a wafer side surface 83 connecting the first wafer main surface 81 and the second wafer main surface 82. The first wafer main surface 81 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 82 corresponds to the second main surface 4 of the chip 2.

[0346] The first wafer main surface 81 and the second wafer main surface 82 are formed by the c-plane of a SiC single crystal. The first wafer main surface 81 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 82 is formed by the carbon plane of the SiC single crystal. The wafer 80 has the aforementioned off-direction and off-angle.

[0347] The wafer 80 has markings 84 on the wafer side surface 83 indicating the crystal orientation of the SiC single crystal. The markings 84 may include either an orientation flat or an orientation notch, or both. In this embodiment, the markings 84 include an orientation notch.

[0348] An orientation flat consists of a notch that is cut out in a straight line when viewed from above. An orientation notch consists of a notch that is cut out in a concave shape (for example, a tapered shape) toward the center of the first wafer main surface 81 when viewed from above.

[0349] The marker 84 may include either or both a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction. The marker 84 may also include either or both an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.

[0350] The wafer 80 includes an n-type first semiconductor layer 6 formed on the surface layer of the second wafer main surface 82. The first semiconductor layer 6 is formed in a layered manner extending along the second wafer main surface 82 and forms the second wafer main surface 82 and the wafer side surface 83. In this embodiment, the first semiconductor layer 6 consists of an n-type semiconductor substrate (SiC substrate) containing a semiconductor single crystal (SiC single crystal) and has the aforementioned off-direction and off-angle.

[0351] The wafer 80 includes an n-type second semiconductor layer 7 formed on the surface layer of the first wafer main surface 81. The second semiconductor layer 7 is formed in a layered manner extending along the first wafer main surface 81 and forms the first wafer main surface 81 and the wafer side surface 83.

[0352] The second semiconductor layer 7 consists of an n-type epitaxial layer (SiC epitaxial layer) containing a semiconductor single crystal (SiC single crystal), and is stacked on top of the first semiconductor layer 6. In other words, in this embodiment, the wafer 80 consists of an epitaxial wafer having a stacked structure including a semiconductor substrate and an epitaxial layer. The second semiconductor layer 7 has the aforementioned off-direction and off-angle.

[0353] The wafer 80 includes a plurality of device regions 85 and a plurality of cutting lines 86. For example, the plurality of device regions 85 and the plurality of cutting lines 86 are demarcated by alignment marks, etc., formed inside the wafer 80 and / or on the first wafer main surface 81. Each device region 85 is a region corresponding to the semiconductor device 1 and is set in a rectangular shape in plan view.

[0354] In this configuration, the multiple device regions 85 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 85 are each spaced inward from the periphery of the first wafer main surface 81 in a plan view. The multiple cutting lines 86 are arranged in a grid pattern extending along the first direction X and the second direction Y to demarcate the multiple device regions 85.

[0355] Figures 21A to 21Q are cross-sectional views showing one step in an example of a semiconductor device 1 manufacturing method. In the following, a method for manufacturing the semiconductor device 1 within a single device region 85 will be mainly illustrated.

[0356] Referring to Figure 21A, the aforementioned wafer 80 (see Figure 20) is prepared, and an active region 8 and an outer region 9 are set on the wafer 80 (device region 85). The active region 8 is set in the inner part of the device region 85, and the outer region 9 is set at the periphery of the device region 85.

[0357] Referring to Figures 21B and 21C, the process of forming a plurality of n-type first pillar regions 21 (see Figure 21B) and the process of forming a plurality of p-type second pillar regions 22 (see Figure 21C) are carried out in any order. The process of forming the second pillar regions 22 may be carried out before the process of forming the first pillar regions 21. The process of forming the second pillar regions 22 may be carried out after the process of forming the first pillar regions 21.

[0358] In the process of forming the first pillar region 21 (see Figure 21B), first, a first mask M1 having a predetermined layout is placed on the main surface 81 of the first wafer. The first mask M1 may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both. The first mask M1 has a plurality of openings that expose the areas in the active region 8 where a plurality of first pillar regions 21 are to be formed.

[0359] Next, n-type impurities (pentavalent elements) are introduced into the second semiconductor layer 7 by ion implantation via the first mask M1. The ion implantation method may be either channeling ion implantation or random ion implantation, or both. In the channeling ion implantation process, n-type impurities are introduced into the second semiconductor layer 7 (wafer 80) approximately parallel to the axial channel (c-axis in this configuration) of the second semiconductor layer 7 (wafer 80). In other words, the implantation angle of the n-type impurities relative to the first wafer main surface 81 is inclined by an off-angle with respect to the vertical axis.

[0360] In the channeling ion implantation process, the collision probability of n-type impurities with the atomic rows of the SiC single crystal is reduced. In other words, n-type impurities are introduced into a relatively large thickness range of the second semiconductor layer 7 while repeatedly undergoing small-angle scattering due to the channeling effect. The implantation depth of the n-type impurities is adjusted by the implantation energy.

[0361] n-type impurities may be implanted into the second semiconductor layer 7 in a single step to a single target thickness range. In this case, multiple first pillar regions 21, each consisting of a single n-type impurity region, are formed. Of course, n-type impurities may also be implanted in multiple steps with different implantation energies to multiple different target thickness ranges of the second semiconductor layer 7. In this case, multiple first pillar regions 21 are formed in which multiple n-type impurity regions are integrated in the thickness direction Z.

[0362] On the other hand, in the random ion implantation process, n-type impurities are introduced into the second semiconductor layer 7 in random directions other than the axial channels (directions intersecting the axial channels). For example, the random direction is the thickness direction Z. In the random ion implantation process, the collision probability of n-type impurities with the atomic rows of the SiC single crystal is high, so the n-type impurities are introduced into a relatively narrow thickness range of the second semiconductor layer 7. The implantation depth of the n-type impurities is adjusted by the implantation energy.

[0363] Therefore, when forming a plurality of relatively deep first pillar regions 21 in a random ion implantation process, it is preferable that n-type impurities are implanted in multiple stages with different implantation energies for multiple different target thickness ranges of the second semiconductor layer 7. In this case, a plurality of first pillar regions 21 are formed in which the plurality of n-type impurity regions are integrated in the thickness direction Z.

[0364] By appropriately adjusting the injection conditions for n-type impurities (injection amount, injection energy, etc.), a first pillar region 21 having a desired depth and concentration gradient is formed. Of course, the n-type impurities may be injected into the second semiconductor layer 7 in a single step to a single target thickness range. In this case, a plurality of relatively shallow first pillar regions 21, each consisting of a single n-type impurity region, are formed.

[0365] In the process of forming the first pillar region 21, n-type impurities are introduced into the surface layer of the second semiconductor layer 7 so as to maintain the n-type impurity concentration at the bottom of the second semiconductor layer 7. After the process of forming the first pillar region 21, the first mask M1 is removed.

[0366] In the process of forming the second pillar region 22 (see Figure 21C), first, a second mask M2 having a predetermined layout is placed on the main surface 81 of the first wafer. The second mask M2 may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both. The second mask M2 has a plurality of openings that expose the areas in the active region 8 where a plurality of second pillar regions 22 are to be formed.

[0367] Next, p-type impurities (trivalent elements) are introduced into the second semiconductor layer 7 by ion implantation via the second mask M2. The ion implantation method may be either channeling ion implantation or random ion implantation, or both. In the channeling ion implantation process, p-type impurities are introduced into the second semiconductor layer 7 (wafer 80) approximately parallel to the axial channel (c-axis in this configuration) of the second semiconductor layer 7 (wafer 80). In other words, the implantation angle of the p-type impurities relative to the first wafer main surface 81 is inclined by an off-angle with respect to the vertical axis.

[0368] In the channeling ion implantation process, the collision probability of p-type impurities with the atomic rows of the SiC single crystal is reduced. In other words, p-type impurities are introduced into a relatively large thickness range of the second semiconductor layer 7 while repeatedly undergoing small-angle scattering due to the channeling effect. The implantation depth of the p-type impurities is adjusted by the implantation energy.

[0369] The p-type impurity may be implanted into the second semiconductor layer 7 in a single step to a single target thickness range. In this case, multiple second pillar regions 22, each consisting of a single p-type impurity region, are formed. Of course, the p-type impurity may also be implanted in multiple steps with different implantation energies to multiple different target thickness ranges of the second semiconductor layer 7. In this case, multiple second pillar regions 22 are formed in which multiple p-type impurity regions are integrated in the thickness direction Z.

[0370] On the other hand, in the random ion implantation process, p-type impurities are introduced into the second semiconductor layer 7 in random directions other than the axial channels (directions intersecting the axial channels). For example, the random direction is the thickness direction Z. In the random ion implantation process, the probability of collisions between p-type impurities and the atomic rows of the SiC single crystal is high, so the p-type impurities are introduced into a relatively narrow thickness range of the second semiconductor layer 7. The implantation depth of the p-type impurities is adjusted by the implantation energy.

[0371] Therefore, when forming a plurality of relatively deep second pillar regions 22 in a random ion implantation process, it is preferable that p-type impurities are implanted in multiple stages with different implantation energies for multiple different target thickness ranges of the second semiconductor layer 7. In this case, a plurality of second pillar regions 22 are formed in which the plurality of p-type impurity regions are integrated in the thickness direction Z.

[0372] The injection energy of p-type impurities may be approximately equal to that of n-type impurities. The injection energy of p-type impurities may be higher than that of n-type impurities. The injection energy of p-type impurities may be lower than that of n-type impurities. By appropriately adjusting the injection conditions of p-type impurities (injection amount, injection energy, etc.), a second pillar region 22 having a desired depth and concentration gradient is formed.

[0373] Of course, the p-type impurities may be injected into the second semiconductor layer 7 in a single step to a single target thickness range. In this case, a plurality of relatively shallow second pillar regions 22, each consisting of a single p-type impurity region, are formed.

[0374] In the process of forming the second pillar region 22, p-type impurities are introduced into the surface layer of the second semiconductor layer 7 so as to maintain the n-type impurity concentration at the bottom of the second semiconductor layer 7. After the process of forming the second pillar region 22, the second mask M2 is removed.

[0375] The process of forming the second pillar region 22 may also serve as the process of forming the p-type outer well region 45 and the process of forming a plurality of p-type field regions 47. In this case, the second mask M2 has openings in the outer region 9 that expose areas where a plurality of outer well regions 45 should be formed, and a plurality of openings in the outer region 9 that expose areas where a plurality of field regions 47 should be formed.

[0376] In the p-type impurity injection step, p-type impurities are introduced into the second semiconductor layer 7 via the second mask M2 in the outer region 9, forming an outer well region 45 and a plurality of field regions 47. Of course, the outer well region formation step 45 and the field region formation step 47 may be performed at any timing before the second pillar region 22 formation step, or at any timing after the second pillar region 22 formation step.

[0377] Referring to Figures 21D to 21F, the process of forming the p-type body region 10 (see Figure 21D), the process of forming the n-type source region 40 (see Figure 21E), and the process of forming the p-type contact region 41 (see Figure 21F) are carried out in any order.

[0378] In the body region 10 formation step (see Figure 21D), a mask (not shown) that exposes the area in the active region 8 where the body region 10 is to be formed is placed on the first wafer main surface 81. The mask may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both.

[0379] Next, p-type impurities (trivalent elements) are introduced into the second semiconductor layer 7 by ion implantation via a mask (random ion implantation). This forms a body region 10 on the surface of the first wafer main surface 81. The body region 10 is formed shallower than the plurality of first pillar regions 21 and the plurality of second pillar regions 22. After the formation of the body region 10, the mask is removed.

[0380] In the process of forming the source region 40 (see Figure 21E), a first mask M1 is placed on the first wafer main surface 81 to expose the area in the active region 8 where the source region 40 is to be formed. The first mask M1 may be the same as the first mask M1 used during ion implantation of the first pillar region 21.

[0381] Next, n-type impurities (pentavalent elements) are introduced into the surface layer of the body region 10 by ion implantation (random ion implantation) through the first mask M1. This forms a source region 40 on the surface layer of the body region 10 that has the same planar pattern as the first pillar region 21. After the formation of the source region 40, the first mask M1 is removed.

[0382] In the process of forming the contact region 41 (see Figure 21F), a second mask M2 is placed on the main surface 81 of the first wafer to expose the area in the active region 8 where the contact region 41 is to be formed. The second mask M2 may be the same as the second mask M2 used during ion implantation of the second pillar region 22.

[0383] Next, p-type impurities (trivalent elements) are introduced into the surface layer of the body region 10 by ion implantation (random ion implantation) through the second mask M2. As a result, a contact region 41 having the same planar pattern as the second pillar region 22 is formed on the surface layer of the body region 10.

[0384] After the contact region 41 formation step, a step for forming a p-type outer contact region 46 may be performed. In the outer contact region 46 formation step, a mask (not shown) that exposes the area in the outer region 9 where the outer contact region 46 is to be formed is placed on the first wafer main surface 81. The mask may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both.

[0385] In the p-type impurity injection step, p-type impurities are introduced into the second semiconductor layer 7 via a mask in the outer region 9, forming the outer contact region 46. Of course, the outer contact region 46 formation step may be performed at any time before the contact region 41 formation step.

[0386] The process of forming the body region 10, the process of forming the source region 40, and the process of forming the contact region 41 may be performed before the process of forming the first pillar region 21 and the process of forming the second pillar region 22.

[0387] Referring to Figure 21G, a process for forming multiple trenches 16 is carried out. In this process, first, a third mask M3 having a predetermined layout is placed on the main surface 81 of the first wafer. The third mask M3 has multiple openings that expose the areas in which the multiple trenches 16 are to be formed. The third mask M3 may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both.

[0388] Next, unwanted portions of the wafer 80 are removed by an etching method via the third mask M3. The etching method may be either a wet etching method or a dry etching method, or both. Preferably, the etching method is the RIE method (Reactive Ion Etching method), which is an example of a dry etching method. This forms a plurality of trenches 16. After the step of forming the plurality of trenches 16, the third mask M3 is removed.

[0389] The steps for forming the first pillar region 21, the second pillar region 22, the body region 10, the source region 40, and the contact region 41 may be performed at any timing after the steps for forming the multiple trenches 16.

[0390] Referring to Figure 21H, a process for forming multiple p-type well regions 20 is carried out. In this process, first, a fourth mask M4 having a predetermined layout is placed on the first wafer main surface 81.

[0391] The fourth mask M4 has openings that expose areas where multiple well regions 20 should be formed (i.e., the bottom walls of multiple trenches 16). The fourth mask M4 may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both.

[0392] Next, p-type impurities (trivalent elements) are introduced into the second semiconductor layer 7 through the bottom walls of multiple trenches 16 by ion implantation via the fourth mask M4. Random ion implantation is preferred. This forms multiple well regions 20. After the formation of the multiple well regions 20, the fourth mask M4 is removed.

[0393] If the bottom walls of the multiple trenches 16 are flat, variations in the introduction depth of n-type impurities caused by variations in the depth of the bottom walls of the multiple trenches 16 are suppressed. As a result, the accuracy of introducing n-type impurities into the second semiconductor layer 7 is improved, and multiple well regions 20 are properly formed. The process of forming the well regions 20 may be carried out using the third mask M3 instead of the fourth mask M4. In this case, the process of forming the fourth mask M4 is omitted.

[0394] Referring to Figure 21I, a process for forming multiple n-type cap regions 42 is carried out. In this process, first, a fifth mask M5 having a predetermined layout is placed on the first wafer main surface 81.

[0395] The fifth mask M5 is embedded in a plurality of trenches 16 and has openings that expose areas where a plurality of cap regions 42 should be formed (i.e., areas outside the plurality of trenches 16). The fifth mask M5 may have a single-layer structure or a multi-layer structure that includes either or both an inorganic mask and an organic mask (resist mask).

[0396] Next, n-type impurities (pentavalent elements) are introduced into the region below the body region 10 by ion implantation via the fifth mask M5. The ion implantation method is preferably random ion implantation. This forms a plurality of cap regions 42. After the formation of the plurality of cap regions 42, the fifth mask M5 is removed. The formation of the cap regions 42 may be performed at any time before the formation of the trench 16.

[0397] Referring to Figure 21J, the process of forming the base insulating film 90 is carried out. The base insulating film 90 serves as the base for the plurality of insulating films 17 and the first interlayer film 51. The base insulating film 90 is formed in a film-like manner on the main surface 81 of the first wafer and on the walls of the plurality of trenches 16 in the active region 8 and the outer region 9. The base insulating film 90 may be formed by either or both of the CVD method and / or an oxidation treatment method (e.g., thermal oxidation treatment).

[0398] Referring to Figure 21K, the process of forming the first base electrode film 91 is carried out. The first base electrode film 91 serves as the base for the multiple embedded electrodes 18 and gate wiring 55. The first base electrode film 91 has a portion that covers the main surface 81 of the first wafer via the base insulating film 90, and a portion that is embedded in the multiple trenches 16 via the base insulating film 90. The base insulating film 90 may be formed by the CVD method.

[0399] Referring to Figure 21L, the first base electrode film 91 removal step is performed. In this step, first, a mask (not shown) having a predetermined layout is placed on the first base electrode film 91. The mask has openings that selectively expose areas other than the area where the gate wiring 55 is to be formed. The mask may have a single-layer structure or a multi-layer structure that includes either an inorganic mask or an organic mask (resist mask) or both.

[0400] Next, any unnecessary portions of the first base electrode film 91 are removed by etching through a mask. The first base electrode film 91 is removed until the base insulating film 90 is exposed. The etching method may be either wet etching or dry etching, or both. This forms a plurality of embedded electrodes 18 and gate wiring 55. After the removal of the first base electrode film 91, the mask is removed.

[0401] Referring to Figure 21M, the process of forming the second interlayer film 52 is carried out. The second interlayer film 52 coats the main surface 81 of the first wafer in a film-like manner via the base insulating film 90 in the active region 8 and the outer region 9 so as to cover the multiple gate structures 15 (embedded electrodes 18) and gate wiring 55. The second interlayer film 52 may be formed by the CVD method. This forms an interlayer film 50 including the first interlayer film 51 and the second interlayer film 52.

[0402] Referring to Figure 21N, the step of removing the interlayer film 50 is performed. In this step, first, a sixth mask M6 having a predetermined layout is placed on the interlayer film 50. The sixth mask M6 has a plurality of openings that expose areas to which one or more (in this embodiment, multiple) source openings 56, one or more (in this embodiment, multiple) gate openings 58, and one or more (in this embodiment, one) outer openings 59 should be formed. The sixth mask M6 may have a single-layer structure or a multi-layer structure that includes either or both an inorganic mask and an organic mask (resist mask).

[0403] Next, any unwanted portions of the interlayer film 50 are removed by etching through the sixth mask M6. The etching method may be either wet etching or dry etching, or both. This creates a plurality of source openings 56, a plurality of gate openings 58, and an outer opening 59. After the removal of the interlayer film 50, the sixth mask M6 is removed.

[0404] In the etching process of the interlayer film 50, the portion of the interlayer film 50 that covers the first wafer main surface 81 and the multiple gate structures 15 is removed until the first wafer main surface 81 is exposed, so that a portion of the interlayer film 50 (second interlayer film 52) remains in the multiple trenches 16 as multiple embedded insulators 19. This forms multiple gate structures 15 including multiple embedded insulators 19.

[0405] After the removal of the first base electrode film 91 (see Figure 21L), a removal of the base insulating film 90 (first interlayer film 51) may be performed. In this case, the base insulating film 90 (first interlayer film 51) is removed by etching until the main surface 81 of the first wafer is exposed.

[0406] As a result, the base insulating film 90 is separated into a plurality of insulating films 17 and a first interlayer film 51. The upper ends of the plurality of insulating films 17 may be located above the electrode surfaces of the plurality of embedded electrodes 18, or they may be located below the electrode surfaces of the plurality of embedded electrodes 18.

[0407] Referring to Figure 21O, the process of forming the second base electrode film 92 is carried out. The second base electrode film 92 is the base for the source electrode 60, source finger 63, gate electrode 64, and gate finger 65, and is formed on the interlayer film 50.

[0408] The second base electrode film 92 has a laminated structure including a base electrode 61 and a main electrode 62. The base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b.

[0409] The first electrode 61a is formed in a film-like manner along the main surface 81 of the first wafer, the interlayer film 50, the walls of the multiple source openings 56, the walls of the multiple gate openings 58, and the walls of the outer opening 59. The first electrode 61a may be formed by either sputtering or vapor deposition, or both.

[0410] The second electrode 61b is formed in a film-like manner on the first electrode 61a along the first wafer main surface 81, the interlayer film 50, the walls of the multiple source openings 56, the walls of the multiple gate openings 58, and the walls of the outer opening 59. The second electrode 61b may be formed by either sputtering or vapor deposition, or both.

[0411] The main electrode 62 is formed in a film-like manner on the base electrode 61 along the first wafer main surface 81, the interlayer film 50, the walls of the multiple source openings 56, the walls of the multiple gate openings 58, and the walls of the outer opening 59. The main electrode 62 may be formed by either sputtering or vapor deposition, or both.

[0412] Referring to Figure 21P, the removal of the second base electrode film 92 is performed. In this step, first, a seventh mask M7 having a predetermined layout is formed on the second base electrode film 92. The seventh mask M7 exposes areas other than the regions where the source electrode 60, source finger 63, gate electrode 64, and gate finger 65 are to be formed.

[0413] Next, unnecessary portions of the second base electrode film 92 are removed by etching through the seventh mask M7. In this step, unnecessary portions of the main electrode 62 are removed until the underlying electrode 61 is exposed. The etching method may be either wet etching or dry etching, or both.

[0414] Next, the unnecessary portions of the base electrode 61 are removed until the interlayer film 50 is exposed. The etching method may be either wet etching or dry etching, or both. In the base electrode 61 removal step, the unnecessary portions of the second electrode 61b and the unnecessary portions of the first electrode 61a are selectively removed by etching in this order.

[0415] This forms the source electrode 60, source finger 63, gate electrode 64, and gate finger 65. After the removal of the second base electrode film 92, the seventh mask M7 is removed.

[0416] Referring to Figure 21Q, a wafer thinning process is carried out. The wafer 80 is thinned from the second wafer main surface 82 side. The wafer thinning process may include either or both an etching process and a grinding process on the second wafer main surface 82. The etching process may include either or both a wet etching method and a dry etching method. The grinding process may include a chemical mechanical polishing method.

[0417] Referring to Figure 21R, the process of forming the drain electrode 66 is carried out. The drain electrode 66 is formed in a film-like manner on the main surface 82 of the second wafer. The drain electrode 66 may be formed by either sputtering or vapor deposition, or both. Thereafter, the wafer 80 is cut along the planned cutting line 86 (see Figure 20), and a plurality of semiconductor devices 1 are cut out. The semiconductor device 1 is manufactured through the process including the above.

[0418] (3) Effects of semiconductor device 1 Above, the semiconductor device 1 may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type body region 10, a trench-type gate structure 15, a p-type well region 20, and a p-type second pillar region 22 (pillar region).

[0419] The second semiconductor layer 7 may have a first main surface 3. The body region 10 may be formed on the surface of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to penetrate the body region 10. The gate structure 15 may extend in a first direction X along the first main surface 3.

[0420] The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may electrically connect the well region 20 to the body region 10.

[0421] This configuration provides a novel semiconductor device 1. For example, with this configuration, the depletion layer caused by the second pillar region 22 improves the electrical breakdown voltage (e.g., breakdown voltage), while the electrical floating state of the well region 20 is suppressed by the second pillar region 22.

[0422] This improves the electrical response characteristics of the well region 20, while simultaneously appropriately mitigating the electric field on the gate structure 15 through the well region 20. Furthermore, the second pillar region 22 intersecting the gate structure 15 limits the formation of non-channel areas along the gate structure 15, thereby suppressing the reduction in current processing capability caused by the reduction in channel area.

[0423] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the breakdown voltage improvement effect of the well region 20 and the second pillar region 22 is effective.

[0424] The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0425] The well region 20 may have a higher p-type impurity concentration than the body region 10. This configuration appropriately improves the electrical response characteristics of the well region 20 and the electric field relaxation effect provided by the well region 20.

[0426] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0427] The second pillar region 22 may have a bottom located below the bottom of the well region 20. With this configuration, the electric field for the gate structure 15 is mitigated by the second pillar region 22 from below the well region 20.

[0428] The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. The second pillar region 22 may have a bottom portion having a p-type impurity concentration lower than that of the well region 20. With these configurations, the depletion layer originating from the second pillar region 22 expands appropriately.

[0429] The semiconductor device 1 may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the region outside the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. With this configuration, a channel can be appropriately formed in the region outside the second pillar region 22.

[0430] The multiple source regions 40 may be arranged, for example, in a first direction X at approximately the same pitch as the first pillar region 21, and may be in the shape of stripes crossing the multiple gate structures 15. This allows the source regions 40 to be formed using the first mask M1 used when forming the first pillar region 21 (see Figure 21E), thereby improving the efficiency of the manufacturing process of the semiconductor device 1.

[0431] The semiconductor device 1 may include a p-type contact region 41. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. With this configuration, the electrical response characteristics of the second pillar region 22 are improved by the contact region 41, and at the same time, the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0432] The multiple contact regions 41 may be arranged, for example, in a stripe shape across the multiple gate structures 15, with approximately the same pitch as the second pillar region 22 in the first direction X. This allows the contact regions 41 to be formed using the second mask M2 used when forming the second pillar region 22 (see Figure 21F), thereby improving the efficiency of the manufacturing process of the semiconductor device 1.

[0433] The semiconductor device 1 may include an n-type first pillar region 21. The first pillar region 21 may extend in a second direction Y within the second semiconductor layer 7 so as to intersect the gate structure 15. The first pillar region 21 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. In this case, the second pillar region 22 may form a pn junction with the first pillar region 21.

[0434] In this configuration, the electrical breakdown voltage is improved by the depletion layer caused by the pn junction between the first pillar region 21 and the second pillar region 22. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. In this configuration, the depletion layer caused by the pn junction is appropriately expanded.

[0435] Multiple first pillar regions 21 may be formed at intervals in the first direction X. Multiple second pillar regions 22 may be formed alternately with the multiple first pillar regions 21 in the first direction X. In this case, the second pillar regions 22 may form a superjunction structure with the first pillar regions 21. This configuration appropriately improves electrical withstand voltage.

[0436] The semiconductor device 1 may include an n-type cap region 42. The cap region 42 may be formed along the gate structure 15 within the second semiconductor layer 7 so as to be interposed between the body region 10 and a portion of the second pillar region 22 in a cross-sectional view. With this configuration, a current path is formed via the cap region 42 near the second pillar region 22, reducing on-resistance.

[0437] The cap region 42 may be connected to the first pillar region 21. With this configuration, a current path is formed through the first pillar region 21 and the cap region 42, and the on-resistance is appropriately reduced.

[0438] The cap region 42 has an n-type impurity concentration higher than the p-type impurity concentration of the second pillar region 22, and the conductivity type of a portion of the second pillar region 22 may be replaced from p-type to n-type. With this configuration, the cap region 42 is appropriately interposed between the body region 10 and a portion of the second pillar region 22 in cross-sectional view. The cap region 42 may be formed with a gap from the bottom wall of the gate structure 15 toward the first main surface 3.

[0439] The cap region 42 may face the source region 40 across the body region 10. With this configuration, a channel can be appropriately formed in the region between the source region 40 and the cap region 42.

[0440] The field region 47 may be formed within the second semiconductor layer 7 of the outer region 9. With this configuration, the electrical breakdown voltage of the active region 8 is improved by the depletion layer originating from the second pillar region 22, and the electrical breakdown voltage of the outer region 9 is improved by the depletion layer originating from the field region 47.

[0441] The field region 47 may be formed deeper than the gate structure 15. With this configuration, the electrical breakdown voltage of the active region 8 is improved by the second pillar region 22 which is deeper than the gate structure 15, and the electrical breakdown voltage of the outer region 9 is improved by the field region 47 which is deeper than the gate structure 15.

[0442] The field region 47 may have a portion extending in a first direction X and a portion extending in a second direction Y. With this configuration, the electrical withstand voltage of the outer region 9 is appropriately improved by the field region 47.

[0443] The field region 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. With this configuration, the electric field at the edge portion of the field region 47 is appropriately mitigated.

[0444] The field region 47 may be formed deeper than the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the field region 47 which is deeper than the well region 20. Such a configuration is particularly effective when a second pillar region 22 which is deeper than the well region 20 is formed.

[0445] The field region 47 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the field region 47, which has a lower concentration than the well region 20. This configuration is particularly effective when a second pillar region 22 with a lower concentration than the well region 20 is formed.

[0446] The semiconductor device 1 may include a p-type outer well region 45. The outer well region 45 may be formed in the second semiconductor layer 7 of the outer region 9. In this case, the field region 47 may be formed at a distance from the outer well region 45 to the peripheral side of the first main surface 3. According to this configuration, the electrical breakdown voltage of the peripheral portion of the active region 8 is improved by the depletion layer caused by the outer well region 45.

[0447] The outer well region 45 may be formed deeper than the gate structure 15. According to this configuration, the electrical breakdown voltage of the peripheral portion of the active region 8 is improved by the outer well region 45 deeper than the gate structure 15. Such a configuration is particularly effective when the second pillar region 22 deeper than the gate structure 15 is formed.

[0448] The outer well region 45 may be formed deeper than the gate structure 15. According to this configuration, the electrical breakdown voltage of the active region 8 is improved by the second pillar region 22 deeper than the gate structure 15, and the electrical breakdown voltage of the outer region 9 is improved by the outer well region 45 deeper than the gate structure 15.

[0449] The gate structure 15 may extend in the first direction X along the first main surface 3. In this case, the second pillar region 22 may extend in the second direction Y along the first main surface 3 so as to intersect the gate structure 15.

[0450] According to this configuration, the design rule limitation of the second pillar region 22 with respect to the gate structure 15 is relaxed. Thereby, the channel formation location is appropriately secured in the region outside the second pillar region 22, and at the same time, the breakdown voltage improvement effect by the second pillar region 22 is appropriately exerted.

[0451] The outer well region 45 may have a portion extending in the first direction X and a portion extending in the second direction Y. According to this configuration, according to this configuration, the electrical breakdown voltage of the outer region 9 is appropriately improved by the outer well region 45.

[0452] The outer well region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. With this configuration, the electric field at the edge portion of the outer well region 45 is appropriately mitigated.

[0453] The semiconductor device 1 may include an interlayer film 50. The interlayer film 50 may cover the first main surface 3 in an active region 8 and an outer region 9. In this case, the semiconductor device 1 may include a gate finger 65 as an example of a gate electrode. The gate finger 65 may contain a metal. The gate finger 65 may be positioned on the interlayer film 50 in the outer region 9 and electrically connected to the gate structure 15.

[0454] The gate finger 65 may be positioned at a distance from the field region 47 towards the active region 8. This configuration prevents the field region 47 from shielding the electric field dispersion path with the gate finger 65. As a result, the electric field (electric field lines) in the outer region 9 is appropriately dispersed by the field region 47.

[0455] The semiconductor device 1 may include gate wiring 55. The gate wiring 55 may include a non-metallic conductor. The gate wiring 55 may be located within the interlayer film 50 in the outer region 9 and electrically connected to the gate structure 15. The gate wiring 55 may be spaced apart from the field region 47 towards the active region 8.

[0456] This configuration prevents the field region 47 from being shielded by the gate wiring 55, thereby ensuring that the electric field (electric field lines) in the outer region 9 is properly dispersed by the field region 47. The gate finger 65 may also be electrically connected to the gate wiring 55 by penetrating the interlayer film 50.

[0457] The semiconductor device 1 may include a source finger 63 as an example of a source electrode. The source finger 63 may be positioned on the interlayer film 50 in the outer region 9 and electrically connected to regions other than the gate structure 15.

[0458] The source finger 63 may be positioned at a distance from the field region 47 towards the active region 8. This configuration suppresses the shielding of the electric field dispersion path by the field region 47 by the source finger 63.

[0459] As a result, the electric field (electric field lines) in the outer region 9 is appropriately dispersed by the field region 47. The source finger 63 may be positioned on the interlayer film 50 at a distance from the gate finger 65 towards the periphery of the first main surface 3 in the outer region 9.

[0460] (4) Modified examples of multiple well regions 20 Figures 22 and 23 show modified examples of the well region 20. Figure 22 shows a horizontal cross-sectional view corresponding to Figure 18, and Figure 23 shows a cross-sectional view corresponding to Figure 9.

[0461] Referring to Figures 22 and 23, the multiple well regions 20 are arranged at intervals along the first direction X below each gate structure 15 within the second semiconductor layer 7.

[0462] Multiple well regions 20 are formed in the regions below (specifically directly below) each gate structure 15, and overlap with the multiple gate structures 15 in a one-to-many correspondence in the thickness direction Z. The multiple well regions 20 are arranged with spacing in the first direction X, following the extending direction of the corresponding gate structure 15 in a plan view. Each well region 20 may be rectangular in shape in a plan view. The multiple well regions 20 mitigate the electric field for the multiple gate structures 15 from the bottom wall side.

[0463] Referring to Figure 22, the semiconductor device 1 includes a p-type second stripe region 87 formed within the second semiconductor layer 7 in a horizontal cross-sectional view. The second stripe region 87 extends in a strip shape in the second direction Y (a-axis direction) along the first main surface 3 at a thickness position spaced apart from the first main surface 3 within the second semiconductor layer 7.

[0464] The second stripe region 87 partitions multiple n-type first stripe regions 88, which serve as multiple current paths, within the second semiconductor layer 7. The second stripe region 87 narrows the current when the device is on and improves short-circuit withstand capability. The second stripe region 87 is formed in a region below the depth position of the bottom of the body region 10. The second stripe region 87 is formed in a region below the bottom walls of the multiple gate structures 15 (trenches 16).

[0465] The second stripe region 87 integrally includes a plurality of p-shaped well regions 20 arranged at intervals in the first direction X, and a plurality of p-shaped second pillar regions 22 extending in a band shape in the second direction Y.

[0466] Multiple well regions 20 are arranged in the second semiconductor layer 7 at intervals in the first direction X at thickness positions separated from the first main surface 3. Each of the multiple well regions 20 is formed in the region below (specifically directly below) each gate structure 15 and overlaps with each gate structure 15 in a one-to-many correspondence in the thickness direction Z. Each well region 20 overlaps with each second pillar region 22 in a one-to-one correspondence below each gate structure 15.

[0467] Below each gate structure 15, the spacing S1 between adjacent well regions 20 in the first direction X may be, for example, greater than 0 μm and 5 μm or less. The spacing S1 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0468] The multiple first stripe regions 88 extend in a direction (second direction Y) that intersects the extending direction of the gate structure 15, passing through the multiple well regions 20 in a plan view. The multiple first stripe regions 88 are partitioned in a line along the second direction Y, following the extending direction of the multiple second pillar regions 22 (multiple first pillar regions 21) in a plan view.

[0469] In this configuration, the multiple first stripe regions 88 are formed by multiple n-type first pillar regions 21 having an n-type impurity concentration higher than that of the second semiconductor layer 7, and extend in a vertically elongated columnar shape along the thickness direction Z. The multiple first stripe regions 88 form low-resistance current paths having a resistance value lower than that of the second semiconductor layer 7.

[0470] Figures 24 to 30 are cross-sectional views showing the first to seventh modified examples of the well region 20, respectively. Figures 24 to 30 are enlarged views showing the main parts of the cross-section shown in Figure 23. Below, a detailed explanation of the structure of the well region 20 will be given with reference to Figures 24 to 30.

[0471] Referring to Figure 24, the first pillar region 21 crosses the boundary 11 between the well region 20 and the second pillar region 22 (second lower region 22L) in the depth direction of the gate structure 15 and is connected to the bottom of the gate structure 15.

[0472] In this configuration, in the extending direction (first direction X) of the gate structure 15, the second pillar region 22 and the well region 20 form continuous surfaces without any steps between them. The surface 12 of the second pillar region 22 that is in contact with the first pillar region 21 in the first direction X, and the surface 13 of the well region 20 that is in contact with the first pillar region 21 in the first direction X, are flush in the depth direction of the gate structure 15. In this configuration, the integration of the surface 12 of the second pillar region 22 and the surface 13 of the well region 20 forms a flat surface of the p-type impurity region extending downward from the bottom of the gate structure 15.

[0473] In this embodiment, the width W11 of the second pillar region 22 in the first direction X is approximately equal to the width W12 of the well region 20 in the first direction X. The widths W11 and W12 may be, for example, greater than 0 μm and 3 μm or less. The widths W11 and W12 may have values ​​that fall within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or more and 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0474] Referring to Figure 25, in the first direction X, the width W11 of the second pillar region 22 may be wider than the width W12 of the well region 20. The second pillar region 22 includes a pillar projection 14 that protrudes outward from the side surface 13 of the well region 20 in the first direction X (away from the side surface 13 in the first direction X). As a result, a step 32 is formed between the side surface 12 of the second pillar region 22 and the side surface 13 of the well region 20, corresponding to the amount of protrusion of the pillar projection 14.

[0475] The pillar projection 14 covers the side surface 13 of the well region 20. As a result, a laminated structure is formed in which the first pillar region 21, the second pillar region 22 (pillar projection 14), and the well region 20 are aligned in order along the first direction X of the bottom of the gate structure 15. The laminated interface of this laminated structure crosses the bottom of the gate structure 15 in the second direction Y.

[0476] In this configuration, the second pillar region 22 includes a pair of pillar projections 14 that project from opposite sides 13 of the well region 20 in the first direction X. The well region 20 is sandwiched between the pair of pillar projections 14 in the first direction X. As a result, a p-type three-layer structure consisting of the well region 20 and the pair of pillar projections 14 (second pillar region 22) sandwiching the well region 20 is interposed between the multiple first pillar regions 21 in the first direction X.

[0477] Referring to Figure 26, the pillar projection 14 may selectively protrude from one of the two sides 13 of the well region 20 in the first direction X. On the opposite side of the pillar projection 14 in the first direction X, similar to Figure 24, the side 12 of the second pillar region 22 and the side 13 of the well region 20 may form a side surface that is continuous with each other without any steps.

[0478] Referring to FIG. 27, in the first direction X, the width W12 of the well region 20 may be wider than the width W11 of the second pillar region 22. The well region 20 includes a well protrusion 23 that protrudes outward (in a direction away from the side surface 12 in the first direction X) from the side surface 12 of the second pillar region 22 in the first direction X. As a result, a step 32 corresponding to the protrusion amount of the pillar protrusion 14 is formed between the side surface 12 of the second pillar region 22 and the side surface 13 of the well region 20.

[0479] The well protrusion 23 extends into the first pillar region 21 across the boundary 24 between the first pillar region 21 and the second pillar region 22 at the bottom of the gate structure 15 and covers the side surface 13 of the well region 20. As a result, a pillar recess 27 is formed in the first pillar region 21 where the portion adjacent to the well protrusion 23 in the first direction X is selectively recessed.

[0480] In this form, the well region 20 includes a pair of well protrusions 23 that protrude from both side surfaces 12 of the second pillar region 22 in the first direction X toward opposite sides. The portion of the first pillar region 21 sandwiched between the pair of well protrusions 23 is formed as a constricted portion 28.

[0481] Referring to FIG. 28, the well protrusion 23 may selectively protrude from one of the both side surfaces 12 of the second pillar region 22 in the first direction X. On the opposite side of the well protrusion 23 in the first direction X, similar to FIG. 24, the side surface 12 of the second pillar region 22 and the side surface 13 of the well region 20 may form continuous side surfaces without a step.

[0482] Referring to FIG. 29, the width W11 of the second pillar region 22 in the first direction X is substantially equal to the width W12 of the well region 20 in the first direction X. The difference from the form of FIG. 24 is that the well region 20 crosses the boundary 24 between the first pillar region 21 and the second pillar region 22 at the bottom of the gate structure 15.

[0483] The well region 20 integrally includes a first well portion 29 positioned on the first pillar region 21 side with respect to the boundary 24, and a second well portion 30 positioned on the second pillar region 22 side with respect to the boundary 24. The widths W13 of the first well portion 29 and W14 of the second well portion 30 in the first direction X are approximately equal to each other. The width W13 of the first well portion 29 may be wider or narrower than the width W14 of the second well portion 30.

[0484] Referring to Figure 30, the well region 20 includes a well bulge 31 that bulges outward from the side surface 12 of the second pillar region 22 in the first direction X (away from the side surface 12 in the first direction X). The well bulge 31 forms a side surface 13 that is seamlessly continuous with the side surface 12 of the second pillar region 22, but bulges outward in an arc shape from the side surface 12. For example, the side surface 13 of the well region 20 may bulge outward in an arc shape from the upper end of the side surface 12 of the second pillar region 22 and be connected to the bottom of the gate structure 15.

[0485] In the above configuration, the multiple well regions 20 may be arranged at intervals along the first direction X below each gate structure 15 within the second semiconductor layer 7. This configuration reduces the contact area between the well regions 20 and the first pillar regions 21 (second semiconductor layer 7). This narrows the depletion layer between the well regions 20 and the first pillar regions 21, thereby suppressing the increase in resistance of the first pillar regions 21 caused by the depletion layer.

[0486] In particular, when the n-type impurity concentration in the first pillar region 21 is lower than the p-type impurity concentration in the well region 20, the depletion layer expansion range becomes wider on the first pillar region 21 side compared to the well region 20 side. Therefore, by arranging multiple well regions 20 with gaps in between, the on-resistance reduction effect can be effectively obtained.

[0487] Furthermore, as shown in Figures 25 and 26, by covering at least one side surface 13 of the well region 20 with the second pillar region 22, the contact area between the well region 20 and the first pillar region 21 (second semiconductor layer 7) can be further reduced.

[0488] While embodiments of this disclosure have been described, this disclosure can also be implemented in other forms.

[0489] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. In this case, the specific configuration can be obtained by replacing n-type with p-type and simultaneously replacing p-type with n-type, as shown in the above description and attached drawings.

[0490] In the embodiments described above, an n-type first semiconductor layer 6 was shown. However, the conductivity type of the first semiconductor layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0491] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0492] [Note 1-1] A semiconductor layer (7) of a first conductivity type having a main surface (3); a body region (10) of a second conductivity type formed on the surface of the main surface (3); a trench-type gate structure (15) formed on the main surface (3) so as to penetrate the body region (10) and extending in a first direction (X) along the main surface (3); a first pillar region (21) of the first conductivity type extending in a second direction (Y) along the main surface (3) within the semiconductor layer (7) so as to intersect the gate structure (15); a second pillar region (22) of the second conductivity type adjacent to the first pillar region (21) in the first direction (X) and forming a pn junction with the first pillar region (21), A semiconductor device (1) comprising a plurality of contact regions (41) of a second conductivity type arranged at intervals along the first direction (X), each selectively positioned on the surface of the body region (10) in the region directly above the second pillar region (22) in the thickness direction (Z) of the semiconductor layer (7), and a contact region (41) of a second conductivity type facing the second pillar region (22) in the thickness direction (Z) of the semiconductor layer (7).

[0493] [Appendix 1-2] The semiconductor device (1) according to Appendix 1-1, further comprising a source region (40) of a first conductivity type, which is located away from the region directly above the second pillar region (22) in the thickness direction (Z) of the semiconductor layer (7), and which is located on the surface of the body region (10) and faces a region outside the second pillar region (22) in the thickness direction (Z) of the semiconductor layer (7).

[0494] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein the plurality of source regions (40) are a plurality of strips intersecting the gate structure (15) and are arranged at intervals along the first direction (X).

[0495] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein the plurality of contact regions (41) are a plurality of strips intersecting the gate structure (15) and are arranged alternately with the plurality of source regions (40) in a stripe pattern along the first direction (X).

[0496] [Appendix 1-5] The semiconductor device (1) according to any one of Appendix 1-2 to 1-4, wherein the second pillar region (22) includes a pillar side portion (96) that forms a boundary with the first pillar region (21) in the first direction (X), and the pillar side portion (96) includes a first side portion (93) located in the region directly below the boundary portion (77) between the contact region (41) and the source region (40) in the thickness direction (Z) of the semiconductor layer (7).

[0497] [Appendix 1-6] The semiconductor device (1) according to any one of Appendix 1-2 to 1-4, wherein the second pillar region (22) includes a pillar side portion (96) that forms a boundary with the first pillar region (21) in the first direction (X), and the pillar side portion (96) includes a second side portion (94) located in the region directly below the inner portion (98) of the source region (40) in the thickness direction (Z) of the semiconductor layer (7).

[0498] [Appendix 1-7] The semiconductor device (1) according to any one of Appendix 1-2 to 1-4, wherein the second pillar region (22) includes a base side portion (93) located in the region directly below the boundary portion (77) between the contact region (41) and the source region (40) in the thickness direction (Z) of the semiconductor layer (7), and a bulging side portion (94) that bulges out from the base side portion (93) along the first direction (X) and is located in the region directly below the inner portion (98) of the source region (40) in the thickness direction (Z) of the semiconductor layer (7).

[0499] [Appendix 1-8] The semiconductor device (1) according to any one of Appendix 1-2 to 1-7, wherein in the first direction (X), the width of the source region (40) is wider than the width of the contact region (41).

[0500] [Appendix 1-9] The semiconductor device (1) according to any one of Appendix 1-2 to 1-7, wherein in the first direction (X), the width of the source region (40) is narrower than the width of the contact region (41).

[0501] [Appendix 1-10] The semiconductor device (1) according to any one of Appendix 1-1 to 1-9, further comprising a second conductivity type well region (20) formed below the gate structure (15) within the semiconductor layer (7).

[0502] [Appendix 1-11] The semiconductor device (1) according to Appendix 1-10, wherein the well region (20) is formed in a strip shape extending in the first direction (X) following the gate structure (15) and is connected to the second pillar region (22).

[0503] [Appendix 1-12] The semiconductor device (1) according to Appendix 1-10, wherein the plurality of well regions (20) are arranged at intervals in the first direction (X) following the gate structure (15), and each is connected to the second pillar region (22).

[0504] [Appendix 1-13] The semiconductor device (1) according to any one of Appendix 1-10 to 1-12, wherein the second pillar region (22) has an impurity concentration lower than that of the well region (20).

[0505] [Appendix 1-14] The semiconductor device (1) according to any one of Appendix 1-10 to 1-12, wherein the well region (20) has a higher impurity concentration than the body region (10).

[0506] [Appendix 1-15] The semiconductor device (1) described in any one of the appendices 1-1 to 1-14, wherein the semiconductor layer (7) includes SiC.

[0507] [Appendix 1-16] The semiconductor device (1) according to Appendix 1-15, wherein the semiconductor layer (7) has an off-angle of 10° or less.

[0508] [Note 1-17] The off-direction of the off-angle is the a-axis direction of the SiC, as described in Note 1-16 (1).

[0509] [Appendix 1-18] The semiconductor device (1) described in Appendix 1-17, wherein the first direction (X) is the m-axis direction of the SiC, and the second direction (Y) is the a-axis direction of the SiC.

[0510] [Note 2-1] A semiconductor device (1) comprising: a semiconductor layer (7) of a first conductivity type having a main surface (3); a body region (10) of a second conductivity type formed on the surface of the main surface (3); a trench-type gate structure (15) formed on the main surface (3) so as to penetrate the body region (10) and extending in a first direction (X) along the main surface (3); a plurality of first pillar regions (21) and a plurality of second pillar regions (22) of the first conductivity type extending in a second direction (Y) along the main surface (3) within the semiconductor layer (7) so as to intersect the gate structure (15) and arranged alternately in stripes along the first direction (X); and a plurality of contact regions (41) of the second conductivity type that are in a stripe shape overlapping the plurality of second pillar regions (22) in the thickness direction (Z) of the semiconductor layer (7) and selectively arranged on the surface of the body region (10).

[0511] [Appendix 2-2] The semiconductor device (1) according to Appendix 2-1, comprising a plurality of source regions (40) of a first conductivity type, which are stripe-shaped and overlap the plurality of first pillar regions (21) in the thickness direction (Z) of the semiconductor layer (7), and which are selectively arranged on the surface layer of the body region (10).

[0512] [Note 2-3] The semiconductor device (1) according to Note 2-2, wherein the second pillar region (22) is located in the region directly below the boundary portion (77) between the contact region (41) and the source region (40), and has pillar side portions (93, 94, 95, 96) that extend in the thickness direction (Z) of the semiconductor layer (7).

[0513] [Note 2-4] The semiconductor device (1) according to Note 2-3, wherein the pillar side portion (93) extends along the extension line (78) of the boundary portion (77) that extends in the thickness direction (Z) of the semiconductor layer (7).

[0514] [Appendix 2-5] The semiconductor device (1) according to Appendix 2-3 or Appendix 2-4, wherein the second pillar region (22) selectively bulges out in the first direction (X) towards the region directly below the source region (40) rather than the region directly below the boundary portion (77), and includes a bulge (71) that overlaps with the source region (40) in the thickness direction (Z) of the semiconductor layer (7).

[0515] [Appendix 2-6] The semiconductor device (1) according to Appendix 2-5, wherein the first pillar region (21) selectively includes a constricted portion (68) that interlocks with the bulging portion (71) in an uneven manner.

[0516] [Note 2-7] The semiconductor device (1) according to Note 2-6, wherein the constricted portion (68) is sandwiched between the bulging portion (71) and the body region (10) in the thickness direction (Z) of the semiconductor layer (7).

[0517] [Note 2-8] The semiconductor device (1) according to Note 2-7, wherein the constricted portion (68) has an impurity concentration higher than that of the second semiconductor layer (7).

[0518] [Note 3-1] The semiconductor layer (7) comprises a first conductivity type having a main surface (3), a second conductivity type body region (10) formed on the surface of the main surface (3), a trench-type gate structure (15) formed on the main surface (3) so as to penetrate the body region (10) and extending in a first direction (X) along the main surface (3), a plurality of second conductivity type pillar regions (22) extending in a second direction (Y) along the main surface (3) within the semiconductor layer (7) so as to intersect the gate structure (15), and a plurality of second conductivity type contact regions (41) arranged in a stripe shape with spacing along the first direction (X) and electrically connected to the body region (10), wherein the pillar regions (22) include constricted portions (72) selectively narrowed in the first direction (X), A semiconductor device (1) wherein the width of each contact area (41) in the first direction (X) is narrower than the width of the constricted portion (72) in the same direction.

[0519] [Note 3-2] The semiconductor device (1) according to Note 3-1, wherein the end portion (99) of the contact region (41) in the first direction (X) is located inside the constricted portion (72) in the first direction (X).

[0520] 1...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor layer, 7...Second semiconductor layer, 8...Active region, 9...Outer region, 10...Body region, 11...Boundary, 12...Side surface, 13...Side surface, 14...Pillar projection, 15...Gate structure, 16...Trench, 17...Insulating film, 18...Buried electrode, 19...Buried insulator, 20...Well region, 21...First pillar region, 21B...First bottom, 21L...First lower region, 21U...First upper region, 22...Second pillar region, 22B...Second Bottom, 22L...Second lower region, 22U...Second upper region, 23...Well protrusion, 24...Boundary, 25...Mesh region, 26...Intermesh region, 27...Pillar recess, 28...Constriction, 29...First well portion, 30...Second well portion, 31...Well bulge, 32...Step, 40...Source region, 41...Contact region, 42...Cap region, 42A...First cap region, 42B...Second cap region, 45...Outer well region, 46...Outer contact region, 47...Field region, 50...Interlayer, 51...First interlayer, 52...Second interlayer, 55...Gate Line, 56...Source opening, 57...Source recess, 58...Gate opening, 59...Outer opening, 60...Source electrode, 60a...First pad portion, 60b...Second pad portion, 60c...Third pad portion, 61...Base electrode, 61a...First electrode, 61b...Second electrode, 62...Main electrode, 63...Source finger, 64...Gate electrode, 65...Gate finger, 66...Drain electrode, 67...First base portion, 68...First constriction portion, 69...First bulge portion, 70...Second base portion, 71...Second bulge portion, 72...Second constriction portion, 73...First side portion, 74...Second side portion, 75...Third side portion, 76...First pillar side, 77...Boundary, 78...Extension line, 80...Wafer, 81...First wafer main surface, 82...Second wafer main surface, 83...Wafer side, 84...Marker, 85...Device area, 86...Planned cutting line, 87...Second stripe area, 88...First stripe area, 90...Base insulating film, 91...First base electrode film, 92...Second base electrode film, 93...First side, 94...Second side, 95...Third side, 96...Second pillar side, 97...End, 98...Inner part, 99...End, 100...Inner part, 101...First stripe area, 102...Second stripe area

Claims

1. A semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a body region of a second conductivity type formed on the surface of the main surface; a trench-type gate structure formed on the main surface so as to penetrate the body region and extending in a first direction along the main surface; a first pillar region of the first conductivity type extending in a second direction along the main surface within the semiconductor layer so as to intersect the gate structure; a second pillar region of the second conductivity type adjacent to the first pillar region in the first direction and forming a pn junction with the first pillar region; and a plurality of contact regions of the second conductivity type arranged at intervals along the first direction, each selectively located on the surface of the body region in the region directly above the second pillar region in the thickness direction of the semiconductor layer, and facing the second pillar region in the thickness direction of the semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a source region of a first conductivity type, which is positioned away from the region directly above the second pillar region in the thickness direction of the semiconductor layer and faces a region outside the second pillar region in the thickness direction of the semiconductor layer on the surface of the body region.

3. The semiconductor device according to claim 2, wherein the plurality of source regions are a plurality of strips intersecting the gate structure and are arranged at intervals along the first direction.

4. The semiconductor device according to claim 2 or 3, wherein the plurality of contact regions are a plurality of strips intersecting the gate structure and are arranged alternately in a stripe pattern with the plurality of source regions along the first direction.

5. The semiconductor device according to any one of claims 2 to 4, wherein the second pillar region includes a pillar side portion that forms a boundary with the first pillar region in the first direction, and the pillar side portion includes a first side portion that is located in the region directly below the boundary between the contact region and the source region in the thickness direction of the semiconductor layer.

6. The semiconductor device according to any one of claims 2 to 4, wherein the second pillar region includes a pillar side portion that forms a boundary with the first pillar region in the first direction, and the pillar side portion includes a second side portion that is located in the region directly below the inner portion of the source region in the thickness direction of the semiconductor layer.

7. The semiconductor device according to any one of claims 2 to 4, wherein the second pillar region includes a base side portion located in the region directly below the boundary between the contact region and the source region in the thickness direction of the semiconductor layer, and a bulging side portion that bulges out from the base side portion along the first direction and is located in the region directly below the inner portion of the source region in the thickness direction of the semiconductor layer.

8. The semiconductor device according to any one of claims 2 to 7, wherein in the first direction, the width of the source region is wider than the width of the contact region.

9. The semiconductor device according to any one of claims 2 to 7, wherein in the first direction, the width of the source region is narrower than the width of the contact region.

10. The semiconductor device according to any one of claims 1 to 9, further comprising a second conductivity type well region formed below the gate structure within the semiconductor layer.

11. The semiconductor device according to claim 10, wherein the well region is formed in a strip shape extending in the first direction following the gate structure and is connected to the second pillar region.

12. The semiconductor device according to claim 10, wherein the plurality of well regions are arranged at intervals in the first direction following the gate structure, and each is connected to the second pillar region.

13. The semiconductor device according to any one of claims 10 to 12, wherein the second pillar region has an impurity concentration lower than the impurity concentration of the well region.

14. The semiconductor device according to any one of claims 10 to 12, wherein the well region has a higher impurity concentration than the body region.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor layer includes SiC.

16. The semiconductor device according to claim 15, wherein the semiconductor layer has an off-angle of 10° or less.

17. The semiconductor device according to claim 16, wherein the off-direction of the off-angle is the a-axis direction of the SiC.

18. The semiconductor device according to claim 17, wherein the first direction is the m-axis direction of the SiC, and the second direction is the a-axis direction of the SiC.

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