Product-sum operation device and product-sum operation method

Abstract

Provided are a product-sum operation device and a product-sum operation method with which it is possible to reduce error in the result of a product-sum operation. A plurality of memory cells 17 storing load values to be synaptic connection loads are arranged in a matrix in a synaptic operation unit 12. Output lines MAL1, MAL2, … are connected to the memory cells 17 in each column, and input lines DL1, DL2, … are connected to the memory cells 17 in each row. In the memory cells 17, the output lines MAL1, MAL2, ... are precharged, and each of the memory cells 17 conducts a cell current corresponding to synaptic coupling load, and thus the output lines MAL1, MAL2, ... are discharged and lose potential. The memory cells 17 are each constituted of a storage element in which a memory transistor, a drain-side transistor, and a source-side transistor are connected in series, and the memory cells 17 are connected between the input lines DL1, DL2, … and the output lines MAL1, MAL2, … The memory transistors each store a load value based on the amount of charge in a charge accumulation layer. The time during which the cell current flows is corrected according to the temperature of the memory transistors on the basis of a forward current flowing to a diode 16a provided in the synapse operation unit 12.

Description

Sum-of-accumulate device and sum-of-accumulate method

[0001] The present invention relates to a sum-of-products device and a sum-of-products method.

[0002] In recent years, neural networks that mimic the information processing patterns of the brain have been studied, and various models have been proposed. A common model for neurons that make up a neural network is one in which the input values ​​from multiple other neurons are weighted by their corresponding synaptic connection weights, and the sum of these weights is used as the input to the next neuron. In a neural network device based on such a model, the synaptic connection weights are stored in memory elements, and a sum-of-products operation is performed between each input value from other neurons and its corresponding synaptic connection weight.

[0003] A multiply-accumulate (MLI) unit is known that has a structure similar to a crosspoint memory array and performs the MILK operation described above. In this MILK unit, memory cells are placed at each intersection of multiple input lines and multiple output lines that intersect them, and memory cells are connected between the input lines and output lines at those intersections.

[0004] For example, the sum-of-accumulate (SUM) arithmetic unit proposed in Patent Document 1 is composed of a switching element with memory cells connected in series and a memory transistor. The memory transistor has a memory gate electrode and a charge storage layer, and stores an amount of charge in the charge storage layer corresponding to the synaptic coupling load. During SUM, a constant gate voltage is applied to the memory gate electrode of the memory transistor, and the switching element is turned on for a certain period of time by an input signal from the input line. When the switching element is turned on, the memory transistor flows a drain current as a cell current corresponding to the amount of charge in its charge storage layer, discharging the pre-charged output line and lowering its potential. Each memory cell connected to the output line flows a cell current corresponding to the amount of charge stored in its charge storage layer when an input signal is input, thereby obtaining the potential of the output line corresponding to the SUM result.

[0005] Japanese Patent Publication No. 2020-21376

[0006] Incidentally, operating a memory transistor in a subthreshold region, where its gate voltage is below the threshold voltage, is advantageous for reducing power consumption. In particular, as in Patent Document 1, the use of the subthreshold region is effective when performing multiply-accumulate operations by operating many memory cells simultaneously. However, the drain current of a memory transistor in the subthreshold region increases or decreases in response to temperature changes. Therefore, when using the subthreshold region when performing multiply-accumulate operations, the drain current, i.e., the cell current, increases or decreases significantly depending on the temperature of the memory transistor, resulting in a large error in the obtained multiply-accumulate operation result.

[0007] This invention has been made in view of the above circumstances, and aims to provide a sum-of-products calculation device and a sum-of-products calculation method that can reduce the error in the result of the sum-of-products calculation.

[0008] The sum-of-accumulate arithmetic device of the present invention comprises a memory transistor in which a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode are sequentially stacked on the surface of a semiconductor region, and the amount of charge stored in the charge storage layer is increased or decreased; a plurality of memory cells that flow a cell current corresponding to the amount of charge stored in the charge storage layer in response to an input signal; an output line to which the plurality of memory cells are connected and whose output line potential changes as the cell current flows; a potential detection unit that detects the output line potential as a calculation result; a temperature sensor that outputs a temperature signal corresponding to the temperature of the memory transistor; and a correction unit that corrects the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode based on the temperature signal until the potential detection unit detects the output line potential.

[0009] The present invention provides a sum-of-accumulate arithmetic device comprising: a memory unit having a memory transistor in which a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode are sequentially stacked on the surface of a semiconductor region, and the amount of charge stored in the charge storage layer is increased or decreased, and a plurality of memory cells arranged in a matrix that flow a cell current corresponding to the amount of charge stored in the charge storage layer in response to the input of an input signal; a plurality of input lines provided in each row, connecting the plurality of memory cells in the row, and inputting the pulse-like input signal in synchronization with the plurality of memory cells in the row; a plurality of output lines provided in each column, connecting the plurality of memory cells in the column, and whose output line potential changes according to the sum of the cell currents of the connected plurality of memory cells; a potential detection unit that detects the output line potential as a calculation result; and a temperature sensor that outputs a temperature signal corresponding to the temperature of the memory transistor, and a correction unit that corrects the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode based on the temperature signal until the potential detection unit detects the output line potential.

[0010] The sum-of-products calculation method of the present invention comprises: a calculation step in which a plurality of memory cells, including a memory transistor in which a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode are sequentially stacked on the surface of a semiconductor region, and the amount of charge stored in the charge storage layer is increased or decreased, changes the output line potential of the output line by flowing a cell current corresponding to the amount of charge stored in the charge storage layer in response to the input of an input signal; a correction step in which the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode is corrected based on a temperature signal corresponding to the temperature of the memory transistor output from a temperature sensor until the output line potential is detected; and an acquisition step in which the calculation result is obtained by detecting the output line potential.

[0011] According to the present invention, the effective length of the input signal or the gate voltage of the memory transistor that contributes to the change in the output line potential is corrected according to the temperature of the memory transistor, so that an output line potential as a sum-of-accumulate calculation result with small errors due to the temperature of the memory transistor can be obtained.

[0012] It is a block diagram showing an overview of a neural network device. It is a circuit diagram showing the configuration of a memory cell. It is a cross-sectional view showing the configuration of a memory element. It is a circuit diagram showing the configuration of a readout section. It is a graph showing the relationship between the gate voltage and drain current of a memory transistor with respect to a measured value and a predetermined calculation formula. It is an explanatory diagram showing the cell current with respect to a load value and the amount of discharge charge at an effective length of a corrected input signal. It is an explanatory diagram showing changes in the cell current flowing through a memory cell, the potential of an output line, and the effective length of an input signal with respect to a change in temperature. It is a timing chart showing potential changes in each part of a readout section when the rate of decrease in the potential of an output line is large. It is a timing chart showing potential changes in each part of a readout section when the rate of decrease in the potential of an output line is small. It is a circuit diagram showing an example of a memory cell composed of three independent transistors. It is a circuit diagram showing an example of a memory cell composed of a memory transistor and one transistor. It is a block diagram showing an example of correcting the gate voltage applied to a memory transistor.

[0013] In FIG. 1, a neural network device NS as a product-sum operation device includes a unit 10 and a unit 10A that is the next stage of this unit 10. The unit 10 includes an input section 11, a synaptic operation section 12, a neuron section 14, a writing section 15, a correction control section 16, and the like. The unit 10A has the same configuration as the unit 10. Further, the neural network device NS includes a control section (not shown) that comprehensively controls each part of the units 10 and 10A.

[0014] The synaptic operation section 12 as a memory section includes a plurality of memory cells 17 that store load values as synaptic coupling loads respectively. The neural network device NS obtains, in the synaptic operation section 12, the sum of values weighted by load values corresponding to a plurality of input values respectively, that is, a product-sum operation value, and acquires the product-sum operation value in the neuron section 14.

[0015] The sum-of-products operation value obtained by the neuron section 14 of the unit 10 is output to the input section 11A of the next-stage unit 10A. In this example, the neuron section 14 binarizes the sum-of-products operation value and outputs it to the input section 11A of the unit 10A. Note that, in this example, the neural network device NS has a configuration in which units are connected in two stages, but it may be connected in three or more stages. Also, the unit may be configured with only one stage.

[0016] Let m and n be integers of 1 or more respectively. In the synaptic operation section 12, memory cells 17 are arranged in a matrix of m rows × n columns (for example, 1024 rows × 1024 columns). The synaptic operation section 12 functions as a sum-of-products operation device that outputs a sum-of-products operation value for each column. Therefore, in this example, the synaptic operation section 12 outputs n sum-of-products operation values for a set of input values consisting of m.

[0017] Input lines DL1, DL2, ··· DLm are provided corresponding to each row in the synaptic operation section 12. Also, corresponding to each column, memory gate lines MGL1, MGL2, ··· MGLn, drain-side gate lines DGL1, DGL2, ··· DGLn, source-side gate lines SGL1, SGL2, ··· SGLn, and output lines MAL1, MAL2, ··· MALn are provided respectively.

[0018] In the following description, when the input lines DL1, DL2, ··· DLm are not particularly distinguished, they will be described generically as the input line DL. Similarly, when the memory gate lines MGL1, MGL2, ··· MGLn, drain-side gate lines DGL1, DGL2, ··· DGLn, source-side gate lines SGL1, SGL2, ··· SGLn, and output lines MAL1, MAL2, ··· MALn are not particularly distinguished, they will be described generically as the memory gate line MGL, drain-side gate line DGL, source-side gate line SGL, and output line MAL respectively. Note that, in this example, the source-side gate line SGL is the first control line, and the drain-side gate line DGL is the second control line.

[0019] Each input line DL extends in the row direction and is connected to each memory cell 17 in the corresponding row. The memory gate line MGL, drain-side gate line DGL, source-side gate line SGL, and output line MAL each extend in the column direction and are connected to each memory cell 17 in the corresponding column. In this way, the synaptic arithmetic unit 12 is arranged in a state where multiple input lines DL and multiple output lines MAL intersect, and memory cells 17 are provided at each intersection point of the input lines DL and output lines MAL, thus having a structure similar to a crosspoint type memory cell array.

[0020] The input unit 11 outputs the input signal as an input value to the input line DL, and inputs the input signal to the memory cell 17 via the input line DL. m input signals corresponding to one set of input values ​​are simultaneously output from the input unit 11 to each input line DL. The input signals are generated based on information processing, such as image processing.

[0021] The input signal is a pulse signal in which the potential of the input line DL changes in a pulse-like manner with a pulse width corresponding to the input value. In this example, the input value is binary ("1" and "0"), and the input unit 11 changes the potential of the input line DL with a predetermined pulse width when the input value is "1", and does not change the potential of the input line DL with a pulse width of "0" when the input value is "0". The potential of the input line DL is normally the power supply potential VDD, and corresponding to the input value "1", it is set to a potential V1 between the reference potential VSS (= 0V) and the power supply potential VDD. The input unit 11, together with the correction control unit 16, constitutes a correction unit CP, and outputs an input signal with a corrected pulse width based on the correction coefficient input from the correction control unit 16. In this example, the power supply potential VDD is 1.0V and the potential V1 is 0.4V. Note that instead of using a single continuous pulse signal, the input signal may be composed of multiple pulse signals.

[0022] The memory cell 17 stores the load value in a non-volatile manner. As shown in FIG. 2, the memory cell 17 includes a memory element 21 including a memory transistor MT. The memory element 21 controls the cell current flowing from the output line MAL to the input line DL in the memory cell 17 in response to a potential change in the input line DL due to an input signal. The memory element 21 allows a larger cell current to flow as the load value is larger. This cell current causes the amount of charge (hereinafter referred to as the discharge charge amount) flowing through one memory cell 17 by the input signal described later to correspond to the result of multiplying the input value by the load value.

[0023] In this example, 128 values, that is, load values W of different magnitudes ０ to load value W １２７ are stored in the memory cell 17. The load values W ０ , W １ , W ２ , ··· W １２７ increase in weight in this order. Note that the load value W<s ０ corresponds to a synaptic coupling load with a weight of "0", and the memory cell 17 storing this load value W ０ hardly allows a cell current to flow during the sum-of-products operation. Note that the load values to be stored are not limited to 128 values.

[0024] The cell current is the drain current flowing through the memory transistor MT of the memory element 21. In this example, during the sum-of-products operation, the memory transistor MT is operated in the subthreshold region (weak inversion region), and the minute drain current flowing in the subthreshold region becomes the cell current. Note that the subthreshold region in which the memory transistor MT is operated during the sum-of-products operation does not need to be strict, and may be a broad subthreshold region including an intermediate transition region between the strong inversion region. This is also the case in this example.

[0025] The magnitude of the cell current also varies depending on the temperature of the memory transistor MT. For example, the smallest cell current corresponding to the load value W<s １ is about 4 nA, and the cell current increases by about 4 nA each time the load value increases by one level (one value). In the load value W １２７ , a cell current of about 0.5 μA flows. Note that in the load value W０ Therefore, the drain current of the memory transistor MT is approximately 10 pA.

[0026] The output line MAL carries the sum of the cell currents of each memory cell 17 connected to it. As will be described later, in this example, a pre-charge method is employed in which the capacity of the output line MAL is pre-charged to a predetermined potential, and then the potential of the output line MAL (output line potential) generated when an input signal is input to the memory cell 17 is detected, and the potential of the output line MAL (or the amount of potential drop) is obtained as a sum-of-products calculation value.

[0027] A write unit 15 and a read unit 18 are provided for each column of the synaptic calculation unit 12. The read unit 18, which acts as a potential detection unit, is located within the neuron unit 14. The write unit 15 and the read unit 18 are connected to the memory gate line MGL, drain-side gate line DGL, source-side gate line SGL, and output line MAL of the corresponding column, respectively.

[0028] The neural network device NS has a program mode in which load values ​​are stored in each memory cell 17, and an operation mode in which the synaptic operation unit 12 performs multiply-accumulate operations. In program mode, the write unit 15 and the input unit 11 store load values ​​in the memory cells 17. In program mode, the write unit 15 controls the potentials of the memory gate line MGL, the drain-side gate line DGL, the source-side gate line SGL, and the output line MAL, and the input unit 11 controls the potential of the input line DL. The load values ​​used are calculated, for example, by an external computer.

[0029] In calculation mode, the sum-of-products calculation value is detected as the potential of the output line MAL, and a binary signal corresponding to the detected sum-of-products calculation value is output. This calculation mode consists of a standby period, a calculation period following the standby period, and a sense period following the calculation period, after which there is another standby period. The neural network device NS corrects the amount of discharge charge in the memory cell 17, i.e., the decrease in the potential of the output line MAL caused by the temperature difference of the memory transistor MT, by correcting the effective length (pulse width) of the input signal during the calculation period.

[0030] The effective length of the input signal is the length (time) of the input signal that contributes to the change in the potential of the output line MAL up to the detection timing when the potential of the output line MAL is detected. In this example, the potential of the output line MAL starts to decrease simultaneously with the input of the input signal, and the system transitions from the calculation period to the sense period simultaneously with the cessation of the input signal to detect the potential of the output line MAL. Therefore, in this example, the pulse width of the input signal is the effective length.

[0031] Furthermore, in a configuration where only a portion of the input signal pulse changes the potential of the output line MAL, the length of that portion is the effective length. Therefore, in a configuration where cell current flows with a certain time delay from the input of the input signal, the portion of the input signal that actually flows the cell current in response to the input signal is the effective length. Similarly, in a configuration where the potential of the output line MAL is detected while the input signal is being input, the portion of the input signal up to the detection is the effective length. Also, when the input signal is composed of multiple pulses, the sum of the pulse widths of each pulse that contributes to the detected change in the potential of the output line MAL is the effective length.

[0032] In this example, the potential of the output line MAL is started to decrease simultaneously with the start of the calculation period due to the input signal, and the system transitions from the calculation period to the sense period and detects the potential of the output line MAL simultaneously with the stop of the input signal. Therefore, the input timing of the input signal is the start of the calculation period, and the stop timing is the end of the calculation period, and the effective length of the input signal and the calculation period are the same length.

[0033] The read unit 18 precharges the output line MAL during the standby period before an input signal is input to the memory cell 17. During the calculation period when an input signal is input to the memory cell 17, the read unit 18 operates the memory element 21 to supply cell current to the memory cell 17, thereby lowering the potential of the output line MAL. The read unit 18 then detects the potential of the output line MAL at the beginning of the sense period (end of the calculation period) and outputs a binary signal.

[0034] The correction control unit 16 comprises a pn junction diode 16a and a correction calculation unit 16b. The diode 16a is provided in the synapse calculation unit 12 as a temperature sensor for measuring the temperature of the memory transistor MT. The correction calculation unit 16b detects the forward current, which is a temperature signal, flowing through the diode 16a when a constant forward voltage is applied to the diode 16a, and determines a correction coefficient to correct the pulse width of the input signal based on the detected forward current. As will be described later, the forward current flowing through the diode 16a has a temperature dependence similar to the drain current (cell current) of the memory transistor MT, so a correction coefficient to correct the length of the calculation period can be easily determined by detecting the forward current. The correction calculation unit 16b sends the correction coefficient to the input unit 11 and the clock generation unit 19.

[0035] The clock generation unit 19 sends a clock signal to the neuron unit 14. Based on this clock signal from the clock generation unit 19, each readout unit 18 of the neuron unit 14 operates. The clock generation unit 19 changes the timing of the clock signal based on the input correction coefficient.

[0036] In Figure 2, the memory element 21 provided in the memory cell 17 has an integrated structure in which a drain-side MOS transistor (hereinafter referred to as the drain-side transistor) DT, a memory transistor MT, and a source-side MOS transistor (hereinafter referred to as the source-side transistor) ST are connected in series. In the calculation mode, the memory cell 17 allows cell current to flow from the output line MAL through the source-side transistor ST, the memory transistor MT, and the drain-side transistor DT to the input line DL.

[0037] In this memory element 21, the memory gate electrode MG of the memory transistor MT is connected to the memory gate line MGL, the drain gate electrode DG of the drain transistor DT is connected to the drain gate line DGL, and the source gate electrode SG of the source transistor ST is connected to the source gate line SGL. In addition, the drain 25 of the memory element 21 is connected to the input line DL, and the source 26 is connected to the output line MAL. In this example, the source transistor ST is the first transistor, and the drain transistor DT is both a switching element and the second transistor.

[0038] The memory transistor MT has a charge storage layer 24. In program mode, charge is stored in the charge storage layer 24 of the memory transistor MT. By increasing or decreasing the amount of charge stored in the charge storage layer 24, the cell current, i.e., the drain current flowing through the memory transistor MT, is increased or decreased. The larger the load value, the less charge is stored in the charge storage layer 24 and the larger the cell current. In arithmetic mode, a constant potential V2 is applied to the memory gate electrode MG via the memory gate line MGL. In this example, the potential V2 is 0.4V.

[0039] During the calculation period, the combined MOS transistor, consisting of the drain transistor DT and the source transistor ST connected in series, is configured to operate in the saturation region under normal circumstances. More specifically, the potentials of each signal line are set such that the difference between the drain potential of the combined MOS transistor (potential of source 26) and the potential of the input line DL (equivalent to the source-drain voltage in a normal MOSFET) is greater than "the potential difference between the input line DL and the drain gate electrode DG (equivalent to the gate-source voltage in a normal MOSFET) - the threshold of the drain transistor DT". This stabilizes the cell current, meaning that the cell current flows at a constant magnitude according to the load value, regardless of the potential change of the output line MAL.

[0040] The operation of the synaptic calculation unit 12 can be in two cases: the normal case where the potential of the output line MAL is near the reference potential Vref of the binary determination criterion, and the case where the potential of the output line MAL drops significantly below the reference potential Vref. The latter occurs when there is a large bias in the input and many memory cells 17 in one row simultaneously supply a large cell current corresponding to a large load value. In such a case, the potential of the output line MAL may drop rapidly, and the composite MOS transistor may move into the non-saturated region during the calculation period. However, at this time, the potential of the output line MAL has already dropped sufficiently below the reference potential Vref by the time it moves into the non-saturated region, so even if the composite MOS transistor moves into the non-saturated region and the cell current changes, it does not affect the binarized result of the sum-of-products calculation and is therefore not a problem.

[0041] In this example, the threshold voltage of the composite MOS transistor is the same as that of the drain transistor DT, which is 0.4V. The threshold voltage of the source transistor ST is 0.2V.

[0042] As shown in the cross-sectional configuration in Figure 3, the memory element 21 is formed on a P-well PW formed on the semiconductor substrate 30. A memory transistor MT, a drain-side transistor DT, and a source-side transistor ST, all of which are N-type MOSFETs, are provided on the P-well PW.

[0043] The drain 25 and source 26 of the memory element 21 are both formed on the surface of the P-well PW as n-type semiconductor regions with a predetermined distance between them. A memory gate structure 33 is placed on the P-well PW between the drain 25 and the source 26, a drain-side gate structure 34 is placed between the memory gate structure 33 and the drain 25, and a source-side gate structure 35 is placed between the memory gate structure 33 and the source 26. Side wall spacers 36 made of insulating material are placed between the memory gate structure 33 and the drain-side gate structure 34, and between the memory gate structure 33 and the source-side gate structure 35.

[0044] The memory gate structure 33 constitutes the memory transistor MT. The drain-side gate structure 34 constitutes the drain-side transistor DT, and the source-side gate structure 35 constitutes the source-side transistor ST. The source-side gate structure 35 is the first gate structure, and the drain-side gate structure 34 is the second gate structure.

[0045] The memory gate structure 33 is constructed by stacking, in order from the P-well PW side, a lower memory gate insulating film 33a as a first gate insulating film, a charge storage layer 24, an upper memory gate insulating film 33b as a second gate insulating film, and a memory gate electrode MG. The charge storage layer 24 is made of, for example, silicon nitride (Si ３ N ４ ) and silicon oxynitride (SiON), alumina (Al ２ O ３ It is formed from ) etc.

[0046] The drain-side gate structure 34 has a drain-side gate insulating film 34a and a drain-side gate electrode DG stacked in order from the P-well PW side. The source-side gate structure 35 has a source-side gate insulating film 35a and a source-side gate electrode SG stacked in order from the P-well PW side. The memory gate electrode MG, drain-side gate electrode DG, and source-side gate electrode SG each extend in the column direction, and they themselves form the memory gate line MGL, drain-side gate line DGL, and source-side gate line SGL. In this example, the P-well PW is set to a reference potential VSS in program mode and to 0.4V in calculation mode.

[0047] Furthermore, drain 25 is both the drain of the memory element 21 and the drain of the drain-side transistor DT, and source 26 is both the source of the memory element 21 and the source of the source-side transistor ST. In addition, no regions that serve as the source or drain of transistors DT, MT, or ST are formed in the P-well PW between the drain-side transistor DT and the memory transistor MT, or between the source-side transistor ST and the memory transistor MT. There is no particular distinction between the drain 25 and source 26 of the memory element 21; they are mutually interchangeable.

[0048] The memory transistor MT described above is preferably of the so-called MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type, in which the memory gate structure 33 is a stacked structure from the semiconductor substrate 30 side, consisting of a silicon oxide film (lower memory gate insulating film 33a), a charge storage layer 24 made of a silicon nitride film or the like, a block insulating film such as a silicon oxide film (upper memory gate insulating film 33b), and a memory gate electrode MG.

[0049] The MONOS type is a preferred structure because it can easily reduce the threshold voltage difference between memory transistors MT and easily ensure the reproducibility of the threshold voltage according to the amount of charge in the charge storage layer 24. The MONOS type includes the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type, in which the gate electrode is formed of highly doped polysilicon, and the SONOS type is more preferable. This is because when a silicon nitride film or the like is used for the charge storage layer 24, charge can be stored discretely in the charge storage layer 24, and even if there are local defects in the tunnel insulating film, charge can be stored spatially uniformly. Due to this property, the difference in threshold voltage between memory transistors MT when charge is stored in the charge storage layer 24 under the same conditions is small, and their reproducibility is stable, so the load value can be accurately stored.

[0050] As shown in Figure 4 as an example, the reading unit 18 is composed of switch elements 41-43, a pre-charge transistor 44, a first sense amplifier unit SA1, a second sense amplifier unit SA2, and the like. The operation of this reading unit 18 is controlled by clock signals / CK1, CK2, / CK3, and CK4 supplied from the clock generation unit 19.

[0051] The clock signal CK1 is activated (low level) at the start of the calculation period, i.e., at the input timing of the input signal, and deactivated (high level) at the end of the calculation period (start of the sense period), i.e., at the stop timing of the input signal. This clock signal CK1 is inactive outside of the calculation period. The clock signal CK2 is activated (high level) only during the first half of the sense period, and deactivated (low level) during the rest of the period. This clock signal CK2 activates the first sense amplifier SA1 during the first half of the sense period to differentially amplify the potential of the output line MAL and the reference potential Vref and output it.

[0052] The clock signal CK3 is activated (low level) at the start of the calculation period and deactivated (high level) at the end of the first half of the sense period. This clock signal CK3 controls the connection between the first sense amplifier section SA1 and the second sense amplifier section SA2, and also differentially amplifies the output of the first sense amplifier section SA1 by the second sense amplifier section SA2 during the second half of the sense period. The clock signal CK4 is activated (high level) at the start of the calculation period and deactivated (low level) at the end of the sense period. During the standby period, the clock signal CK4 is inactive. This clock signal CK4 is used to control the pre-charge of the output line MAL and to control the timing of the latch of the input section 11A of the next stage unit 10A.

[0053] Switch elements 41 to 43 are composed of MOSFETs or the like and are controlled by the control unit. Switch elements 41 to 43 are turned on during the calculation mode. When switch element 41 is turned on, the memory gate line MGL is set to potential V2 and a constant potential V2 is applied to the memory gate electrode MG. When switch element 42 is turned on, the drain-side gate line DGL is set to the power supply potential VDD and this power supply potential VDD is applied to the drain-side gate electrode DG. Switch element 43 is connected between the output line MAL and the source-side gate line SGL, and when switch element 43 is turned on, the source-side gate line SGL and the output line MAL are electrically connected. When switch elements 41 to 43 are off, the source-side gate line SGL, the drain-side gate line DGL, and the memory gate line MGL are grounded or in a floating state.

[0054] It is preferable that the switch element 42 be controllable on / off for each column. That is, it is preferable to control the on / off state of the drain-side transistor DT for each column by independently controlling the potential of the drain-side gate line DGL. In this way, it becomes possible to activate only the columns that perform multiply-accumulate operations in the synaptic calculation unit 12, for example, only specific columns, only odd-numbered columns, only even-numbered columns, etc., thereby suppressing the flow of cell current to memory cells 17 that do not perform multiply-accumulate operations and saving power.

[0055] The transistor 44, which is a P-type MOSFET, controls the pre-charging of the output line MAL. Its source is the power supply potential VDD, and its drain is connected to the output line MAL. A clock signal CK4 is input to the gate of this transistor 44. As a result, the transistor 44 turns on during the standby period and pre-charges the output line MAL to the power supply potential VDD. The switch element 43 is turned on in the calculation mode and electrically connects the source-side gate line SGL and the output line MAL.

[0056] The first sense amplifier section SA1 is a non-latching differential current amplifier. This first sense amplifier section SA1 includes transistors 47a and 48a that act as load resistors, an input transistor 47b with an output line MAL connected to its gate, an input transistor 48b with a reference potential Vref input to its gate, and a drive control circuit 49 consisting of transistors 49a and 49b. Transistors 47a to 49a are P-type MOSFETs, and input transistors 47b to 49b are N-type MOSFETs.

[0057] Input transistors 47b and 48b perform differential amplification by comparing the potential of the output line MAL with the reference potential Vref. The reference potential Vref is the threshold value when binarizing the sum-of-products value. A clock signal / CK1 is input to the gates of transistors 47a and 48a. The drive control circuit 49 has the drains of transistors 49a and 49b connected to each other, forming an inverter logic. A clock signal CK2 is input to the gates of transistors 49a and 49b, respectively.

[0058] The first sense amplifier section SA1 is activated in the first half of the sense period when a high-level clock signal CK2 is input to the drive control circuit 49, and differentially amplifies the potential of the output line MAL and the reference potential Vref and outputs them to connection points S1n and S1p. During periods other than the first half of the sense period, the first sense amplifier section SA1 is not activated when a low-level clock signal CK2 is input to the drive control circuit 49.

[0059] During the calculation period when the first sense amplifier section SA1 is not activated, transistors 47a and 48a are turned on by an L-level clock signal / CK1, and the first sense amplifier section SA1 is precharged to the power supply potential VDD. During the sense period when it is activated, transistors 47a and 48a are turned off by an H-level clock signal / CK1, and the precharging is stopped.

[0060] The second sense amplifier section SA2 is connected to the first sense amplifier section SA1 via P-type MOSFET transistors 51a and 51b. Transistors 51a and 51b are controlled on / off by a clock signal / CK3, and simultaneously with the start of operation of the second sense amplifier section SA2, the connection between the first sense amplifier section SA1 and the second sense amplifier section SA2 is disconnected.

[0061] The second sense amplifier section SA2 is a latch-type sense amplifier and consists of a cross-coupled latch consisting of cross-coupled inverters 52 and 53, and a drive control circuit 54 that controls the operation of this cross-coupled latch. Inverter 52 consists of transistors 52a and 52b, and inverter 53 consists of transistors 53a and 53b. The drive control circuit 54 consists of transistors 54a and 54b. Transistors 52a to 54a are P-type MOSFETs, and transistors 52b to 54b are N-type MOSFETs.

[0062] In inverter 52, transistors 52a and 52b have their drains connected to each other, and the source of transistor 52a is at the power supply potential VDD. In inverter 53, transistors 53a and 53b are connected in the same way as in inverter 52. The gates of transistors 52a and 52b, which are inputs to inverter 52 and connected to each other, are connected to connection point S2p, where the drains of transistors 53a and 53b, which are outputs of inverter 53, are connected to each other. Also, the gates of transistors 53a and 53b, which are inputs to inverter 53 and connected to each other, are connected to connection point S2n, where the drains of transistors 52a and 52b, which are outputs of inverter 52, are connected to each other. Connection point S2n is connected to connection point S1n via transistor 51a, and connection point S2p is connected to connection point S1p via transistor 51b.

[0063] The drive control circuit 54 has transistors 54a and 54b that constitute an inverter logic. The connection is the same as that of the drive control circuit 49, except that a clock signal / CK3 is input to the gates of each transistor 54a and 54b. A common source for transistors 52b and 53b is connected to this drive control circuit 54.

[0064] The second sense amplifier unit SA2 is activated in the latter half of the sense period when a high-level clock signal / CK3 is input to the drive control circuit 54. The activated second sense amplifier unit SA2 amplifies the difference between the potential of connection point S1n input to connection point S2n and the potential of connection point S1p input to connection point S2p, thereby setting one of connection points S2n and S2p to a high level and the other to a low level. The potential of connection point S2p is output from unit 10.

[0065] The latch circuit 57 of the input section 11A of unit 10A latches and outputs the potential of the connection point S2p at the end of the sense period based on the clock signal CK4. The output of the latch circuit 57 is output to the input line DLA of unit 10A as an input signal to unit 10A via the inverter 58. The input signal to unit 10A is at an H level when the potential of the output line MAL at the end of the calculation period is lower than the reference potential Vref, and at an L level when the potential of the output line MAL is equal to or greater than the reference potential Vref. The inverter 58 sets the input line DLA to the power supply potential VDD when the input signal is at an H level, and to potential V1 when the input line DLA is at an L level.

[0066] The following describes how to write load values ​​in program mode. Writing load values ​​involves performing an erase process and a write process in sequence. The erase process is performed collaboratively by the writing unit 15 and the input unit 11.

[0067] In the erase process, with the potentials of all drain-side gate lines DGL, source-side gate line SGL, input line DL, and output line MAL, and the P-well PW set to 0V, an erase potential (e.g., -12V) is applied to each memory gate electrode MG via each memory gate line MGL. As a result, electrons are extracted from the charge storage layer 24 towards the P-well PW due to the potential difference between the memory gate electrode MG and the P-well PW, and the quantum tunneling effect, and holes are also injected.

[0068] In the write process following the erase process, the memory cell 17 is selected while the load value W ０ ~W １２７The following is written. In this writing process, the load value W is applied to all memory cells 17. ０ ~W １２７ Write one of the following:

[0069] For example, when the memory cell 17 in the xth row (x = 1, 2, ... m) and yth column (y = 1, 2, ... n) is to be written to, the potential of each drain-side gate line DGL is set to 1.0V, the potential of each source-side gate line SGL is set to 0V, the potential of each output line MAL is set to 1.2V, and the potential of the P-well PW is set to 0V. In addition, the potential of the input line DLx in the xth row of the memory cell 17 to be written to is set to 0V, and the potential of the input lines DL in each of the other rows is set to 1.2V. As a result, the drain-side transistor DT of the memory cell 17 in the xth row and yth column is turned ON.

[0070] In the above state, the memory gate line MGLy of the y-th column is programmed to a potential Vp corresponding to the load value for a predetermined time. ０ ~Vspi １２７ Choose one of the following. Also, set the potential of each memory gate line MGL other than the y-th column to 0V.

[0071] Program Potential Vp ０ ~Vspi １２７ The larger the load value, the lower the potential. For example, load value W ０ The corresponding program potential Vp ０ The voltage is 12V, and the load value is W. １２７ The corresponding program potential Vp １２７ The voltage is 6.5V.

[0072] In the memory transistor MT within the memory cell 17 at row x, column y, the potential difference between its memory gate electrode MG and the P-well PW causes a number of electrons (charges) corresponding to that potential difference to be injected into the charge storage layer 24. As a result, the smaller the load value, the greater the number of electrons stored in the charge storage layer 24, and the higher the threshold voltage of the memory transistor MT.

[0073] On the other hand, in the memory cell 17 that is not to be written to, within the same y-th column as the memory cell 17 to be written to, applying the potential as described above causes the drain transistor DT and the source transistor ST to turn off. In this state, when the program potential is applied to the memory gate electrode MG, a depletion layer is formed inside the P-well PW below the memory gate structure 33, and the capacitive coupling between this depletion layer and the memory gate structure 33 causes the potential on the surface of the P-well PW below the memory gate structure 33 to rise, reducing the voltage difference between the memory gate electrode MG and the P-well PW. As a result, electrons are not injected into the charge storage layer 24.

[0074] Furthermore, in memory cells 17 other than the y-th column, the potential of the memory gate electrode MG is 0V, and the potential of the P-well PW is also 0V, so the potential difference between the memory gate electrode MG and the P-well PW is 0V or nearly 0V. For this reason, electron injection into the charge storage layer 24 due to the quantum tunneling effect does not occur.

[0075] As described above, the amount of charge in the charge storage layer 24 of the memory cell 17 at the xth row and yth column that is to be written is set to an amount corresponding to the load value. It is recommended to perform verification and trimming so that the target cell current corresponding to each load value flows.

[0076] When performing the writing process as described above, the load value W ０ The write stress is quite high and the disturbance is significant. That is, the load value W １ ~W １２７ After writing, load value W ０ When you write the value, the load value W １ ~W １２７ The charge amount of the memory cell 17 may fluctuate, causing the cell current to deviate from the desired value. Therefore, the load value W is initially... ０ The memory cell 17 is written to, and then the load value W １ ~W １２７ It is preferable to write to the memory cell 17.

[0077] In this example, the amount of charge in the charge storage layer 24 is changed by varying the magnitude of the potential difference between the memory gate electrode MG and the P-well PW. However, the amount of charge may also be changed by increasing or decreasing the application time while using the same potential difference.

[0078] As described above, the neural network device NS corrects the amount of discharge charge in the memory cell 17 caused by temperature differences in the memory transistor MT by correcting the pulse width (effective length) of the input signal using a correction coefficient from the correction control unit 16. During this correction, the forward voltage V in the pn junction diode 16a, which acts as a temperature sensor, is corrected. Ｆ , forward current I Ｆ The relationship between and temperature T (K) is expressed as shown in equation (1).

[0079]

[0080] In the above formula (1), "I Ｓ " is the reverse saturation current (A) of diode 16a, "k" is the Boltzmann constant, and "q" is the electron charge (C). Also, "n" is the coupling coefficient of diode 16a, and for an ideal diode, n=1. "A" is the area parameter of diode 16a, and "Eg" is the energy gap of silicon at temperature T (K). ０ " is the energy gap at 0K (absolute zero), and "α" and "β" are adjustment coefficients based on actual measurements.

[0081] Forward voltage V in equation (1) Ｆ As shown in equation (2), the gate voltage V applied to the memory gate electrode MG of the memory transistor MT is ＭＧ And given with a correction value B corresponding to the dose amount of the channel, and A, Eg in equation (1) ０ By using values ​​corresponding to the memory transistor MT for α and β, the forward current I shown in equation (1) above can be expressed. ＦThis can be considered as the drain current in the subthreshold region of the memory transistor MT (hereinafter referred to as the subthreshold current). This has been confirmed by the measured results shown in Figure 5. The graph in Figure 5 shows the relationship between the gate voltage and drain current of the memory transistor MT measured at three different temperatures (27°C, -40°C, and 125°C). The straight lines in the figure show the relationship between the gate voltage and drain current obtained by equation (1) by applying equation (2) at the three different temperatures. Note that in equation (1) by applying equation (2), the same values ​​are used for all values ​​except temperature.

[0082]

[0083] From the above, it can be seen that the subthreshold current of the memory transistor MT and the forward current of the diode 16a exhibit the same temperature dependence, differing only in the ratio (slope) of the increase in current (subthreshold current, forward current) to the increase in applied voltage (gate voltage, forward voltage). In other words, the subthreshold current corresponding to a specific load value is equal to the forward voltage V determined in relation to that load value. Ｆ When the forward current I is applied to diode 16a Ｆ This means that it will be proportional to [something].

[0084] Therefore, when a subthreshold current (cell current) corresponding to a specific load value flows at any given temperature, the forward voltage V Ｆ The forward current I flowing through diode 16a to which the current is applied Ｆ By using the reciprocal of (or its integral value) as a correction coefficient and multiplying it by the pulse width of the original input signal, a corrected pulse width of the input signal can be obtained that keeps the discharge charge amount of the memory cell 17 constant regardless of temperature. The same applies to the length of the calculation period.

[0085] In this example, the maximum load value W １２７A correction coefficient is determined using a specific load value. Therefore, as shown in Figure 6(A), even if the load value is the same, the cell current (Imc) flowing through the memory transistor MT fluctuates depending on the temperature. However, as shown in Figure 6(B), the discharge charge amount (Imc * Tp) due to the pulse width of the input signal of the corrected length (Tp) is less affected by temperature fluctuations, and the maximum load value W is achieved. １２７ These are unaffected by temperature. Figure 6 schematically shows three types of temperatures: HT (high temperature), RT (room temperature), and LT (low temperature).

[0086] As described above, the maximum load value W １２７ Correcting the temperature-dependent variation in the discharge charge to be minimized ("0") is advantageous in terms of ensuring accuracy in actual sum-of-products calculations.

[0087] Figure 7 shows a specific load value W. １２７ When a configuration is set in which only one memory cell 17 that stores the data is connected to the output line MAL, the relationship between the cell current flowing through the memory cell 17, the potential of the output line MAL, and the pulse width of the input signal is schematically shown for three different temperatures (HT, RT, LT) of the memory transistor MT.

[0088] As shown in Figure 7(A), when the memory transistor MT is at temperature RT (room temperature), the cell current I ＲＴ The current flows, and by the end of the calculation period (time T2), the output line MAL reaches potential V due to the input signal. Ｗ１２７ It decreases to this level. On the other hand, when the memory transistor MT is at a high temperature (HT), the cell current I is larger than at room temperature, as shown in Figure 7(B). ＨＴ A large cell current I flows through it. ＨＴ Accordingly, the input signal with a corrected pulse width (Tp) shorter than that for the temperature RT causes the output line MAL to reach potential V by the end of the calculation period (time T2). Ｗ１２７ It decreases to this level. Also, when the memory transistor MT is at temperature LT (low temperature), the cell current I is smaller compared to room temperature, as shown in Figure 7(C). ＬＴ A current flows, and that small cell current I ＬＴThe input signal, with a pulse width corrected to be longer than the temperature RT, causes the output line MAL to reach potential V by the end of the calculation period. Ｗ１２７ It drops to a certain level. In all temperature cases, at the end of the calculation period, the output line MAL is at potential V Ｗ１２７ It will become.

[0089] Next, the operation of the above configuration will be explained. When using the neural network device NS, the weight values ​​are stored in each memory cell 17 in advance.

[0090] As shown in Figures 8 and 9, during the waiting period before time T1 when the input signal is output from the input unit 11, the input line DL is at a high level. Also, since the switch elements 41 and 42 are on, the memory gate line MGL is at potential V2, and the drain-side gate line DGL is at the power supply potential VDD. Furthermore, the clock signals / CK1 and / CK3 are at a high level, and the clock signals CK2 and CK4 are at a low level.

[0091] The low-level clock signal CK4 turns on transistor 44, so the output line MAL is at the power supply potential VDD. In other words, when the clock signal CK4 becomes low, transistor 44 turns on, and the output line MAL is precharged to the power supply potential VDD, and maintains that state. The source-side gate line SGL is connected to the output line MAL by the switching element 43 turning on, and therefore, like the output line MAL, is precharged to the power supply potential VDD.

[0092] In each memory cell 17 memory element 21, the drain gate electrode DG is at the same potential as the drain gate line DGL, the drain 25 is at the same potential as the input line DL, the source gate electrode SG is at the same potential as the source gate line SGL and the output line MAL, and the source 26 is at the same potential as the output line MAL. During this standby period, the drain transistor DT and the source transistor ST are both off, and no cell current flows.

[0093] At time T1, the input signals output from the input unit 11 are input to each memory cell 17 connected to the input line DL via the input line DL. Immediately before this, a constant forward voltage is applied to the diode 16a by the correction calculation unit 16b, and the forward current flowing through the diode 16a at this time is detected. A correction coefficient is then determined based on this detected forward current, and the determined correction coefficient is sent to the input unit 11 and the clock generation unit 19. At time T1, the input unit 11 outputs an input signal with a corrected pulse width obtained by multiplying the original pulse width by the correction coefficient. In addition, the clock generation unit 19 corrects the timing of the clock signal generation using the correction coefficient from the correction calculation unit 16b.

[0094] When the input value of the input signal is "1", the potential of the input line DL drops in a pulsed manner from the power supply potential VDD to potential V1. On the other hand, when the input value is "0", the potential of the input line DL is maintained at the power supply potential VDD. At this time T1, the clock signal CK4 turns to a high level and transistor 44 turns off. As a result, the potential of the pre-charged output line MAL decreases due to the cell current flowing through the memory cell 17 connected to it.

[0095] Now, focusing on one memory cell 17, for example, if the input value is "1", that is, if the connected input line DL is set to potential V1, the drain 25 of the memory element 21 within that memory cell 17 will be at potential V1. As a result, the drain-side transistor DT and the source-side transistor ST will turn on. The charge storage layer 24 of the memory transistor MT will have a load value W １ ~W １２７ When a corresponding amount of charge is stored, cell current flows from the output line MAL to the input line DL via the source transistor ST, memory transistor MT, and drain transistor DT.

[0096] A constant potential V2 is supplied to the memory gate electrode MG of the memory transistor MT from the memory gate line MGL. The magnitude of the cell current flowing through the memory cell 17 is such that the smaller the amount of charge stored in the charge storage layer 24, that is, the larger the load value, the larger the cell current that flows through the memory cell 17.

[0097] Furthermore, the charge storage layer 24 of the memory transistor MT has a load value W. ０ When the corresponding amount of charge is stored, no cell current flows to the memory cell 17. Also, if the input value is "0", no cell current flows to the memory cell 17.

[0098] As cell current flows through the memory cell 17, the potential of the output line MAL to which this memory cell 17 is connected decreases from the power supply potential VDD. Of course, the potential of the output line MAL also decreases when other memory cells 17 connected to it flow cell current.

[0099] In this way, each memory cell 17 flows a cell current of a magnitude corresponding to the result of multiplying the load value it stores by the input value being input. Each output line MAL is then discharged with a current of a magnitude corresponding to the sum of the cell currents of each memory cell 17 connected to it, i.e., the sum-of-products calculation value. Since transistor 44 is off, the output line MAL is discharged with a current corresponding to the sum-of-products calculation value of the corresponding column, and its potential gradually decreases from the power supply potential VDD at a rate corresponding to the magnitude of that current.

[0100] At time T2, the input unit 11 sets each input line DL to the power supply potential VDD and stops the input signal, so the discharge of the output line MAL by each memory cell 17 stops. As a result, the decrease in the potential of the output line MAL stops and the calculation period ends. From the start of input signal input at time T1 until it stops at time T2, the pulse width of the input signal is corrected by the correction coefficient as described above, and its length is corresponding to the temperature of the memory transistor MT.

[0101] As described above, the cell current flowing through the memory cell 17 during the calculation period fluctuates depending on the temperature of the memory transistor MT, even if the amount of charge stored in the charge storage layer 24 is the same. However, since the pulse width of the input signal is corrected by the correction coefficient of the correction control unit 16, the amount of discharged charge in each memory cell 17 at the end of the calculation period has a small error from the expected amount of discharged charge. As a result, the potential of the output line MAL is the sum-of-products calculation value with reduced temperature influence.

[0102] At time T2, changes in the clock signals CK1 and CK2 cause transistors 47a and 48a to turn off, and transistor 49b to turn on. As a result, the first sense amplifier SA1 activates simultaneously with the end of the calculation period, initiating the sense period. Consequently, the potential at connection point S1n gradually decreases at a rate corresponding to the potential of the output line MAL immediately after the start of the sense period, and the potential at connection point S1p gradually decreases at a rate corresponding to the reference potential Vref.

[0103] Then, the potentials at connection points S2n and S2p decrease as the potentials at connection points S1n and S1p decrease. Here, since the output line MAL is connected to connection point S1n, the lower the potential of the output line MAL, the smaller the rate of decrease in the potential of connection point S1n. When the potential of the output line MAL is lower than the reference potential Vref, the rate of decrease in the potential of connection point S1n is smaller than that of connection point S1p, and when the potential of the output line MAL is higher than the reference potential Vref, the rate of decrease in the potential of connection point S1n is larger than that of connection point S1p.

[0104] Therefore, as shown in Figure 8, if the potential of the output line MAL immediately after the start of the sense period is lower than the reference potential Vref, the potential of connection point S1n will be higher than the potential of connection point S1p. On the other hand, as shown in Figure 9, if the potential of the output line MAL immediately after the start of the sense period is higher than the reference potential Vref, the potential of connection point S1n will be lower than the potential of connection point S1p.

[0105] When a predetermined time has elapsed from time T2 and it is time T3, which marks the second half of the sensing period, the clock signal / CK3 becomes high. As a result, transistor 54a turns off and transistor 54b turns on, causing the second sense amplifier unit SA2 to start operating, and transistors 51a and 51b turn off, disconnecting the connections between connection point S1n and connection point S2n, and between connection point S1p and connection point S2p, respectively. Simultaneously with the clock signal / CK3 becoming high, the clock signal CK2 turns low, causing transistor 49a to turn on and transistor 49b to turn off, and the first sense amplifier unit SA1 stops.

[0106] When the second sense amplifier section SA2 starts operating, the potential difference between connection point S2n and connection point S2p is amplified, causing one of connection points S2n or S2p to reach a high level and the other to reach a low level. Then, at time T4, after one of connection points S2n or S2p has reached a high level and the other a low level, the clock signal CK4 turns to a low level, ending the sense period and returning to the standby period.

[0107] As described above, when the clock signal CK4 switches to a low level, the potential of the connection point S2p at that time is latched by the latch circuit 57 of the input section 11A of the next stage unit 10A. Then, the input signal based on the latched signal is output from the inverter 58 to the input line DLA in the unit 10A.

[0108] As shown in Figure 8, when the potential of the output line MAL is lower than the reference potential Vref, the connection point S2p becomes L level, and the inverter 58 outputs a value of "0" (power supply potential VDD) as a binarized sum-of-products calculation value to the next stage's input line DLA. Also, as shown in Figure 9, when the potential of the output line MAL is higher than the reference potential Vref, the connection point S2p becomes H level, and the inverter 58 outputs a value of "1" (potential V1) as a binarized sum-of-products calculation value to the next stage's input line DLA.

[0109] As described above, the synaptic calculation unit 12 outputs an input signal to the next stage input unit 11A. This input signal is obtained by the synaptic calculation unit 12 correcting the pulse width of the input signal from the input unit 11 based on the temperature of the memory transistor MT, thereby reducing the error of the sum-of-products calculation value, and binarizing it. Thus, the influence of temperature is suppressed.

[0110] In the example above, a memory element comprising a memory transistor, a first transistor, and a second transistor is used as the memory element constituting the memory cell. However, the configuration is not limited to memory cells that use memory transistors and whose cell current is controlled by the memory transistors.

[0111] For example, as shown in Figure 10, the memory cell 17 may be configured in a series circuit in which memory transistors 61, 62, and 63, which are independent elements, are connected in series. The memory transistor 61 has a memory gate structure formed on a semiconductor layer, similar to a memory element, which includes a memory gate electrode 61a and a charge storage layer 61b, and in program mode, it stores an amount of charge in the charge storage layer 61b according to the load value. The source of transistor 62 is connected to the drain of memory transistor 61, and the drain of transistor 63 is connected to the source of memory transistor 61. These memory transistors 61, 62, and 63 correspond to the memory transistor MT, drain-side transistor DT, and source-side transistor ST, respectively. Note that the transistor 63 and source-side gate line SGL may be omitted, and the memory cell 17 may be configured with memory transistors 61 and 62 connected in series, as shown in Figure 11. A diode can also be used instead of transistor 62.

[0112] In the example above, the input values ​​are binary, but the input values ​​can also be analog or multi-level. In this case, the pulse width that constitutes the effective input signal can be increased or decreased according to the magnitude of the analog or multi-level input values, and the pulse width can be further corrected according to the temperature of the memory transistor. Alternatively, instead of changing the pulse width according to the input value, the number of pulse signals used as the input signal can be changed. In this case, the pulse width or the number of pulse signals of each individual pulse signal can be corrected according to the temperature of the memory transistor. The output of the readout section can also be multi-level. In this case, for example, the potential of the output line MAL can be compared with several different reference potentials.

[0113] In the above example, the effective length of the input signal is corrected according to the temperature of the memory transistor MT. However, as shown in the example in Figure 12, the error in the sum-of-accumulate calculation can also be reduced by correcting the gate voltage of the memory transistor MT according to the temperature of the memory transistor MT. The correction unit CP in this example includes a diode 16a, a correction control unit 16 including a correction calculation unit 16b, and a voltage correction unit 16c. The correction calculation unit 16b detects the forward current flowing through the diode 16a to which a constant forward voltage is applied, similar to the above example, and determines a correction coefficient to correct the gate voltage based on this forward current. The voltage correction unit 16c increases or decreases the gate voltage applied to the memory gate electrode MG of the memory transistor MT based on the obtained correction coefficient, correcting it so that the actual cell current flowing approaches the magnitude of the intended cell current corresponding to the load value. Specifically, the higher the temperature of the memory transistor MT, the lower the gate voltage applied to the memory gate electrode MG is corrected.

[0114] Furthermore, although the above example describes an example using a diode as a temperature sensor, the temperature sensor is not particularly limited as long as it can provide a temperature signal corresponding to the temperature. For example, a polysilicon resistor or a metal film can be used as a temperature sensor. For example, when a polysilicon resistor is used as a temperature sensor, the current flowing through the polysilicon resistor when a constant voltage is applied, or the voltage drop across the polysilicon resistor when a constant current is flowing, can be used as the temperature signal. Alternatively, a conversion table may be prepared in the correction unit that associates the temperature signal for each temperature with the pulse width of the input signal or the base voltage of the memory transistor. This conversion table can be used to identify the pulse width of the input signal or the base voltage of the memory transistor corresponding to the temperature signal obtained from the temperature sensor, and the system may be controlled so that the pulse width of the input signal or the base voltage of the memory transistor becomes the identified value.

[0115] 11 Input unit 10 Unit 12 Synaptic calculation unit 16 Correction control unit 16a Diode 16b Correction calculation unit 17 Memory cell 18 Read unit 19 Clock generation unit 21 Memory element 24 Charge storage layer MT Memory transistor NS Neural network device

Claims

1. A sum-of-accumulate arithmetic device characterized by having a memory transistor in which a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode are sequentially stacked on the surface of a semiconductor region, and the amount of charge stored in the charge storage layer is increased or decreased, and a plurality of memory cells that flow a cell current corresponding to the amount of charge stored in the charge storage layer in response to an input signal, an output line to which the plurality of memory cells are connected and whose output line potential changes as the cell current flows, a potential detection unit that detects the output line potential as a calculation result, and a temperature sensor that outputs a temperature signal corresponding to the temperature of the memory transistor, and a correction unit that corrects the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode based on the temperature signal until the potential detection unit detects the output line potential.

2. A memory unit comprising: a memory transistor having a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode stacked in order on the surface of a semiconductor region, wherein the amount of charge stored in the charge storage layer is increased or decreased, and a plurality of memory cells arranged in a matrix that flow a cell current corresponding to the amount of charge stored in the charge storage layer in response to the input of an input signal; a plurality of input lines provided in each row, connecting the plurality of memory cells in the row, and inputting the pulse-like input signal in synchronization with the plurality of memory cells in the row; a plurality of output lines provided in each column, connecting the plurality of memory cells in the column, and whose output line potential changes according to the sum of the cell currents of the connected plurality of memory cells; a potential detection unit that detects the output line potential as a calculation result; and a temperature sensor that outputs a temperature signal corresponding to the temperature of the memory transistor, and a correction unit that corrects the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode based on the temperature signal until the potential detection unit detects the output line potential.

3. The sum-of-accumulate device according to claim 1 or 2, wherein the temperature sensor is a diode, and the correction unit corrects the effective length of the input signal or the gate voltage based on the forward current that flows when a constant forward voltage is applied to the diode.

4. The sum-of-accumulate device according to claim 1 or 2, characterized in that the memory transistor operates in the subthreshold region.

5. A sum-of-products calculation method characterized by comprising: a calculation step in which a plurality of memory cells, including a memory transistor in which a first gate insulating film, a charge storage layer, a second gate insulating film, and a memory gate electrode are sequentially stacked on the surface of a semiconductor region, and the amount of charge stored in the charge storage layer is increased or decreased, changes the output line potential of the output line by flowing a cell current corresponding to the amount of charge stored in the charge storage layer in response to the input of an input signal; a correction step in which the effective length of the input signal that contributes to the change in the output line potential or the gate voltage applied to the memory gate electrode is corrected based on a temperature signal corresponding to the temperature of the memory transistor output from a temperature sensor until the output line potential is detected; and an acquisition step in which the calculation result is obtained by detecting the output line potential.

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