Vapor deposition mask and method for manufacturing electronic device

Abstract

The purpose of the present invention is to provide a vapor deposition mask wherein the occurrence of cracking can be suppressed and the mask surface loss rate can be reduced, and a method for manufacturing an electronic device using said vapor deposition mask. [Solution] A vapor deposition mask according to the present invention is for vapor-depositing a vapor deposition material from a vapor deposition source onto a surface of a vapor deposition-receiving substrate via openings, and is characterized by having: a membrane that has a first surface facing the vapor deposition-receiving substrate side, and a second surface located on the opposite side from the first surface and facing the vapor deposition source side, and has a plurality of openings penetrating between the first surface and the second surface; and a support substrate that supports the membrane, wherein at least one of the membrane and the support substrate has a Si polycrystalline structure.

Description

Method for manufacturing vapor deposition masks and electronic devices

[0001] This disclosure relates to a vapor deposition mask and a method for manufacturing an electronic device.

[0002] For example, vapor deposition masks are known to be used for separating the RGB three colors in the fabrication of organic EL displays.

[0003] Patent Document 1 discloses an invention relating to a vapor deposition mask having a first region and a second region surrounding the first region, wherein the first region has a first substrate with a plurality of openings formed therein and a second substrate.

[0004] Japanese Patent Publication No. 2022-175925

[0005] In the invention described in Patent Document 1, the first and second substrates are formed of single-crystal Si, which has the problem that cracks tend to occur in the cleavage direction.

[0006] This disclosure aims to provide a vapor deposition mask that can suppress the occurrence of cracks and reduce the mask surface loss rate, and a method for manufacturing an electronic device using the vapor deposition mask.

[0007] The deposition mask of the present disclosure is a deposition mask for depositing a deposition material from a deposition source onto the surface of a substrate to be deposited through an opening, and comprises a membrane having a first surface facing the substrate to be deposited and a second surface located on the opposite side of the first surface and facing the deposition source, with a plurality of openings penetrating between the first surface and the second surface, and a support substrate supporting the membrane, wherein at least one of the membrane or the support substrate has a polycrystalline structure of Si.

[0008] According to this disclosure, by having at least one of the membrane or the support substrate have a polycrystalline structure of Si, a clear cleavage direction is eliminated, and the occurrence of cracks can be suppressed. Note that "crack" includes not only fissures but also chipping and fractures.

[0009] This is a plan view showing the deposition mask of this embodiment. This is a cross-sectional view showing a cut section of the deposition mask of this embodiment shown in Figure 1. This is a partially enlarged plan view showing an enlarged view of multiple cell regions of the deposition mask. This is a partially enlarged cross-sectional view showing an enlarged view of a part of the deposition mask shown in Figure 3. This is a partially enlarged cross-sectional view showing an enlarged view of a part of the opening of the deposition mask of this embodiment. This is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask of this embodiment. This is an image diagram of adjacent pixels formed on a substrate to be deposited. This is a process diagram showing an example of a method for manufacturing the deposition mask of this embodiment. This is a process diagram showing an example of a method for manufacturing the deposition mask of this embodiment. This is a cross-sectional view showing an example of a deposition mask of another

[0010] The embodiments will be described below with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions, proportions, and numbers in each drawing are not necessarily the same as those in reality. Also, even when the same part is represented between drawings, the relationship of dimensions, proportions, and numbers may be represented differently. For example, the number of openings along the C-C line in Figure 1 and the number of openings appearing in the cross-section in Figure 2 do not match, but in Figure 2, the number of openings has been reduced for clarity. The embodiments described below are examples of structures to embody the technical concept of this disclosure and do not specify the technical concept of this disclosure. In the following description, elements having the same function and configuration are denoted by the same reference numeral, and redundant explanations are omitted. Also, the lower and upper limits of numerical ranges include the error range. Also, the notation "~" includes the lower and upper limits.

[0011] <Background to this embodiment> Vapor deposition masks used for RGB color separation in OLED display fabrication are well known, and there is a growing need for vapor deposition masks for RGB color separation. However, in the manufacturing of high-definition OLED display devices, the shadow effect caused by the deposition of vapor deposition material on apertures affects device performance.

[0012] To suppress the shadow effect, it is desirable to make the deposition mask thinner. However, thinning the mask can lead to deformation due to its own weight bending and stress imbalances in the manufacturing process. For example, if a scratch occurs, it can cause cracks to form from that point towards the edge of the deposition mask, resulting in a high rate of mask surface loss.

[0013] Therefore, after conducting diligent research, the inventors of the present invention have developed a vapor deposition mask that can suppress crack formation, considering that when the membrane and support substrate constituting the vapor deposition mask are formed of single-crystal Si, cracks tend to occur in the cleavage direction.

[0014] <Outline Description of the Evaporation Mask 1 in this Embodiment> Figure 1 is a plan view showing the evaporation mask 1 of this embodiment. Figure 2 is a cross-sectional view of the evaporation mask 1 shown in Figure 1, cut along the line C-C and viewed from the direction of the arrow. Figure 3 is a partially enlarged plan view showing multiple cell regions of the evaporation mask 1. Figure 4 is a cross-sectional view showing a part of the evaporation mask 1 shown in Figure 3 in an enlarged view.

[0015] As shown in Figures 1 and 2, the deposition mask 1 has a laminated structure consisting of a membrane 2, an insulating layer 3, and a support substrate 4, and is preferably made of, for example, an SOI (Silicone on Insulator) substrate 9. However, in this embodiment, as will be described later, the membrane 2 may be made of SiN or the like, in which case it does not correspond to an SOI substrate 9.

[0016] In FIG. 1, the planar shape of the membrane 2 appearing on the surface of the vapor deposition mask 1 is shown, and an insulating layer 3 and a support substrate 4 are disposed on the back side of the membrane 2. The membrane 2 is also called a semiconductor layer, an active layer, etc. Although the thickness of the membrane 2 is not limited, it is about 0.3 μm to 300 μm. In addition, 0.5 μm to 50 μm is preferable, 0.5 μm to 20 μm, 0.5 μm to 10 μm, or 0.5 μm to 7.5 μm is more preferable. By setting it within this range, when forming the vapor deposition film, it is difficult for the vapor deposition material to adhere to the side wall surface of the opening 5 formed in the membrane 2, so that the vapor deposition efficiency can be increased. The membrane 2 may have a single-layer structure or a laminated structure of multiple layers. For example, a single-layer structure of Si or SiN can be exemplified, or a laminated structure including these material layers can also be used. As an example of the membrane 2, Si, SiN, SiN / Si, Si / SiN, SiN / Si / SiO ２ 、SiN / SiO ２ / Si, Si / SiN / SiO ２ 、Si / SiO ２ / SiN, SiN / SiO ２ / SiN, SiN / Si / SiN, etc. can be mentioned. Here, the symbol " / " means the structure when a plurality of layers are laminated in order from the vapor deposition source side.

[0017] As shown in FIGS. 1 and 2, the vapor deposition mask 1 has a plurality of opening regions 15 and a peripheral region 16 located around the opening regions 15. In the peripheral region, a structure in which the membrane 2, the insulating layer 3, and the support substrate 4 are laminated is formed. On the other hand, only the membrane 2 is disposed in the opening region 15, that is, the insulating layer 3 and the support substrate 4 are removed, and a plurality of minute openings 5 are formed in each opening region 15. However, this is an example, and for example, the insulating layer 3 may be left on the back side of the membrane 2 in the opening region 15.

[0018] As shown in FIG. 2, the membrane 2 includes a first surface 2a and a second surface 2b facing each other in the thickness direction. The insulating layer 3 and the support substrate 4 are provided on the second surface 2b side. The first surface 2a is a surface facing the vapor deposition substrate 10 (FIG. 6 described later), and the second surface 2b is a back surface facing the vapor deposition source 11 (FIG. 6 described later).

[0019] As shown in FIGS. 1 and 2, a plurality of openings 5 penetrating between the first surface 2a and the second surface 2b are formed in each opening region 15 of the membrane 2. For example, as shown in FIGS. 2 and 4, the opening width of each opening 5 gradually decreases from the second surface 2b to the first surface 2a. Therefore, the side wall surface 6 of the opening 5 is inclined. However, this is just an example, and the opening width may be substantially the same from the second surface 2b to the first surface 2a. Also, in FIG. 4, the opening width W1 is defined as the width dimension in the plane direction along the first surface 2a. Thus, in FIG. 4, the opening width W1 is shown at the location where the width dimension is the narrowest. In FIG. 4, although the reference numerals of the opening width W1 and the side wall surface 6 are shown only for one opening 5, they are similarly applied to the other openings 5. The shape of the side wall surface 6 of the opening 5 will be described in detail later.

[0020] The planar pattern of the opening 5 shown in FIGS. 1 and 3 (the shape seen from directly above the membrane 2 toward the first surface 2a) is not to be limited, but for example, a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse can be exemplified. Also, all the openings 5 may have the same planar pattern, or some of them may be different. Also, the openings 5 may be regularly arranged, or may be irregularly arranged, or may be a mixture of regular and irregular arrangements.

[0021] The outer peripheral shape of the membrane 2 can be a polygonal shape or a disk shape, but by making it a polygonal shape, the chamfering efficiency can be improved, and particularly, by making it a square shape, the chamfering efficiency can be further improved. The size of the membrane 2 (the length of one side in the case of a polygonal shape, the diameter in the case of a disk shape) is not limited, but it is preferably about 100 mm to 500 mm.

[0022] The horizontal width W4 and the vertical width W5 of each opening region 15 shown in FIG. 3 are not limited, but for example, they are about 5 mm to​​Further, the horizontal width W6 and the vertical width W7 of the peripheral region 16 are not limited, but for example, they are about 1 mm to 40 mm, and the horizontal width W6 and the vertical width W7 may be the same or different.

[0024] The horizontal width W4 and the vertical width W5 of the opening region 15 are preferably larger than the horizontal width W6 and the vertical width W7 of the peripheral region 16.

[0025] The insulating layer 3 can be exemplified by an oxide layer or a nitride layer, but is preferably an oxide layer. Specifically, it is preferably a silicon oxide (SiO ２ ) layer. The insulating layer 3 is also called a BOX layer (Buried Oxide Layer). The thickness of the insulating layer 3 is not limited, but for example, it is about 100 nm to 20 μm. The insulating layer 3 may have a single structure or a laminated structure of multiple layers. For example, a single structure of SiO ２ or SiN can be exemplified, or a laminated structure including these material layers can also be used. Further, the insulating layer 3 has an upper layer and a lower layer, and another insulating layer or a non-insulating layer such as a Si layer may be interposed therebetween.

[0026] The support substrate 4 shown in FIG. 2 is a semiconductor substrate, for example, a Si substrate. Note that the support substrate 4 may have a laminated structure composed of a plurality of layers including SiN, SiO ２ etc. instead of a single Si layer. The thickness of the support substrate 4 is not limited, but for example, it is about 100 μm to 1000 μm. As an example of the case where the support substrate 4 has a multilayer structure, SiO ２ / Si, SiN / Si, SiO ２ / SiN / Si, SiN / SiO ２ / Si, etc. can be mentioned.

[0027] As shown in Figure 2, the support substrate 4 can function as a columnar portion 16a and an outer peripheral frame 16b surrounding the peripheral region 16 of the opening region 15 on the second surface 2b of the membrane 2. Therefore, the membrane 2 can maintain a taut state due to the support substrate 4, eliminating the need for tensioning, and the deposition mask 1 of this embodiment can be brought into close contact with the substrate 10 to be deposited using an electrostatic chuck that utilizes electrostatic force. As shown in Figure 2, the columnar portion 16a is located inside the outer peripheral frame 16b, and they are all the same length (height), but for example, the height of the columnar portion 16a may be lower than that of the outer peripheral frame. However, maintaining the same height allows for better strength.

[0028] <Characteristic configuration of the deposition mask 1 in this embodiment> In the deposition mask 1 of this embodiment, at least one of the membrane 2 or the support substrate 4 has a polycrystalline structure of Si (silicon).

[0029] A "polycrystalline structure" is a structure composed of numerous crystal grains (single crystals) with grain boundaries between them. While not limiting to specific structures, columnar silicon is a preferred example.

[0030] In this embodiment, we can present configurations in which the membrane 2 has a polycrystalline structure of Si and the support substrate 4 has a single-crystal structure of Si; configurations in which the membrane 2 has a single-crystal structure of Si or a crystalline structure of something other than Si, such as SiN, and the support substrate 4 has a polycrystalline structure of Si; or configurations in which both the membrane 2 and the support substrate 4 have a polycrystalline structure of Si. This makes it possible to further improve the crack suppression effect.

[0031] In other words, as shown in Figure 1, even if a scratch S occurs on the deposition mask 1, for example, there is no clear cleavage direction as in the case of a single crystal structure, so the problem of the crack extending from the scratch S to the edge can be suppressed. In a single crystal structure, cracks can extend to the edge of the deposition mask, resulting in a high mask surface loss rate, but by using a polycrystalline structure, even if a crack occurs, the problem of it extending to the edge of the deposition mask can be suppressed, and the mask surface loss rate can be reduced. A crack suppression effect is achieved by having at least one of the membrane 2 or the support substrate 4 have a polycrystalline structure of Si, but the crack suppression effect can be further enhanced if at least the membrane 2 has a polycrystalline structure of Si. Furthermore, if the membrane 2 is composed of a stacked structure of multiple semiconductor substrates, it is preferable that at least one semiconductor substrate has a polycrystalline structure of Si. The above describes an example in which a crack occurs in the deposition mask 1, but it is possible to improve the mechanical strength against defects such as damage, cracks, and chips, including cracks. Furthermore, even if defects occur in the surrounding region 16 (corresponding to the beam portion in Patent Document 1) located around the opening region 15, the mechanical strength can be effectively improved.

[0032] In this embodiment, since the mask surface loss rate can be reduced, a vapor-deposited film 13 (see Figure 6) having a desired pattern width can be accurately formed using the vapor deposition mask 1, thereby improving the yield.

[0033] To accurately form the vapor-deposited film 13, it is preferable to control the size of the openings 5 ​​formed in the membrane 2 and the shape of the sidewalls 6, in addition to reducing the mask surface loss rate. The openings 5 ​​formed in the membrane 2 will be described below.

[0034] <Explanation of Aperture 5> Figure 5 is a partially enlarged cross-sectional view showing one of the apertures 5 formed in the deposition mask 1, with the middle section of the aperture 5 in the height direction (thickness direction of the membrane 2) extracted and shown. Although the reference numerals are mainly attached only to the side wall surface 6 of the aperture 5 on the left side of the figure, the cross-sectional shape is approximately symmetrical, and the side wall surface 6 on the right side of the figure has a similar configuration.

[0035] As shown in Figure 5, the side wall surface 6 of the opening 5 is formed with an uneven shape. Specifically, the side wall surface 6 has a plurality of convex portions 7 that protrude inward from the opening 5, and concave portions 8 located between the convex portions 7, which are continuously and repeatedly formed along the height direction of the opening 5.

[0036] In this embodiment, the difference in height of the unevenness of the aperture 5 is calculated as follows. [Method for calculating the difference in height of the unevenness] First, an SEM (scanning electron microscope) image of the cross-section of the aperture 5 was acquired. Although the SEM is not limited, for example, a Regulus 8220 manufactured by Hitachi High-Tech was used.

[0037] At the midpoint located exactly in the middle of the thickness between the first surface 2a and the second surface 2b of the opening 5, the length was measured using an SEM for 5 pitches, with adjacent irregularities considered as 1 pitch. While not limited to 5 pitches, if the number of pitches is too small, parameter noise increases, and if the number of pitches is too large, it may not be possible to secure that number of pitches depending on the thickness. Furthermore, calculating the parameters becomes time-consuming and complicated. Therefore, it is preferable to use a number of pitches between a few and 10. In this embodiment, measurement is basically performed with 5 pitches, but if this is difficult, the number of pitches can be appropriately changed.

[0038] Alternatively, instead of using the pitch concept described above, one could measure the length at, for example, five points in the center of the thickness where height can be confirmed using SEM imaging. In this case, the points with height can be considered convex, and the areas between them can be considered concave.

[0039] In Figure 5, only two pitches are illustrated and explained. In Figure 5, the two convex portions 7 are labeled 7a and 7b to distinguish them. Each convex portion 7a and 7b is positioned on the first surface 2a side (upper side in the illustration) and forms a half-pitch with the recess 8. The two recesses 8 are also labeled 8a and 8b to distinguish them. The convex portion 7a and the recess 8a are designated as the first half-pitch P1, and the convex portion 7b and the recess 8b are designated as the second half-pitch P2. Note that pitch refers to the distance between convex portions or between recesses, and half of that distance is defined as the half-pitch.

[0040] As shown in Figure 5, an approximate straight line T1 was drawn connecting the lowest points (bottom A) of each recess 8a and 8b within the measurement range. Bottom A is, for example, the furthest point from the center line O in the width direction of the opening 5. The approximate straight line T1 can be determined by the least squares method. If an irregular recess 8 is formed within the measurement range (for example, if bottom A is extremely lower than top B), the approximate straight line T1 can be drawn excluding that recess 8.

[0041] Next, as shown in Figure 5, the highest position (peak) B of the convex portion 7a was determined in the first half-pitch P1. Peak B is the closest position when viewed from the center line O in the width direction of the opening 5. Then, as shown in Figure 5, a straight line S1 was drawn perpendicular to the approximate straight line T1 so as to intersect peak B. The length of the straight line S1 from the approximate straight line T1 to peak B was determined. This length of the straight line S1 was taken as the height difference D1 of the convexity in the first half-pitch P1.

[0042] The difference in surface height for the second half-pitch P2 and other half-pitches can be determined using the same method as for the first half-pitch P1. Specifically, the straight-line length from the approximate straight line T1 to the top B of each convex part is determined, and this straight-line length is taken as the difference in surface height for each pitch. Incidentally, Figure 3 illustrates the difference in surface height D2 for the second half-pitch P2.

[0043] Based on the above, it is possible to determine multiple differences in the height of uneven surfaces. When measuring over five pitches, five differences in uneven surface height Dn (n = 1 to 5) are calculated. Then, the average value Ave of these differences in uneven surface height Dn was calculated.

[0044] Although fine irregularities may be formed on the surfaces of each recess 8a and 8b (or the edges of the convex portions 7a and 7b), these fine irregularities can be ignored. For example, fine irregularities with wavelengths of a few nanometers or smaller can be cut off, and a undulation curve can be created to determine the difference in irregularity height.

[0045] [Method for Calculating Aperture Width W1] As shown in Figure 4, the aperture 5 gradually narrows from the second surface 2b to the first surface 2a, and the aperture width differs depending on the measurement location. Therefore, as shown in Figure 4, the aperture width W1 was determined by the dimension in the surface direction along the first surface 2a, where it is narrowest. The aperture width W1 can be determined from the SEM image obtained using the eCD-2 manufactured by KLA-Tencor.

[0046] [Method for Calculating the Ratio of Unevenness] The ratio of unevenness R was determined using the average value Ave of the unevenness height difference Dn and the opening width W1 measured above. That is, the ratio of unevenness R was calculated as (average value Ave of unevenness height difference Dn / opening width W1). A small ratio of unevenness R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is large, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is small. On the other hand, a large ratio of unevenness R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is small, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is large. Thus, in this embodiment, the ratio of unevenness R can be controlled to fall within a predetermined range by adjusting one or both of the average value Ave of the unevenness height difference Dn and the opening width W1.

[0047] [Method for calculating the taper angle θ1 of the opening 5 and the inclination angle θ4 of the side wall surface 6] In this embodiment, the taper angle θ1 of the opening 5 is determined as follows. That is, as shown in Figure 4, the end of the opening width W1 in the surface direction along the first surface 2a and the end of the opening width W1 in the surface direction along the second surface 2b are connected by a straight line, and the inclination angle between this straight line and the first surface 2a can be set as the taper angle θ1 of the opening 5. The taper angle θ1 was determined by measuring the length from an SEM image obtained using a Hitachi High-Tech Regulus 8220.

[0048] Furthermore, as shown in Figure 5, the inclination angle θ4 of the side wall surface 6 can be determined from the inclination angle between the approximate straight line T1 and the first surface 2a.

[0049] The taper angle θ1 and the inclination angle θ4 are the same or approximate, but depending on the state of the uneven shape of the side wall surface 6 and the pitch, for example, the slope of the approximate straight line T1 may change, and the taper angle θ1 and the inclination angle θ4 may diverge. Therefore, the inclination of the side wall surface 6 was determined by measuring the taper angle θ1 of the opening 5.

[0050] [Method for calculating the unevenness angles θ2 and θ3] The unevenness angle θ2 can be determined as shown in Figure 5 by the angle between the straight line L1 connecting the top B of the convex portion 7a and the lowest bottom A of the recess 8a located on the substrate 10 side (upper side in the figure) when viewed from the convex portion 7a (viewed from the center line O in the width direction of the opening 5), and the approximate straight line T1. The unevenness angle θ3 can be determined as shown in Figure 5 by the angle between the straight line L2 connecting the top B of the convex portion 7a and the lowest bottom A of the recess 8b located on the deposition source 11 side (lower side in the figure, see Figure 6) when viewed from the convex portion 7a (viewed from the center line O in the width direction of the opening 5), and the approximate straight line T1.

[0051] A small angle between the convex and concave sections θ2 and θ3 means that the height of the convex section 7 is low (the depth of the concave section 8 is shallow) and the undulation of the side wall surface 6 is small.

[0052] The following describes the first to sixth embodiments, in which the opening 5 is defined from a different perspective.

[0053] <First Embodiment> In the first embodiment, the deposition mask 1 has a membrane 2 having a polycrystalline structure of Si, and the side wall surface 6 of the opening 5 is formed in an uneven shape, (1) the opening width W1 is 1 μm or more and 30 μm or less, and (2) the unevenness ratio R (average value Ave of unevenness height difference Dn / opening width W1) is 0.0001 or more and 0.0550 or less.

[0054] Herein, the lower and upper limits of the numerical ranges described herein may be determined by taking into consideration at least one of the following points.

[0055] Firstly, measurement errors may be included. For example, if the measurement error is approximately ±5%, the numerical range may be determined by taking a 5% error into account. Secondly, the numerical values ​​in this specification may include values ​​rounded to the next significant digit.

[0056] By adopting this configuration, clogging of the opening 5 can be reduced, and the problem of deposition material accumulating on the side wall surface 6 and deteriorating the pattern width accuracy of the deposited film 13 can be addressed more effectively.

[0057] In the first embodiment, the aperture width W1 was set to a range of 1 μm to 30 μm. This satisfies the requirements of the deposition mask 1 equipped with the membrane 2, and in particular, for deposition masks used for RGB color separation in the manufacturing process of OLED microdisplays, it is necessary to further reduce the aperture width W1. In the first embodiment, the aperture width W1 is preferably 20 μm or less, and more preferably 10 μm or less. Furthermore, the aperture width W1 is more preferably 2 μm or more, and even more preferably 3 μm or more.

[0058] In the first embodiment, the surface roughness ratio R was set to 0.0001 or more and 0.0550 or less. By adjusting the surface roughness ratio R within this range, it becomes possible to set the pattern width of the deposited film formed using the deposition mask 1 to 80% or more of the opening width W1 of the deposition mask 1.

[0059] Figure 6 is a cross-sectional view showing the deposition mask 1 of this embodiment placed between the substrate 10 to be deposited and the deposition source 11, illustrating one step in the manufacturing process of an electronic device.

[0060] As shown in Figure 6, the deposition material (deposited particles) 12 from the deposition source 11 passes through the opening 5 of the deposition mask 1 and reaches the surface 10a of the substrate 10 to be deposited, and a deposition film 13 is formed. When the pattern width W3 of the deposition film 13 is measured and the ratio with the opening width W1 is calculated, if the pattern width ratio ((pattern width W3 / opening width W1) × 100 (%)) is 80% or more, it is designated as this embodiment, and if the unevenness ratio R is less than 80%, it is designated as a comparative example.

[0061] The lower limit of the surface roughness ratio R, 0.0001, is almost at the manufacturing limit, and therefore, it was set to 0.0001 or higher. Furthermore, in the first embodiment in which the membrane 2 has a polycrystalline structure of Si, it is known that when the surface roughness ratio R exceeds the upper limit of 0.0550, the surface roughness ratio R with respect to the aperture width W1 increases exponentially. That is, for example, even if the average value Ave of the surface roughness height difference Dn is the same, in the range where the surface roughness ratio R exceeds 0.0550, even a slight shift in the direction that decreases the aperture width W1 will cause the surface roughness ratio R to fluctuate in the direction that becomes very large, and the pattern width ratio of the deposited film 13 deteriorates. Therefore, the surface roughness ratio R was set to 0.0550 or less so that a pattern width ratio of 80% or more can be stably obtained. The reason for setting the required pattern width ratio to 80% or more is that if it falls below 80%, the deviation from the desired pattern width W3 of the deposited film 13 will be too large, leading to a decrease in yield. It also leads to a reduction in the area that should emit light at the design position, such as coordinate position accuracy, resulting in a decrease in the brightness of the light-emitting element itself. Alternatively, it is a value required for product quality assurance. To increase production efficiency, the pattern width ratio should be set to 85% or more, preferably 90% or more, and more preferably 95% or more.

[0062] Furthermore, in the first embodiment, the surface roughness ratio R is preferably 0.0530 or less, more preferably 0.0520 or less, even more preferably 0.0510 or less, and most preferably 0.0500 or less.

[0063] In the first embodiment, the lower limit of the surface roughness ratio R can be set to approximately 0.0003 or 0.0004.

[0064] Furthermore, the average value Ave of the unevenness height difference Dn is preferably 0.250 μm or less, more preferably 0.220 μm or less, even more preferably 0.215 μm or less, and most preferably 0.200 μm or less. Also, the average value Ave of the unevenness height difference Dn is preferably 0.003 μm or more, more preferably 0.005 μm or more, and even more preferably 0.008 μm or more. By adjusting the average value Ave of the unevenness height difference Dn within the above range, the unevenness ratio R can be easily controlled to a range of 0.0001 to 0.0550, and even further, to a preferred range of unevenness ratio R. In addition, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be reduced, and the number of times the vapor deposition mask 1 needs to be washed can be reduced, among other effects.

[0065] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.340 μm or less. While this does not limit the lower limit of the maximum value of the unevenness height difference Dn, the maximum value of the unevenness height difference Dn is approximately 0.005 μm or more.

[0066] <Second Embodiment> In the second embodiment, the deposition mask 1 has a membrane 2 with a single-crystal structure of Si, a support substrate 4 with a polycrystalline structure of Si, and the side wall surface 6 of the opening 5 is formed with an uneven shape, (3) the opening width W1 is 1 μm or more and 30 μm or less, and (4) the unevenness ratio R (average value Ave of unevenness height difference Dn / opening width W1) is 0.0001 or more and 0.0420 or less.

[0067] By adopting this configuration, similar to the first embodiment, the occurrence of clogging of the opening 5 can be reduced, and the problem of deposition material accumulating on the side wall surface 6 and deteriorating the pattern width accuracy of the deposited film 13 can be addressed more effectively.

[0068] In the second embodiment, the membrane 2 is formed from a single-crystal structure of Si, and the support substrate 4 is formed from a polycrystalline structure of Si. This differs from the first embodiment, in which the membrane 2 is formed from a polycrystalline structure of Si, in the range of the surface roughness ratio R that can obtain a pattern width ratio of 80% or more. The reason why the range of the surface roughness ratio R that can obtain a pattern width ratio of 80% or more differs between the first and second embodiments is not clear, but it is presumed to be due to the difference in processability between polycrystalline and single-crystal materials when forming the sidewall surface 6.

[0069] In the second embodiment, by setting the surface roughness ratio R to 0.0001 or more and 0.0420 or less, it becomes possible to set the pattern width of the deposited film formed using the deposition mask 1 to 80% or more of the opening width W1 of the deposition mask 1.

[0070] In the second embodiment, the surface roughness ratio R is preferably 0.0410 or less, more preferably 0.0400 or less, and most preferably 0.0395 or less.

[0071] In the second embodiment, the lower limit of the surface roughness ratio R can also be set to approximately 0.0003 or 0.0004.

[0072] Furthermore, the average value Ave of the unevenness height difference Dn is preferably 0.250 μm or less, more preferably 0.200 μm or less, even more preferably 0.190 μm or less, and most preferably 0.180 μm or less. Also, the average value Ave of the unevenness height difference Dn is preferably 0.003 μm or more, more preferably 0.005 μm or more, and even more preferably 0.007 μm or more. By adjusting the average value Ave of the unevenness height difference Dn within the above range, the unevenness ratio R can be easily controlled to a range of 0.0001 to 0.0420, and furthermore, to a preferred range of unevenness ratio R. In addition, the deposition of the vapor deposition material 12 on the side wall surface 6 of the opening 5 can be reduced, and the number of times the vapor deposition mask 1 needs to be washed can be reduced, among other effects.

[0073] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.400 μm or less, even more preferably 0.300 μm or less, and most preferably 0.295 μm or less. While this does not limit the lower limit of the maximum value of the unevenness height difference Dn, the maximum value of the unevenness height difference Dn is approximately 0.005 μm or more.

[0074] The opening width W1 on the side facing the substrate 10 to be deposited is narrowed, and the side wall surface 6 of the opening 5 is formed as an inclined surface, which makes it easier to stably form a deposited film 13 having a desired pattern width W3. Also, when the deposited material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it is less likely to fly towards the substrate 10 to be deposited. Furthermore, from a manufacturing standpoint, inclining the side wall surface 6 of the opening 5 makes it easier to form the side wall surface 6. Although not limited, in the first and second embodiments, the taper angle θ1 of the opening 5 is preferably 60° or more, and more preferably 70° or more. Also, the taper angle θ1 is preferably less than 90°, more preferably 85° or less, and even more preferably 80° or less. The taper angle θ1 is preferably 60° or more and 80° or less. When the taper angle θ1 falls below 60°, the amount of deposition material 12 deposited on the sidewall surface 6 increases, and the pattern width ratio of the deposited film tends to fall below 80%. It is also possible to form the sidewall surface 6 almost vertically, up to a taper angle of about 90°, but in that case, the influence of the difference in unevenness height Dn on the sidewall surface 6 during deposition is considered to be large, and in particular, as the opening width W1 narrows, it is necessary to minimize the average value Ave and maximum value of the difference in unevenness height Dn. There is also a relationship with the thickness of the membrane 2. That is, as the thickness of the membrane 2 increases, it becomes difficult to form the sidewall surface 6 as a vertical surface. Therefore, in this embodiment, the taper angle θ1 is controlled to be less than 90°, preferably 85° or less, and more preferably 80° or less.

[0075] <Third and Fourth Embodiments> In the third embodiment, the deposition mask 1 has a membrane 2 with a polycrystalline structure of Si, (5) the aperture width W1 is greater than 3 μm and 5 μm or less, and (6) the taper angle θ1 of the aperture 5 is greater than 50°.

[0076] In the fourth embodiment, the deposition mask has a membrane 2 with a single-crystal structure of Si and a support substrate 4 with a polycrystalline structure of Si, (7) the aperture width W1 is greater than 3 μm and 5 μm or less, and (8) the taper angle θ1 of the aperture 5 is greater than 50°.

[0077] By adopting the third and fourth embodiments, it is possible to more effectively address the problem of deposition material accumulating on the side wall surface 6 of the opening 5, which worsens the pattern dimensions of the deposited film 13.

[0078] As described above, in both the third embodiment in which the membrane 2 has a polycrystalline structure of Si, and the fourth embodiment in which the membrane 2 has a single-crystal structure of Si and the support substrate 4 has a polycrystalline structure of Si, the numerical ranges of the aperture width W1 and the taper angle θ1 of the aperture 5 that yield a pattern width ratio of 80% or more were approximately the same. This is presumed to be because the aperture width W1 and the taper angle θ1 of the aperture 5 are parameters that are not affected, or are not affected, by the polycrystalline structure and the single-crystal structure.

[0079] Thus, in the third and fourth embodiments, the aperture width W1 was set to a range greater than 3 μm and less than or equal to 5 μm. Preferably, the aperture width W1 is 4 μm or more and less than or equal to 5 μm. This ensures that the requirements for the deposition mask 1 equipped with the membrane 2 are met, and it is particularly suitable for use as a deposition mask for RGB color separation in the manufacturing process of OLED microdisplays.

[0080] In the third and fourth embodiments, the side wall surface 6 of the opening is inclined such that the opening width narrows from the second surface 2b to the first surface 2a. This allows for the stable formation of a vapor-deposited film 13 having a desired pattern width W3. In other words, the size control of the vapor-deposited film 13 can be easily achieved. Furthermore, when the vapor-deposited material 12 deposited on the side wall surface 6 peels off from the side wall surface 6, it is less likely to fly towards the substrate 10 to be vapor-deposited. Also, from a manufacturing standpoint, inclining the side wall surface 6 of the opening 5 allows for the efficient formation of multiple openings 5 ​​in the membrane 2 by deep etching.

[0081] In the third and fourth embodiments, unlike the first and second embodiments, the side wall surface 6 is inclined to obtain excellent deposition results regardless of the uneven shape of the side wall surface 6, and in this case, the taper angle θ1 of the opening 5 is defined as greater than 50°. Furthermore, it is preferable that the taper angle θ1 is 60° or more. The upper limit of the taper angle θ1 is less than 90°, preferably 88° or less, more preferably 85° or less, and even more preferably 80° or less. Note that the taper angle θ1 includes an error of about ±3°.

[0082] Thus, in the third and fourth embodiments, by defining both the opening width W1 and the taper angle θ1, it becomes possible to set the pattern width of the deposited film formed using the deposition mask 1 to 80% or more of the opening width W1 of the deposition mask 1.

[0083] In the third and fourth embodiments, it is preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 60° or more. This effectively makes it possible to achieve a pattern width ratio of 80% or more. Alternatively, it is preferable that the opening width W1 is 4 μm or more and 5 μm or less, and the taper angle θ1 is 70° or more. This makes it possible to obtain embodiments in which the pattern width ratio exceeds 90%.

[0084] In the third embodiment, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.230 μm or less, and even more preferably 0.225 μm or less. While there is no lower limit to the average value Ave of the difference in surface height Dn, it can be, for example, around 0.003 μm.

[0085] By adjusting the average value Ave of the unevenness height difference Dn within the above range, the deposition of the deposition material 12 on the side wall surface 6 of the opening 5 can be minimized, thereby more effectively reducing the number of times the deposition mask 1 is washed and extending the lifespan of the deposition mask 1.

[0086] In the third embodiment, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.340 μm or less.

[0087] In the fourth embodiment, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.200 μm or less, even more preferably 0.190 μm or less, and most preferably 0.185 μm or less. While there is no limit to the lower value of the average value Ave of the difference in surface height Dn, it can be, for example, around 0.003 μm.

[0088] In the fourth embodiment, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.400 μm or less, even more preferably 0.350 μm or less, even more preferably 0.330 μm or less, and most preferably 0.320 μm or less.

[0089] <Fifth and Sixth Embodiments> In the fifth embodiment, the deposition mask 1 has a membrane 2 with a polycrystalline structure of Si, (9) the aperture width is greater than 3 μm and less than 15 μm, and (10) the variation σ of the aperture width is 0.02 μm or more and less than 0.09 μm.

[0090] In the sixth embodiment, the deposition mask 1 has a membrane 2 with a single-crystal structure of Si and a support substrate 4 with a polycrystalline structure of Si, (11) the aperture width is greater than 3 μm and less than 15 μm, and (12) the variation σ of the aperture width is 0.02 μm or more and less than 0.09 μm. By adopting the fifth and sixth embodiments, it is possible to be more effective against issues such as the risk of color mixing between adjacent pixels.

[0091] As described above, in both the fifth embodiment, in which the membrane 2 has a polycrystalline structure of Si, and the sixth embodiment, in which the membrane 2 has a single-crystal structure of Si and the support substrate 4 has a polycrystalline structure of Si, the numerical range of the aperture width variation σ for which a pattern width ratio of 80% or more was obtained was the same. This is presumed to be because the aperture width variation is a parameter that is not affected, or is less affected, by the polycrystalline structure and the single-crystal structure.

[0092] The variation σ can be determined, for example, by the standard deviation σ of the opening widths W1 of 100 adjacent openings 5.

[0093] When the aperture width W1 is 15 μm or more, the variation σ becomes 0.09 μm or more, and tends to increase further to 0.10 μm or more. Figure 7 is an image diagram in which RGB pixels 23 are arranged in a matrix in a vapor-deposited film 13 formed on the surface of a substrate to be vapor-deposited using a vapor deposition mask 1. When the aperture width W1 of the vapor deposition mask 1 is large, the effect of variation σ is less likely to affect the light-emitting area of ​​each pixel 23, but the risk of color mixing with adjacent pixels 23, as shown in Figure 7, increases. The risk of color mixing is determined by the absolute value of variation σ, and the larger the variation σ, the higher the risk of color mixing. Therefore, in this embodiment, the variation σ is defined in the range of 0.02 μm or more and less than 0.09 μm, and preferably the variation σ is set to 0.02 μm or more and 0.08 μm or less.

[0094] In the fifth and sixth embodiments, openings 5 ​​are formed in the membrane 2 by dry etching. At this time, for example, the etching may be slightly oversized compared to the width dimension W2 of the through-hole 14a shown in Figure 8, which will be described later, resulting in variations in the opening width W1. In this case, if the opening width W1 is made larger, it is more likely to be formed by over-etching, and as a result, the variation σ is thought to increase. For this reason, in the fifth and sixth embodiments, it was found that the variation σ can be suppressed to a smaller extent by setting the opening width W1 to a range greater than 3 μm and less than 15 μm.

[0095] Furthermore, in the fifth embodiment, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.230 μm or less, and even more preferably 0.225 μm or less. While there is no limit to the lower value of the average value Ave of the difference in surface height Dn, it can be, for example, around 0.003 μm.

[0096] Furthermore, in the sixth embodiment, the average value Ave of the unevenness height difference Dn is preferably 0.250 μm or less, more preferably 0.200 μm or less, and even more preferably 0.180 μm or less. While there is no limit to the lower value of the average value Ave of the unevenness height difference Dn, it can be, for example, around 0.003 μm.

[0097] In the first to sixth embodiments, the unevenness angles θ2 and θ3 described in Figure 5 are in the range of approximately 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less. By reducing the unevenness angles θ2 and θ3, the protruding height of the convex portion 7 can be reduced, or the spacing between adjacent convex portions 7 can be widened (the range of the recess 8 can be widened), thereby suppressing the deposition of the vapor deposition material 12 on the side surface of the convex portion 7. The most preferred range for the unevenness angles θ2 and θ3 is approximately 0.5° to 2°. Furthermore, it is preferable that the unevenness angle θ3 shown in Figure 5 is smaller than the unevenness angle θ2. This makes it possible to suppress the deposition of the vapor deposition material 12 on the side wall surface 6.

[0098] <About the manufacturing method of the deposition mask 1 in this embodiment> Figure 8 is a process diagram showing the first manufacturing method of the deposition mask 1 in this embodiment. Here, the deposition mask 1 in the manufacturing process shown in Figure 8 and Figure 9, which will be described later, shows only the vicinity of one aperture region 15, similar to Figure 4, but in reality, multiple aperture regions 15 as shown in Figure 2 are formed simultaneously. In Figure 8(a), the SOI substrate 9 is prepared. The SOI substrate 9 consists of a laminated structure of a membrane 2, an insulating layer 3, and a support substrate 4. The material and thickness of each layer are explained in Figure 1, so please refer to that.

[0099] In the case of the SOI substrate 9, there is no limit to the diameter, but in this embodiment, it can accommodate diameters up to approximately 500 mm.

[0100] In Figure 8(b), a mask layer 14 is patterned on the surface of the membrane 2. The mask layer 14 is preferably made of a resist and can be patterned by exposure and development. Multiple through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming an opening 5 in the membrane 2, and the width dimension W2 of the through holes 14a is formed to a small dimension of 30 μm or less.

[0101] Next, in Figure 8(c), the membrane 2 exposed through the through-hole 14a of the mask layer 14 is dry-etched. In this embodiment, the membrane 2 is deep-etched. This is done using a so-called Bosch process, for example, SF ６ Etching of Si by and C ４ F ８ It is preferable to use a method that involves repeatedly generating a polymer film by this process to deeply etch the silicon, and to alternately carry out sidewall protection and bottom etching. The sidewall surface 6 of the opening 5 formed in the membrane 2 by the Bosch process becomes uneven in shape.

[0102] At this time, as shown in Figure 8(c), the composition and flow rate of the etching gas, the internal pressure of the etching chamber, and the power of the high-frequency power supply are adjusted as appropriate to form an inverse tapered surface. Furthermore, these adjustments allow for control of the inclination angle of the inverse tapered surface (taper angle θ1 of the opening 5) and the difference in height Dn of the unevenness.

[0103] For example, with a dry etching apparatus, SF ６ Gas and C ４ F ８ The Bosch process was performed using alternating gases. SF ６ Anisotropic dry etching using fluoride ions was performed by applying a bias to the substrate to be etched using the same gas as in the mode of isotropic dry etching using fluorine radicals. The processing conditions were SF ６ Gas 0-500 sccm, C ４ F ８ The gas was set to 0-300 sccm, the platen LF to 0-1500 W, the coil RF to 300-1500 W, and the chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0104] The Bosch process described above allows for the deep formation of multiple openings 5 ​​in the membrane 2, and at this time, the taper angle θ1 and the difference in height of the unevenness of the openings 5 ​​can be adjusted as appropriate.

[0105] In this embodiment, reducing the unevenness height difference Dn can be achieved not only by adjusting the conditions in the etching process described above, but also, for example, by performing a smoothing process (a process to reduce the unevenness height difference) by deep etching the silicon followed by laser hydrogen annealing. Next, in the process shown in Figure 8(d), the mask layer 14 is removed. This completes the SOI substrate 9 in which a plurality of openings 5 ​​are formed in the membrane 2.

[0106] Next, in the step shown in Figure 8(e), a protective layer 20 is formed on the surface of the membrane 2. This provides adequate protection for the entire surface of the membrane 2. The protective layer 20 is, for example, a resist film, although this is not limited to it.

[0107] Next, in the step shown in Figure 8(f), a mask layer 21 is formed on the surface of the support substrate 4, which is the back surface of the SOI substrate 9. The mask layer 21 is a resist pattern, although this is not limited to it. As shown in Figure 8(f), the mask layer 21 is not formed in the opening region 15 that is opposite the opening 5 formed in the membrane 2 in the thickness direction, but is provided only in the surrounding region 16 (see also Figure 2). The mask layer 21 may also be formed together with the mask layer 14 during the step shown in Figure 8(b).

[0108] Then, in the step shown in Figure 8(g), the support substrate 4 not covered by the mask layer 21 is removed by dry etching, and in the step shown in Figure 8(h), the insulating layer 3 that appears after removing the support substrate 4 is removed by wet etching. At this time, the membrane 2 is not affected by wet etching and maintains its shape with multiple openings 5.

[0109] Then, in the step shown in Figure 8(i), the protective layer 20 and the mask layer 21 are removed. This completes the vapor deposition mask 1.

[0110] Figure 9 is a process diagram showing a second manufacturing method for the deposition mask 1 of this embodiment. In Figure 9(a), the SOI substrate 9 is prepared. The SOI substrate 9 consists of a laminated structure of a membrane 2, an insulating layer 3, and a support substrate 4. The material and thickness of each layer are explained in Figure 2, so please refer to that.

[0111] While the diameter of the SOI substrate 9 is not limited, in this embodiment it can accommodate diameters up to approximately 500 mm.

[0112] Next, in the process shown in Figure 9(b), a mask layer 21 is formed on the surface of the support substrate 4, which is the back surface of the SOI substrate 9. The mask layer 21 is a resist pattern, although this is not limited to it. Similar to Figure 8(f), the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.

[0113] Next, in the step shown in Figure 9(c), the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching, and in the step shown in Figure 9(d), the insulating layer 3 that appears after removing the support substrate 4 is removed by wet etching.

[0114] Next, in the step shown in Figure 9(e), a mask layer 22 is formed on the back surface of the membrane 2. Although not limited to this, the mask layer 22 can be formed with a resist pattern. As shown in Figure 9(e), multiple openings 22a are patterned in the mask layer 22 by exposure and development.

[0115] Next, in the step shown in Figure 9(f), the membrane 2 exposed through the opening 22a is etched. This etching process is dry etching, and although not limited to this, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a noble gas.

[0116] Fluorine compounds include, for example, CF ４ SF ６ NF ３ BF ３ , PF ５ and F ２ You can select one or more from these options, and for the noble gas, you can select one or more from helium and argon.

[0117] For example, in a dry etching apparatus, CF ４ Gas, O ２ Etching was performed using gas and Ar gas. The processing conditions were CF ４ The gas is 10-100 sccm, O ２The gas was set to 0-100 sccm, the Ar gas to 0-200 sccm, the IPC power to 200-1000 W, the RIE power to 0-1000 W, and the chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0118] In the step shown in Figure 9(f), an opening 5 can be formed in the membrane 2, the width of which gradually decreases as it moves away from the mask layer 22 (towards the first surface 2a of the membrane 2). This allows the side wall surface 6 of the opening 5 to be formed as an inclined surface. Then, in the step shown in Figure 9(g), the mask layer 22 is removed. This completes the deposition mask 1.

[0119] In both the manufacturing method shown in Figure 8 and the manufacturing method shown in Figure 9, multiple openings 5 ​​can be formed in the membrane 2, and the side walls 6 of the openings 5 ​​can be formed as inclined surfaces such that the opening width gradually narrows from the back surface (second surface 2b) of the membrane 2 facing the deposition source 11 to the front surface (first surface 2a) facing the substrate 10 to be deposited.

[0120] In this embodiment, although not limited thereto, the opening width W1 and the taper angle θ1 can be adjusted by various gas flow rates, chamber pressure, and the power of the plasma generation source.

[0121] In the Bosch process described in Figure 8, where the membrane 2 is deeply etched to form the opening 5, the difference in surface height Dn on the sidewall surface 6 is larger compared to the dry etching process described in Figure 9. Therefore, it is preferable to apply the manufacturing method shown in Figure 9 when the opening width W1 is narrow (for example, when the opening width W1 is 5 μm or less), and to apply the manufacturing method shown in Figure 8 when the opening width W1 is 5 μm or more. However, even when applying the manufacturing method shown in Figure 8, it is possible to reduce the difference in surface height by laser hydrogen annealing or the like, as described above.

[0122] <Method of manufacturing an electronic device in this embodiment> In this embodiment, as shown in Figure 6, the deposition mask 1 is placed between the substrate 10 to be deposited and the deposition source 11. At this time, the first surface 2a of the membrane 2 of the deposition mask 1 is oriented toward the substrate 10, and the second surface 2b of the membrane 2 is oriented toward the deposition source 11. Multiple openings 5 ​​are formed in the membrane 2, and the opening width is narrower on the first surface side than on the second surface side.

[0123] The deposition mask 1 is placed in a holder (not shown) of the deposition apparatus, and at this time, the deposition mask 1 and the substrate 10 to be deposited can be fixed with an electrostatic chuck. The deposition mask 1 and the substrate 10 to be deposited are rotated with the center of the holder's axis as the axis of rotation.

[0124] The deposition material (deposited particles) 12 from the deposition source 11 reaches the surface 10a of the substrate 10 through the opening 5 of the deposition mask 1, and a deposition film 13 is formed.

[0125] In this embodiment, examples of electronic devices include OLED microdisplay panels, liquid crystal panels, and solar cells, and it is particularly suitable for manufacturing OLED microdisplay panels as organic electronic devices.

[0126] By using the deposition mask 1 of this embodiment, the pattern width W3 of the deposited film 13 can be secured to be 80% or more of the opening width W1, preferably 85% or more, and more preferably 90% or more. In this way, a deposited film 13 with excellent pattern dimensions can be formed.

[0127] <Effects of using the deposition mask 1 of this embodiment> In this embodiment, at least one of the membrane 2 or the support substrate 4 has a polycrystalline structure of Si, so there is no clear cleavage direction, and as shown in Figure 1, even if a scratch S is made on the deposition mask 1, for example, it is possible to suppress the problem of a crack extending from that point to the edge. In this embodiment, it is possible to improve the mechanical strength against defects such as damage, cracks, and chips, including cracks. As a result, the mask surface loss rate can be reduced.

[0128] Thus, in addition to the low mask surface loss rate, in this embodiment, by appropriately adjusting the opening width W1, the unevenness ratio R, the taper angle θ1, or the variation σ of the opening 5 formed in the membrane 2, a high pattern dimension of the deposited film 13 can be stably obtained. Although embodiments and modifications have been described, other embodiments may be combinations of the above embodiments and modifications, either entirely or partially.

[0129] Furthermore, this disclosure is not limited to the embodiments and modifications described above, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Moreover, if the technical idea can be realized in a different way by advances in the art or by other derived arts, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea. An embodiment with a different layer configuration from the deposition mask 1 shown in Figure 2 will be described.

[0130] For example, as shown in Figure 10, SiN and SiO ２ A membrane 31 made of the above is formed into a film, and a plurality of openings 32 are formed in the membrane 31 in the central region where the silicon substrate 30 has been removed. Alternatively, it may be configured as a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (a polycrystalline Si substrate is preferred). The membrane is formed by CVD, but from the viewpoint of easy stress control, it is preferable to use SiN. In Figure 10, the silicon substrate 30 can be formed from polycrystalline Si and can function as a support substrate. In addition, in the single-layer structure, a support substrate (either a polycrystalline or single-crystal structure of Si) can be placed in a later step.

[0131] In another embodiment shown in Figures 11 to 13, an SOI substrate 9 is used, similar to Figure 1. However, in Figure 11, a SiN layer 33 is formed on the back side of the SOI substrate 9 (the side facing the support substrate 4, the side facing the deposition source 11). In Figure 12, a SiN layer 33 is formed on the front side of the SOI substrate 9 (the side facing the membrane 2, the side facing the substrate to be deposited 10). In Figure 13, a SiN layer 33 is formed on both the back and front sides of the SOI substrate 9. In the configuration where the SiN layer 33 is formed on the front side of the SOI substrate 9 (the side facing the membrane 2), an opening 5 is formed continuously with the membrane 2, as shown in Figures 12 and 13. By providing the SiN layer 33, it is easier to control the stress of the deposition mask and suppress strain and other distortions.

[0132] Furthermore, it is preferable that the SiN layer 33 formed on the surface side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited to these, the thickness of the SiN layer 33 formed on the surface side of the SOI substrate 9 is approximately 0.05 μm to 0.5 μm, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is approximately 0.05 μm to 3 μm. Since the membrane 2 is thinner than the support substrate 4 and also has numerous openings 5 ​​formed in the membrane 2, the SiN layer 33 formed on the surface side of the SOI substrate 9 is made thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control stress in a balanced manner between the surface and back sides.

[0133] In Figures 11 to 13, at least one of the membrane 2 or the support substrate 4 has a polycrystalline structure of Si. ２ The layer may be stacked together with the SiN layer, or in place of the SiN layer. ２ In a configuration where layers and SiN layers are stacked, the stacking order is not limited. Therefore, even if the outermost layer is a SiN layer, SiO ２ It doesn't matter whether it's a layer or not.

[0134] Figure 14 is a schematic cross-sectional view of a vapor deposition mask showing another embodiment. In Figure 14, there is a two-layer structure consisting of a membrane 2 having a plurality of openings 5 ​​and a support substrate 4 that supports the membrane 2. The membrane 2 shown in Figure 14 is, for example, a SiN layer, and the support substrate 4 is a Si layer.

[0135] Figure 15 is a schematic cross-sectional view of a vapor deposition mask showing another embodiment. As shown in Figure 15, a first back layer 41 and a second back layer 42, which will become the back layer 40, are laminated on the back surface 4a (the side facing the vapor deposition source 11) of the support substrate 4. For example, the first back layer 41 is made of SiO ２ The second back layer 42 is a SiN layer.

[0136] As shown in Figure 15, the membrane 2 is, for example, a SiN layer. An insulating layer 3 is interposed between the membrane 2 and the support substrate 4. The insulating layer 3 is, for example, SiO ２ This is a layered structure. As a result, the arrangement of the material layers above and below the support substrate 4 becomes approximately symmetrical, maintaining stress balance and suppressing the occurrence of warping and other deformations.

[0137] As shown in Figures 10 to 15, when the membrane 2 or support substrate 4 has a SiN layer, the opening 5 is created by the existing etching process. This etching process is dry etching, and although not limited to this, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a noble gas.

[0138] Fluorine compounds include, for example, CF ４ SF ６ NF ３ BF ３ , PF ５ and F ２ You can select one or more from these options, and for the noble gas, you can select one or more from helium and argon.

[0139] For example, in a dry etching apparatus, CF ４ Gas, O ２ Etching was performed using gas and Ar gas. The processing conditions were CF ４ The gas is 10-100 sccm, O ２ The gas was set to 0-100 sccm, the Ar gas to 0-200 sccm, the IPC power to 200-1000 W, the RIE power to 0-1000 W, and the chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0140] The effects of this disclosure will be explained below with reference to examples and comparative examples of the present invention. However, this disclosure is not limited in any way by the following examples. First, the common manufacturing conditions in each experiment shown in Tables 1 to 6 will be explained.

[0141] <SOI Substrate> The SOI substrate used was a support substrate (625 μm) / insulating layer (0.5 μm) / membrane (5 μm). The numbers in parentheses indicate the thickness. The support substrate is a Si substrate, the membrane is a Si layer, and the insulating layer is SiO ２ It was a layer. The outer diameter of the SOI substrate was 200 mm.

[0142] <Original Plate Used> In the process shown in Figure 8(b) and Figure 9(e), an aperture pattern is formed on the mask layer (resist layer) by i-line exposure. The aperture width of the original plate used to form this aperture pattern was adjusted to be within the range of 3.0 μm to 20 μm.

[0143] <Method for Manufacturing Vapor Deposition Mask> A vapor deposition mask 1 was formed using the manufacturing method shown in Figures 8 and 9. In the experiment, the aperture width W1 was varied depending on the original plate used. The aperture width W1 and taper angle θ1 formed on the membrane 2 were also adjusted by various gas flow rates, chamber pressure, and power of the plasma source. For example, in the dry etching shown in Figure 8(c), SF ６ Anisotropic dry etching using fluoride ions was performed by applying a bias to the substrate to be etched using the same gas as in the mode of isotropic dry etching using fluorine radicals. The processing conditions were SF ６ Gas 0-500 sccm, C ４ F ８ The gas was set to 0-300 sccm, the Platen LF to 0-1500 W, the Coil RF to 300-1500 W, and the chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0144] Furthermore, in the dry etching shown in Figure 9(f), CF ４ The gas is 10-100 sccm, O ２The gas was set to 0-100 sccm, the Ar gas to 0-200 sccm, the IPC power to 200-1000 W, the RIE power to 0-1000 W, and the chamber pressure to 1-10 Pa, and various conditions were adjusted.

[0145] <Dimensions of the aperture 5 formed in the deposition mask 1> In the experiment, the aperture width W1, the average value Ave of the difference in surface height Dn, the maximum value of the difference in surface height Dn, and the taper angle θ1 were determined. As shown in Figure 4, the aperture width W1 was defined as the width dimension in the surface direction along the first surface 2a of the membrane 2. The aperture width W1 can be determined from the SEM image obtained using an eCD-2 manufactured by KLA-Tencor.

[0146] The difference in surface height Dn and the taper angle θ1 were determined from SEM images obtained using a Hitachi High-Tech Regulus 8220, using the method described in Figure 5. As explained in Figure 5, the differences were determined by observing the surface irregularities formed on the side wall 6 at the midpoint of the opening height, specifically the 5-pitch area in the center of the thickness. For detailed information on how to determine the difference in surface height Dn and the taper angle θ1, please refer to the explanations in Figures 4 and 5.

[0147] <Regarding Determination of Deposition Pattern Dimensions> Using the multiple deposition masks formed as described above, the green light-emitting material Alq3 (tris(8-hydroxyquinoline)aluminum) was deposited into a pattern on the glass surface through the deposition mask using a vacuum resistance heating deposition method, and evaluated.

[0148] Then, the pattern width W3 of the deposited film was measured using a laser microscope (model VK-X210 (manufactured by Keyence)), and the ratio of the pattern width of the deposited film to the aperture width W1 of the deposition mask ((W3 / W1) × 100 (%)) was calculated. Experiments with a pattern width ratio of less than 70% were marked with ×, experiments with a pattern width ratio of 70% to less than 80% were marked with △, experiments with a pattern width ratio of 80% to 90% were marked with ○, and experiments with a pattern width ratio of more than 90% were marked with ◎.

[0149] Furthermore, in the deposition pattern dimension determination for each experiment shown in Tables 1 to 6, the surface roughness ratio R was adjusted in Tables 1 and 2, the taper angle θ1 in Tables 3 and 4, and the variation σ in Tables 5 and 6, so that experimental examples with × and △ (i.e., experimental examples where the pattern width ratio is less than 80%) are always produced in each experiment. Therefore, even if the average value Ave of the surface roughness height difference Dn and the maximum value of the surface roughness height difference Dn are similar in the experimental results of each table, the deposition pattern dimension determination may differ.

[0150] <About the experiments in Tables 1 and 2> In the experiment shown in Table 1 below, the membrane was formed from polycrystalline Si and the support substrate was formed from single-crystal Si (corresponding to the first embodiment).

[0151] Furthermore, in the experiment shown in Table 2 below (corresponding to the second embodiment), the membrane was formed from single-crystal Si and the support substrate was formed from polycrystalline Si.

[0152] Note that the experimental examples for which pitch was determined are limited to those with odd numbers in Tables 1 and 2. On the other hand, for the experimental examples with even numbers, five points with high height were determined at the center of the thickness, and the area between them was considered a recess to determine the difference in unevenness height Dn, etc. The odd-numbered experimental examples were formed using the manufacturing method shown in Figure 8, and the unevenness is relatively large, making it easy to measure as pitch. However, the even-numbered experimental examples were formed using the manufacturing method shown in Figure 9, and the unevenness is small, making it difficult to identify as pitch. For this reason, for the even-numbered experimental examples, five points that could be recognized as height were measured and various parameters were measured by applying the measurement method in Figure 5.

[0153] Then, the unevenness ratio R (= average value Ave of unevenness height difference Dn / opening width W1) was calculated from the average value Ave of unevenness height difference Dn and the opening width W1.

[0154] The experimental results are shown in the "Determination of Vapor Deposition Pattern Dimensions" column of Tables 1 and 2 below. Note that the "Taper Angle" shown in Tables 1 and 2 is expressed in 10° increments; however, this is a representative value, and it was confirmed that all experimental examples fell within ±3° of each representative value.

[0155]

[0156]

[0157] As shown in Tables 1 and 2, there are 40 experimental examples, No. 1 to No. 40, with an aperture width W1 in the range of 3 μm to 20 μm. Experimental examples No. 1, 3, 21, and 23 had a vapor deposition result of ×, and experimental examples No. 5 and 25 had a vapor deposition result of △; these are all comparative examples. The remaining experimental examples had a vapor deposition result of ○ or ◎, and all of them are examples.

[0158] From the experiments shown in Table 1, it was found that in a configuration where the membrane 2 has a polycrystalline structure of Si, by setting the aperture width W1 to 1 μm or more and 30 μm or less, and adjusting the surface roughness ratio R to within the range of 0.0001 or more and 0.0550 or less, the deposition of the deposition material 12 on the side wall surface 6 of the aperture 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the aperture width W1 is 80% or more, preferably more than 90%. In this example, the requirements for the deposition mask 1 equipped with the membrane 2 can be met, and in particular, the aperture width W1 was set to 30 μm or less, preferably 20 μm or less, to be preferably applicable as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays. Furthermore, based on the experimental example, the aperture width W1 was further preferred to be within the range of 3 μm or more and 20 μm or less.

[0159] Furthermore, from the experiments shown in Table 1, in the configuration where membrane 2 has a polycrystalline structure of Si, in order to stably obtain a pattern width ratio of more than 90%, the surface roughness ratio R was preferably set to 0.0530 or less, more preferably to 0.0520 or less, even more preferably to 0.0510 or less, and most preferably to 0.0500 or less.

[0160] Furthermore, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.220 μm or less, even more preferably 0.215 μm or less, and most preferably 0.200 μm or less.

[0161] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.340 μm or less.

[0162] Furthermore, from the experiments shown in Table 2, it was found that in a configuration where the membrane 2 has a single-crystal structure of Si and the support substrate has a polycrystalline structure of Si, by setting the opening width W1 to 1 μm or more and 30 μm or less, and adjusting the surface roughness ratio R to within the range of 0.0001 or more and 0.0420 or less, the deposition of the deposition material 12 on the side wall surface 6 of the opening 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the opening width W1 is 80% or more, preferably more than 90%.

[0163] Furthermore, from the experiments shown in Table 2, in a configuration where the membrane 2 has a single-crystal structure of Si and the support substrate has a polycrystalline structure of Si, the surface roughness ratio R was preferably set to 0.0410 or less, more preferably to 0.0400 or less, and even more preferably to 0.0395 or less, in order to stably obtain a pattern width ratio of over 90%.

[0164] Furthermore, the average value Ave of the difference in surface height Dn was preferably 0.250 μm or less, more preferably 0.200 μm or less, even more preferably 0.190 μm or less, and most preferably 0.180 μm or less.

[0165] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.400 μm or less, even more preferably 0.300 μm or less, and most preferably 0.295 μm or less.

[0166] Furthermore, Tables 1 and 2 show that, based on experimental results, the taper angle θ1 is preferably 60° or greater, and more preferably 70° or greater. Experimental examples indicate that the taper angle θ1 can be set within the range of 60° to 80°. A tolerance of approximately ±3° is allowed for the taper angle θ1.

[0167] Furthermore, the concavity angles θ2 and θ3, as explained in Figure 5, were generally between 11° and 41° in the odd-numbered experimental examples. In contrast, the concavity angles θ2 and θ3 were generally between 1.0° and 1.5° in the even-numbered experimental examples.

[0168] The smaller the unevenness angles θ2 and θ3, the smaller the protruding height of the convex portion 7 (see Figure 5), which is preferable as it suppresses the deposition of the vapor-deposited material 12. From experimental examples, the unevenness angles θ2 and θ3 can be set within a range of about 0.5° to 50°, and when the aperture width W1 is 5 μm or less, it is desirable to make the unevenness angles θ2 and θ3 as small as possible, setting them to 10° or less, with the most preferable range being about 0.5° to 2°. Furthermore, it was found that the unevenness angle θ3 is smaller than the unevenness angle θ2, which suppresses the deposition of the vapor-deposited material.

[0169] <About the experiments in Tables 3 and 4> In the experiment shown in Table 3 below, the membrane was formed from polycrystalline Si and the support substrate was formed from single-crystal Si (corresponding to the third embodiment).

[0170] Furthermore, the experiment shown in Table 4 below is an example in which the membrane was formed from single-crystal Si and the support substrate was formed from polycrystalline Si (corresponding to the fourth embodiment).

[0171] In the experiment, the opening width W1, the taper angle θ1 of the side wall surface 6, the average value Ave of the difference in unevenness height Dn, and the maximum value of the difference in unevenness height Dn were determined. The experimental results are shown in Tables 3 and 4 below. Note that the "taper angle" shown in Tables 3 and 4 is described in units of 10°, but this is a representative value, and it was confirmed that all experimental examples fell within ±3° of each representative value.

[0172]

[0173]

[0174] As shown in Tables 3 and 4, there were experimental examples No. 41 to No. 64, with the aperture width W1 being in the range of greater than 3 μm and 5 μm or less. Experimental examples No. 41, 45, 53, and 57, where the aperture width W1 was 3 μm or 4 μm and the taper angle θ1 was 50°, had a pattern width ratio of less than 70%, and were evaluated as ×. Also, experimental examples 42 to 44 and 54 to 56, where the aperture width W1 was 3 μm and the taper angle θ1 was 60° to 80°, and experimental examples 49 and 61, where the aperture width W1 was 5 μm and the taper angle θ1 was 50°, all had a pattern width ratio of 70% to less than 80%, and were evaluated as △. Thus, experimental examples with a pattern width ratio evaluation of × or △ are comparative examples. On the other hand, experimental examples No. 46 to No. 48, No. 50 to No. 52, No. Numbers 58 to 60 and 62 to 64 have a pattern width ratio evaluation of ○ or ◎ and correspond to the examples.

[0175] From this experiment, it was found that by setting the aperture width W1 to be greater than 3 μm and 5 μm or less, and the taper angle θ1 to be greater than 50°, the deposition of the deposition material 12 on the side wall surface 6 of the aperture 5 can be suppressed, and a deposition film can be formed in which the pattern width W3 relative to the aperture width W1 is 80% or more. In this embodiment, the requirements for a deposition mask 1 equipped with a membrane 2 can be met, and in particular, to suit application as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays, the aperture width W1 was set to 4 μm or more and 5 μm or less, and the taper angle θ1 was set to 60° or more. As a result, a deposition film with a stable pattern width ratio of 80% or more can be formed. Furthermore, by setting the aperture width W1 to 4.5 μm or more and 5 μm or less, and the taper angle θ1 to 70° or more, a deposition film with a pattern width ratio exceeding 90% can be stably formed.

[0176] Furthermore, from the experiments shown in Table 3, it was determined that in a configuration where membrane 2 has a polycrystalline structure of Si, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.230 μm or less, and even more preferably 0.225 μm or less.

[0177] Furthermore, the maximum value of the unevenness height difference Dn is preferably 0.500 μm or less, more preferably 0.450 μm or less, even more preferably 0.400 μm or less, even more preferably 0.350 μm or less, and most preferably 0.300 μm or less.

[0178] Furthermore, from the experiments shown in Table 4, in a configuration where membrane 2 has a single-crystal structure of Si and the support substrate has a polycrystalline structure of Si, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.200 μm or less, even more preferably 0.190 μm or less, and most preferably 0.185 μm or less.

[0179] Furthermore, the maximum value of the unevenness height difference Dn was preferably 0.500 μm or less, more preferably 0.400 μm or less, even more preferably 0.350 μm or less, even more preferably 0.330 μm or less, and most preferably 0.320 μm or less. In addition, in the experiments shown in Tables 3 and 4, the unevenness angle θ2 explained in Figure 5 was between 11° and 41°.

[0180] <About the experiments in Tables 5 and 6> In the experiment shown in Table 5 below, the membrane was formed from polycrystalline Si and the support substrate was formed from single-crystal Si (corresponding to the fifth embodiment).

[0181] Furthermore, the experiment shown in Table 6 below is an example in which the membrane was formed from single-crystal Si and the support substrate was formed from polycrystalline Si (corresponding to the sixth embodiment).

[0182] In the experiment, the average values ​​Ave of the aperture width W1, variation σ, and difference in surface height Dn were determined for each taper angle (88°, 80°, and 60°). The experimental results are shown in Tables 5 and 6 below.

[0183]

[0184]

[0185] For the aperture variation judgments shown in Tables 5 and 6, experimental cases where the variation (standard deviation) σ of the aperture width W1 was 0.08 μm or less were marked with ○, experimental cases where it was within the range of 0.09 μm to 0.10 μm were marked with △, and experimental cases where it was greater than 0.10 μm were marked with ×.

[0186] Note that the "taper angle" descriptions in Tables 5 and 6 are representative values, and it was confirmed that all experimental examples fell within ±3° of each representative value.

[0187] As shown in Tables 5 and 6, the experimental examples range from No. 65 to No. 100, with the aperture width W1 being in the range of 3 μm to 20 μm. Experimental examples No. 65, 71, 77, 83, 89, and 95 all received a × for vapor deposition pattern dimension determination and are therefore comparative examples. Experimental examples No. 69, 70, 75, 76, 81, 82, 87, 88, 93, 94, 99, and 100 all received a △ or × for aperture variation determination and are therefore comparative examples. The remaining experimental examples received a ○ or ◎ for vapor deposition pattern dimension determination and a ○ for aperture variation determination and are therefore examples.

[0188] From the experimental results shown in Tables 5 and 6, it was found that by setting the aperture width W1 to be greater than 3 μm and less than 15 μm, the deposition of the deposition material 12 on the side wall surface 6 of the aperture 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the aperture width W1 is 80% or more, preferably more than 90%. In addition, it was found that the variation σ of the aperture width W1 can be reduced, specifically, the variation σ can be set in the range of 0.02 μm or more and less than 0.09 μm. In this embodiment, it is preferable that the variation σ is 0.02 μm or more and 0.08 μm or less. Furthermore, in this embodiment, the needs required for a deposition mask 1 equipped with a membrane 2 can be met, and it is particularly suitable for use as a deposition mask for RGB color separation in the manufacturing process of OLED microdisplays.

[0189] Furthermore, from the experiments shown in Table 5, it was determined that in a configuration where membrane 2 has a polycrystalline structure of Si, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.230 μm or less, and even more preferably 0.225 μm or less.

[0190] Furthermore, from the experiments shown in Table 6, in a configuration where the membrane 2 has a single-crystal structure of Si and the support substrate has a polycrystalline structure of Si, the average value Ave of the difference in surface height Dn is preferably 0.250 μm or less, more preferably 0.200 μm or less, and even more preferably 0.180 μm or less.

[0191] Furthermore, based on the experimental results shown in Tables 5 and 6, it was determined that a taper angle of 60° or greater is preferable. The lower limit of the taper angle (inclination angle) can be less than 90° or 88° or less. An error of approximately ±3° is acceptable for the taper angle.

[0192] Furthermore, the experimental results in Tables 5 and 6 showed that the unevenness angles θ2 and θ3, as explained in Figure 5, can be set within a range of approximately 0.5° to 50°. Preferably, they are set to 10° or less, and a more preferable range is approximately 0.5° to 2°. In addition, the unevenness angle θ3 is smaller than the unevenness angle θ2, which was found to be a configuration that can suppress the deposition of the vapor-deposited material.

[0193] This application is based on Japanese Patent Application No. 2025-017990, filed on February 6, 2025. All of its contents are included here.

Claims

1. A vapor deposition mask for depositing a deposition material from a deposition source onto the surface of a substrate to be deposited through an opening, comprising: a membrane having a first surface facing the substrate to be deposited and a second surface located on the opposite side of the first surface and facing the deposition source, and having a plurality of openings penetrating between the first surface and the second surface; and a support substrate supporting the membrane, wherein at least one of the membrane or the support substrate has a polycrystalline structure of Si.

2. The vapor deposition mask according to claim 1, characterized in that the membrane has at least one of a Si layer or a SiN layer.

3. The vapor deposition mask according to claim 1 or 2, characterized in that the vapor deposition mask is polygonal.

4. The vapor deposition mask according to claim 1 or 2, characterized in that the membrane has a polycrystalline structure of Si, the side wall surface of the opening is formed in an uneven shape, the opening width is 1 μm or more and 30 μm or less, and the unevenness ratio (average value of the difference in unevenness height / opening width) is 0.0001 or more and 0.0550 or less.

5. The vapor deposition mask according to claim 1 or 2, characterized in that the membrane has a single-crystal structure of Si, the support substrate has a polycrystalline structure of Si, the side wall surface of the opening is formed with an uneven shape, the opening width is 1 μm or more and 30 μm or less, and the unevenness ratio (average value of the difference in unevenness height / opening width) is 0.0001 or more and 0.0420 or less.

6. The vapor deposition mask according to claim 1 or 2, characterized in that the aperture width is greater than 3 μm and 5 μm or less, and the taper angle of the aperture is greater than 50°.

7. The vapor deposition mask according to claim 1 or 2, characterized in that the aperture width is greater than 3 μm and less than 15 μm, and the variation σ of the aperture width is 0.02 μm or more and less than 0.09 μm.

8. The vapor deposition mask according to claim 1 or 2, characterized in that the opening width narrows from the second surface to the first surface.

9. The vapor deposition mask according to claim 4, characterized in that the average value of the difference in the height of the unevenness is 0.250 μm or less, or the maximum value of the difference in the height of the unevenness is 0.500 μm or less.

10. The support substrate is made of a polycrystalline structure of Si, and at least one of the support substrates, either on the membrane side or on the deposition source side opposite to the membrane, contains SiO ２ A vapor deposition mask according to claim 1 or 2, characterized by having at least one of a layer or a SiN layer.

11. The deposition mask according to claim 2, characterized in that the membrane has a SiN layer.

12. The vapor deposition mask according to claim 1 or 2, characterized in that the support substrate has a SiN layer on the surface facing the vapor deposition source.

13. A method for manufacturing an electronic device, characterized by arranging the deposition mask described in claim 1 or claim 2 between a substrate to be deposited and a deposition source such that the first surface faces the substrate to be deposited and the second surface faces the deposition source, and depositing a deposition material onto the surface of the substrate through the opening.

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