Light detection device and method for designing light detection device

Abstract

This light detection device comprises: a first chip and a second chip stacked on each other; a pixel array section provided on the first chip; a circuit section provided on the second chip; a plurality of via group sections provided across the first chip and the second chip and used for electrically connecting the pixel array section and the circuit section; and a plurality of signal line groups provided on the first chip and each connecting the pixel array section and a corresponding via group section among the plurality of via group sections. The plurality of via group sections are arranged at intervals along an array direction so as to face the pixel array section, and each of the plurality of signal line groups connects a corresponding via group section among the plurality of via group sections and a corresponding pixel of the pixel array section.

Description

Optical Detection Device and Design Method of Optical Detection Device

[0001] The present disclosure relates to an optical detection device and a design method of an optical detection device.

[0002] For example, as disclosed in Patent Document 1, a solid-state imaging device including two chips stacked on each other is known.

[0003] International Publication No. 2016 / 170833, Japanese Patent Application Laid-Open No. 2017-123533, International Publication No. 2019 / 049662

[0004] Min-Woong Seo et al., "A Programmable Sub-Nanosecond Time-Gated 4-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy", IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 70-72, Feb 2017. Keita Yasutomi et al., "A 38μm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent Reference", IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 100-102, Feb, 2022.

[0005] In a solid-state imaging device with the above configuration, for example, a chip with a pixel array and a chip with a circuit are electrically connected via vias. To address the difference between the pixel pitch and the via pitch, it is conceivable to use diagonal wiring for connecting pixels and vias. If the length of the wiring differs significantly between the center and the edges of the pixel array due to diagonal wiring, variations in electrical characteristics may occur, potentially degrading the performance of the device. The same can be said not only for solid-state imaging devices but also for various photodetectors equipped with a pixel array.

[0006] One aspect of this disclosure is to suppress the degradation of the device's performance.

[0007] A photodetector according to one aspect of the present disclosure comprises a first chip and a second chip stacked on top of each other, a pixel array portion provided on the first chip, a circuit portion provided on the second chip, a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion, and a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions and a corresponding pixel in the pixel array portion.

[0008] A design method relating to one aspect of the present disclosure is a design method for a photodetector, the photodetector comprising: a first chip and a second chip stacked on top of each other; a pixel array portion provided on the first chip; a circuit portion provided on the second chip; a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion; and a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions to a corresponding pixel in the pixel array portion, the design method comprising: preparing a unit layout for the photodetector; and repeatedly arranging the prepared unit layout, the unit layout comprising: a via group portion; a signal line group corresponding to the via group portion; a portion of the pixel array portion corresponding to the via group portion; and a portion of the circuit portion corresponding to the via group portion.

[0009] This is a diagram showing an example of the schematic configuration of the photodetector 100 according to the embodiment. This is a diagram showing an example of the schematic configuration of chip 1 and chip 2. This is a diagram showing an example of the schematic configuration of chip 1 and chip 2. This is a diagram showing an example of the schematic configuration of chip 1 and chip 2. This is a diagram showing an example of the schematic configuration of chip 1 and chip 2. This is a diagram showing a comparative example. This is a diagram showing a comparative example. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a multi-pixel configuration. This is a diagram showing a comparative example. This is a diagram showing an example of the type of unit layout L. This is a diagram showing an example of the design of the photodetector 100. This is a diagram showing an example of the design of the photodetector 100. This is a flowchart showing an example of the design method for the photodetector 100. This is a diagram showing an example of the schematic configuration of the photodetector 100. This is a diagram showing a first configuration example of the pad portion 6. This is a diagram showing an example of the manufacturing method of the photodetector 100. This is a diagram showing a second configuration example of the pad portion 6. This is a diagram showing an example of the manufacturing method of the photodetector 100. This is a diagram showing a third configuration example of the pad portion 6. This is a diagram showing an example of the manufacturing method of the photodetector 100. This is a diagram showing an example of the planar layout of the pad portion 6. This figure shows an example of the planar layout of the pad section 6. This figure shows an example of the separation structure. This figure shows an example of the separation structure. This block diagram shows an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit. This figure shows an example of the schematic configuration of an endoscopic surgery system. This block diagram shows an example of the functional configuration of the camera head and CCU.

[0010] Embodiments of this disclosure will be described in detail below with reference to the drawings. In each of the following embodiments, the same elements will be denoted by the same reference numerals to avoid redundant descriptions.

[0011] This disclosure will be described in the following order of items: 0. Introduction 1. Embodiments 2. Example of Planar Layout 3. Example of Multi-Pixel Design 4. Example of Design Method 5. Example of Pad Configuration 5.1 First Configuration Example 5.2 Second Configuration Example 5.3 Third Configuration Example 6. Example of Separation Structure 7. Others 7.1 Application Example to Mobile Devices 7.2 Application Example to Endoscopic Surgical Systems 8. Summary

[0012] 0. In stacked photodetectors, such as solid-state imaging devices (also called image sensors), a chip with pixels and a chip with circuits are electrically connected via vias. Pads for signals, power, etc., are arranged around the chip. Several challenges exist in this configuration.

[0013] When the pixel pitch and via pitch differ, the wiring connecting the pixels and vias may be diagonal or have a steep incline. This can lead to significant differences (variations) in wiring length between the center and edges of the pixel array, potentially resulting in differences in electrical characteristics. Furthermore, the larger the pitch difference and the larger the pixel size, the more space is required for diagonal wiring, and the larger the chip size becomes.

[0014] The chip also contains wiring to connect pads to pixels or circuits. Due to limitations in the available wiring layers, many wires must pass through the vias mentioned above. This results in thin and long wires, leading to problems such as increased impedance, voltage drop, and degraded noise immunity. The increased wiring density also leads to problems of performance degradation due to signal interference.

[0015] Because vias are provided across two chips, mechanical stress is easily applied. In particular, if a large number of vias are provided in a one-dimensional direction near the edge of the chip, the likelihood of problems with thermal strain and resistance to external stress increases.

[0016] As pixel size decreases, processing speed increases, and functionality improves, power consumption increases and the number of signals increases, leading to an expected increase in the number of wires. The aforementioned problems will become even more apparent. Furthermore, if vias used to supply power to the pixel array and each part (block) of the circuit cannot be secured, power can only be supplied from pads provided at the edge of the chip, which may cause performance degradation due to voltage gradients.

[0017] At least some of the aforementioned problems are addressed by the disclosed technology. As detailed below, for example, via groups are divided and arranged, thereby reducing variations in wiring length. Other problems can also be addressed. The technological advantages are maintained even as the pixel size increases.

[0018] By utilizing the space between via groups, connections from pads to pixel arrays and circuits become easier. For example, by directly connecting wiring from pads to pixel arrays and circuits without using vias, power supply noise can be suppressed and electrical characteristics can be improved. Interference with other wiring, such as vias and wiring between pixels, can also be physically reduced.

[0019] Design becomes easier. For example, by treating the via group section, corresponding signal line group, pixel array section, and circuit section as a single unit layout and repeating this layout according to the number of pixels, reusable designs become possible.

[0020] 1. Figure 1 of the embodiment shows an example of the schematic configuration of a photodetector 100 according to the embodiment. The photodetector has a stacked structure in which a plurality of chips (e.g., semiconductor chips) are stacked. In this example, the photodetector 100 includes two chips stacked on top of each other. The first chip is referred to as chip 1 and is shown in the figure. The second chip is referred to as chip 2 and is shown in the figure.

[0021] The XYZ coordinate system is also shown. The X-axis and Y-axis directions (XY plane directions) correspond to the plane directions of chip 1 and chip 2. The Z-axis direction corresponds to the thickness direction of chip 1 and chip 2. In this example, chip 2 and chip 1 are stacked in this order in the positive Z-axis direction. The Z-axis direction can also be called the stacking direction of chip 1 and chip 2.

[0022] One example of an application of light detection by the light detection device 100 is imaging, in which case the light detection device 100 is an imaging device (for example, a solid-state imaging device). Another example of an application of light detection is distance measurement, in which case the light detection device 100 is a distance measuring device. The light detection device 100 may also have both imaging and distance measuring functions. Hereafter, unless otherwise specified, the light detection device 100 will be assumed to be a solid-state imaging device.

[0023] Figures 2 to 5 show examples of the schematic configurations of chip 1 and chip 2. Figure 2 schematically shows the layout of chip 1 when viewed from above (viewed in the negative Z-axis direction). Figure 3 schematically shows the layout of chip 2 when viewed from above. Figure 4 schematically shows the cross-sections of chip 1 and chip 2 when viewed along the line IV-IV in Figures 2 and 3. Figure 5 schematically shows the cross-sections of chip 1 and chip 2 when viewed along the line V-V in Figures 2 and 3.

[0024] At least one of the aforementioned chips 1 and 2 is provided with the elements of the light detection device 100. Specifically, the light detection device 100 includes a pixel array section 3, a circuit section 4, a via group section 5, a pad section 6, a signal line group 7, and wiring 8.

[0025] Chip 1 includes a wiring layer 11 and a semiconductor layer 12. Various wirings, vias, etc. are formed on the wiring layer 11. Transistors, etc. are formed on the semiconductor layer 12. The wiring layer 11 and the semiconductor layer 12 are stacked in this order in the positive Z-axis direction.

[0026] Chip 2 includes a wiring layer 21 and a semiconductor layer 22. Various wirings, vias, etc. are formed on the wiring layer 21. Transistors, etc. are formed on the semiconductor layer 22. The semiconductor layer 22 and the wiring layer 21 are stacked in this order in the positive Z-axis direction.

[0027] The side of chip 1 facing the wiring layer 11 (negative Z-axis direction) is referred to as the main surface 1a and is shown in the figure. Some of the wirings formed on the wiring layer 11 are exposed on the main surface 1a. The side of chip 1 facing the semiconductor layer 12 (positive Z-axis direction) is referred to as the back surface 1b and is shown in the figure.

[0028] The side of chip 2 facing the wiring layer 21 (positive Z-axis direction) is referred to as the main surface 2a and is shown in the figure. Some of the wirings formed on the wiring layer 21 are exposed on the main surface 2a. The side of chip 2 facing the semiconductor layer 22 (negative Z-axis direction) is referred to as the back surface 2b and is shown in the figure.

[0029] Chip 1 and Chip 2 are stacked on top of each other such that the main surfaces 1a of Chip 1 and the main surfaces 2a of Chip 2 are in surface contact with each other. Wiring exposed on the main surface 1a of Chip 1 and wiring exposed on the main surface 2a of Chip 2 are in contact (connected, joined, etc.), thereby electrically connecting Chip 1 and Chip 2. Connections using wiring containing copper (Cu) are also called Cu-Cu connections, etc.

[0030] The pixel array unit 3 is provided on the chip 1. The pixel array unit 3 includes a plurality of pixels 30 arranged in two dimensions. Each pixel 30 outputs a voltage corresponding to the amount of incident light. This voltage is also called the pixel signal.

[0031] When the chip 1 is viewed from above (in the negative Z-axis direction), the pixel array portion 3 has a substantially rectangular shape. The central portion of the pixel array portion 3 is referred to as the central portion 31 and is shown in the figure. The ends of the pixel array portion 3 are referred to as the ends 32 and are shown in the figure. The ends 32 may be the four corner portions of the pixel array portion 3. The central portion 31 may be the portion of the pixel array portion 3 other than the ends 32.

[0032] The circuit unit 4 is provided on the chip 2. The circuit unit 4 drives the pixel array unit 3 and processes the pixel signals from the pixel array unit 3. The circuit unit 4 also performs overall control of the light detection device 100. In the example shown in Figure 3, the circuit unit 4 includes a vertical drive circuit 41, a column processing unit 42, and a processing control unit 43.

[0033] The vertical drive circuit 41 scans the pixels 30 in pixel row units. The vertical drive circuit 41 drives the pixels 30 for each pixel row. The vertical drive circuit 41 can also be called a row scanning circuit. Pixel signals are read out from the pixels 30 selected by the row scanning. The pixel signals here are analog voltage signals and are sent to the column processing unit 42.

[0034] The column processing unit 42 processes the pixel signals from the pixels 30 for each pixel column. Specifically, the column processing unit 42 converts the pixel signals from the pixels 30 of the corresponding pixel column into digital signals.

[0035] The processing control unit 43 processes pixel signals from the column processing unit 42 and controls the vertical drive circuit 41 and the column processing unit 42. One example of pixel signal processing is image generation based on the pixel signals. One example of controlling the vertical drive circuit 41 and the column processing unit 42 is the generation of a reference clock signal and a control signal. It can be used for reading out pixel signals, timing control, etc.

[0036] Various known circuit configurations may be used for the vertical drive circuit 41, column processing unit 42, and processing control unit 43; for one example, please refer to Patent Document 1.

[0037] The via group 5 is provided across chip 1 and chip 2 and is used to electrically connect the pixel array 3 and the circuit 4. Multiple via group 5 exist, and each via group 5 may contain two or more vias 50. The via group 5 also includes the wiring exposed on the main surface 1a of chip 1 and the main surface 2a of chip 2, as described above, and this wiring is electrically connected to the vias 50. Through these vias 50, chip 1 and chip 2 are electrically connected, and therefore, corresponding parts of the pixel array 3 and the circuit 4 are electrically connected to each other.

[0038] Various known configurations may be used for the via 50. For example, the configuration suitable for Cu-Cu connection described above may be used. Also, through-vias that penetrate the wiring layer 11 of chip 1 or the wiring layer 21 of chip 2 may be used. Solder balls may also be used.

[0039] The shape of via 50 when viewed from above (in the Z-axis direction) is not particularly limited. For example, via 50 may have a horizontally elongated shape with the X-axis direction as its longitudinal direction, or a vertically elongated shape with the Y-axis direction as its longitudinal direction.

[0040] The arrangement of vias 50 in the via group portion 5 is not particularly limited. The vias 50 may be arranged in a single row or may be arranged over two or more rows. For example, each via 50 is arranged in a manner suitable for connection to each signal of the signal line group 7.

[0041] The plurality of via group portions 5 are arranged at intervals along the array direction so as to face the pixel array portion 3. It can also be said that the via group portions 5 are arranged in a divided manner. For example, each via group portion 5 is arranged such that a structure other than the via group portion 5 exists between the wiring patterns of adjacent via group portions 5. The distance between adjacent via group portions 5 may be longer than the distance between adjacent vias 50 within the same via group portion 5.

[0042] The plurality of via group portions 5 may be arranged at equal intervals or may be arranged at different intervals. In the example shown in FIG. 2, there are a plurality of via group portions 5 arranged at the same interval along the row direction (X-axis direction) and a plurality of via group portions 5 arranged at the same interval along the column direction (Y-axis direction).

[0043] Among the plurality of via group portions 5, the via group portion 5 arranged to face the central portion 31 of the pixel array portion 3 is referred to as the via group portion 5-1 (first via group portion) and is illustrated. The via group portion 5 arranged to face the end portion 32 of the pixel array portion 3 is referred to as the via group portion 5-2 (second via group portion) and is illustrated. When these are not particularly distinguished, they are simply referred to as the via group portion 5.

[0044] The plurality of via group portions 5 arranged in the array direction may be arranged symmetrically with respect to the central position of the whole of them. It can also be said that the plurality of via group portions 5 are arranged (mirror arrangement) having a target structure.

[0045] The pad portion 6 is provided across the chips 1 and 2. There are a plurality of pad portions 6, and each pad portion 6 enables electrical access to the outside of the chips 1 and 2. For example, a power supply voltage, an electrical signal, etc. from the outside are supplied to the pad portion 6.

[0046] When viewed from the pixel array unit 3, at least some of the plurality of pad units 6 are located between adjacent via group units 5. In this example, when viewed in the positive Y-axis direction, some pad units 6 are located between adjacent via group units 5. Similarly, when viewed in the negative X-axis direction, some pad units 6 are located between adjacent via group units 5.

[0047] In the examples shown in FIGS. 4 and 5, the pad unit 6 includes a pad via 61. The illustrated pad via 61 extends through the chip 1 to the chip 2. However, the configuration of the pad unit 6 is not limited to this, and some specific examples will be described later again.

[0048] Various elements other than the pad unit 6 may also be arranged between adjacent via group units 5. For example, other vias (through vias, via arrays, etc.) may be arranged.

[0049] The signal line group 7 is provided in the chip 1. There are a plurality of signal line groups 7 corresponding to the plurality of via group units 5, and each signal line group 7 connects the corresponding via group unit 5 among the plurality of via group units 5 and the corresponding pixel 30 of the pixel array unit 3. For example, pixel signals from the corresponding pixel 30 of the pixel array unit 3 are supplied to the signal line group 7. One signal line in the signal line group 7 may be connected to one via 50 in the corresponding via group unit 5.

[0050] In the examples shown in FIGS. 4 and 5, the wiring 8 is provided in the chip 2. The pad unit 6 or the via 50 of the via group unit 5 is connected to the wiring 8. For example, the power supply voltage from the pad unit 6 and the pixel signal from the via 50 are supplied to the circuit unit 4 via the wiring 8 and other vias, wirings, etc. in the chip 2. Also, signals from the circuit unit 4 are supplied to the pixel 30 via them. An example of the material of the wiring 8 is Al (aluminum), and in that case, the wiring 8 can also be called an Al wiring.

[0051] In the region shown in Figure 4, a via group 5 exists between the pad portion 6 and the circuit portion 4. The pad via 61 of the pad portion 6 is connected to the circuit portion 4 via other vias and wiring within the wiring layer 21 of the chip 2, bypassing not only the wiring 8 but also the via 50 of the via group 5. Because wiring needs to be rerouted, the wiring resistance increases and interference with other signals becomes more likely.

[0052] In the region shown in Figure 5, there is no via group 5 between the pad section 6 and the circuit section 4. The pad vias 61 of the pad section 6 are directly connected to the circuit section 4 via wiring 8. The bypass wiring shown in Figure 4 above is unnecessary. This suppresses the increase in wiring resistance and interference with other signals. The same applies to the connection between the pad section 6 and the pixel array section 3.

[0053] The photodetector 100 having the configuration described above can suppress performance degradation of the device. A comparative example will also be used to illustrate this point.

[0054] Figures 6 and 7 show comparative examples. The photodetector according to the comparative example is referred to as photodetector 100E and is shown in the figure. Components of photodetector 100E are shown with the letter E added to their reference numerals. Figure 6 schematically shows the planar layout of chip 1E of photodetector 100E. Figure 7 schematically shows the planar layout of chip 2E of photodetector 100E. In this example, regarding signal line groups, only the signal line group 7E connected to the via group section 5E for the column processing section 42 is shown. The cross-section along IV-IV in Figures 6 and 7 corresponds to the same cross-section as in Figure 4, but with the reference numerals changed to those of photodetector 100E.

[0055] In the comparative example, the photodetector 100E is not divided into sections, and therefore, there is a large variation in the length of the signal lines in the signal line group 7E connecting the via group 5E and the pixel array 3E. This can lead to a large variation in electrical characteristics and potentially degrade the performance of the device.

[0056] In contrast, in the optical detection device 100 according to the embodiment (Figures 1 to 5), the via group section 5 is divided and arranged. This makes it possible to reduce the variation in the length of the signal lines of the multiple signal line groups 7 corresponding to the multiple via group sections 5. As a result, it is possible to reduce variations in electrical characteristics and suppress a decrease in the performance of the device.

[0057] Furthermore, in the optical detection device 100 according to this embodiment, the signal lines of signal line group 7 can be made shorter than the signal lines of signal line group 7E of the optical detection device 100E. This increases the possibility of further improving the electrical characteristics and further enhancing the performance of the device.

[0058] In the comparative example of the photodetector 100E, via group sections 5E exist between most of the pad sections 6E and the circuit section 4E. It is necessary to connect the pad section 6E and the circuit section 4E in a way that bypasses the vias 50E of the via group section 5E. As explained earlier with reference to Figure 4, bypass wiring can increase wiring resistance and make interference with other signals more likely.

[0059] In contrast, in the optical detection device 100 according to this embodiment, wiring connecting the pad section 6 and the circuit section 4 can be passed through the region between adjacent via group sections 5. This avoids the aforementioned problems caused by bypass wiring. The same applies to the connection between the pad section 6 and the pixel array section 3. By adjusting the number of via group sections 5 (number of divisions), more specifically the number of regions between via group sections 5, the voltage gradients of each part of the circuit section 4 and each part of the pixel array section 3 can be reduced, thereby improving the characteristics.

[0060] In the comparative example, the photodetector 100E has a large number of vias 50E densely arranged in the via group 5E extending in the array direction, which may result in insufficient strength. For example, it may not be possible to obtain sufficient strength against thermal strain and external stress.

[0061] In contrast, in the optical detection device 100 according to this embodiment, the via group portion 5 is divided and arranged, which allows for the dispersion of mechanical stress. This increases the strength against thermal strain and external stress.

[0062] Furthermore, the light detection device 100 offers advantages in its design. These will be explained in more detail later.

[0063] 2. Examples of Planar Layouts Several examples of planar layouts for chip 1 and chip 2, based on the technologies described above, are presented below.

[0064] Figures 8 to 13 show examples of planar layouts. Figure (A) of each figure schematically shows a planar layout of a part of chip 1. Figure (B) of each figure schematically shows a planar layout of a part of chip 2. As an example of multiple via group sections 5, three via group sections 5 arranged at intervals in the X-axis direction are shown.

[0065] In some configurations, the circuit section 4 on the chip 2 is also divided and arranged at intervals along the arrangement direction of the multiple via group sections 5. Specifically, in the examples shown in Figures 8 to 10 and Figure 12, the column processing section 42 of the circuit section 4 is divided and arranged to correspond to the multiple via group sections 5. The column processing section 42 connected to via group section 5-1 is referred to as column processing section 42-1 and is shown in the figure. The column processing section 42 connected to via group section 5-2 is referred to as column processing section 42-2 and is shown in the figure. When not specifically distinguished, they are simply called column processing section 42.

[0066] In the example shown in Figure 8, the distance between each of the multiple via group portions 5 and the pixel array portion 3 in the chip 1 is equal (in this example, the length in the Y-axis direction). That is, the distance between via group portion 5-1 and the central portion 31 of the pixel array portion 3, and the distance between via group portion 5-2 and the end portion 32 of the pixel array portion 3 are equal.

[0067] In the example shown in Figure 9, the photodetector 100 further includes wiring extending from the pad portion 6. Of the wiring extending from the pad portion 6, the wiring provided on the chip 1 is referred to as wiring 91 and is shown in the figure. Wiring 91 is composed of at least one of surface wiring and inner wiring. Wiring provided on the chip 2 is referred to as wiring 92 and is shown in the figure. Wiring 92 is composed of at least one of surface wiring and inner wiring.

[0068] Chip 1 has multiple wirings 91 corresponding to multiple pad portions 6, and each wiring 91 extends from the corresponding pad portion 6 to the pixel array portion 3. At least some of the wirings 91 extend between adjacent via group portions 5.

[0069] The chip 2 has multiple wirings 92 corresponding to multiple pad portions 6, and each wiring 92 extends from the corresponding pad portion 6 to the circuit portion 4, and more specifically in this example to the corresponding column processing portion 42. At least some of the wirings 92 extend between adjacent via group portions 5.

[0070] As mentioned earlier, a power supply voltage may be supplied to the pad section 6, and in this case, the wiring 91 and wiring 92 can be called power lines. Power lines may be a pair of wirings, for example, one of which has a power supply voltage and the other has a reference voltage (such as GND voltage). In the case of signal lines, a pair of wirings that handle differential signals may be used. Compared to the case where the via group section 5 is not divided, in chip 1, power and signals can be supplied from each pad section 6 to each part of the pixel array section 3 using short wiring 91. This reduces voltage variations in each part of the pixel array section 3 that may occur due to wiring length, and improves the characteristics. Similarly, in chip 2, voltage and signals can be supplied from each pad section 6 to each part of the circuit section 4 (each column processing section 42 in this example) using short wiring 92. This reduces voltage variations in each column processing section 42 that may occur due to wiring length, and improves the circuit characteristics.

[0071] In the example shown in Figure 10, the light detection device 100 is configured to have a distance measurement function. One example of a distance measurement method is ToF (Time of Flight), in which case the light detection device 100 emits pulsed light and detects the pulsed light reflected from the object to be measured with the pixels 30. The light source for emitting the pulsed light may also be included in the light detection device 100.

[0072] Each pixel 30 is driven to enable distance measurement. The drive signal for this purpose is called the distance measurement drive signal. The distance measurement drive signal is also supplied from the circuit section 4 of the chip 2 to each pixel 30 of the pixel array section 3 of the chip 1. The via group section 5 used for supplying the distance measurement drive signal is referred to as via group section 5-3 (third via group section) and is shown in the figure. Via group section 5-3 supplies the distance measurement drive signal to the corresponding pixel 30 of the pixel array section 3.

[0073] For the sake of explanation, in Figure 10, the signal line group 7 connected to via group 5-1 is referred to as signal line group 7-1. The signal line group 7 connected to via group 5-2 is referred to as signal line group 7-2. Pixel signals from the corresponding pixels 30 of the pixel array 3 are supplied to signal line group 7-1 and signal line group 7-2.

[0074] Multiple via group sections 5-3 are provided separately from via group sections 5-1 and 5-2, and are also arranged at intervals along the array direction so as to face the pixel array section 3. In this example, some via group sections 5-3 are arranged between other via group sections 5 (via group section 5-1, via group section 5-2).

[0075] A signal line group 7 also exists corresponding to each via group 5-3, and is referred to as signal line group 7-3 and shown in the figure. Each via group 5-3 is connected to the corresponding pixel 30 of the pixel array 3 via the corresponding signal line group 7-3. In this example, the signal lines of signal line group 7-3 corresponding to the same pixel 30 and the signal lines of signal line group 7-1 and signal line group 7-2 extend in different directions (they are not parallel).

[0076] Although not shown in Figure 10, the via group section 5-3 may be arranged, for example, so as to face the four sides of the pixel array section 3.

[0077] Since via group 5-3 is positioned at a distance from the other via group 5 (via group 5-1, via group 5-2), interference between the distance measuring drive signal and the pixel signal is made easier to prevent. In addition, supplying the distance measuring drive signal from multiple via group 5-3 makes it easier to suppress timing differences in signal supply to each pixel 30.

[0078] The circuit section 4 further includes a signal generation section 44. The signal generation section 44 is a circuit that generates the distance measuring drive signal described above, and can also be called a distance measuring drive circuit. Various known circuit configurations may be adopted. For specific examples, please refer to, for example, Patent Documents 2 and 3, and Non-Patent Documents 1 and 2. In the example shown in Figure 10(B), similar to the column processing section 42, the signal generation section 44 is divided and arranged to correspond to a plurality of via group sections 5-3. By arranging the column processing section 42 and the signal generation section 44 separately, interference can be easily suppressed.

[0079] Chip 2 has multiple drive lines DL corresponding to multiple via group sections 5-3, and each drive line DL extends from the corresponding via group section 5-3 to the circuit section 4, specifically the corresponding signal generation section 44 in this example. The distance measuring drive signal from the signal generation section 44 is supplied to the corresponding pixel 30 of the pixel array section 3 via the corresponding drive line DL, via group section 5-3, and signal line group 7-3.

[0080] In the example shown in Figure 11, the multiple via group sections 5 include via group sections 5 whose lengths in the arrangement direction differ from each other. This can contribute to increased design flexibility. The length of the via group section 5 may decrease as you move from the central section 31 of the pixel array section 3 towards the end section 32. In this example, the length of via group section 5-2 in the X-axis direction is smaller than the length of via group section 5-1. Conversely, the length of via group section 5-1 is larger than the length of via group section 5-2.

[0081] Similarly, the multiple parts of the divided circuit section 4 include parts whose lengths differ from each other in the orientation direction. In this example, the length of the column processing section 42-2 in the X-axis direction is shorter than the length of the column processing section 42-1. Conversely, the length of the column processing section 42-1 is longer than the length of the column processing section 42-2.

[0082] In the examples shown in Figures 12 and 13, multiple via groups 5 are arranged such that the lengths of each signal line within the signal line group 7 are equal. Here, "equal" may mean substantial equality and may include errors such as those caused by manufacturing variations.

[0083] By aligning the lengths of each signal line within the signal line group 7, stress on the via group 5 can be further reduced. In addition, the chip 2 is provided with multiple signal line groups 72 corresponding to multiple via group 5. Each signal line group 72 connects the circuit section 4 to the corresponding via group 5.

[0084] In the example shown in Figure 12, the distance between the via group 5 and the pixel array 3 decreases as you move from the central part 31 of the pixel array 3 towards the end part 32. The distance between via group 5-2 and the end part 32 of the pixel array 3 is smaller than the distance between via group 5-1 and the central part 31 of the pixel array 3.

[0085] The same applies to the distance between the via group section 5 and the circuit section 4 (the column processing section 42 in this example). That is, multiple via group sections 5 are arranged such that the distance between the via group section 5 and the circuit section 4 decreases as you move from the center of the circuit section 4 towards the edges.

[0086] In the example shown in Figure 13, the shape of the via group 5 is modified. The central part of the via group 5 in the direction of arrangement (in this example, the X-axis direction) is referred to as the central part 51 and is shown in the figure. The ends are referred to as the ends 52 and are shown in the figure. When the chip 1 is viewed from above, each via group 5 has a curved shape such that the distance between the via group 5 and the pixel array 3 (length in the Y-axis direction) decreases as you move from the central part 51 to the ends 52 of the via group 5. In each via group 5, the distance between the end 52 and the pixel array 3 is smaller than the distance between the central part 51 and the pixel array 3.

[0087] 3. Example of increasing pixel count The optical detection device 100 described above can change the size (area) of chips 1 and 2 by treating one via group 5 and its surrounding elements as a single unit element. Scaling can be easily performed even when increasing the number of pixels 30 that make up the pixel array 3 (increasing pixel count). This will be explained with reference to Figures 14 and 15.

[0088] Figure 14 shows an example of increasing the number of pixels. Three via group sections 5 and their surrounding elements are schematically shown from among the multiple via group sections 5 provided on the chip 1. To increase the number of pixels 30 in the pixel array section 3 (increase the number of pixels), the number of via group sections 5 and their surrounding elements should be increased in accordance with the increase in the number of pixels. In the example shown at the bottom of Figure 14, two more via group sections 5 are added to accommodate the increase in the number of pixels, and surrounding elements are also added along with them.

[0089] By adding via group sections 5 and their surrounding elements of the same size as a single unit, the technical advantages described above can be obtained even when the size (area) of chips 1 and 2 increases. The same applies when the size decreases. A comparative example will also be used to explain this.

[0090] Figure 15 shows a comparative example. As shown in the upper part of Figure 15, in the optical detection device 100E according to the comparative example, the via group section 5E is not divided. When increasing the number of pixels from this configuration, the slope of the signal lines in the signal line group 7E becomes even greater, as shown in the lower part of Figure 15. This is because, from the viewpoint of interference suppression, it is necessary to maintain the wiring spacing so that the wiring density does not become too high. There is also the option of increasing the wiring layer, but this complicates the wiring. Because the slope of the diagonal wiring is large, the distance between the via group section 5E and the pixel array section 3E also increases, and the signal lines in the signal line group 7E become longer. The wiring 91E connecting the pad section 6E and the pixel array section 3E also becomes longer.

[0091] In the optical detection device 100 according to this embodiment (Figure 14), the sizes of chips 1 and 2 can be easily changed while maintaining the patterns of each via group 5 and signal line group 7. Even when the size is increased, the distance between the via group 5 and the pixel array 3 remains small, the signal lines of the signal line group 7 do not become longer, and the variation remains small. Because the distance between the via group 5 and the pixel array 3 is small, the benefit of reducing the chip size can also be obtained. The same applies to the wiring 91 connecting the pad 6 and the pixel array 3.

[0092] By repeatedly arranging via group sections 5 with the same length and spacing (derivative design), the stress verification of via group sections 5 can be simplified.

[0093] 4. Example of Design Method The design method for the light detection device 100 is described below. The light detection device 100 can be designed by treating the via group section 5 and its surrounding elements as a single unit and repeatedly arranging these units. One unit is referred to as the unit layout L.

[0094] For example, a unit layout L includes a via group 5, a signal line group 7 corresponding to the via group 5, a portion of the pixel array 3 corresponding to the via group 5 (which can also be called a pixel block), and a portion of the circuit 4 corresponding to the via group 5 (which can also be called a circuit block). The unit layout L may be classified into several types. This will be explained with reference to Figure 16.

[0095] Figure 16 shows examples of unit layout L types. Four types of unit layout L are exemplified: unit layout La, unit layout Lb, unit layout Lc, and unit layout Ld. When no particular distinction is made between them, they are collectively referred to as unit layout L.

[0096] The unit layout La is part of the layout of the chip 1 and includes a via group 5 for connecting the pixel array section 3 and the column processing section 42, and its surrounding elements. Specifically, the unit layout La includes the via group 5, a signal line group 7 corresponding to the via group 5, and the portion of the pixel array section 3 corresponding to the via group 5. In this example, several pad sections 6 and wiring 91 are also included in the unit layout La.

[0097] The unit layout Lb is part of the layout of the chip 1 and includes via group sections 5 for connecting the pixel array section 3 and the processing control section 43, and its peripheral elements. Specifically, the unit layout Lb includes via group sections 5 and signal line groups 7 corresponding to one of the via group sections 5. In this example, several pad sections 6 and wiring 91 are also included in the unit layout Lb.

[0098] The unit layout Lc is part of the layout of the chip 2 and includes a via group 5 for connecting the pixel array section 3 and the processing control section 43, and its surrounding elements. Specifically, the unit layout Lc includes the via group 5 and the portion of the column processing section 42 and the processing control section 43 corresponding to the via group 5. In this example, several pad sections 6 are also included in the unit layout Lc.

[0099] The unit layout Ld is part of the layout of the chip 2 and includes a via group 5 for connecting the pixel array 3 and the processing control unit 43, and its peripheral elements. Specifically, the unit layout Ld includes the via group 5 and the portion of the processing control unit 43 corresponding to the via group 5. In this example, several pads 6 are also included in the unit layout Ld.

[0100] Figures 17 and 18 show design examples of the light detection device 100. (A) of each figure schematically shows the layout of chip 1. (B) of each figure schematically shows the layout of chip 2.

[0101] The photodetector 100 shown in Figure 17 is designed by repeatedly arranging two unit layouts L (La, Lb, Lc, and Ld) in a mirror arrangement. The photodetector 100 shown in Figure 18 is designed by repeatedly arranging four unit layouts L in a mirror arrangement. Scaling of chips 1 and 2 can be easily performed simply by adjusting the number of unit layouts L. For example, scaling can be performed by simply arranging the unit layouts L without changing the column pitch from an existing design, making design reuse easy. Furthermore, various factors such as the power supply capacity to each part of the pixel array section 3 and the circuit section 4, the variation in the characteristics of signal lines for pixel signals, etc., and the stress of the via group section 5 can be handled in the same way, making it easy to verify them and, consequently, design derivative types.

[0102] Figure 19 is a flowchart showing an example of a design method for the light detection device 100. Explanations of content that overlaps with previous explanations will be omitted as appropriate. In step S1, a unit layout L is prepared. For example, a unit layout L like the one shown in Figure 16, which was explained earlier, is prepared. In step S2, the unit layout L is repeatedly arranged. For example, the unit layout L is repeatedly arranged to match the number of pixels 30 in the pixel array section 3. The arrangement may be a mirror arrangement. In this way, for example, a light detection device 100 including chips 1 and 2 of a desired size can be easily designed.

[0103] 5. Example of Pad Configuration A specific example of the configuration of pad section 6 will be explained.

[0104] Figure 20 shows an example of the schematic configuration of the light detection device 100. The basic configuration of the light detection device 100 is the same as that shown in Figure 2. The pad portion 6 will be explained using cross-sectional views taken along lines A-A, B-B, and C-C in Figure 20.

[0105] 5.1 First Configuration Example Figure 21 shows a first configuration example of the pad portion 6. Figure 21(A) schematically shows a cross-section along the line A-A in Figure 20. Figure 21(B) schematically shows a cross-section along the line B-B in Figure 20. Figure 21(C) schematically shows a cross-section along the line C-C in Figure 20.

[0106] As mentioned in the previously described embodiment, the pad portion 6 includes a pad via 61. The pad via 61 extends through the chip 1 to the chip 2. More specifically, the pad via 61 extends from the back surface 1b, through the main surface 1a of the chip 1 and the main surface 2a of the chip 2, to the wiring 8 inside the chip 2.

[0107] <Manufacturing Method> Figure 22 shows an example of a manufacturing method for the light detection device 100. In particular, the process related to the formation of the pad portion 6 is shown.

[0108] As shown in Figure 22(A), prepare chip 1 including a wiring layer 11 and a semiconductor layer 12. As shown in Figure 22(B), prepare chip 2 including a wiring layer 21 and a semiconductor layer 22. As shown in Figure 22(C), bond the prepared chips 1 and 2 together. A via group portion 5 including vias 50 is obtained. As shown in Figure 22(D), form pad vias 61. A pad portion 6 including pad vias 61 is obtained.

[0109] 5.2 Second Configuration Example Figure 23 shows a second configuration example of the pad portion 6. Figure 23(A) schematically shows a cross-section along the line A-A in Figure 20. Figure 23(B) schematically shows a cross-section along the line B-B in Figure 20. Figure 23(C) schematically shows a cross-section along the line C-C in Figure 20.

[0110] The pad portion 6 includes a pad via 62 and an extension portion 63. The pad via 62 extends from the back surface 1b of the chip 1 into the chip 1. The extension portion 63 extends from the pad via 62 into the chip 2. In this example, the extension portion 63 includes wiring 8 provided on the chip 1, wiring 8 provided on the chip 2, vias connecting them, etc.

[0111] <Manufacturing Method> Figure 24 shows an example of a manufacturing method for the light detection device 100. In particular, the process related to the formation of the pad portion 6 is shown.

[0112] As shown in Figure 24(A), prepare chip 1 including a wiring layer 11 and a semiconductor layer 12. As shown in Figure 22(B), prepare chip 2 including a wiring layer 21 and a semiconductor layer 22. As shown in Figure 22(C), bond the prepared chips 1 and 2 together. A via group portion 5 including vias 50 and an extended portion 63 are obtained. As shown in Figure 22(D), form a pad via 62. A pad portion 6 including the pad via 62 and the extended portion 63 is obtained.

[0113] 5.3 Third Configuration Example Figure 25 shows a third configuration example of the pad portion 6. The pad portion 6 includes a pad wiring 64 and an extension portion 65. The pad wiring 64 is provided so as to be exposed on the side of the chip 1 opposite to the chip 2, i.e., on the back surface 1b of the chip 1. The material of the pad wiring 64 may be the same as the material of the wiring 8, and in this sense, the pad wiring 64 may be appropriately read as wiring 8. The extension portion 65 extends from the pad wiring 64 through the chip 1 to the inside of the chip 2. In this example, the extension portion 65 includes wiring provided on the chip 1, wiring provided on the chip 2, and vias, etc., that connect them.

[0114] In this third configuration example, as shown by the white arrow in Figure 25(B), in areas where the via group 5 does not exist, the uppermost wiring layers of the wiring layer 11 of chip 1 and the wiring layer 21 of chip 2 can be used. Furthermore, the pad wiring 64 can be arranged so that it overlaps the via group 5 when viewed from above, and this will be explained later with reference to Figure 27.

[0115] <Manufacturing Method> Figure 26 shows an example of a manufacturing method for the light detection device 100. In particular, the process related to the formation of the pad portion 6 is shown.

[0116] As shown in Figure 26(A), prepare chip 1 including a wiring layer 11 and a semiconductor layer 12. As shown in Figure 26(B), prepare chip 2 including a wiring layer 21 and a semiconductor layer 22. As shown in Figure 26(C), bond the prepared chips 1 and 2 together. A via group portion 5 including vias 50 and a portion of the extension portion 65 are obtained. As shown in Figure 26(D), form the pad wiring 64 and the remaining portion of the extension portion 65. A pad portion 6 including the pad wiring 64 and the extension portion 65 is obtained.

[0117] <Example of planar layout of pad portion 6> Figures 27 and 28 show an example of a planar layout of the pad portion 6.

[0118] The pad section 6 shown in Figure 27 has the same configuration as the third configuration example (Figure 25) described earlier, and includes pad wiring 64. In this example, when the chip 1 is viewed from above (viewed in the negative Z-axis direction), a portion of the pad wiring 64 overlaps with a portion of the via group section 5. This improves design flexibility. For example, the spacing of the via group section 5 can be narrowed, and manufacturing can be improved.

[0119] The pad section 6 shown in Figure 28(A) has the same configuration as the first configuration example (Figure 21) described earlier and includes a pad via 61. The pad section 6 shown in Figure 28(B) has the same configuration as the second configuration example (Figure 23) described earlier and includes a pad via 62. The shape, arrangement, etc., of the pad via 61 or pad via 62 are designed so that they do not overlap with the via group section 5 and the signal line group 7.

[0120] 6. Example of a separation structure In one embodiment, a separation structure may be provided between the via group portion 5 and the pad portion 6. This will be explained with reference to Figures 29 and 30.

[0121] Figures 29 and 30 show examples of separation structures. The photodetector 100 includes a separation structure 66. The separation structure 66 is provided between the pad portion 6 and the via group portion 5, spanning chip 1 and chip 2. The pad portion 6 and the via group portion 5 can be physically or electrically separated. Electrical interference can be suppressed and stress can be relieved. The separation structure may include wiring, vias, walls, etc.

[0122] In the example shown in Figure 30, a voltage in phase with the voltage supplied to the pad portion 6 is supplied to the isolation structure 66. The circuit that supplies voltage to the pad portion 6 is referred to as circuit 26 and is shown in the figure. The circuit that supplies voltage to the isolation structure 66 is referred to as circuit 266 and is shown in the figure. Circuits 26 and 266 are composed of, for example, transistors formed in the semiconductor layer 22 of the chip 2. By supplying a voltage in phase, the capacitance between the pad portion 6 and the isolation structure 66, for example, the capacitance between the vias and wiring of the pad portion 6 and the vias and wiring of the isolation structure 66 can be canceled out. This can contribute to increasing the speed of signals, etc.

[0123] 7. Others Above, the via group section 5, mainly for connecting the column processing section 42 of the circuit section 4 and the pixel array section 3, and its surrounding elements have been described. A similar configuration may also be applied to the via group section 5 for connecting the vertical drive circuit 41 of the circuit section 4 and the pixel array section 3.

[0124] The above explanation used a two-chip configuration, consisting of chip 1 and chip 2, as an example. However, the light detection device 100 may include three or more chips.

[0125] 7.1 Examples of Applications to Mobile Devices The technology relating to this disclosure (the Technology) can be applied to a variety of products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0126] Figure 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0127] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 31, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0128] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0129] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0130] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0131] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0132] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0133] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0134] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0135] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0136] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 31, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0137] Figure 32 shows an example of the installation position of the imaging unit 12031.

[0138] In Figure 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0139] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0140] Figure 32 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0141] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0142] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0143] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0144] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0145] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031, etc., among the configurations described above. Specifically, the light detection device 100 described earlier can be used as the imaging unit 12031. This makes it possible to improve the performance of the imaging unit 12031. For example, it becomes possible to obtain clearer images, thereby reducing driver fatigue.

[0146] 7.2 Application Examples to Endoscopic Surgical Systems The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be applied to an endoscopic surgical system.

[0147] Figure 33 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0148] Figure 33 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0149] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0150] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0151] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0152] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0153] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0154] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0155] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0156] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0157] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0158] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0159] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0160] Figure 34 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 33.

[0161] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0162] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0163] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0164] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0165] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0166] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0167] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0168] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0169] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0170] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0171] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0172] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0173] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0174] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0175] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0176] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0177] The above describes an example of an endoscopic surgical system to which the technology relating to this disclosure may be applied. The technology relating to this disclosure can be applied to the configuration described above, for example, the imaging unit 11402 of the camera head 11102. Specifically, the light detection device 100 described earlier can be used as the imaging unit 10402. This improves the performance of the imaging unit 11402. For example, a clearer image of the surgical site can be obtained, allowing the surgeon to reliably confirm the surgical site. A lower latency image of the surgical site can be obtained, allowing the surgeon to perform the procedure with the same sensation as when palpating the surgical site.

[0178] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0179] 8. Summary The technology described above can be identified, for example, as follows: One of the disclosed technologies is a photodetector 100. As described with reference to Figures 1 to 5, 8 to 13, 20, 21, 23, 25 and 27 to 30, the photodetector 100 comprises a chip 1 (first chip) and a chip 2 (second chip) stacked on top of each other, a pixel array section 3 provided on chip 1, a circuit section 4 provided on chip 2, a plurality of via group sections 5 provided across chip 1 and chip 2 and used to electrically connect the pixel array section 3 and the circuit section 4, and a plurality of signal line groups 7 provided on chip 1, each connecting the pixel array section 3 and a corresponding via group section 5 among the plurality of via group sections 5. The plurality of via group sections 5 are arranged at intervals along the array direction (for example, the X-axis direction and the Y-axis direction) so as to face the pixel array section 3. Each of the multiple signal line groups 7 connects a corresponding via group 5 from among the multiple via group sections 5 to a corresponding pixel 30 of the pixel array section 3.

[0180] According to the above-described optical detection device 100, since the via group section 5 is divided and arranged, the variation in the length of the signal lines of the multiple signal line groups 7 can be reduced. This reduces the variation in electrical characteristics and suppresses the degradation of the device's performance. Because the via group section 5 is divided and arranged, mechanical stress can be distributed. This increases the strength against thermal strain and external stress. In addition to these, various other technical advantages described above can be obtained.

[0181] As explained with reference to Figures 12 and 13, multiple via group sections 5 may be arranged such that the length of each signal line within the signal line group 7 is equal. This can further reduce variations in electrical characteristics. For example, as shown in Figure 12, multiple via group sections 5 may be arranged such that the distance between the via group section 5 and the pixel array section 3 decreases as you move from the central section 31 to the end section 32 of the pixel array section 3. Alternatively, as shown in Figure 13, each of the multiple via group sections 5 may have a curved shape so that when the chip 1 is viewed in plan (viewed in the negative Z-axis direction), the distance between the via group section 5 and the pixel array section 3 decreases as you move from the central section 51 to the end section 52 of the via group section 5. Furthermore, the light detection device 100 is provided on the chip 2 and includes multiple signal line groups 72, each connecting a circuit section 4 to a corresponding via group section 5 among the multiple via group sections 5, and multiple via group sections 5 may be arranged such that the length of each signal line within the signal line group 72 of the chip 2 is equal. The variation in electrical characteristics in circuit section 4 can also be reduced.

[0182] The circuit section 4 may be divided and arranged in accordance with the divided arrangement of the via group section 5. For example, as explained with reference to Figures 8 to 11 and Figure 13, the circuit section 4 may be divided and arranged with intervals along the arrangement direction of the multiple via group sections 5.

[0183] As explained with reference to Figure 11, etc., the multiple via group sections 5 may include via group sections 5 whose lengths in the arrangement direction differ from each other. This can contribute to improving design flexibility, etc.

[0184] As explained with reference to Figure 3, the circuit unit 4 may include a column processing unit 42 that processes pixel signals from the pixel array unit 3 for each pixel row. The circuit unit 4 may also include a vertical drive circuit 41 that drives the pixel array unit 3 for each pixel row. For example, via group units 5 for connecting such a circuit unit 4 to the pixel array unit 3 can be divided and arranged.

[0185] As described with reference to Figures 2 to 5, 8 to 13, 20, 21, 23, 25, 27, and 28, the light detection device 100 includes a plurality of pad portions 6 provided across chip 1 and chip 2, and at least some of the pad portions 6 may be located between adjacent via group portions 5 of the plurality of via group portions 5 when viewed from the pixel array portion 3. For example, as described with reference to Figure 9, the light detection device 100 includes a plurality of wirings 91 provided on chip 1, each extending from a corresponding pad portion 6 of the plurality of pad portions 6 to the pixel array portion 3, and at least some of the wirings 91 may extend between adjacent via group portions 5 of the plurality of via group portions 5. Each pad portion 6 can be connected to the corresponding part of the pixel array portion 3 with a short wiring 91. Similarly, the photodetector 100 includes a plurality of wirings 92 provided on the chip 2, each extending from a corresponding pad portion 6 of a plurality of pad portions 6 to a circuit portion 4, and at least some of the wirings 92 may extend between adjacent via group portions 5 of a plurality of via group portions 5. Short wirings 92 can be used to connect the pad portions 6 to the corresponding portions of the circuit portion 4 (for example, each column processing portion 42). Variations that may occur due to wiring length can be reduced and characteristics can be improved.

[0186] Various configurations of the pad portion 6 can be used. For example, as explained with reference to Figures 4, 5 and 21, the pad portion 6 may include a pad via 61 that penetrates the chip 1 and extends to the chip 2. Alternatively, as explained with reference to Figure 23, the pad portion 6 may include a pad via 62 that extends into the chip 1 and an extension portion 63 that extends from the pad via 62 into the chip 2. Alternatively, as explained with reference to Figure 25, the pad portion 6 may include a pad wiring 64 provided on the back surface 1b of the chip 1 (the side of the chip 1 opposite to the chip 2) and an extension portion 65 that extends from the pad wiring 64 through the chip 1 into the chip 2. In this case, as explained with reference to Figure 27, when the chip 1 is viewed in plan (viewed in the negative Z-axis direction), a part of the pad wiring 64 may overlap with a part of the via group portion 5. This improves the degree of design freedom.

[0187] As explained with reference to Figures 29 and 30, the photodetector 100 may include a separation structure 66 provided between the pad section 6 and the via group section 5. The pad section 6 and the via group section 5 can be physically or electrically separated. As explained with reference to Figure 30, a voltage in phase with the voltage supplied to the pad section 6 may be supplied to the separation structure 66. This can cancel capacitance and contribute to increasing the speed of the signal.

[0188] The degree of freedom in signal wiring layout is increased, making it easier to supply signals related to distance measurement, for example. As explained with reference to Figure 10, etc., signal line group 7 includes signal line groups 7-1 and 7-2 to which pixel signals from corresponding pixels 30 of the pixel array unit 3 are supplied, and signal line group 7-3 to which distance measurement drive signals are supplied to corresponding pixels 30 of the pixel array unit 3. The signal lines of these signal line groups 7-1, 7-2 and signal line group 7-3 corresponding to the same pixel 30 may extend in different directions from each other.

[0189] The design method for the photodetector 100, as described with reference to Figures 16 to 19, is also one of the disclosed technologies. The design method for the photodetector 100 having the above configuration includes preparing a unit layout L for the photodetector 100 (step S1) and repeatedly arranging the prepared unit layout L (step S2). The unit layout L includes a via group section 5, a signal line group 7 corresponding to the via group section 5, a portion of the pixel array section 3 corresponding to the via group section 5 (pixel block), and a portion of the circuit section 4 corresponding to the via group section (circuit block). By simply adjusting the number of unit layouts L, the chips 1 and 2 can be easily scaled. Design reuse is also easy. Furthermore, various factors such as power supply capacity, signal line characteristic variations, and stress can be handled similarly, making it easy to verify them.

[0190] The effects described in this disclosure are merely illustrative and not limited to those disclosed. Other effects may also occur.

[0191] While embodiments of this disclosure have been described above, the technical scope of this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Furthermore, components from different embodiments and modifications may be combined as appropriate.

[0192] Furthermore, this technology can also take the following configurations: (1) A light detection device comprising: a first chip and a second chip stacked on top of each other; a pixel array portion provided on the first chip; a circuit portion provided on the second chip; a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion; and a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions and a corresponding pixel in the pixel array portion. (2) The light detection device according to (1), wherein the plurality of via group portions are arranged such that the lengths of each signal line in the signal line group are equal. (3) The optical detection device according to (2), wherein the plurality of via group portions are arranged such that the distance between the via group portion and the pixel array portion decreases as you move from the center of the pixel array portion towards the edge. (4) The optical detection device according to (2), wherein each of the plurality of via group portions has a curved shape such that when the first chip is viewed from above, the distance between the via group portion and the pixel array portion decreases as you move from the center of the via group portion towards the edge. (5) The optical detection device according to any one of (2) to (4), wherein the second chip is provided with a plurality of signal line groups, each connecting the circuit portion and a corresponding via group portion among the plurality of via group portions, and the plurality of via group portions are arranged such that the lengths of each signal line in the signal line group of the second chip are equal. (6) The optical detection device according to any one of (1) to (5), wherein the circuit portion is divided and arranged at intervals along the direction of arrangement of the plurality of via group portions. (7) The photodetector according to any one of (1) to (6), wherein the plurality of via group portions include via group portions whose lengths in the arrangement direction of the plurality of via group portions differ from each other.(8) The photodetector according to any one of (1) to (7), wherein the circuit section includes a column processing section that processes pixel signals from the pixel array section for each pixel row. (9) The photodetector according to any one of (1) to (8), wherein the circuit section includes a vertical drive circuit that drives the pixel array section for each pixel row. (10) The photodetector according to any one of (1) to (9), comprising a plurality of pad sections provided across the first chip and the second chip, wherein, when viewed from the pixel array section, at least some of the pad sections of the plurality of pad sections are located between adjacent via group sections of the plurality of via group sections. (11) The photodetector according to (10), comprising a plurality of wiring provided on the first chip, each extending from a corresponding pad section of the plurality of pad sections to the pixel array section, wherein at least some of the wiring extends between adjacent via group sections of the plurality of via group sections. (12) The photodetector according to (10) or (11), wherein the second chip is provided with a plurality of wirings, each extending from a corresponding pad portion of the plurality of pad portions to the circuit portion, and at least a portion of the wirings extends between adjacent via groups of the plurality of via groups. (13) The photodetector according to any one of (10) to (12), wherein the pad portion includes a pad via that penetrates the first chip and extends to the second chip. (14) The photodetector according to any one of (10) to (12), wherein the pad portion includes a pad via that extends into the first chip and an extending portion that extends from the pad via through the first chip to the second chip. (15) The photodetector according to any one of (10) to (12), wherein the pad portion includes a pad wiring provided on the side of the first chip opposite to the second chip, and an extending portion extending from the pad wiring through the first chip to the inside of the second chip. (16) The photodetector according to (15), wherein when the first chip is viewed from above, a part of the pad wiring overlaps with a part of the via group portion.(17) The optical detection device according to any one of (10) to (16), further comprising a separation structure provided between the pad portion and the via group portion. (18) The optical detection device according to (17), wherein a voltage in phase with the voltage supplied to the pad portion is supplied to the separation structure. (19) The optical detection device according to any one of (1) to (18), wherein the signal line group includes a signal line group to which pixel signals from corresponding pixels of the pixel array portion are supplied, and a signal line group to which distance measuring drive signals are supplied to corresponding pixels of the pixel array portion, and the signal lines of those signal line groups corresponding to the same pixel extend in different directions from each other. (20) A method for designing a photodetector, the photodetector comprising: a first chip and a second chip stacked on top of each other; a pixel array portion provided on the first chip; a circuit portion provided on the second chip; a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion; a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions to a corresponding pixel of the pixel array portion, the design method comprising: preparing a unit layout for the photodetector; and repeatedly arranging the prepared unit layout. A method for designing an optical detection device, wherein the unit layout includes a via group section, a signal line group corresponding to the via group section, a portion of the pixel array section corresponding to the via group section, and a portion of the circuit section corresponding to the via group section.

[0193] 1 Chip 1a Main surface 1b Back surface 11 Wiring layer 12 Semiconductor layer 2 Chip 2a Main surface 2b Back surface 21 Wiring layer 22 Semiconductor layer 26 Circuit 266 Circuit 3 Pixel array section 30 Pixel 31 Center section 32 Edge section 4 Circuit section 41 Vertical drive circuit 42 Column processing section 43 Processing control section 44 Signal generation section 5 Via group section 50 Via 51 Center section 52 Edge section 6 Pad section 61 Pad via 62 Pad via 63 Extension section 64 Pad wiring 65 Extension section 66 Separation structure 7 Signal line group 72 Signal line group 8 Wiring 91 Wiring 92 Wiring 100 Photodetector DL ​​Drive wiring L Unit layout La Unit layout Lb Unit layout Lc Unit layout Ld Unit layout

Claims

1. A light detection device comprising: a first chip and a second chip stacked on top of each other; a pixel array portion provided on the first chip; a circuit portion provided on the second chip; a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion; and a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions and a corresponding pixel in the pixel array portion.

2. The optical detection device according to claim 1, wherein the plurality of via groups are arranged such that the lengths of each signal line within the signal line group are equal.

3. The photodetector according to claim 2, wherein the plurality of via groups are arranged such that the distance between the via group and the pixel array decreases as you move from the center of the pixel array towards the edges.

4. The light detection device according to claim 2, wherein each of the plurality of via group portions has a curved shape such that, when the first chip is viewed from above, the distance between the via group portion and the pixel array portion decreases as the distance from the center of the via group portion toward the edge decreases.

5. The photodetector according to claim 2, comprising a plurality of signal line groups provided on the second chip, each connecting the circuit section to a corresponding via group section among the plurality of via group sections, wherein the plurality of via group sections are arranged such that the lengths of each signal line within the signal line group of the second chip are equal.

6. The light detection device according to claim 1, wherein the circuit section is divided and arranged at intervals along the arrangement direction of the plurality of via group sections.

7. The photodetector according to claim 1, wherein the plurality of via group portions include via group portions whose lengths in the arrangement direction of the plurality of via group portions differ from each other.

8. The photodetector according to claim 1, wherein the circuit section includes a column processing section that processes pixel signals from the pixel array section for each pixel row.

9. The photodetector according to claim 1, wherein the circuit section includes a vertical drive circuit that drives the pixel array section for each pixel row.

10. The photodetector according to claim 1, comprising a plurality of pad portions provided across the first chip and the second chip, wherein, when viewed from the pixel array portion, at least some of the pad portions of the plurality of pad portions are located between adjacent via groups of the plurality of via groups.

11. The photodetector according to claim 10, comprising a plurality of wirings provided on the first chip, each extending from a corresponding pad portion among the plurality of pad portions to the pixel array portion, wherein at least a portion of the wirings extends between adjacent via group portions among the plurality of via group portions.

12. The photodetector according to claim 10, wherein the second chip is provided with a plurality of wirings, each extending from a corresponding pad portion among the plurality of pad portions to the circuit portion, and at least a portion of the wirings extends between adjacent via group portions among the plurality of via group portions.

13. The photodetector according to claim 10, wherein the pad portion includes a pad via that penetrates the first chip and extends to the second chip.

14. The photodetector according to claim 10, wherein the pad portion includes a pad via extending into the first chip and an extending portion extending from the pad via through the first chip into the second chip.

15. The photodetector according to claim 10, wherein the pad portion includes a pad wiring provided on the side of the first chip opposite to the second chip, and an extending portion extending from the pad wiring through the first chip to the inside of the second chip.

16. The light detection device according to claim 15, wherein, when the first chip is viewed from above, a portion of the pad wiring overlaps with a portion of the via group.

17. The photodetector according to claim 10, further comprising a separation structure provided between the pad portion and the via group portion.

18. The photodetector according to claim 17, wherein a voltage in phase with the voltage supplied to the pad portion is supplied to the separation structure.

19. The photodetector according to claim 1, wherein the signal line group includes a signal line group to which pixel signals from corresponding pixels of the pixel array are supplied, and a signal line group to which distance measuring drive signals are supplied to corresponding pixels of the pixel array, and the signal lines of those signal line groups corresponding to the same pixel extend in different directions from each other.

20. A method for designing a photodetector, the photodetector comprising: a first chip and a second chip stacked on top of each other; a pixel array portion provided on the first chip; a circuit portion provided on the second chip; a plurality of via group portions provided across the first chip and the second chip and used to electrically connect the pixel array portion and the circuit portion; a plurality of signal line groups provided on the first chip, each connecting the pixel array portion and a corresponding via group portion among the plurality of via group portions, wherein the plurality of via group portions are spaced apart along the array direction so as to face the pixel array portion, and each of the plurality of signal line groups connects a corresponding via group portion among the plurality of via group portions to a corresponding pixel in the pixel array portion, the design method comprising: preparing a unit layout for the photodetector; and repeatedly arranging the prepared unit layout. A method for designing an optical detection device, wherein the unit layout includes a via group section, a signal line group corresponding to the via group section, a portion of the pixel array section corresponding to the via group section, and a portion of the circuit section corresponding to the via group section.

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