Silicon carbide semiconductor device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-02-03
- Publication Date
- 2026-08-13
Smart Images
Figure JP2026003861_13082026_PF_FP_ABST
Abstract
Description
Silicon carbide semiconductor equipment Cross-references to related applications
[0001] This application is based on Japanese Patent Application No. 2025-017857, filed on February 5, 2025, the contents of which are incorporated herein by reference.
[0002] This disclosure relates to a SiC semiconductor device constructed using silicon carbide (hereinafter simply referred to as SiC).
[0003] Conventionally, SiC semiconductor devices have been proposed in which MOSFETs (i.e., Metal Oxide Semiconductor Field Effect Transistors) with a p-type base layer and an n-type source region are formed on a semiconductor substrate made of SiC. Development efforts are underway to reduce the on-resistance of such SiC semiconductor devices. However, as the on-resistance of a SiC semiconductor device decreases, the saturation current increases. Therefore, if a short circuit occurs in the load to which the SiC semiconductor device is connected, the SiC semiconductor device may be destroyed by the flow of a large current.
[0004] Therefore, for example, Non-Patent Document 1 describes locally forming a low-doping concentration region in the source region, where the doping concentration is lower than that of the source region. In such a SiC semiconductor device, when a large current flows and the temperature of the SiC semiconductor device rises, the resistance of the low-doping concentration region increases. As a result, when the load to which the SiC semiconductor device is connected is short-circuited, the increased resistance of the low-doping concentration region reduces the current that can flow through the SiC semiconductor device, thereby suppressing damage to the SiC semiconductor device.
[0005] World's Lowest Power Loss SiC Power Semiconductor Device Developed (October 29, 2014, Internet Search) <URL: http: / / www.mitsubishielectric.co.jp / news / 2017 / pdf / 0922.pdf>
[0006] However, in SiC semiconductor devices as described above, the manufacturing process tends to become complex because a localized low-doping concentration region is formed within a narrow source region.
[0007] The purpose of this disclosure is to provide a SiC semiconductor device that can suppress destruction while also making it easier to suppress the complexity of the manufacturing process.
[0008] According to one aspect of this disclosure, the SiC semiconductor device comprises an impurity layer of a first conductivity type or a second conductivity type, a drift layer of a first conductivity type disposed on the impurity layer and having a lower doping concentration than the impurity layer, a base layer of a second conductivity type disposed on the drift layer, an impurity region of a first conductivity type disposed on the surface of the base layer and having a higher doping concentration than the drift layer, a gate insulating film disposed on the surface of the base layer between the drift layer and the impurity region, a gate electrode disposed on the gate insulating film, a first electrode electrically connected to the base layer and the impurity region, and a second electrode electrically connected to the impurity layer, wherein when a predetermined voltage is applied to the gate electrode, a channel is formed in the portion of the base layer between the drift layer and the impurity region and current flows, and the drift layer has a low-doping concentration region located away from the base layer and having a lower doping concentration than the drift layer.
[0009] According to this, the drift layer contains a low-doping concentration region with a lower doping concentration than the drift layer itself. Therefore, when a load connected to the SiC semiconductor device short-circuits and a large current flows, the resistance of the low-doping concentration region increases, resulting in a higher on-resistance. Consequently, the reduced current flow suppresses the temperature rise of the SiC semiconductor device, thus preventing damage to the SiC semiconductor device. Furthermore, the low-doping concentration region is located in a drift layer that is sufficiently larger than the impurity region (e.g., the source region). Therefore, compared to the case where the low-doping concentration region is locally located within the impurity region, the complexity of the manufacturing process can be suppressed. In addition, the low-doping concentration region is located away from the base layer. Therefore, when the SiC semiconductor device is in the ON state, electrons flowing from the impurity region through the channel diffuse through the drift layer before flowing into the low-doping concentration region. Consequently, compared to the case where the low-doping concentration region is located in contact with the bottom surface of the base layer, the increase in on-resistance caused by arranging the low-doping concentration region can be suppressed.
[0010] This is a cross-sectional view of a SiC semiconductor device in the first embodiment. This is a perspective cross-sectional view of a cell region. This is a diagram illustrating the relationship between temperature and mobility. This is a diagram illustrating the relationship between temperature and resistance. This is a diagram showing the relationship between time and current for a SiC semiconductor device in the first embodiment and a comparative example. This is a diagram showing the relationship between time and temperature for a SiC semiconductor device in the first embodiment and a comparative example. This is a diagram showing the temperature distribution in a planar gate type SiC semiconductor device. This is a cross-sectional view of a SiC semiconductor device in the second embodiment. This is a cross-sectional view of a SiC semiconductor device in the third embodiment. This is a cross-sectional view of a SiC semiconductor device in the fourth embodiment.
[0011] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.
[0012] (First Embodiment) The SiC semiconductor device of the first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device in which a trench gate structure MOSFET is formed in the cell region RS will be described.
[0013] As shown in Figure 1, the SiC semiconductor device has a configuration comprising a cell region RS on which a trench gate structure MOSFET is formed, and an outer peripheral region RO surrounding the cell region RS. The outer peripheral region RO has a configuration comprising a guard ring region RG and a connecting region RJ located on the cell region RS side of the guard ring region RG. In other words, the outer peripheral region RO has a configuration comprising a guard ring region RG and a connecting region RJ located between the cell region RS and the guard ring region RG.
[0014] As shown in Figures 1 and 2, the SiC semiconductor device comprises a semiconductor substrate 10 having one surface 10a and the other surface 10b. In the following description, the depth (i.e., thickness) direction of the semiconductor substrate 10 will be referred to as the Z-axis direction, one direction parallel to the surface 10a of the semiconductor substrate 10 (i.e., one direction perpendicular to the Z-axis direction) will be referred to as the X-axis direction, and the directions perpendicular to the X-axis direction and the Z-axis direction will be referred to as the Y-axis direction. Note that the Z-axis direction is also the normal direction to the surface 10a of the semiconductor substrate 10. The Y-axis direction can also be referred to as the first direction, the X-axis direction as the second direction, and the Z-axis direction as the third direction. Furthermore, in the following description, the part of each part located on the surface 10a side of the semiconductor substrate 10 will be referred to as the top surface or upper part, and the part located on the other surface 10b side of the semiconductor substrate 10 will be referred to as the bottom surface or lower part. Furthermore, in the following description, the direction toward the other surface 10b side of the semiconductor substrate 10 will be referred to as downward, and the direction toward the surface 10a side of the semiconductor substrate 10 will be referred to as upward.
[0015] The semiconductor substrate 10 has n that constitutes the other surface 10b ＋ It is equipped with a substrate 11 of type n. The substrate 11 is made of a SiC single crystal substrate or the like, and for example, the doping concentration of n type is 1.0 × 10 １９ cm －３It is assumed that the surface is the (0001) Si plane and the off-direction is the <11-20> direction. In this embodiment, the substrate 11 corresponds to the impurity layer and constitutes the drain layer.
[0016] On the substrate 11, an n-type drift layer 12 made of SiC with a lower doping concentration than the substrate 11 is formed. － The drift layer 12 is, for example, 5.0×10 １６ cm －３ or more, and the doping concentration is higher than that of the low doping concentration region 81 described later. And on the drift layer 12, in the cell region RS and the connecting region RJ, a p-type base layer 13 is formed. －
[0017] The base layer 13 is a portion where a channel is formed. For example, the p-type doping concentration is about 2.0×10 １７ cm －３ and the thickness is 300 nm. In the surface layer portion of the base layer 13, in the cell region RS, a source region 14 with a higher n-type doping concentration than the drift layer 12 and a contact region 15 with a higher p-type doping concentration than the base layer 13 are formed. Specifically, a plurality of source regions 14 are formed at predetermined distances in the X-axis direction, and the contact region 15 is disposed between adjacent source regions 14 in the X-axis direction.
[0018] The source region 14, for example, has an n-type doping concentration of 2.5×10 １８ cm －３ or more and 1.0×10 １９ cm －３ or less, and the thickness is about 0.5 μm. The contact region 15, for example, has a p-type doping concentration of 2.5×10 １８ cm －３ or more and 1.0×10 １９ cm －３ or less, and the thickness is about 0.5 μm. In this embodiment, the source region 14 corresponds to the impurity region. Also, in this embodiment, in the base layer 13 in the connecting region RJ, a contact region 16 is formed in the surface layer portion.
[0019] In this embodiment, in the guard ring region RG, a recess 20 is formed so as to penetrate the base layer 13 from one side 10a of the semiconductor substrate 10 and reach the drift layer 12. As a result, the cell region RS and the connecting region RJ are mesa portions that protrude more than the guard ring region RG.
[0020] In the cell region RS, multiple trenches 31 are formed, for example, with a width of 0.8 μm and a depth of 1.0 μm, penetrating the base layer 13 and the source region 14 to reach the drift layer 12. More specifically, each trench 31 is formed with the Y-axis direction as its longitudinal direction, and these are arranged at equal intervals in the X-axis direction to form a stripe pattern.
[0021] The inner surface (i.e., the side and bottom surface) of each trench 31 is covered with a gate insulating film 32. A gate electrode 33 is positioned on the gate insulating film 32 within each trench 31. Each gate electrode 33 is insulated from the semiconductor substrate 10 by the gate insulating film 32. The upper surface of each gate electrode 33 is covered with an interlayer insulating film 40 positioned on one surface 10a of the semiconductor substrate 10. The interlayer insulating film 40 is also positioned in the outer peripheral region RO. In this embodiment, the portion of the inner surface of the trench 31 located between the drift layer 12 and the source region 14 corresponds to the surface of the base layer 13 located between the drift layer 12 and the source region 14.
[0022] Furthermore, in the cell region RS of this embodiment, a p-type trench lower layer 51 is formed in the portion of the drift layer 12 facing the lower part of each trench 31, with a higher p-type doping concentration than the base layer 13. In this embodiment, the trench lower layer 51 is formed to be in contact with the lower part of the trench 31 (i.e., the gate insulating film 32 located at the lower part of the trench 31). However, the trench lower layer 51 may be formed slightly away from the lower part of the corresponding trench 31.
[0023] When viewed from the Z-axis direction, the trench lower layer 51 extends long along the longitudinal direction of the corresponding trench 31 (i.e., the Y-axis direction), and continuously extends from one end to the other end in the longitudinal direction of the trench 31. In the present embodiment, an example where the trench lower layer 51 continuously extends from one end to the other end in the longitudinal direction of the trench 31 will be described. However, the trench lower layer 51 may be arranged so as to have a portion divided between one end and the other end in the longitudinal direction of the trench 31.
[0024] In the cell region RS, a p-type deep layer 52 having a higher p-type doping concentration than the base layer 13 is formed on the surface layer portion of the drift layer 12. Specifically, the deep layer 52 protrudes in the Z-axis direction from the lower surface of the base layer 13 and is formed to extend long in the X-axis direction. That is, the deep layer 52 is formed so as to be orthogonal to the longitudinal direction of the trench 31 (i.e., the Y-axis direction in the present embodiment). In FIG. 2, only one deep layer 52 is shown, but actually a plurality of deep layers 52 are arranged at intervals in the Y-axis direction.
[0025] The deep layer 52 is formed deeper than the lower part of the trench 31. And the deep layer 52 intersects with the trench lower layer 51 disposed below the trench 31 and is connected to the trench lower layer 51. Thereby, the trench lower layer 51 is connected to the base layer 13 via the deep layer 52. Note that the deep layer 52 may extend to the connection region RJ in addition to the cell region RS.
[0026] In the interlayer insulating film 40 disposed on one surface 10a of the semiconductor substrate 10, contact holes 41 for exposing the source region 14 and the contact region 15 are formed in the cell region RS. Also, in the interlayer insulating film 40, contact holes 42 for exposing the contact region 16 are formed in the connection region RJ.
[0027] On the interlayer insulating film 40, a source electrode 61, a gate wiring layer (not shown), and the like are formed. The source electrode 61 and the gate wiring layer are configured such that the portions in contact with the n-type source region 14 can form an ohmic contact with n-type SiC, and the portions in contact with the p-type contact regions 15 and 16 can form an ohmic contact with p-type SiC, and are made of, for example, Al—Si or the like. The source electrode 61 is electrically connected to the source region 14 and the contact region 15 through the contact hole 41 in the cell region RS. The source electrode 61 is electrically connected to the contact region 16 through the contact hole 42 in the connection region RJ. The gate wiring layer is electrically connected to the gate electrode 33 in a cross section different from that in FIG. 1. In the present embodiment, the source electrode 61 corresponds to the first electrode.
[0028] On the other surface 10b side of the semiconductor substrate 10, a drain electrode 62 corresponding to a second electrode electrically connected to the substrate 11 is disposed.
[0029] In the guard ring region RG, as described above, the recess 20 is formed so as to penetrate the base layer 13 and reach the drift layer 12. Therefore, at a position away from the cell region RS, the source region 14 and the base layer 13 are removed and the drift layer 12 is exposed. The interlayer insulating film 40 is disposed on the drift layer 12 in the guard ring region RG.
[0030] In the guard ring region RG, a plurality of p-type guard rings 71 are provided on the surface layer portion of the drift layer 12 so as to surround the cell region RS and the connection region RJ. The guard ring 71 is, for example, in a rectangular shape with rounded corners when viewed from the Z-axis direction, but may be in a circular shape or the like.
[0031] In addition, in the guard ring 71 of the present embodiment, the interval between the guard rings 71 in the portion on the cell region RS side is made narrower than the interval between the guard rings 71 in the portion on the side opposite to the cell region RS side. However, the intervals between the guard rings 71 may be equal.
[0032] The above describes the basic configuration of the SiC semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. The drift layer 12 in this embodiment is formed, for example, by epitaxial growth of SiC on the substrate 11. The base layer 13, source region 14, contact regions 15, 16, etc., are formed, for example, by ion implantation of impurities into the epitaxial layer.
[0033] Furthermore, in this embodiment, a low-doping concentration region 81 is provided in the drift layer 12, where the n-type doping concentration is lower than that of the drift layer 12. In this embodiment, the low-doping concentration region 81 is arranged planarly so as to divide the drift layer 12 into a portion on one side 10a of the semiconductor substrate 10 and a portion on the other side 10b.
[0034] Furthermore, the low-doping concentration region 81 is located below the current diffusion layer 12a, where the portion of the drift layer 12 located between adjacent trenches 31 in the X-axis direction is considered the current diffusion layer 12a. In other words, the low-doping concentration region 81 is located on the current diffusion layer 12a side of the drift layer 12, for example, in the drift layer 12, it is located in a portion of the drift layer 12 that is less than 1 / 3 of the thickness of the drift layer 12 from the interface with the lower surface of the base layer 13. In this embodiment, the low-doping concentration region 81 is located in contact with the trench lower layer 51 and the deep layer 52. However, the low-doping concentration region 81 is located away from the base layer 13. For example, the low-doping concentration region 81 is located at a distance of the thickness of the low-doping concentration region 81 from the base layer 13. In other words, the low-doping concentration region 81 is located between the base layer 13 and the low-doping concentration region 81, such that a drift layer 12 of approximately the same thickness as the low-doping concentration region 81 is located between the base layer 13 and the low-doping concentration region 81. Furthermore, the low-doping concentration region 81 in this embodiment is formed only in the cell region RS and not in the outer peripheral region RO.
[0035] In this embodiment, the low doping concentration region 81 is configured, for example, by adjusting the supply amount of dopant gas such as nitrogen supplied during epitaxial growth of the drift layer 12. In this case, the doping concentration is 1.0 × 10⁻⁶ １５ cm －３ If the concentration is less than 5.0 × 10⁻¹⁰, the constraints during the manufacturing process will increase, potentially making the manufacturing process more complex. Also, as will be discussed later, the doping concentration is 5.0 × 10⁻¹⁰. １６ cm －３ As a result, the effect of phonon scattering becomes less pronounced, and the resistance does not increase easily even at high temperatures. Therefore, in this embodiment, the low doping concentration region 81 is defined as a doping concentration of 1.0 × 10⁻⁶ １５ cm －３ The above 5.0 x 10 １６ cm －３ It is set to be less than [amount missing]. In addition, in this embodiment, the low doping concentration region 81 has a thickness of 0.2 μm or more and 2 μm or less.
[0036] The above describes the configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, when a potential higher than that of the source electrode 61 is applied to the drain electrode 62 and a potential above the gate threshold is applied to the gate electrode 33, a channel is formed in the portion of the base layer 13 that is in contact with the gate insulating film 32. The source region 14 and the drift layer 12 are then connected through the channel. As a result, electrons flow from the source region 14 to the substrate 11 via the channel and the drift layer 12, and the SiC semiconductor device enters an ON state in which current flows. At this time, the electrons flowing from the source region 14 to the drift layer 12 through the channel are diffused in the current diffusion layer 12a as they flow. In other words, in this embodiment, the portion of the drift layer 12 into which electrons flow through the channel becomes the current diffusion layer 12a. Also, in this embodiment, the low doping concentration region 81 is located away from the base layer 13. As a result, electrons flowing from the source region 14 through the channel are diffused in the drift layer 12 before flowing into the low doping concentration region 81. In other words, in this embodiment, when electrons flow through the channel to the drift layer 12, the electrons do not flow directly into the low-doping concentration region 81 with high resistance, but rather diffuse before flowing into the low-doping concentration region 81. Therefore, compared to the case where the low-doping concentration region 81 is placed in contact with the lower surface of the base layer 13, the increase in on-resistance can be suppressed by placing the low-doping concentration region 81.
[0037] Furthermore, in the SiC semiconductor device, when the potential of the gate electrode 33 is lowered from a value above the gate threshold to a value below the gate threshold, the channel disappears, the flow of electrons stops, and the device enters an off state where no current flows.
[0038] When the SiC semiconductor device is in the off state, a reverse voltage is applied to the pn junction between the trench lower layer 51 and the deep layer 52 and the drift layer 12. As a result, the depletion layer spreads from the trench lower layer 51 and the deep layer 52 to the drift layer 12. Consequently, the electric field concentration near the bottom of the trench 31 is mitigated, and the drain-source DS breakdown voltage is improved.
[0039] Here, the mobility of the carrier (i.e., electrons in this embodiment) is affected by impurity scattering and phonon scattering. Specifically, as shown in Figure 3, mobility is more susceptible to impurity scattering at temperatures below room temperature and more susceptible to phonon scattering at temperatures above room temperature (e.g., several hundred degrees Celsius). Furthermore, the carrier mobility also depends on the doping concentration; at lower doping concentrations, it is more susceptible to impurity scattering and phonon scattering than at higher doping concentrations. In Figure 3, a low concentration is represented as a doping concentration of 1.0 × 10⁻⁶. １５ cm －３ The above 5.0 x 10 １６ cm －３ Assuming the case is less than 5.0, a high concentration would be considered a doping concentration of 5.0 × 10⁻⁶. １６ cm －３ The relationships shown are based on the above scenarios.
[0040] Furthermore, resistance is inversely proportional to the product of mobility and doping concentration. Therefore, the relationship between resistance, temperature, and doping concentration is as shown in Figure 4. That is, as shown in Figure 4, when the doping concentration is low, resistance increases sharply as the temperature increases. For this reason, the low doping concentration region 81 does not increase the on-resistance at normal operating temperatures (for example, around room temperature), but the resistance increases at high temperatures, increasing the on-resistance of the SiC semiconductor device.
[0041] Hereafter, a SiC semiconductor device in which the drift layer 12 does not have a low-doping concentration region 81 and the other configurations are the same as those of the SiC semiconductor device of this embodiment will be referred to as the comparative example SiC semiconductor device. When the connected load is short-circuited, a large current flows through the SiC semiconductor device. In this case, as shown in Figures 5 and 6, when the temperature of the SiC semiconductor device of this embodiment rises to a predetermined temperature at time T1 due to the flow of current, the resistance of the low-doping concentration region 81 increases, so the rate of increase in the flowing current decreases. Therefore, the SiC semiconductor device of this embodiment is prevented from continuing to rise in temperature and is prevented from being destroyed. On the other hand, in the comparative example SiC semiconductor device, the temperature rises as the current increases over time and it is destroyed at time T2.
[0042] Furthermore, the inventors investigated the temperature distribution of a SiC semiconductor device when a load is short-circuited and a large current flows, and obtained the results shown in Figure 7. Figure 7 shows the temperature distribution results for a planar gate type SiC semiconductor device. In the planar gate type SiC semiconductor device shown in Figure 7, a base layer 13 is selectively formed on the surface of the drift layer 12, and a source region 14 is formed on the surface of the base layer 13. The gate electrode 33 is positioned to face the portion of the base layer 13 that is between the drift layer 12 and the source region 14.
[0043] In such a planar gate type SiC semiconductor device, similar to a trench gate type SiC semiconductor device, when a potential above the gate threshold is applied to the gate electrode 33, a channel is formed in the portion of the base layer 13 that is in contact with the gate insulating film 32, and the source region 14 and the drift layer 12 are connected by this channel. At this time, electrons flowing from the source region 14 through the channel to the drift layer 12 flow while diffusing. For this reason, in a planar gate type SiC semiconductor device, the portion of the drift layer 12 located between adjacent base layers 13 becomes the current diffusion layer 12a.
[0044] As shown in Figure 7, when the load is short-circuited and a large current flows through the SiC semiconductor device, it is confirmed that the portion of the drift layer 12 on the current diffusion layer 12a side of the SiC semiconductor device is at its highest temperature. In other words, it is confirmed that the drift layer 12 is at its highest temperature directly beneath the current diffusion layer 12a. Furthermore, as shown in Figure 7, it is confirmed that the source region 14 is at a lower temperature than the portion of the drift layer 12 that becomes the current diffusion layer 12a and the portion directly beneath the current diffusion layer 12a. In addition, although not specifically shown, in a trench gate type SiC semiconductor device, when the load is short-circuited and a large current flows through the SiC semiconductor device, the temperature distribution is similar to that of a planar gate type SiC semiconductor device.
[0045] Therefore, in this embodiment, as described above, the low-doping concentration region 81 is located in the portion of the drift layer 12 that is on the current diffusion layer 12a side. In other words, the low-doping concentration region 81 is located in the portion of the drift layer 12 that is prone to high temperatures. For this reason, the SiC semiconductor device of this embodiment can improve its responsiveness to temperature compared to, for example, the case in which the low-doping concentration region 81 is located in the source region 14. The inventors have also confirmed that the SiC semiconductor device of this embodiment was not destroyed even when the load was actually short-circuited. Furthermore, as shown in Figure 7, it has been confirmed that the drift layer 12 has a high-temperature portion from the portion located between the base layers 13 to a portion that is about 1 / 3 or less of the thickness of the drift layer 12. This is presumed to be due to the following reason: Carriers (i.e., electrons in this embodiment) that flow from the base layer 13 to the current diffusion layer 12a (i.e., the drift layer 12) rapidly diffuse along the plane direction of the semiconductor substrate 10 to form a uniform current density distribution. However, in areas where the thickness of the drift layer 12 is less than one-third, carriers are not yet uniformly diffused and tend to concentrate. Therefore, it is assumed that high-temperature areas are likely to occur in areas where the thickness of the drift layer 12 is less than one-third. Accordingly, as in this embodiment, by placing the low-doping concentration region 81 in the area of the drift layer 12 from the interface with the lower surface of the base layer 13 to less than one-third of the thickness of the drift layer 12, it is possible to easily improve the responsiveness to temperature.
[0046] In this embodiment described above, a low-doping concentration region 81 with a lower doping concentration than the drift layer 12 is arranged in the drift layer 12. Therefore, when a load connected to the SiC semiconductor device is short-circuited and a large current flows, the resistance of the low-doping concentration region 81 increases, resulting in increased on-resistance. Consequently, the current becomes less able to flow, suppressing the temperature rise of the SiC semiconductor device and preventing the SiC semiconductor device from being destroyed. Furthermore, the low-doping concentration region 81 is located in the drift layer 12, which is sufficiently larger in the plane direction of the semiconductor substrate 10 than the source region 14. Therefore, compared to the case where the low-doping concentration region 81 is locally located within the source region 14, the complexity of the manufacturing process can be suppressed.
[0047] Furthermore, in this embodiment, the low-doping concentration region 81 is located away from the base layer 13. In other words, a drift layer 12 is placed between the low-doping concentration region 81 and the base layer 13. Therefore, when the SiC semiconductor device is ON, electrons flowing from the source region 14 through the channel are diffused in the drift layer 12 before flowing into the low-doping concentration region 81. Consequently, compared to the case where the low-doping concentration region 81 is placed in contact with the lower surface of the base layer 13, the increase in ON resistance can be suppressed by placing the low-doping concentration region 81.
[0048] (1) In this embodiment, the low doping concentration region 81 is located in the portion of the drift layer 12 that is on the current diffusion layer 12a side. In other words, the low doping concentration region 81 is located in the portion of the drift layer 12 that is prone to high temperatures. Therefore, the responsiveness to temperature can be improved.
[0049] (2) In this embodiment, the low doping concentration region 81 is located only in the cell region RS. Therefore, compared to the case in which the low doping concentration region 81 is also located in the outer peripheral region RO, the low doping concentration region 81 is less likely to affect the pressure resistance design on the outer peripheral region RO side, and the complexity of the design can be suppressed.
[0050] (3) In this embodiment, the low doping concentration region 81 is defined as a doping concentration of 1.0 × 10⁻⁶ １５cm －３ The above 5.0 x 10 １６ cm －３ It is set to be less than [a certain value]. Therefore, it can fully satisfy the requirement that the resistance is low at room temperature and high at high temperatures.
[0051] (Second Embodiment) The second embodiment will now be described. This embodiment adds a superjunction structure (hereinafter simply referred to as the SJ structure) to the first embodiment. Other aspects are the same as the first embodiment, so the explanation will be omitted here.
[0052] In the SiC semiconductor device of this embodiment, as shown in Figure 8, the drift layer 12 has multiple p-type column regions 91b that extend along the Y-axis direction below the trench lower layer 51, and the portion of the drift layer 12 between the p-type column regions 91b is an n-type column region 91a. In other words, the drift layer 12 has an SJ structure that is formed to extend along the Y-axis direction (i.e., the longitudinal direction of the trench 31) and consists of n-type column regions 91a and p-type column regions 91b that are alternately arranged in the X-axis direction.
[0053] Furthermore, the depth of the deep layer 52 is adjusted so as to connect to each p-type column region 91b. As a result, the p-type column regions 91b are electrically connected to the base layer 13 via the deep layer 52.
[0054] Furthermore, the width and doping concentration in the X-axis direction of the n-type column region 91a and the p-type column region 91b are adjusted so as to maintain charge balance. The statement that the n-type column region 91a and the p-type column region 91b are formed to extend in the Y-axis direction (i.e., the longitudinal direction of the trench 31) includes not only cases where the directions are perfectly aligned, but also slight manufacturing tolerances. In this embodiment, the n-type column region 91a corresponds to the first column region, and the p-type column region 91b corresponds to the second column region.
[0055] In this embodiment, the low-doping concentration region 81 is located in each n-type column region 91a of the drift layer 12.
[0056] The above describes the configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, as in the first embodiment, when a potential above the gate threshold is applied to the gate electrode 33, it enters an ON state in which current flows. At this time, electrons that flow from the source region 14 through the channel to the drift layer 12 flow through the n-type column region 91a when passing through the SJ structure. As a result, the SiC semiconductor device tends to become hotter due to the concentration of current in the n-type column region 91a. Therefore, by arranging a low-doping concentration region 81 in the n-type column region 91a of the drift layer 12, the responsiveness to temperature can be improved compared to, for example, the case where the low-doping concentration region 81 is arranged in the source region 14.
[0057] According to the embodiment described above, the low-doping concentration region 81 is located in the drift layer 12 at a position separate from the base layer 13. Therefore, the same effects as in the first embodiment can be obtained.
[0058] (1) In this embodiment, an SJ structure is arranged. The low doping concentration region 81 is located in the n-type column region 91a of the drift layer 12. In other words, the low doping concentration region 81 is located in a part where the temperature tends to rise. For this reason, the responsiveness to temperature can be improved in this embodiment as well.
[0059] (Third Embodiment) The third embodiment will now be described. This embodiment is a modification of the second embodiment in which the location of the low-doping concentration region 81 is changed. As other aspects are the same as in the second embodiment, further explanation will be omitted here.
[0060] In the SiC semiconductor device of this embodiment, as shown in Figure 9, the low-doping concentration region 81 is located between the SJ structure and the substrate 11. In such a SiC semiconductor device, when in the ON state, electrons that have passed through each n-type column region 91a of the SJ structure converge between the SJ structure and the substrate 11. For this reason, the temperature of the SiC semiconductor device tends to rise even in the portion of the drift layer 12 between the SJ structure and the substrate 11. Therefore, by arranging the low-doping concentration region 81 in the portion of the drift layer 12 between the SJ structure and the substrate 11, the responsiveness to temperature can be improved compared to, for example, the case where the low-doping concentration region 81 is located in the source region 14.
[0061] According to the embodiment described above, the low-doping concentration region 81 is located in the drift layer 12 at a position separate from the base layer 13. Therefore, the same effects as in the first embodiment can be obtained.
[0062] (1) In this embodiment, an SJ structure is arranged. The low doping concentration region 81 is located in the portion of the drift layer 12 between the SJ structure and the substrate 11. In other words, the low doping concentration region 81 is located in a portion where the temperature tends to rise. Therefore, in this embodiment as well, the responsiveness to temperature can be improved.
[0063] (Fourth Embodiment) The fourth embodiment will now be described. This embodiment differs from the third embodiment in that it does not include an SJ structure. Other aspects are the same as the third embodiment, so further explanation will be omitted here.
[0064] In the SiC semiconductor device of this embodiment, as shown in Figure 10, the drift layer 12 does not have an SJ structure. The low doping concentration region 81 is located in the portion of the drift layer 12 that is on the substrate 11 side. The portion of the drift layer 12 that is on the substrate 11 side is, for example, the portion of the drift layer 12 in which the change in resistance can be effectively utilized even at low temperatures.
[0065] Furthermore, in this embodiment, the low-doping concentration region 81 is achieved by doping the drift layer 12 with a recombination-promoting element such as vanadium, resulting in a lower doping concentration than that of the drift layer 12. The recombination-promoting element is doped, for example, by ion implantation.
[0066] The above describes the configuration of the SiC semiconductor device in this embodiment. In this SiC semiconductor device, the on and off states are controlled in the same way as in the first embodiment. In this SiC semiconductor device, the substrate 11 may contain a basal plane dislocation. In this SiC semiconductor device, a parasitic diode is configured, which includes an n-type drift layer 12, a p-type base layer 13, a trench sublayer 51, and a deep layer 52. When the parasitic diode operates in the SiC semiconductor device, electrons and holes flow. At this time, holes pass near the basal plane dislocation, which may cause the basal plane dislocation to expand into a stacking fault. A stacking fault is a defect that occupies a larger area than a basal plane dislocation and is more likely to degrade the electrical characteristics of the SiC semiconductor device than a basal plane dislocation.
[0067] Therefore, in this embodiment, the low doping concentration region 81 contains a recombination-promoting element. Consequently, when the parasitic diode of the SiC semiconductor device operates, holes moving from the drift layer 12 toward the substrate 11 can be easily recombined with the recombination-promoting element and annihilated. This makes it more difficult for holes to reach the substrate 11, and prevents basal plane dislocations from expanding into stacking faults, thus suppressing a decrease in the electrical properties of the SiC semiconductor device.
[0068] Furthermore, when vanadium is doped as a recombination-promoting element, the defect levels formed due to vanadium are located approximately in the center of the band gap in SiC. Therefore, doping with vanadium as a recombination-promoting element makes it easier to recombine electrons along with holes. Consequently, it becomes easier to suppress holes from reaching the substrate 11.
[0069] According to the embodiment described above, the low-doping concentration region 81 is located in the drift layer 12 at a position separate from the base layer 13. Therefore, the same effects as in the first embodiment can be obtained.
[0070] (1) In this embodiment, the low-doping concentration region 81 is located on the substrate 11 side of the drift layer 12. The low-doping concentration region 81 is doped with vanadium as a recombination promoting element, so that the doping concentration is lower than that of the drift layer 12. Therefore, when a parasitic diode in a SiC semiconductor device operates, it is easier to suppress holes from reaching the substrate 11, and the deterioration of electrical characteristics can be suppressed.
[0071] (Other Embodiments) While this disclosure has been described in accordance with embodiments, it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of this disclosure.
[0072] For example, in each of the above embodiments, a SiC semiconductor device was described using an n-channel type trench gate structure MOSFET with a first conductivity type of n-type and a second conductivity type of p-type as an example. However, the SiC semiconductor device may be configured by forming a p-channel type trench gate structure MOSFET, for example, by inverting the conductivity types of each component compared to the n-channel type. Furthermore, the SiC semiconductor device may be configured to have IGBTs (Insulated Gate Bipolar Transistors) with a similar structure in addition to MOSFETs. In the case of IGBTs, the n in each of the above embodiments is ＋ The substrate 11 of type p ＋ Aside from changing the collector layer type, it is the same as the MOSFET described in each of the embodiments above.
[0073] Furthermore, in each of the above embodiments, the SiC semiconductor device may be configured with a planar gate structure MOSFET instead of a trench gate structure MOSFET. In the case of a SiC semiconductor device with a planar gate structure MOSFET, the current diffusion layer 12a is composed of the portion of the drift layer 12 located between adjacent base layers 13 along the plane direction of the semiconductor substrate 10.
[0074] Furthermore, in each of the above embodiments, the SiC semiconductor device may not be provided with a trench lower layer 51 and a deep layer 52. Also, in each of the above embodiments, the low doping concentration region 81 may be formed in the outer peripheral region RO as well.
[0075] Furthermore, in the first to third embodiments described above, the doping concentration in the low-doping concentration region 81 may be lower than that in the drift layer 12 by doping with a recombination-promoting element such as vanadium. Similarly, in the fourth embodiment described above, the doping concentration may be lower than that in the drift layer 12 by adjusting the supply amount of dopant gas during epitaxial growth.
[0076] Furthermore, in the first embodiment described above, an example was described in which the low-doping concentration region 81 is arranged in contact with the trench lower layer 51 and the deep layer 52. However, the low-doping concentration region 81 may be formed in contact with the lower part of the trench 31, or it may be arranged in a position that becomes the current diffusion layer 12a. Also, the low-doping concentration region 81 may be arranged to divide the current diffusion layer 12a into a portion on one side 10a of the semiconductor substrate 10 and a portion on the other side 10b.
[0077] [Perspective of this Disclosure] The above disclosure can be understood, for example, from the following perspectives. [First Perspective] A silicon carbide semiconductor device comprising: an impurity layer (11) which is a first conductivity type or a second conductivity type; a drift layer (12) which is disposed on the impurity layer and has a lower doping concentration than the impurity layer; a base layer (13) which is disposed on the drift layer and has a second conductivity type; an impurity region (14) which is disposed on the surface of the base layer and has a higher doping concentration than the drift layer; a gate insulating film (32) which is disposed on the surface of the base layer between the drift layer and the impurity region; a gate electrode (33) which is disposed on the gate insulating film; a first electrode (61) which is electrically connected to the base layer and the impurity region; and a second electrode (62) which is electrically connected to the impurity layer, wherein when a predetermined voltage is applied to the gate electrode, a channel is formed in the portion of the base layer between the drift layer and the impurity region and current flows. A silicon carbide semiconductor device wherein the drift layer has a low-doping concentration region (81) located away from the base layer, where the doping concentration is lower than that of the drift layer. [Second viewpoint] The silicon carbide semiconductor device according to the first viewpoint, wherein the low-doping concentration region is located on the current-diffusing layer side of the drift layer, where the portion of the drift layer through which carriers flow in through the channel is defined as the current-diffusing layer (12a). [Third viewpoint] The silicon carbide semiconductor device according to the first viewpoint, wherein the drift layer has a superjunction structure in which a plurality of second column regions (91b) of a second conductivity type extending along one direction in the plane direction of the impurity layer are formed, and the portion between the second column regions is defined as a first column region (91a) of a first conductivity type, and the low-doping concentration region is located in the first column region.[Fourth viewpoint] The drift layer has a plurality of second column regions (91b) of a second conductivity type extending in one direction in the plane direction of the impurity layer, and a superjunction structure is arranged in which the portion between the second column regions is a first column region (91a) of a first conductivity type, and the low doping concentration region is arranged between the superjunction structure and the impurity layer of the drift layer, as described in the first viewpoint. [Fifth viewpoint] The low doping concentration region is arranged on the impurity layer side of the drift layer, as described in the first viewpoint. [Sixth viewpoint] The silicon carbide semiconductor device according to any one of the first to fifth viewpoints, having a cell region (RS) in which the gate electrode is arranged and current flows, and an outer peripheral region (RO) surrounding the cell region, and the low doping concentration region is formed only in the cell region. [Seventh viewpoint] The low doping concentration region has a doping concentration of 1.0 × 10. １５ cm －３ The above 5.0 x 10 １６ cm －３ A silicon carbide semiconductor device according to any one of the first to sixth aspects, wherein the doping concentration is less than [eighth aspect] The silicon carbide semiconductor device according to any one of the first to seventh aspects, wherein the low doping concentration region is doped with vanadium.
Claims
1. A silicon carbide semiconductor device comprising: an impurity layer (11) of a first conductivity type or a second conductivity type; a drift layer (12) of a first conductivity type disposed on the impurity layer and having a lower doping concentration than the impurity layer; a base layer (13) of a second conductivity type disposed on the drift layer; an impurity region (14) of a first conductivity type disposed on the surface of the base layer and having a higher doping concentration than the drift layer; a gate insulating film (32) disposed on the surface of the base layer between the drift layer and the impurity region; a gate electrode (33) disposed on the gate insulating film; a first electrode (61) electrically connected to the base layer and the impurity region; and a second electrode (62) electrically connected to the impurity layer, wherein when a predetermined voltage is applied to the gate electrode, a channel is formed in the portion of the base layer between the drift layer and the impurity region, allowing current to flow. A silicon carbide semiconductor device wherein the drift layer has a low-doping concentration region (81) located at a position away from the base layer, where the doping concentration is lower than that of the drift layer.
2. The silicon carbide semiconductor device according to claim 1, wherein the low doping concentration region is located on the current diffusion layer side of the drift layer, with the portion of the drift layer through which carriers flow in (12a) being the current diffusion layer.
3. The silicon carbide semiconductor device according to claim 1, wherein the drift layer has a plurality of second column regions (91b) of a second conductivity type extending in one direction along the plane direction of the impurity layer, and the portion between the second column regions is a first column region (91a) of a first conductivity type, and the low doping concentration region is located in the first column region.
4. The silicon carbide semiconductor device according to claim 1, wherein the drift layer has a plurality of second column regions (91b) of a second conductivity type extending along one direction in the planar direction of the impurity layer, and a superjunction structure is arranged in which the portion between the second column regions is a first column region (91a) of a first conductivity type, and the low doping concentration region is arranged between the superjunction structure and the impurity layer of the drift layer.
5. The silicon carbide semiconductor device according to claim 1, wherein the low doping concentration region is located on the impurity layer side of the drift layer.
6. A silicon carbide semiconductor device according to any one of claims 1 to 5, comprising a cell region (RS) in which the gate electrode is arranged and current flows, and an outer peripheral region (RO) surrounding the cell region, wherein the low doping concentration region is formed only in the cell region.
7. The low doping concentration region is defined as a doping concentration of 1.0 × 10⁻⁶. １５ cm －３ The above 5.0 x 10 １６ cm －３ A silicon carbide semiconductor device according to any one of claims 1 to 5, which is less than [amount].
8. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the low doping concentration region is doped with vanadium.