Method for producing multilayered structure

Abstract

A method for producing a multilayered structure according to the present invention comprises: a first epitaxial film formation step for forming, through sputtering on the (100) plane of a silicon substrate, a first layer oriented in the (100) plane; a second epitaxial film formation step for forming, through sputtering on the first layer, a second layer of Pt oriented in the (100) plane; and a third epitaxial film formation step for forming, through sputtering on the second layer, a third layer oriented in the (100) plane.

Description

Method for manufacturing a multilayer structure

[0001] The present invention relates to a method for manufacturing a multilayer structure. This application claims priority based on Japanese Patent Application No. 2025-017080 filed in Japan on February 4, 2025, the content of which is incorporated herein by reference.

[0002] Pure zirconia (Pure-ZrO ２ ) usually has a monoclinic crystal structure. In order to obtain a cubic crystal structure, it is necessary to use yttria-stabilized zirconia (YSZ).

[0003] Patent Document 1 describes a technique for growing a cubic film using YSZ. In the disclosure of Patent Document 1, in order to grow Pt or SrRuO ３ on the YSZ layer on the (100) plane, a ceria (CeO ２ ) film is inserted between ZrO ２ and the upper layer, rotated by 45°, and epitaxially grown parallel to the Si<110> direction. Patent Document 2 describes that by using ZrO ２ , Pt can be oriented on the (100) plane and epitaxially grown parallel to Si<100> without using CeO ２ .

[0004] Japanese Patent Application Laid-Open No. 2005-005450, U.S. Patent No. 11785854

[0005] However, in the technique disclosed in Patent Document 1, since the number of layers increases, it is not preferable as a mass production technique. Further, in the technique disclosed in Patent Document 2, usually ZrO ２ has a monoclinic crystal structure, and the kinetic energy in the sputtering method is 10 －１ eV to 10 －２ eV, which is higher than that in the vapor deposition method of 10 ２ eV to 10 ３ eV. Therefore, the film is likely to be distorted, and it is difficult to obtain a cubic crystal with Pure-ZrO ２ . In the technique disclosed in Patent Document 2, two different chambers, a chamber for vapor deposition and a chamber for sputtering, are required, which is not preferable.

[0006] This invention has been made in view of the above circumstances and aims to achieve the following objectives: 1. To enable all film deposition by sputtering and to enable manufacturing by in-situ integrated film deposition. 2. To enable the manufacture of films oriented in the same direction as the silicon substrate. 3. To reduce the number of processes and improve manufacturing efficiency.

[0007] Lead zirconate titanate (Pb(Zr,Ti)O ３ Piezoelectric elements using ferroelectric materials such as PZT are known. Such piezoelectric elements are applied in MEMS (MicroElectromechanical Systems) technology to devices such as inkjet heads, micromirrors, gyro sensors, PMUTs (Piezoelectric Micromachined Ultrasonic Transducers), vibration elements, elastic wave elements, and acceleration sensors. Among these, PZT films are attracting particular attention.

[0008] In each device using PZT, the preferred index of performance (e ３１，ｆ ) ２ It is known that there is a figure of performance (e) / ε [GPa]. The range of the figure of performance differs for each device. ３１，ｆ ) ２ / ε[GPa] is the piezoelectric constant e ３１，ｆ [C / s] ２ ], relative permittivity ε ｒ This is determined by the following. Here, depending on the device, there is a requirement to increase the piezoelectric constant and decrease the dielectric constant. In this case, the figure of merit will not improve unless both conditions are met. For this purpose, it is preferable to epitaxially grow a c-axis oriented PZT film with a tetragonal composition.

[0009] Here, it is usually difficult to orient a tetragonal PZT thin film on a Si substrate along the c axis by epitaxial growth. This is said to be due to the difference in thermal expansion coefficients between Si and PZT, and it is known that the film preferentially orients along the a axis. In the technology disclosed in Patent Document 1, the crystal orientation of the PZT film rotates, making it impossible to grow it in the same direction as Si. There was also a demand to enable epitaxial growth of tetragonal PZT thin films by reducing the number of layers. At the same time, there was a demand to enable in-situ consistent film deposition processing and improve throughput.

[0010] The inventors, through diligent research, have found that CeO ２ We have discovered, for the first time in sputtering, a method for orienting Pt to (100) and epitaxially growing it parallel to Si<100> without using any other method. Furthermore, we have made it possible to provide a process in which all steps for fabricating PZT epitaxial films suitable for devices such as sensors can be consistently processed by sputtering.

[0011] A method for manufacturing a multilayer structure according to one aspect of the present invention solves the above problems by the following steps. A method for manufacturing a multilayer structure according to one aspect of the present invention comprises: a first epitaxial film formation step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering; a second epitaxial film formation step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering; and a third epitaxial film formation step of forming a third layer oriented to the (100) plane on the second layer by sputtering. The first epitaxial film deposition step comprises: etching the surface of the silicon substrate; and depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 700°C or higher; or depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 650°C or higher without removing silicon oxide from the surface of the silicon substrate; or depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer to a thickness of 200 nm to 500 nm on the seed layer at 650°C or higher. The first epitaxial deposition process comprises either a step of depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate, or a step of depositing YSZ as the first layer to a thickness of 18 nm to 67 nm at 650°C or higher. In other words, the first epitaxial deposition process comprises any of the following steps 1 to 4. The first step comprises etching the surface of the silicon substrate and depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 700°C or higher. The second step comprises depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 650°C or higher without removing silicon oxide from the surface of the silicon substrate. The third step includes the steps of forming a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate, and forming a YSZ film on the seed layer as the first layer to a thickness of 200 nm to 500 nm at 650°C or higher.The fourth step includes a step of forming a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate, and a step of forming YSZ as the first layer on the seed layer to a thickness of 18 nm to 67 nm at 650°C or higher. A method for manufacturing a multilayer structure according to one aspect of the present invention includes a first epitaxial film formation step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering, a second epitaxial film formation step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering, and a third epitaxial film formation step of forming a third layer oriented to the (100) plane on the second layer by sputtering. The first epitaxial deposition step comprises depositing YSZ as the first layer to a thickness of 25 nm to 50 nm, and the second epitaxial deposition step comprises depositing Pt as the second layer at a temperature of 500°C or higher. In a method for manufacturing a multilayer structure according to one aspect of the present invention, in the third epitaxial deposition step, the third layer is SrRuO. ３ , or LaNiO ３ This may also be the case. A method for manufacturing a multilayer structure according to one aspect of the present invention may include a fourth epitaxial deposition step in which, after the third epitaxial deposition step, a PZT layer oriented to the (100) plane is formed on the third layer by sputtering. In a method for manufacturing a multilayer structure according to one aspect of the present invention, in the fourth epitaxial deposition step, the PZT layer may be doped with lanthanum and nickel.

[0012] A method for manufacturing a multilayer structure according to one aspect of the present invention comprises: a first epitaxial deposition step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering; a second epitaxial deposition step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering; and a third epitaxial deposition step of forming a third layer oriented to the (100) plane on the second layer by sputtering.

[0013] According to the method described above, all layers can be manufactured by consistent in-situ sputtering, and all layers can be grown in stacks with the same plane orientation. This makes it possible to obtain a Pt layer oriented in the same (100) plane as silicon by epitaxial growth, which was not possible with conventional methods. Therefore, by forming a PZT layer on top of the Pt layer, it becomes possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction. This improves the film properties of the PZT film, reduces the number of steps, and improves manufacturing efficiency.

[0014] In a method for manufacturing a multilayer structure according to one aspect of the present invention, the first epitaxial film formation step comprises any of the first to fourth steps described above.

[0015] According to the above method, by selecting one of the first to fourth steps as the condition for the first epitaxial deposition step, a cubic YSZ film capable of forming a Pt layer oriented to the (100) plane by epitaxial growth can be obtained. In particular, even when performing X-ray scans such as φ scan and 2θ scan, no side peaks other than (100) appear, i.e., a YSZ film oriented to the (100) plane can be obtained. Here, YSZ is Y ２ O ３ ZrO doped ２ ;Y-ZrO ２ In particular, when a seed layer is used, it is preferable to perform RTA (Rapid Thermal Anneal) heat treatment after sputtering a zirconium metal film. Furthermore, the seed layer is not particularly limited in terms of whether it is integrated with the first layer as a multilayer structure, or whether it is movable and can be separated and detected.

[0016] In a method for manufacturing a multilayer structure according to one aspect of the present invention, the first epitaxial film formation step comprises forming a film of YSZ as the first layer to a thickness of 25 nm to 50 nm, and the second epitaxial film formation step comprises forming a film of Pt as the second layer at a temperature of 500°C or higher.

[0017] According to the above method, by selecting the above conditions as the conditions for the first epitaxial film deposition step and the second epitaxial film deposition step, it becomes possible to form a Pt layer oriented in a single direction (100) across the entire film deposition surface. By forming a PZT layer on this Pt layer, it becomes possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction. This improves the film properties of the PZT film, reduces the number of steps, and improves manufacturing efficiency.

[0018] In a method for manufacturing a multilayer structure according to one aspect of the present invention, in the third epitaxial film formation step, the third layer is SrRuO ３ , or LaNiO ３ That is the case.

[0019] According to the above method, a third layer (buffer layer) is formed on the (100)-oriented Pt. Therefore, all layers can be deposited by consistent in-situ sputtering, and epitaxial PZT films with a tetragonal composition and c-axis orientation can be grown in stacked layers. Moreover, in the PZT layer, the piezoelectric constant e ３１，ｆ [C / s] ２ It is possible to set the ratio to 10.0 to 11.9, the dielectric loss to 1.0% to 1.8%, and the relative permittivity to 200 to 375 [dimensionless]. Here, SrRuO ３ The film thickness is preferably 15 nm to 25 nm.

[0020] A method for manufacturing a multilayer structure according to one aspect of the present invention includes a fourth epitaxial deposition step, after the third epitaxial deposition step, in which a PZT layer oriented in the (100) plane is formed on the third layer by sputtering.

[0021] According to the above method, by making the process continuous in-situ up to the fourth epitaxial deposition step, the piezoelectric constant e is used in the deposition of the PZT layer oriented on the (100) plane. ３１，ｆ [C / s] ２It is possible to set the ratio to 10.0 to 11.9, the dielectric loss to 1.0% to 1.8%, and the relative permittivity to 200 to 375 [dimensionless]. Here, in the fourth epitaxial film deposition step, it is preferable that the PZT layer is deposited at 575°C to 650°C.

[0022] In a method for manufacturing a multilayer structure according to one aspect of the present invention, in the fourth epitaxial film formation step, the PZT layer is doped with lanthanum and nickel.

[0023] According to the above method, it is possible to significantly reduce the tensile internal stress. This makes it possible to suppress the occurrence of cracks in the PZT layer and provide a PZT film that is suitable for practical use. Here, it is preferable that at least one of lanthanum (La) and nickel (Ni) is doped into the PZT layer in a range of 0.1 [at%] to 5 [at%] as an impurity to be doped into the PZT layer.

[0024] According to the present invention, it is possible to reduce the number of steps and improve manufacturing efficiency, to achieve all film deposition by sputtering, and to produce a PZT film that can be deposited consistently in-situ, thereby providing a method for manufacturing a multilayer structure. Furthermore, it is possible to provide a multilayer structure with improved film properties.

[0025] This is a schematic cross-sectional view showing a multilayer structure according to the first embodiment of the present invention. This is a flowchart showing a method for manufacturing a multilayer structure according to the first embodiment of the present invention. This is a schematic plan view showing a manufacturing apparatus used in the method for manufacturing a multilayer structure according to the first embodiment of the present invention. This is a diagram showing the shape of the X-ray diffraction peaks of each layer constituting the multilayer structure according to the first embodiment of the present invention. This is a diagram showing the shape of the X-ray diffraction peaks of each layer constituting the multilayer structure according to the first embodiment of the present invention. This is a diagram showing the shape of the X-ray diffraction peaks of each layer constituting the multilayer structure according to the first embodiment of the present invention. This is a diagram showing the shape of the X-ray diffraction peaks of each layer constituting the multilayer structure according to the first embodiment of the present invention. This is a diagram showing the shape of the X-ray diffraction peaks of each layer constituting the multilayer structure according to the first embodiment of the present invention. This is a diagram showing the thickness of the YSZ layer in the multilayer structure according to the first embodiment of the present invention and the presence or absence of a (111) side peak in X-ray diffraction. This is a diagram showing the thickness of the YSZ layer in the multilayer structure according to the first embodiment of the present invention and the presence or absence of a (111) side peak in X-ray diffraction. This is a diagram showing the thickness of the YSZ layer and the deposition temperature of the Pt layer in the multilayer structure according to the first embodiment of the present invention and the orientation direction of Pt in X-ray diffraction. This is a diagram showing the X-ray diffraction peak of the YSZ layer. This figure shows the X-ray diffraction peaks of the YSZ layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the X-ray diffraction peaks of the YSZ layer shown in Figure 10. This figure shows the X-ray diffraction peaks of the silicon substrate on which the YSZ layer shown in Figure 10 has been deposited. This figure shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the X-ray diffraction peaks of the PZT layer shown in Figure 14. This figure shows the internal stress distribution of the PZT layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the surface observation results of the PZT layer shown in Figure 16. This figure shows the internal stress distribution of the PZT layer. This figure shows the surface observation results of the PZT layer shown in Figure 18. This figure shows the relative permittivity of the PZT layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the dielectric loss of the PZT layer in the multilayer structure according to the first embodiment of the present invention.The piezoelectric constant e of the PZT layer in the multilayer structure according to the first embodiment of the present invention. ３１，ｆ This figure shows the performance index of the PZT layer in the multilayer structure according to the first embodiment of the present invention. This figure shows the X-ray diffraction peak of the PZT layer in the multilayer structure according to the second embodiment of the present invention. This figure shows the X-ray diffraction peak of the PZT layer in the multilayer structure according to the second embodiment of the present invention. This figure shows the X-ray diffraction peak of the PZT layer shown in Figure 25. This figure shows the change in the PZT layer in the multilayer structure according to this embodiment due to a change in film deposition temperature, analyzed by X-ray diffraction.

[0026] Hereinafter, a method for manufacturing a multilayer structure and a multilayer structure according to the first embodiment of the present invention will be described with reference to the drawings. Figure 1 is a schematic cross-sectional view showing a multilayer structure in this embodiment. In the figure, reference numeral 100 denotes the multilayer structure.

[0027] As shown in Figure 1, the multilayer structure 100 according to this embodiment has a structure in which a first layer 11, a second layer 12, a third layer 13, and a fourth layer 14 are stacked on a silicon substrate 10.

[0028] The silicon substrate 10 is a silicon single crystal substrate. The (100) plane of the silicon substrate 10 is the lamination plane. The (100) plane of the silicon substrate 10 corresponds to the "surface of the silicon substrate". The lattice constant of silicon is 5.431 angstroms.

[0029] The first layer 11 is formed on the silicon substrate 10. The first layer 11 contains zirconium. The first layer 11 is yttria-stabilized zirconia (YSZ; Y ２ O ３ ZrO doped ２ ;Y-ZrO ２ The (100) plane of the first layer 11 is oriented as a (100) plane with respect to the Si(100) plane. The arrangement of the (100) planes of the first layer 11 is the same as that of the silicon substrate 10. The lattice constant of YSZ is 5.139 angstroms.

[0030] The second layer 12 is deposited on the first layer 11. The second layer 12 is a platinum (Pt) layer. The second layer 12 is oriented with respect to the (100) plane of the first layer 11. The (100) plane of the second layer 12 is oriented with respect to the YSZ(100) plane. The arrangement of the (100) plane of the second layer 12 is the same as that of the silicon substrate 10 and the first layer 11. The lattice constant of Pt is 3.920 angstroms.

[0031] The third layer 13 is deposited on the second layer 12. The third layer 13 is a buffer layer. The third layer 13 is a buffer layer. The third layer 13 is strontium ruthenate (SRO; SrRuO ３ The third layer 13 is oriented with respect to the (100) plane of the second layer 12. The (100) plane of the third layer 13 is oriented with respect to the Pt(100) plane. The arrangement of the (100) plane of the third layer 13 is the same as that of the silicon substrate 10, the first layer 11, and the second layer 12. SrRuO ３ The lattice constant is 3.930 angstroms.

[0032] The fourth layer 14 is deposited on the third layer 13. The fourth layer 14 is a PZT layer. The fourth layer 14 is a tetragonal c-axis oriented lead zirconate titanate (Pb(Zr,Ti)O ３ The lattice constant of PZT is approximately 3.9 angstroms, which is the same as that of a typical simple perovskite oxide.

[0033] In the multilayer structure 100 according to this embodiment, a first layer 11, a second layer 12, and a third layer 13 are laminated on a silicon substrate 10. A fourth layer 14 is laminated on the third layer 13, thereby reducing the piezoelectric constant e ３１，ｆ [C / s] ２ ], a PZT layer can be obtained in which the dielectric constant ε [F / m] is within a predetermined range.

[0034] Figure 2 is a flowchart showing the method for manufacturing a multilayer structure according to this embodiment. Figure 3 is a schematic plan view showing the manufacturing apparatus used in the method for manufacturing a multilayer structure according to this embodiment. As shown in Figure 2, the method for manufacturing a multilayer structure according to this embodiment includes a substrate preparation step S00, a first epitaxial film deposition step S01 for depositing a first layer 11, a second epitaxial film deposition step S02 for depositing a second layer 12, a third epitaxial film deposition step S03 for depositing a third layer 13, and a fourth epitaxial film deposition step S04 for depositing a fourth layer 14.

[0035] The substrate preparation step S00 involves preparing a single-crystal silicon substrate 10. Here, the (100) plane of the silicon substrate 10 is designated as the lamination plane. As will be described later, different surface treatments are performed on the silicon substrate 10 depending on the conditions in the first epitaxial film deposition step S01. Specifically, as a surface treatment for the silicon substrate 10, etching can be performed to remove the native oxide film. Alternatively, the state in which the native oxide film is not removed can be maintained. Regardless of whether or not the native oxide film is removed, a surface cleaning treatment can be performed. In this case, a cleaning treatment such as etching can be selected.

[0036] The first epitaxial deposition process S01 involves epitaxially depositing a first layer 11 onto the laminated surface of the silicon substrate 10. The first epitaxial deposition process S01 is performed using the manufacturing apparatus 1 shown in Figure 3. As shown in Figure 3, the manufacturing apparatus 1 (sputtering apparatus) includes a load / unload chamber 2, a plurality of deposition chambers 4 (chambers), and a transport chamber 3 located between the deposition chambers 4 and the load / unload chambers 2 (chambers). In the example shown in Figure 3, four deposition chambers are shown. The four deposition chambers are the first deposition chamber 4A, the second deposition chamber 4B, the third deposition chamber 4C, and the fourth deposition chamber 4D. In describing these deposition chambers, when it is not necessary to distinguish between multiple deposition chambers, or when describing a single deposition chamber, it may simply be referred to as deposition chamber 4.

[0037] The manufacturing apparatus 1 is a vacuum processing apparatus. The manufacturing apparatus 1 can perform sputtering film deposition on a silicon substrate 10 in each film deposition chamber 4. The manufacturing apparatus 1 is arranged such that a load / unload chamber 2 and a plurality of chambers constituting the plurality of film deposition chambers 4 surround the transport chamber 3. In the manufacturing apparatus 1, partition valves are formed between each of the plurality of chambers and the transport chamber 3. The manufacturing apparatus 1 can move the silicon substrate 10 between the load / unload chamber 2, the plurality of film deposition chambers 4, and the transport chamber 3 while maintaining a vacuum, reduced pressure, and sealed state.

[0038] The load / unload chamber 2 is a loading chamber for loading silicon substrates 10 from the outside to the inside of the manufacturing apparatus 1. The load / unload chamber 2 is an unloading chamber for unloading silicon substrates 10 from the inside to the outside of the manufacturing apparatus 1. The load / unload chamber 2 is configured to be usable for both loading and unloading silicon substrates 10. In addition, the manufacturing apparatus 1 may have multiple load / unload chambers 2. In this case, each of the multiple load / unload chambers 2 will independently perform the loading and unloading operations of silicon substrates 10.

[0039] The load / unload chamber 2 may be equipped with a positioning member capable of setting and aligning the placement position of the silicon substrate 10 brought in from outside the manufacturing apparatus 1. The load / unload chamber 2 is equipped with a rough vacuum exhaust device (rough vacuum exhaust device, low vacuum exhaust device) such as a rotary pump for roughly evacuating the interior. The transport chamber 3 is equipped with a rough vacuum exhaust device (rough vacuum exhaust device, low vacuum exhaust device) such as a rotary pump for roughly evacuating the interior. A transport device 3a (transport robot) is arranged inside the transport chamber 3.

[0040] The transport device 3a includes a rotating shaft, a robot arm attached to the rotating shaft, a robot hand formed at one end of the robot arm, and a vertical movement device for moving the robot hand up and down. The robot arm is composed of a first active arm, a second active arm, a first driven arm, and a second driven arm that can bend relative to each other. The transport device 3a can move the silicon substrate 10, which is the object to be transported, between each of the multiple chambers (load / unload chambers 2 and multiple film deposition chambers 4) and the transport chamber 3.

[0041] Each of the multiple deposition chambers 4 has a configuration that allows for sputtering deposition. Each of the multiple deposition chambers 4 may have the same configuration. However, each of the multiple deposition chambers 4 has a configuration that allows for separate processing corresponding to multiple different deposition processes. The following description will focus on the case where each of the multiple deposition chambers 4 of the manufacturing apparatus 1 has a configuration corresponding to the first epitaxial deposition process S01 to the fourth epitaxial deposition process S04, but the configuration of the manufacturing apparatus 1 is not limited to the configuration described below.

[0042] The film deposition processes performed in the multiple deposition chambers 4 may be different from each other. As will be described later, it may be possible to process different film deposition processes in the same chamber by changing the target, etc. In addition, one of the multiple deposition chambers 4 may have a configuration that allows for processes other than sputtering deposition, such as etching, heat treatment, substrate processing with a predetermined gas atmosphere, etc.

[0043] Each deposition chamber 4 includes a substrate holding mechanism 41, a deposition mechanism 42, and a gas atmosphere adjustment mechanism 43. In Figure 3, the substrate holding mechanism 41, the deposition mechanism 42, etc., are shown schematically and are not limited by the figure. The substrate holding mechanism 41 receives the silicon substrate 10 transported by the transport device 3a. The substrate holding mechanism 41 holds the silicon substrate 10 inside the deposition chamber 4. The substrate holding mechanism 41 can transport the silicon substrate 10 inside the deposition chamber 4. The substrate holding mechanism 41 transfers the silicon substrate 10 to the transport device 3a.

[0044] The substrate holding mechanism 41 holds the silicon substrate 10 so as to face the target 42a of the film deposition mechanism 42 during film deposition. The substrate holding mechanism 41 can set the distance between the silicon substrate 10 and the film deposition mechanism 42 during film deposition. The substrate holding mechanism 41 can apply bias power to the silicon substrate 10 during film deposition. The substrate holding mechanism 41 has a temperature control unit that can set the temperature of the silicon substrate 10 during film deposition. The temperature control unit has a built-in heating element and a heating power supply. For example, SiC is used as the heating element. The heating element may be located below the silicon substrate 10. The temperature control unit may have a cooling unit. For example, it can be configured to circulate a temperature-controlled cooling medium inside the cooling unit.

[0045] The film deposition mechanism 42 is located inside the film deposition chamber 4. The film deposition mechanism 42 performs epitaxial film deposition. The film deposition mechanism 42 supplies the film deposition material for the epitaxial film deposition process. The film deposition mechanism 42 includes a target 42a, a cathode electrode 42b (backing plate), and a power supply 42c.

[0046] Target 42a supplies the film deposition material corresponding to the film deposition process using target 42a. Target 42a is manufactured in a predetermined shape according to the composition of the film to be deposited on the surface of the silicon substrate 10. Target 42a is positioned inside the deposition chamber 4, facing the silicon substrate 10. Target 42a is attached to the cathode electrode 42b. The cathode electrode 42b is positioned above the deposition chamber 4 via an insulating member. The cathode electrode 42b and the wall of the deposition chamber 4 are electrically insulated. The wall of the deposition chamber 4 is at ground potential. One side of the cathode electrode 42b is locally exposed inside the deposition chamber 4. Target 42a is fixed in close contact with the center of the exposed area on one side of the cathode electrode 42b. Target 42a and the cathode electrode 42b are electrically connected.

[0047] The power supply 42c (sputtering power supply) applies a negative potential sputtering voltage to the cathode electrode 42b. The power supply 42c is located outside the deposition chamber 4. The power supply 42c is electrically connected to the cathode electrode 42b, and the power supply 42c can apply an AC voltage to the target 42a via the cathode electrode 42b.

[0048] The gas atmosphere adjustment mechanism 43 includes a gas introduction mechanism and a high vacuum evacuation mechanism. The gas introduction mechanism introduces sputtering gas and deposition gas corresponding to the deposition process using the gas atmosphere adjustment mechanism 43 into the deposition chamber 4. The high vacuum evacuation mechanism evacuates the inside of the deposition chamber 4. The high vacuum evacuation mechanism is, for example, a turbomolecular pump. The gas atmosphere adjustment mechanism 43 can set the pressure inside the deposition chamber 4 during deposition. The deposition mechanism 42 may have a magnetron magnetic circuit. The magnetron magnetic circuit forms a predetermined magnetic field on the target 42a. The magnetron magnetic circuit is positioned on the opposite side of the cathode electrode 42b from the target 42a, i.e., on the other side of the cathode electrode 42b.

[0049] The first epitaxial film deposition step S01 is performed, for example, in the first deposition chamber 4A in Figure 3. In this case, plasma treatment such as etching is possible in the first deposition chamber 4A. In addition, in the first deposition chamber 4A, the target 42a has a composition that enables epitaxial deposition of the first layer 11. The target 42a can be a single target made of yttria-stabilized zirconia. Alternatively, the target 42a may be a plurality of targets having targets containing zirconium oxide or zirconia and targets containing yttrium, etc.

[0050] In this case, in the first deposition chamber 4A, the gas atmosphere adjustment mechanism 43 sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 also sets the necessary deposition temperature and vial power. In the first epitaxial deposition process S01, the inside of the first deposition chamber 4A is depressurized by the gas atmosphere adjustment mechanism 43, and thereafter, vacuum evacuation is continued to maintain the vacuum atmosphere inside the first deposition chamber 4A.

[0051] Then, Ar gas is introduced into the first deposition chamber 4A as a sputtering gas from the gas atmosphere adjustment mechanism 43. Simultaneously, high frequency (negative high frequency power) is applied to the cathode electrode 42b from the power supply 42c to cause a discharge at the cathode electrode 42b. This generates a plasma of Ar gas introduced into the deposition chamber 4, producing positive ions such as Ar ions and forming a plasma space. The positive ions in the formed plasma space sputter the target 42a held by the cathode electrode 42b. The constituent elements of the sputtered target 42a are emitted from the target 42a and, in a neutral or ionized state, are sputtered onto the (100) surface of the silicon substrate 10 held by the substrate holding mechanism 41.

[0052] Specifically, the first epitaxial film deposition process comprises one of the following steps 1 to 4. [Step 1] Step 1 is a step of etching the surface of the silicon substrate 10 and YSZ(Y ２ O ３ ZrO doped ２ ;Y-ZrO ２ The process includes a step of epitaxially depositing a first layer 11 of ) to a thickness of 200 nm to 500 nm at a temperature of 700°C or higher. In this case, in the etching step, the native oxide film 10a is removed by dry etching using plasma, for example. Alternatively, the native oxide film 10a can be removed by wet etching, and then dry etching using plasma can be performed. In this case, the YSZ film deposition conditions can be such that 100% Ar gas is used as the supply gas and 1500 W is applied as the plasma generation power.

[0053] [Second Step] The second step involves epitaxially depositing YSZ as the first layer 11 at a temperature of 650°C or higher to a thickness of 200 nm to 500 nm without removing the silicon oxide 10a (native oxide film) on the surface of the silicon substrate 10. In this case, the YSZ is deposited while the native oxide film 10a remains. In this case, the YSZ deposition conditions can be achieved by using 100% Ar gas as the supply gas and applying a plasma generation power of 1500 W. In this case, after the YSZ is deposited, RTA treatment can be performed in a vacuum at a processing temperature of 650°C. After the RTA treatment, the native oxide film 10a becomes integrated with the YSZ first layer 11. Alternatively, it is also possible to perform a treatment to form silicon oxide on the surface of the silicon substrate 10 in advance.

[0054] [Third Step] The third step includes the steps of depositing a Zr seed layer 11a to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing the silicon oxide 10a on the surface of the silicon substrate 10, and epitaxially depositing YSZ as the first layer 11 on the seed layer 11a to a thickness of 200 nm to 500 nm at 650°C or higher. In this case, the seed layer 11a and YSZ are deposited while the native oxide film 10a remains. In this case, the conditions for depositing the seed layer 11a can be set to use a metal zirconium as the target, 100% Ar gas as the supply gas, and a plasma generation power of 0.3 kW. In this case, the conditions for depositing the YSZ can be set to use YSZ ceramics as the target, 100% Ar gas as the supply gas, and a plasma generation power of 1500 W. In this case, after forming the YSZ film, RTA treatment can be performed in a vacuum at a processing temperature of 650°C. After the RTA treatment, the native oxide film 10a and the seed layer 11a become integrated with the first layer 11, including the YSZ.

[0055] [Fourth Step] The fourth step includes the steps of depositing a Zr seed layer 11a to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing the silicon oxide 10a on the surface of the silicon substrate 10, and depositing YSZ as the first layer on the seed layer 11a to a thickness of 18 nm to 67 nm at 650°C or higher. In this case, the seed layer 11a and YSZ are deposited while the native oxide film 10a remains. In this case, the conditions for depositing the seed layer 11a can be set to a metal zirconium as the target, 100% Ar gas as the supply gas, and a plasma generation power of 0.3 kW.

[0056] In this case, the YSZ film deposition conditions are as follows: YSZ ceramics are used as the target, 100% Ar gas is used as the supply gas, and 1500W of plasma generation power can be applied. In this case, RTA treatment can be performed after the YSZ film deposition. After the RTA treatment, the native oxide film 10a and the seed layer 11a become integrated with the YSZ first layer 11.

[0057] Once the film deposition in the first epitaxial deposition process S01 is complete, the voltage application from the power supply 42c to the cathode electrode 42b is stopped, and the introduction of sputter gas into the deposition chamber 4 from the gas atmosphere adjustment mechanism 43 is stopped. The first epitaxial deposition process S01 allows the first layer 11, which is a cubic YSZ structure, to be deposited on the silicon substrate 10 with its (100) plane oriented in the <100> direction relative to the (110) plane. After the deposition of the first layer 11 in the first epitaxial deposition process S01 is complete, the silicon substrate 10 is moved to the second deposition chamber 4B via the transport chamber 3.

[0058] The second epitaxial deposition step S02 involves epitaxially depositing the second layer 12 on the first layer 11. The second epitaxial deposition step S02 is carried out similarly, for example, in the second deposition chamber 4B in Figure 3. In this case, the target 42a in the second deposition chamber 4B has a composition that allows for epitaxial deposition of the second layer 12. In this case, the target 42a can be a single target made of platinum. Also in this case, the gas atmosphere adjustment mechanism 43 in the second deposition chamber 4B sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 sets the necessary deposition temperature and vial power. In this case, the Pt deposition conditions can be set with Pt as the target, 100% Ar gas as the supply gas, and 0.5 kW applied as the plasma generation power.

[0059] The second epitaxial film formation step S02 includes a step of forming a film of Pt as the second layer at a temperature of 500°C or higher. At this time, in the first epitaxial film formation step S01, the first layer 11 can be formed to a thickness of 25 nm to 50 nm.

[0060] According to the above method, by selecting the above conditions in the first epitaxial film deposition step and the second epitaxial film deposition step, it becomes possible to form a Pt layer oriented in a single direction (100) across the entire film deposition surface. By forming a PZT layer on this Pt layer, it becomes possible to manufacture an epitaxial PZT film with a tetragonal composition and orientation in a predetermined direction. This improves the film properties of the PZT film, reduces the number of steps, and improves manufacturing efficiency.

[0061] In the second epitaxial deposition step S02, the (100) plane of the second layer 12, which is made of cubic Pt, can be oriented in the <100> direction relative to the (110) plane of the silicon substrate 10 and the (100) plane of the first layer 11, which is made of YSZ. The Pt (100) plane of the second layer 12 is not rotated in plane relative to the (100) plane of the first layer 11, which is made of YSZ, and the (110) plane of the silicon substrate 10. After the deposition of the second layer 12 in the second epitaxial deposition step S02 is completed, the silicon substrate 10 is moved to the third deposition chamber 4C via the transport chamber 3.

[0062] The third epitaxial deposition step S03 involves epitaxially depositing a third layer 13 on top of the second layer 12. The third epitaxial deposition step S03 is performed, for example, in the third deposition chamber 4C in Figure 3. In this case, the target 42a in the third deposition chamber 4C has a composition that allows for epitaxial deposition of the third layer 13. In this case, the target 42a is strontium ruthenate (SRO; SrRuO ３ It can be a single target consisting of ). Alternatively, multiple targets may be used to enable the deposition of strontium ruthenate.

[0063] In this case, in the third deposition chamber 4C, the gas atmosphere adjustment mechanism 43 sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 sets the necessary deposition temperature and vial power. In this case, the Pt deposition conditions are SrRuO ３ With Ar gas and O as the target, the supply gas is Ar gas and O ２ Using gas, a plasma generation power of 1500W can be applied. The film thickness of the third layer 13 is preferably about 20 nm, or 15 nm to 25 nm.

[0064] In the third epitaxial film deposition step S03, a cubic crystal structure of SrRuO is deposited on the (110) plane of the silicon substrate 10, the YSZ(100) plane of the first layer 11, and the Pt(100) plane of the second layer 12. ３ The third layer 13 can be formed so that its (100) plane is oriented in the <100> direction. ３ (100) plane is SrRuO of the second layer 12 ３ The (100) plane, the YSZ(100) plane of the first layer 11, and the (110) plane of the silicon substrate 10 are not rotated in the plane. After the deposition of the third layer 13 by the third epitaxial deposition process S03 is completed, the silicon substrate 10 is moved to the fourth deposition chamber 4D via the transport chamber 3.

[0065] The fourth epitaxial deposition step S04 involves epitaxially depositing a fourth layer 14, which is PZT, on a third layer 13, which is a buffer layer. The fourth epitaxial deposition step S04 is performed, for example, in the fourth deposition chamber 4D in Figure 3. In this case, in the fourth deposition chamber 4D, the target 42a has a composition that allows for epitaxial deposition of the fourth layer 14. In this case, the target 42a is lead zirconate titanate [Pb(Zr)] doped with lanthanum (La) and / or nickel (Ni) as impurities. ｘ Ti １－ｘ ) O ３ A single target consisting of [PZT] can be used. Alternatively, multiple targets may be used to deposit lead zirconate titanate doped with lanthanum (La) and / or nickel (Ni) as impurities.

[0066] In this case, in the fourth deposition chamber 4D, the gas atmosphere adjustment mechanism 43 sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 sets the necessary deposition temperature and vial power. In this case, the PZT deposition conditions target PZT containing La / Ni, and Ar / O ２ Using gas as the supply gas, it is possible to achieve a temperature of 575°C or higher and a plasma generation power of 2.75 kW.

[0067] In the fourth epitaxial film deposition step S04, the (110) plane of the silicon substrate 10, the YSZ(100) plane of the first layer 11, the Pt(100) plane of the second layer 12, and the SrRuO of the third layer 13 are deposited. ３ The (100) plane of the fourth layer 14, which is a cubic PZT, can be formed so that its (100) plane is oriented in the <100> direction relative to the (100) plane. The PZT (100) plane of the fourth layer 14 is the SrRuO of the third layer 13. ３ (100) plane, second layer 12 SrRuO ３ The (100) plane, the YSZ(100) plane of the first layer 11, and the (110) plane of the silicon substrate 10 are not rotated in the plane.

[0068] In this embodiment, the first epitaxial deposition process S01 to the fourth epitaxial deposition process S04 are carried out in-situ within the manufacturing apparatus 1. As a result, a c-axis oriented PZT film with a tetragonal composition can be obtained as the fourth layer 14. In the PZT film which is the fourth layer 14, the piezoelectric constant e ３１，ｆ [C / s] ２ The ratio is 10.0 to 11.9, the dielectric loss is 1.0% to 1.8%, the relative permittivity ε is 200 to 375 [dimensionless], and the practical figure of merit (e ３１，ｆ ) ２ The ε / GPa is approximately 33.9. The fourth layer 14 is formed by sputtering, which dops the crystallized PZT film with lanthanum (La) and / or nickel (Ni) during the deposition process. As a result, internal stress in the PZT film occurs on the compression side of the PZT film rather than the tensile side, making it possible to suppress the occurrence of cracks.

[0069] In this embodiment, a c-axis oriented PZT film with a tetragonal composition can be obtained using a single manufacturing apparatus 1, without mixing different film formation methods such as sputtering and vapor deposition, thereby reducing manufacturing costs. This multilayer structure 100 is suitably used, for example, in piezoelectric elements, gyro sensors, PMUTs, etc., in which a PZT film with high piezoelectricity and voltage resistance is formed on a CMOS substrate having aluminum wiring.

[0070] The following describes the verification of each layer of the multilayer structure 100 in this embodiment. In the manufacturing method of the multilayer structure 100, a YSZ layer is formed on a silicon substrate, a Pt layer is formed on the YSZ layer, and SrRuO is formed on the Pt layer. ３ A layer is formed, and SrRuO ３ A PZT layer is deposited on top of the layer. The conditions for stacking the multilayer structure 100 on a silicon substrate in this manner are as follows: Target YSZ composition: 12% Y ２ O ３ -88% ZrO ２ • Target Pt, deposition temperature: 700°C, supply gas: 100% Ar, film thickness: 30 nm • Target SrRuO３ Composition; SrRuO ３ Film deposition temperature: 600°C, supply gas: O ２ / (Ar+O ２ ) = 20%, film thickness; 20 nm; target PZT composition, La, Ni doped PZT, deposition temperature; 625°C, supply gas; O ２ (Ar+O ２ The multilayer structure 100 formed under these conditions was analyzed by X-ray diffraction. (percentage: 2.5%, film thickness: 2 μm)

[0071] Figures 4A to 4C show the X-ray diffraction peaks of each layer constituting the multilayer structure 100 according to this embodiment. Figure 4A shows the four peaks of Si(110) obtained by φ-scan measurement on the silicon substrate 10. Figure 4B shows the four peaks of YSZ(110) obtained by φ-scan measurement on the first layer 11. Figure 4C shows the four peaks of Pt(110) obtained by φ-scan measurement on the second layer 12. Figures 5A to 5C show the X-ray diffraction peaks of each layer constituting the multilayer structure 100 according to this embodiment. Figure 5A shows the SrRuO(110) obtained by φ-scan measurement on the third layer 13. ３ Figure 5B shows the four peaks of PZT(110) obtained by φ-scan measurement of the fourth layer 14. Figure 5C shows the peaks obtained by 2θ-ω-scan measurement of the PZT constituting the fourth layer 14.

[0072] In the multilayer structure 100 of this embodiment, the four peaks of the silicon substrate 10 shown in Figure 4A, the four peaks of the first layer 11 shown in Figure 4B, the four peaks of the second layer 12 shown in Figure 4C, the four peaks of the third layer 13 shown in Figure 5A, and the four peaks of the fourth layer 14 shown in Figure 5B all coincide.

[0073] Furthermore, as is clear from the 2θ-ω scan measurement results of the fourth layer 14, the PZT in the fourth layer 14 is a cubic crystal oriented along the c-axis, as shown in Figure 5C. Therefore, it can be seen that in the multilayer structure 100 according to this embodiment, the first layer 11 to the fourth layer 14 are all cubic crystals and are oriented in the same plane orientation.

[0074] Figure 6 shows the film thickness of the YSZ layer in the multilayer structure according to this embodiment and the presence or absence of a (111) side peak in X-ray diffraction. Figure 6 shows the results when the film thickness of the YSZ layer is 200 nm to 500 nm. The film deposition conditions for the YSZ layer deposited on the silicon substrate are: Target YSZ composition: 12% Y ２ O ３ -88% ZrO ２ The deposition temperature is 700°C, the supply gas is 100% Ar, and the film thickness is 20 nm. In this case, etching, that is, removing the native oxide film 10a on the surface of the silicon substrate 10, and depositing at a temperature of 600°C, results in a large side peak other than (100). Furthermore, removing the native oxide film 10a and depositing at a temperature of 650°C results in some side peaks other than (100). Moreover, even if the native oxide film 10a is removed, depositing at a temperature of 700°C results in no side peaks other than (100).

[0075] When the YSZ layer thickness is 200 nm to 500 nm, if the YSZ layer is deposited without etching, leaving the native oxide film 10a on the surface of the silicon substrate 10, it can be seen that a large side peak other than (100) appears when the deposition temperature is 600°C. Similarly, it can be seen that no side peaks other than (100) appear when the deposition temperature is 650°C and 700°C. When the YSZ layer thickness is 200 nm to 500 nm, if the YSZ layer is deposited after depositing a zirconium metal as a seed layer 11a, leaving the native oxide film 10a on the surface of the silicon substrate 10 without etching, it can be seen that no side peaks other than (100) appear when the deposition temperature is 650°C.

[0076] Figure 7 shows the film thickness of the YSZ layer in the multilayer structure according to this embodiment and the presence or absence of a (111) side peak in X-ray diffraction. Figure 7 shows the results when the film thickness of the YSZ layer is 60 nm or less. The film deposition conditions for depositing the YSZ layer on the silicon substrate are: Target YSZ composition: 12% Y ２ O ３ -88% ZrO ２The deposition temperature is 700°C, and the supply gas is 100% Ar. In this case, if the YSZ layer is deposited without etching, leaving the native oxide film 10a on the surface of the silicon substrate 10, it can be seen that when the deposition temperature is 650°C, a large side peak other than (100) appears. Similarly, when the deposition temperature is 700°C, it can be seen that a small amount of side peaks other than (100) appear. When the thickness of the YSZ layer is 60 nm or less, if the YSZ layer is deposited after depositing a zirconium metal as a seed layer 11a, it can be seen that no side peaks other than (100) appear at deposition temperatures of 650°C and 700°C.

[0077] Figure 8 shows the film thickness of the YSZ layer, the deposition temperature of the Pt layer, and the orientation direction of Pt in X-ray diffraction in the multilayer structure according to this embodiment. The Pt layer is deposited on top of the YSZ layer. The deposition conditions for the YSZ layer and Pt layer at this time are: Target YSZ composition: 12% Y ２ O ３ -88% ZrO ２ The film deposition temperature is 700°C, and the supply gas is 100% Ar.

[0078] When the Pt layer is deposited at 500°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 20 nm. When the Pt layer is deposited at 500°C, a peak indicating (200) orientation occurs when the YSZ layer thickness is 30 nm; that is, it is formed in (100) orientation, but at the same time, a peak indicating (111) orientation occurs. When the Pt layer is deposited at 500°C, a peak indicating (111) orientation occurs when the YSZ layer thickness is 60 nm. However, when the Pt layer is deposited at 500°C, a peak indicating (200) orientation occurs only when the YSZ layer thickness is 40 nm, and no peak indicating (111) orientation occurs. In other words, the Pt layer is oriented to the (100) plane.

[0079] Similarly, when the Pt layer is deposited at 600°C, a peak indicating (111) orientation is generated when the YSZ layer thickness is 20 nm. When the Pt layer is deposited at 600°C, a peak indicating (200) orientation is generated when the YSZ layer thickness is 30 nm; that is, it is formed in (100) orientation, but at the same time, a peak indicating (111) orientation is generated. When the Pt layer is deposited at 600°C, a peak indicating (111) orientation is generated when the YSZ layer thickness is 60 nm. However, when the Pt layer is deposited at 600°C, only a peak indicating (200) orientation is generated when the YSZ layer thickness is 40 nm, and no peak indicating (111) orientation is generated. In other words, the Pt layer is oriented to the (100) plane.

[0080] Figure 9 shows the X-ray diffraction peaks of the YSZ layer. A Zr metal seed layer was epitaxially grown at 400°C on the (100) plane of a silicon substrate without removing the native oxide film. After being left in air for one week, a YSZ layer was epitaxially deposited to a thickness of 50 nm. Verification was performed by X-ray diffraction (2θ).

[0081] As a result, as shown in Figure 9, it was found that the YSZ was oriented not only in (200) but also in (111). This is thought to be because the YSZ was oxidized in air, causing 111 crystals to form. Therefore, it can be seen that the entire surface of the YSZ will not be oriented in (100) direction simply by forming a seed layer. In Figure 9, 1-C is the wafer center position of sample 1, and 1-E is the wafer edge position of sample 1. 2-C is the wafer center position of sample 2, and 2-E is the wafer edge position of sample 2.

[0082] Figure 10 shows the X-ray diffraction peaks of the YSZ layer in the multilayer structure according to this embodiment. Figure 11 shows the X-ray diffraction peaks of the YSZ layer shown in Figure 10. Figure 12 shows the X-ray diffraction peaks of the silicon substrate on which the YSZ layer shown in Figure 10 was deposited. Similarly, metal Zr was epitaxially grown as a seed layer at 400°C on the (100) plane of a silicon substrate in which the native oxide film had not been removed. After being left in a vacuum for one week, YSZ was epitaxially deposited to a thickness of 50 nm. Verification was performed by X-ray diffraction (2θ) and X-ray diffraction (φ).

[0083] As a result, as shown in Figure 10, it was found that the YSZ was (200) single-oriented. This is thought to be because the YSZ was not oxidized in air and no 111 crystals were formed. Therefore, it can be seen that by forming a seed layer and then depositing YSZ in situ, the entire surface becomes (100) single-oriented. In Figure 10, 2+18nm, 2+28nm, 2+48nm, 2+98nm, and 2+198nm represent the thickness of the seed layer (nm) + the thickness of the YSZ (nm), respectively. Also, as shown in Figures 11 and 12, it can be seen that the YSZ (110) plane shows a peak that coincides with the (110) plane of the silicon substrate.

[0084] Figure 13 shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to this embodiment. As a multilayer structure, a YSZ layer is deposited on a silicon substrate, a Pt layer is deposited on the YSZ layer, and SrRuO is deposited on the Pt layer. ３ A layer was deposited. The deposition conditions were the same as those shown in Figures 4, 5A to 5C. Furthermore, SrRuO ３ A multilayer structure was obtained by depositing a PZT layer on top of the layer. During this process, the deposition temperature was varied from 450°C to 625°C, and each PZT layer was analyzed by X-ray diffraction. Furthermore, when the deposition temperature was 575°C, SrRuO ３ The peak of the layer was 98.2°. As a result, it was observed that the peak of the PZT layer shifted to a lower angle as the deposition temperature increased, as shown in Figure 13. Furthermore, it was found that the c-axis could be observed in the PZT layer when the deposition temperature rose to 625°C.

[0085] Figure 14 is a diagram showing the X-ray diffraction peak (2θ-ω) of the PZT layer in the multilayer structure according to this embodiment. Figure 15 is a diagram showing the X-ray diffraction peak (φ scan) of the PZT layer shown in Figure 14. Similar to the PZT layer in Figure 13, as a multilayer structure, a PZT layer was formed on an 8-inch silicon wafer, and its in-plane distribution was observed. As a result, as shown in Figures 14 and 15, it can be seen that the YSZ layer, Pt layer, SrRuO ３ layer, and PZT layer are all formed almost uniformly with an orientation in the (100) plane.

[0086] Figure 18 is a diagram showing the internal stress distribution of the PZT layer in the multilayer structure according to this embodiment. Similarly, as a multilayer structure, a YSZ layer, Pt layer, SrRuO ３ layer, and PZT layer were formed on a silicon substrate, and the internal stress in this PZT layer was measured. At this time, the PZT layer was doped with La and Ni so that each became 3 atm%. The results are shown in Figure 18. Here, the measurement of the internal stress was performed by a thin-film stress measurement device FLX-2320-R manufactured by Toho Technology Co., Ltd. In addition, the surface of this PZT layer was observed with a microscope to confirm the presence or absence of cracks. The results are shown in Figure 19.

[0087] As a result, it was found that no cracks occurred in the PZT film, and the average value of the internal stress in the PZT layer was +80 MPa. Here, the plus sign of the internal stress value means that the internal stress is on the tensile side, that is, it is applied in the tensile direction.

[0088] Figure 16 shows the internal stress distribution of the PZT layer. For comparison, PZT layers without La and Ni doping were manufactured in the same manner, and the internal stress in the PZT layer was measured. The results are shown in Figure 16. In addition, the surface of the undoped PZT layer was observed with a microscope to check for the presence or absence of cracks. The results are shown in Figure 17. As a result, it was found that cracks had formed in the undoped PZT layer, and the stress was relieved by the cracks, resulting in an average internal stress of +32 MPa. Here, the positive sign of the internal stress value means that the internal stress is applied on the tensile side, that is, in the tensile direction. Note that Figure 17 is an image with cracks, showing the case without doping. Figure 19 is an image without cracks, showing the case with doping. Figure 16 shows the stress with cracks, showing the case without doping. Figure 18 shows the stress without cracks, showing the case with doping. When cracks occur, the dielectric strength decreases significantly, which is undesirable.

[0089] The results shown in Figures 18 and 19 indicate that by applying a predetermined amount of doping, the internal stress of the PZT layer shifts more toward the compression direction, allowing for relaxation of tensile stress and preventing crack formation.

[0090] Figure 20 shows the relative permittivity of the PZT layer in the multilayer structure according to this embodiment. Similarly, as a multilayer structure, a YSZ layer, a Pt layer, and a SrRuO layer are placed on a silicon substrate. ３ A PZT layer was fabricated, and the relative permittivity of the PZT layer was measured. The results are shown in Figure 20. Here, the relative permittivity was measured using an Agilent Technologies 4284A LCR analyzer after the formation of the MIM structure. In Figure 20, the horizontal axis (position) represents the radial position of the Φ200 mm wafer.

[0091] From the results shown in FIG. 20, it can be seen that the relative permittivity ε of the PZT layer in the multilayer structure according to the present embodiment is 200 to 375 [dimensionless]. On the other hand, for polycrystalline PZT formed by sputtering, it can be seen that the relative permittivity is 1000 to 1200. It can be seen that the permittivity can be reduced in the PZT layer in the multilayer structure of the present invention.

[0092] FIG. 21 is a diagram showing the dielectric loss of the PZT layer in the multilayer structure according to the present embodiment. Similarly, as the multilayer structure, a YSZ layer, a Pt layer, a SrRuO ３ layer, and a PZT layer were formed on a silicon substrate, and the dielectric loss in this PZT layer was measured. The results are shown in FIG. 21. Here, the dielectric loss was measured with an Agilent Technologies 4284A LCR meter after forming the MIM structure. Also, in FIG. 21, the horizontal axis (position) is the radial position of a Φ200 mm wafer.

[0093] From the results shown in FIG. 21, it can be seen that the dielectric loss of the PZT layer in the multilayer structure according to the present embodiment is 1% to 1.8%. On the other hand, for polycrystalline PZT formed by vapor deposition, it is known that the dielectric loss is 3% to 5%. It can be seen that the dielectric loss can be reduced in the PZT layer in the multilayer structure according to the present embodiment.

[0094] FIG. 22 is a diagram showing the piezoelectric constant e ３１，ｆ of the PZT layer in the multilayer structure according to the present embodiment. Similarly, as the multilayer structure, a YSZ layer, a Pt layer, a SrRuO ３ layer, and a PZT layer were formed on a silicon substrate, and the piezoelectric constant e ３１，ｆ in this PZT layer was measured. The results are shown in FIG. 22. Here, the measurement of the piezoelectric constant e ３１，ｆ was performed by inverse piezoelectric measurement using a laser Doppler after creating a cantilever. Also, in FIG. 22, the vertical axis is the displacement of the cantilever, and the horizontal axis is the applied AC voltage.

[0095] From the results shown in FIG. 22, the piezoelectric constant e ３１，ｆ of the PZT layer in the multilayer structure according to the present embodiment is 10.0 to 11.9 [C / m ２], 10.9 [C / m ２ It can be seen that it is around this level. The piezoelectric constant becomes smaller, but the relative permittivity also becomes smaller, which improves the figure of merit for sensor applications.

[0096] Figure 23 shows the figure of merit of the PZT layer in the multilayer structure according to this embodiment. Similarly, as a multilayer structure, a YSZ layer, a Pt layer, and a SrRuO layer are placed on a silicon substrate. ３ A layer and a PZT layer are fabricated, and the figure of performance (e) of this PZT layer is formed. ３１，ｆ ) ２ The value of / ε was measured. The results are shown in Figure 23. Here, the figure of performance (e ３１，ｆ ) ２ The measurement of / ε is e ３１ The value was calculated from the measurement results of the cantilever and the relative permittivity. In Figure 22, the vertical axis represents the displacement of the cantilever, and the horizontal axis represents the applied AC voltage.

[0097] From the results shown in Figure 23, the figure of merit (FOM; Figure of Merit) of the PZT layer in the multilayer structure according to this embodiment is (e ３１，ｆ ) ２ It can be seen that / ε is approximately 10.0 to 11.9 [GPa] and 33.9 [GPa]. In contrast, for polycrystalline PZT deposited by the sputtering method, the figure of merit (e ３１，ｆ ) ２ It is known that / ε is approximately 21.3 [GPa]. In the PZT layer of the multilayer structure according to this embodiment, the figure of merit (e ３１，ｆ ) ２ We can see that we can increase / ε.

[0098] Furthermore, this embodiment offers the advantage of reducing dielectric loss to 1-1.8%.

[0099] Hereinafter, a method for manufacturing a multilayer structure and a multilayer structure according to the second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the difference from the first embodiment described above is in the respect to the third layer, and other components corresponding to the first embodiment described above are denoted by the same reference numerals and their descriptions are omitted.

[0100] In this embodiment, the third layer 13 is made of lanthanum nickel oxide (LaNiO). ３ ) is a film. The third layer 13 is deposited on the second layer 12. The third layer 13 is a buffer layer. The third layer 13 is oriented with respect to the (100) plane of the second layer 12. The (100) plane of the third layer 13 is oriented with respect to the Pt(100) plane. The arrangement of the (100) plane of the third layer 13 is the same as that of the silicon substrate 10, the first layer 11, and the second layer 12. LaNiO ３ The lattice constant is 3.857 angstroms.

[0101] In this embodiment, the third epitaxial deposition step S03 involves epitaxially depositing a third layer 13 on the second layer 12. The third epitaxial deposition step S03 is performed, for example, in the third deposition chamber 4C in Figure 3. In this case, the target 42a in the third deposition chamber 4C has a composition that allows for epitaxial deposition of the third layer 13. In this case, the target 42a is lanthanum nickelate (LaNiO). ３ ) can be a single target consisting of ). Alternatively, multiple targets may be used to deposit lanthanum nickelate. In this case, in the third deposition chamber 4C, the gas atmosphere adjustment mechanism 43 sets the gas atmosphere and pressure range, which are the necessary deposition conditions. At the same time, the deposition mechanism 42 sets the necessary deposition power. The substrate holding mechanism 41 sets the necessary deposition temperature and vial power. In this case, the Pt deposition conditions are LaNiO ３ Targeting, supply gas; O ２ (Ar+O ２ The ratio can be set to 60%, gas partial pressure to 0.5 Pa, and plasma generation power to 0.5 kW.

[0102] In this embodiment, the third epitaxial film deposition step S03 involves sputtering LaNiO ３ A buffer layer 13 is formed consisting of the following. This buffer layer 13 can be formed by the Pulse-DC sputtering method. Here, as the sputtering target 42a, LaNiO ３Using a target, the temperature of the silicon substrate 10 can be set to approximately 550°C or higher during pulsed sputtering (frequency 50 kHz, off time 5 μsec) in a sputtering gas, such as argon gas. For example, it can be set to 525°C to 725°C. ３ The thickness of the buffer layer 13, which consists of the above, can be set to 100 nm or less. ３ If the thickness of the buffer layer 6 exceeds 100 nm, it may not be possible to form a perovskite single-phase film. The thickness of the third layer 13 is preferably about 20 nm, or 15 nm to 25 nm.

[0103] Furthermore, in this embodiment, the PZT layer as the fourth layer 14 can be formed by RF sputtering. In the fourth epitaxial growth step S04, a PZT target doped with a nickel (Ni)-containing metal is used as the sputtering target. Here, the nickel (Ni)-containing metal is nickel or lanthanum-nickel alloy (LaNi) ５ Examples include: a nickel-doped PZT target or a lanthanum-nickel alloy-doped PZT target. The doping amount is preferably set to 0.1 atm% to 5 atm% relative to 100 atm% of PZT, more preferably to 0.5 atm% to 5 atm% relative to 100 atm% of PZT, and even more preferably to 1 atm% to 3 atm% relative to 100 atm% of PZT.

[0104] Figure 24 shows the X-ray diffraction peaks of the PZT layer in the multilayer structure according to this embodiment. As a multilayer structure, a YSZ layer is deposited on a silicon substrate, a Pt layer is deposited on the YSZ layer, and LaNiO is deposited on the Pt layer. ３ A layer was formed. LaNiO ３ The film deposition conditions other than the layer are the same as those in the first embodiment shown in Figures 4 and 5A to 5C. Furthermore, LaNiO ３A PZT layer was deposited on top of the layer to obtain a multilayer structure. When the deposition temperature was 625°C, the PZT(004) peak obtained by X-ray diffraction was 96.800°. As a result, as shown in Figure 24, LaNiO was used as the third layer. ３ When formed as a layer, the SrRuO shown in Figure 13 ３ Similar to the layers, it was found that the c-axis of the PZT layer could be observed at a deposition temperature of 625°C.

[0105] Figure 25 shows the X-ray diffraction peak (2θ-ω) of the PZT layer in the multilayer structure according to this embodiment. Figure 26 shows the X-ray diffraction peak (φ scan) of the PZT layer in Figure 25. Similar to the PZT layer in Figure 24, a PZT layer was formed on a silicon substrate as a multilayer structure, and its in-plane distribution was observed. As a result, as shown in Figures 25 and 26, the YSZ layer, Pt layer, and LaNiO ３ It can be seen that both the layer and the PZT layer are epitaxially grown oriented to the (100) plane.

[0106] Figure 27 shows the changes in the PZT layer in the multilayer structure according to this embodiment, analyzed by X-ray diffraction, due to changes in the film deposition temperature. The figure shows the X-ray diffraction peak (2θ). As a multilayer structure, a YSZ layer is deposited on a silicon substrate, a Pt layer is deposited on the YSZ layer, and LaNiO is deposited on the Pt layer. ３ A layer was formed. LaNiO ３ The film deposition conditions other than the layer are the same as those shown in Figure 24. Furthermore, LaNiO ３ A multilayer structure was obtained by depositing a PZT layer on top of the layer. In this process, LaNiO ３ Figure 27 shows the results of analyzing each PZT layer by X-ray diffraction, with the deposition temperature of the layers varying from 350°C to 650°C. Here, at a deposition temperature of 350°C, LaNiO ３ A side peak (110) was observed. From the results of X-ray diffraction, LaNiO ３ It can be seen that a (100) peak appears in the layer when the substrate temperature is 550°C or higher.

[0107] In this embodiment, the same effects as those of the above-described embodiment can be achieved. Furthermore, in this embodiment, the buffer layers of poly-PZT and epi-PZT can be made identical, which is an additional benefit.

[0108] In the present invention, the following can be done: [1] In the sputtering method, ZrO ２ To make it cubic, Y-doped ZrO ２(YSZ) is required. [2] It was found that either A or B below can be used to (epitaxially grow) YSZ. [2A] Silicon surface etching => YSZ (700°C or higher) [2B] Native oxide film present => YSZ (650°C or higher) [3] However, in thin films with a YSZ of 60 nm or less, the YSZ (111) side peak is detected in the above A / B methods. [4] It was found that in order to align YSZ (100) single-particle when the YSZ is 60 nm or less, [4C] Native oxide film => Seed layer (Zr) => YSZ (650°C or higher) must be used. [5] The optimal thickness of the seed layer is 2 nm (try 1.5 nm, 2, 3, 5 nm). [6] At room temperature, YSZ (111) is detected when the seed layer is deposited. 400°C is the BKM (Best Known Method). [7] Seed layer => Open to air => In YSZ film deposition, YSZ(111) is detected, so in-situ treatment is essential. [8] In order for Pt to be oriented as a single Pt(100) and for Pt<100> to grow epitaxially parallel to Si<100>, the YSZ needs to be thinner than 60 nm. In other words, the YSZ needs to be deposited using the [4C] method. Furthermore, the YSZ needs to be thicker than 20 nm and thinner than 60 nm. If the YSZ is 20 nm or 60 nm, Pt will grow on the Pt(111) plane. (TEM data) [9] In order to epitaxially grow a single Pt(100), the Pt deposition temperature needs to be higher than 500°C.

[10] There are optimal conditions for SRO of the buffer layer. Film thickness also has an effect, with 20 nm being BKM.

[11] When PZT is epitaxially grown under undoped conditions, cracks occur due to large tensile stresses. In contrast, by depositing the film by RF sputtering with La and Ni doping, the film stress in PZT can be reduced, and a crack-free epitaxial film can be deposited. To epitaxially grow the PZT film along the c axis, a deposition temperature higher than 575°C is required. As a result, the entire process can be carried out in an integrated manner using sputtering.

[0109] Furthermore, in the present invention, it is also possible to individually select and combine each of the configurations in the above-described embodiments.

[0110] Examples of applications of the present invention include its use in MEMS (MicroElectromechanical Systems) technology, specifically in devices such as inkjet heads, micromirrors, gyro sensors, PMUTs (Piezoelectric Micromachined Ultrasonic Transducers), vibration elements, elastic wave elements, and acceleration sensors.

[0111] 100...Multilayer structure 10...Silicon substrate 10a...Native oxide film 11...First layer (YSZ) 12...Second layer (Pt) 13...Third layer (Buffer layer) 14...Fourth layer (PZT) 11a...Seed layer

Claims

1. A first epitaxial film deposition step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering; a second epitaxial film deposition step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering; and a third epitaxial film deposition step of forming a third layer oriented to the (100) plane on the second layer by sputtering, wherein the first epitaxial film deposition step comprises etching the surface of the silicon substrate and depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 700°C or higher, or depositing YSZ as the first layer to a thickness of 200 nm to 500 nm at 650°C or higher without removing silicon oxide from the surface of the silicon substrate. A method for manufacturing a multilayer structure, comprising the steps of: depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 200 nm to 500 nm at 650°C or higher; or depositing a Zr seed layer to a thickness of 1.5 nm to 3.5 nm at 400°C or higher without removing silicon oxide from the surface of the silicon substrate; and depositing YSZ as the first layer on the seed layer to a thickness of 18 nm to 67 nm at 650°C or higher.

2. A method for manufacturing a multilayer structure, comprising: a first epitaxial deposition step of forming a first layer oriented to the (100) plane on the (100) plane of a silicon substrate by sputtering; a second epitaxial deposition step of forming a second layer of Pt oriented to the (100) plane on the first layer by sputtering; and a third epitaxial deposition step of forming a third layer oriented to the (100) plane on the second layer by sputtering, wherein the first epitaxial deposition step involves forming a film of YSZ as the first layer to a thickness of 25 nm to 50 nm, and the second epitaxial deposition step involves forming a film of Pt as the second layer at a temperature of 500°C or higher.

3. In the third epitaxial film formation step, the third layer is made of SrRuO ３ , or LaNiO ３ The method for manufacturing a multilayer structure according to claim 1 or claim 2.

4. A method for manufacturing a multilayer structure according to claim 1 or 2, further comprising a fourth epitaxial deposition step of forming a PZT layer oriented to the (100) plane on the third layer by sputtering after the third epitaxial deposition step.

5. The method for manufacturing a multilayer structure according to claim 4, wherein in the fourth epitaxial film formation step, the PZT layer is doped with lanthanum and nickel.

Images