Semiconductor device

Abstract

Provided is a pn diode 1 including: a n-type semiconductor layer 11 made of a gallium oxide-based semiconductor; a p-type semiconductor layer 13 provided on the n-type semiconductor layer 11 and forming a pn junction with the n-type semiconductor layer 11; and an annular acceptor implantation region 12 provided in the n-type semiconductor layer 11 so as to be in contact with the p-type semiconductor layer 13. An outer edge 130 of the p-type semiconductor layer 13 is positioned over a uniform concentration region 121 of the acceptor implantation region 12. An overlap width W 1, which is the width of the overlap between the uniform concentration region 121 and the p-type semiconductor layer 13 as viewed from above, is equal to or larger than 50 μm.

Description

Semiconductor equipment

[0001] This invention relates to a semiconductor device.

[0002] Conventionally, Schottky barrier diodes using gallium oxide semiconductors as the semiconductor layer are known (see Patent Document 1). Gallium oxide semiconductors are excellent semiconductor materials for power devices because they have a high dielectric breakdown field (for example, gallium oxide has a dielectric breakdown field of about 8 MV / cm) and a wide band gap (for example, gallium oxide has a dielectric breakdown field of about 4.8 eV).

[0003] Japanese Patent Publication No. 2016-178250

[0004] However, in the Schottky barrier diode described in Patent Document 1, because it has a simple termination structure, the electric field concentrates at the outer edge of the Schottky barrier electrode provided on the n-type semiconductor layer made of gallium oxide semiconductor during current interruption. As a result, the breakdown voltage of the Schottky barrier diode decreases, and the high dielectric breakdown field of the gallium oxide semiconductor cannot be fully utilized.

[0005] Furthermore, similar problems occur in other semiconductor devices as well. For example, even in the case of a simple termination structure in a pn diode, the electric field concentrates at the outer edge of the p-type semiconductor layer on the n-type semiconductor layer, reducing the breakdown voltage.

[0006] Therefore, in order to manufacture high-voltage semiconductor devices by taking advantage of the high dielectric breakdown field of gallium oxide semiconductors, it is necessary to mitigate the concentration of the electric field by providing a termination structure, such as a Schottky barrier electrode, near the outer periphery of an n-type semiconductor layer made of gallium oxide semiconductor.

[0007] The object of the present invention is to provide a semiconductor device using a semiconductor layer made of a gallium oxide-based semiconductor, which has a termination structure that can effectively suppress the concentration of electric fields that reduce breakdown voltage.

[0008] One aspect of the present invention provides the following semiconductor device to achieve the above objective.

[0009] [1] A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide semiconductor; a p-type semiconductor layer provided on the n-type semiconductor layer and forming a pn junction with the n-type semiconductor layer; an anode electrode provided on the p-type semiconductor layer; a cathode electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided within the n-type semiconductor layer so as to be in contact with the p-type semiconductor layer, wherein the outer edge of the p-type semiconductor layer is located on a constant-concentration region in which the acceptor concentration in the acceptor injection region is constant, and the overlap width, which is the overlap width between the constant-concentration region and the p-type semiconductor layer in a top view, is 50 μm or more. [2] A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide semiconductor; an anode electrode provided on the n-type semiconductor layer and forming a Schottky junction with the n-type semiconductor layer; a cathode electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided in the n-type semiconductor layer so as to be in contact with the anode electrode, wherein the outer edge of the anode electrode is located on a constant-concentration region in the acceptor injection region where the acceptor concentration is constant, and the overlap width, which is the overlap width between the constant-concentration region and the anode electrode in a top view, is 50 μm or more. [3] A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide semiconductor; a source region containing donor impurities provided in the surface layer of the n-type semiconductor layer; an acceptor-containing region containing acceptor impurities provided in the surface layer of the n-type semiconductor layer surrounding the source region; a source electrode provided on the n-type semiconductor layer and connected to the source region; a gate electrode provided on the n-type semiconductor layer via an insulating film; a drain electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided in the n-type semiconductor layer so as to be in contact with the acceptor-containing region, wherein the outer edge of the acceptor-containing region is located on a constant-concentration region in which the acceptor concentration in the acceptor injection region is constant, and the overlap width, which is the overlap width between the constant-concentration region and the acceptor-containing region in a top view, is 50 μm or more.[4] The acceptor injection region has a transition concentration region below the constant concentration region, where the acceptor concentration decreases as it moves away from the constant concentration region. The width W in the depth direction of the constant concentration region ４ (cm) is the width in the depth direction of the transition concentration region, and W ５ (cm). The carrier concentration and dielectric constant of the region where acceptor impurities are not injected in the acceptor injection region of the n-type semiconductor layer are N Ｄ (cm ―３ ), respectively, and ε (F / cm). The breakdown voltage V of the semiconductor device ＢＲ (V), the breakdown electric field of the n-type semiconductor layer 11 is E Ｃ (V / cm), and when the elementary charge is q (C), the semiconductor device according to any one of the above [1] to [3] satisfies the relationship represented by the following formula (1). [5] The bottom of the acceptor injection region reaches the lower surface of the n-type semiconductor layer. The semiconductor device according to any one of the above [1] to [3]. [6] The acceptor injection region has transition concentration regions inside and outside the constant concentration region, where the acceptor concentration decreases as it moves away from the constant concentration region. When the overlap width is W １ (m), and the width of the transition concentration region is W ２ (m), then W ２ ≤ 3W １ - 10 × 10 －６ satisfies the relationship. The semiconductor device according to any one of the above [1] to [3]. [7] When the donor concentration of the n-type semiconductor layer is N Ｄ (m －３ ), and the acceptor concentration of the constant concentration region of the acceptor injection region is N Ａ (m －３ ), then N Ａ > N Ｄ satisfies the relationship. The breakdown electric field of the n-type semiconductor layer is E [[ID=]] Ｃ (V / m), the breakdown voltage of the semiconductor device is V ＢＲ (V), and when the difference between the width of the constant concentration region and the overlap width is W ３ (m), then V ＢＲ / W ３ > E ＣA semiconductor device according to any one of the above items [1] to [3] that satisfies the relationship. [8] The semiconductor device according to the above item [1] or [2], wherein the acceptor injection region contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities. [9] The semiconductor device according to the above item [3], wherein at least one of the acceptor injection region and the acceptor-containing region contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities.

[0010] According to the present invention, it is possible to provide a semiconductor device using a semiconductor layer made of a gallium oxide-based semiconductor, which has a termination structure that can effectively suppress the concentration of electric fields that reduce breakdown voltage.

[0011] Figure 1 is a vertical cross-sectional view of a pn diode according to the first embodiment of the present invention. Figure 2 is a vertical cross-sectional view of a pn diode when the bottom of the constant concentration region does not reach the bottom surface of the n-type semiconductor layer. Figure 3 is a graph showing the measured values ​​of the reverse current density-voltage characteristics of two pn diodes with different overlap widths. Figure 4 is a vertical cross-sectional view of an SBD according to the second embodiment of the present invention. The SBD is a vertical SBD having a planar structure. Figure 5 is a vertical cross-sectional view of a MOS SBD according to the third embodiment of the present invention. Figure 6 is a vertical cross-sectional view of a JBS according to the fourth embodiment of the present invention. Figure 7A is a vertical cross-sectional view of a modified JBS according to the fourth embodiment of the present invention. Figure 7B is a vertical cross-sectional view of a modified JBS according to the fourth embodiment of the present invention. Figure 8 is a vertical cross-sectional view of a MOSFET according to the fifth embodiment of the present invention. Figure 9A is a vertical cross-sectional view of a modified MOSFET according to the fifth embodiment of the present invention. Figure 9B is a vertical cross-sectional view of a modified MOSFET according to the fifth embodiment of the present invention.

[0012] [First Embodiment] As a first embodiment of the present invention, a pn diode 1, which is an example of a semiconductor device according to the present invention, will be described.

[0013] Figure 1 is a vertical cross-sectional view of a pn diode 1 according to a first embodiment of the present invention. The pn diode 1 is a vertical pn diode having a planar structure.

[0014] The pn diode 1 comprises an n-type semiconductor layer 11 made of a gallium oxide semiconductor, a p-type semiconductor layer 13 provided on the n-type semiconductor layer 11 and forming a pn junction with the n-type semiconductor layer 11, an anode electrode 14 provided on the p-type semiconductor layer 13, a cathode electrode 15 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, and an annular acceptor injection region 12 provided in the n-type semiconductor layer 11 so as to be in contact with the p-type semiconductor layer 13.

[0015] In the pn diode 1, when a reverse voltage (positive voltage on the cathode electrode 15 side and negative voltage on the anode electrode 14 side) is applied, the electric field concentrates near the outer edge 130 of the p-type semiconductor layer 13 in the n-type semiconductor layer 11. However, in the acceptor injection region 12, the effective donors are reduced or eliminated by the injection of acceptor impurities, and the strength of the electric field generated by these ionized effective donors decreases or disappears. Therefore, compared to the case where the acceptor injection region 12 is not formed, the electric field concentration near the outer edge 130 of the p-type semiconductor layer 13 in the n-type semiconductor layer 11 is greatly mitigated, and the decrease in the breakdown voltage of the pn diode 1 is suppressed.

[0016] The gallium oxide-based semiconductor material for the n-type semiconductor layer 11 is Ga ２ O ３ Or Ga in which part of the Ga is replaced with Al, In, or both. ２ O ３ (Ga ｘ Al ｙ In （１－ｘ－ｙ） ) ２ O ３ It has a composition represented by (0 < x ≤ 1, 0 ≤ y < 1, 0 < x + y ≤ 1). ２ O ３ Replacing some of the Ga with Al widens the band gap, while replacing it with In narrows the band gap.

[0017] In the pn diode 1, the n-type semiconductor layer 11 contains donor impurities such as Si, Sn, Ge, and Cl. The donor concentration of the n-type semiconductor layer 11 is, for example, 5 × 10⁻¹⁰ １５ ~1 x 10１７ cm －３ Furthermore, the thickness of the n-type semiconductor layer 11 is, for example, 1 to 50 μm.

[0018] The n-type semiconductor layer 11 is typically laminated on the substrate 10, as shown in Figure 1. For example, the substrate 10 is a substrate made of an n-type gallium oxide semiconductor containing donor impurities such as Si, and the n-type semiconductor layer 11 is an epitaxial film formed on the substrate 10 by epitaxial growth.

[0019] The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. １８ ~1 x 10 ２０ cm －３ , has . When the substrate 10 is used, the cathode electrode 15 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via the substrate 10.

[0020] The acceptor implantation region 12 is formed from the upper surface 111 of the n-type semiconductor layer 11 to a predetermined depth by ion implanting acceptor impurities such as N, Mg, Zn, and P into the n-type semiconductor layer 11.

[0021] The acceptor implantation region 12 preferably contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities. Multiple acceptor ions interact with each other in the gallium oxide crystal, modulating the acceptor levels and improving the controllability of the electrical properties.

[0022] The acceptor injection region 12 has a constant-concentration region 121 near its center in the width direction, which is a continuous region where the acceptor concentration is almost constant (for example, the difference in acceptor concentration from the center in the width direction of the acceptor injection region 12 is 5 atomic percent or less), and also has a transition-concentration region 122 and a transition-concentration region 123 inside and outside the constant-concentration region 121, respectively, where the acceptor concentration decreases as you move away from the constant-concentration region 121.

[0023] The transition concentration regions 122 and 123 are formed by the diffusion of implanted acceptor impurities during the annealing process following ion implantation. This annealing process is carried out, for example, using an infrared lamp annealing apparatus, under conditions of 1000°C for 1 hour in a nitrogen atmosphere.

[0024] This annealing process provides effects such as recovery from ion implantation damage and an increase in the depth of the acceptor implantation region 12 due to the diffusion of acceptor impurities in the depth direction.

[0025] The outer edge 130 of the p-type semiconductor layer 13 is located above the constant-concentration region 121 of the acceptor injection region 12, and the overlap width W is the overlap width between the constant-concentration region 121 and the p-type semiconductor layer 13 when viewed from above (i.e., when viewed from above in Figure 1). １ However, it is 50 μm or more. This effectively mitigates the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13. Note that the overlap width W １ Typically, it is constant, but if it is not constant, its minimum width is 50 μm or more.

[0026] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13, the overlap width W １ (m) and the width W of the transition concentration regions 122 and 123. ２ (m) is W ２ ≤3W １ -10 x 10 －６ It is preferable that the relationship is satisfied.

[0027] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13, the donor concentration N of the n-type semiconductor layer 11 is increased. Ｄ (m －３ ) and the acceptor concentration N of the constant concentration region 121 of the acceptor injection region 12 Ａ (m －３ ) but, N Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field E of the n-type semiconductor layer 11 Ｃ (V / m), dielectric breakdown voltage V of pn diode 1 ＢＲ(V) Width W of the constant concentration region 121 that extends outside the p-type semiconductor layer 13 in a top view. ３ (m), that is, the width (m) of the constant concentration region 121 and the overlap width W. １ The difference in (m) is V ＢＲ / W ３ > E Ｃ It is preferable that the relationship is satisfied.

[0028] The resist mask used for ion implantation to form the acceptor implantation region 12 is preferably formed using alignment exposure technology. By using alignment exposure technology, the acceptor implantation region 12 can be formed accurately at the desired position, thus achieving the overlap width W as designed. １ You can obtain this.

[0029] Specifically, first, the wafer on which the n-type semiconductor layer 11 is formed is cleaned by organic cleaning, acid cleaning, etc. Then, multiple alignment marks are formed on the surface of the wafer by etching using photolithography and dry etching technology. After forming a resist film on the upper surface 111 of the n-type semiconductor layer 11, alignment exposure is performed using the formed alignment marks to form a resist mask used for ion implantation to form the acceptor implantation region 12.

[0030] To more effectively mitigate the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13, it is preferable that the bottom of the constant-concentration region 121 of the acceptor injection region 12 reaches the lower surface 112 of the n-type semiconductor layer 11 (the thickness of the constant-concentration region 121 in the depth direction is equal to the thickness of the n-type semiconductor layer 11), as shown in Figure 1.

[0031] Figure 2 is a vertical cross-sectional view of the pn diode 1 when the bottom of the constant concentration region 121 does not reach the bottom surface 112 of the n-type semiconductor layer 11. In this case, the acceptor injection region 12 has a transition concentration region 124 below the constant concentration region 121 (on the substrate 10 side) where the acceptor concentration decreases as it moves away from the constant concentration region 121.

[0032] As shown in Figure 2, if the bottom of the constant concentration region 121 does not reach the lower surface 112 of the n-type semiconductor layer 11, the width in the depth direction of the constant concentration region 121 (depth from the upper surface 111 of the n-type semiconductor layer 11 at the bottom of the constant concentration region 121) W is used to more effectively mitigate the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13. ４ (cm) represents the width in the depth direction of the transition concentration region 124, W. ５ (cm), the carrier concentration and dielectric constant of the central region of the n-type semiconductor layer 11 (the region surrounded by the acceptor injection region 12 where acceptor impurities have not been injected) are set to N, respectively. Ｄ (cm ―３ ) and ε (F / cm), and the dielectric breakdown voltage of pn diode 1 is V ＢＲ (V), the dielectric breakdown field of the n-type semiconductor layer 11 is E Ｃ When the voltage is (V / cm) and the elementary charge is q (C), it is preferable that the relationship expressed by the following equation (1) is satisfied.

[0033]

[0034] The p-type semiconductor layer 13 is, for example, NiO, Cu ２ O, CuO, AgO, SnO ２ , GeO ２ , Ir ２ O ３ , Rh ２ O ３ It consists of p-type semiconductors such as diamond.

[0035] The p-type semiconductor layer 13 may be single crystal, polycrystalline, or amorphous. When the p-type semiconductor layer 13 is single crystal, the quality of the interface between the p-type semiconductor layer 13 and the n-type semiconductor layer 11 is stable, and the electrical characteristics of the pn diode 1 are stable (individual variations are reduced).

[0036] When the p-type semiconductor layer 13 is polycrystalline or amorphous, it can be formed relatively easily using a sputtering apparatus or the like, without requiring a large-scale epitaxial growth apparatus. For example, polycrystalline NiO, Cu ２ O and other elements can be suitably used as the material for the p-type semiconductor layer 13.

[0037] The p-type semiconductor layer 13 is formed, for example, by the lift-off method. A specific example is described below. First, a resist film is formed on the upper surface 111 of the n-type semiconductor layer 11, and a resist mask is formed by opening the region for forming the p-type semiconductor layer 13 using photolithography. During this photolithography, alignment exposure can be performed using the alignment marks formed on the wafer when forming the acceptor injection region 12. Next, a p-type semiconductor film is formed on the upper surface 111 of the n-type semiconductor layer 11 on which the resist mask has been formed by sputtering. Then, ultrasonic vibration is applied to the wafer in an organic solvent to remove (lift off) the resist mask along with the unwanted p-type semiconductor film formed thereon, thereby forming a circular p-type semiconductor layer 13.

[0038] Furthermore, the p-type semiconductor layer 13 can be a gallium oxide-based semiconductor or (Ir Ｘ Rh Ｙ Ga １－Ｘ－Ｙ ) ２ O ３ A layer made of a gallium oxide mixed crystal such as (0 ≤ X + Y ≤ 1) can be used. Even in this case, rectification characteristics can be obtained. Since layers made of gallium oxide semiconductors or gallium oxide mixed crystals are easily formed as single crystals on the upper surface 111 of the n-type semiconductor layer 11 made of gallium oxide semiconductors, the electrical characteristics of the pn diode 1 are stabilized.

[0039] The anode electrode 14 has, for example, a Ni / Al stacked structure and is in ohmic contact with the p-type semiconductor layer 13. The anode electrode 14 is formed, for example, on the p-type semiconductor layer 13 by a lift-off method in which a Ni film and an Al film are sequentially formed by electron beam deposition on a resist mask formed by photolithography, and then the resist mask is removed.

[0040] The cathode electrode 15 has, for example, a Ti / Ni / Al multilayer structure and makes ohmic contact with the substrate 10. The cathode electrode 15 is formed, for example, by sequentially forming a Ti film, a Ni film, and an Al film on the back surface of the substrate 10 by electron beam deposition.

[0041] Figure 3 shows the overlap width W.１ It is a graph showing the measured values of the reverse current density-voltage characteristics of two different pn diodes.

[0042] The two pn diodes for which the measurement in FIG. 3 was carried out have a donor concentration of 5.6×10 １８ cm －３ of Ga ２ O ３ consisting of a substrate 10, an n-type semiconductor layer 11 with a thickness of 7.6 μm and a donor concentration of 3.4×10 １６ cm －３ of Ga ２ O ３ (the total thickness of the substrate 10 and the n-type semiconductor layer 11 is on average 642 μm), an acceptor implantation region 12 formed by performing an annealing treatment at 1000°C for 1 hour in a nitrogen atmosphere after ion implantation of Mg, and a p-type semiconductor layer 13 made of NiO with a planar shape being a circle with a diameter of 1 mm. And one of these two pn diodes has an overlap width W １ of 50 μm (corresponding to the pn diode​​​​​​​​​​​​​​​​​​​​​​​​(Effects of the First Embodiment) In the pn diode 1 according to the first embodiment of the present invention, the acceptor injection region 12 effectively mitigates the concentration of the electric field near the outer edge 130 of the p-type semiconductor layer 13 in the n-type semiconductor layer 11 and near the outer edge of the layer made of gallium oxide semiconductor or gallium oxide mixed crystal when a reverse voltage is applied, thereby suppressing a decrease in breakdown voltage.

[0046] [Second Embodiment] As a second embodiment of the present invention, an example of a semiconductor device according to the present invention, an SBD (Schottky barrier diode) 2, will be described. Note that the same points as in the first embodiment described above may be omitted or simplified.

[0047] Figure 4 is a vertical cross-sectional view of an SBD2 according to a second embodiment of the present invention. The SBD2 is a vertical SBD having a planar structure.

[0048] The SBD2 comprises an n-type semiconductor layer 11 made of a gallium oxide semiconductor, an anode electrode 20 provided on the n-type semiconductor layer 11 and forming a Schottky junction with the n-type semiconductor layer 11, a cathode electrode 15 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, and an annular acceptor injection region 12 provided in the n-type semiconductor layer 11 so as to be in contact with the anode electrode 20.

[0049] In SBD2, when a reverse voltage (positive voltage on the cathode electrode 15 side and negative voltage on the anode electrode 20 side) is applied, the electric field concentrates near the outer edge 200 of the anode electrode 20 in the n-type semiconductor layer 11. However, in the acceptor injection region 12, the injection of acceptor impurities reduces or eliminates effective donors, and the intensity of the electric field generated by these ionized effective donors decreases or disappears. Therefore, compared to the case where the acceptor injection region 12 is not formed, the electric field concentration near the outer edge 200 of the anode electrode 20 in the n-type semiconductor layer 11 is greatly mitigated, and the decrease in the breakdown voltage of SBD2 is suppressed.

[0050] In SBD2, the n-type semiconductor layer 11 contains donor impurities such as Si, Sn, Ge, and Cl. Furthermore, the donor concentration of the n-type semiconductor layer 11 is, for example, 5 × 10⁻⁶. １５ ~1 x 10 １７ cm －３ Furthermore, the thickness of the n-type semiconductor layer 11 is, for example, 1 to 50 μm.

[0051] The n-type semiconductor layer 11 is typically laminated on the substrate 10, as shown in Figure 4, similar to that of the pn diode 1 in the first embodiment. The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. １８ ~1 x 10 ２０ cm －３ , has . When the substrate 10 is used, the cathode electrode 15 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via the substrate 10.

[0052] The configuration of the acceptor injection region 12 is the same as that of the pn diode 1 according to the first embodiment.

[0053] The outer edge 200 of the anode electrode 20 is located above the constant concentration region 121 of the acceptor injection region 12, and the overlap width W is the overlap width between the constant concentration region 121 and the anode electrode 20 when viewed from above (i.e., when viewed from above in Figure 4). １ However, it is 50 μm or more. This effectively mitigates the concentration of the electric field near the outer edge 200 of the anode electrode 20. Note that the overlap width W １ Typically, it is constant, but if it is not constant, its minimum width is 50 μm or more.

[0054] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 200 of the anode electrode 20, the overlap width W １ (m) and the width W of the transition concentration regions 122 and 123. ２ (m) is W ２ ≤3W １ -10 x 10 －６ It is preferable that the relationship is satisfied.

[0055] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 200 of the anode electrode 20, the donor concentration N of the n-type semiconductor layer 11 is increased. Ｄ (m －３ ) and the acceptor concentration N of the constant concentration region 121 of the acceptor injection region 12 Ａ (m －３ ) but, N Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field E of the n-type semiconductor layer 11 Ｃ (V / m), Dielectric breakdown voltage of SBD2 V ＢＲ (V) The width W of the constant concentration region 121 that extends outside the anode electrode 20 in a top view. ３ (m), that is, the width (m) of the constant concentration region 121 and the overlap width W. １ The difference in (m) is V ＢＲ / W ３ > E Ｃ It is preferable that the relationship is satisfied.

[0056] To more effectively mitigate the concentration of the electric field near the outer edge 200 of the anode electrode 20, it is preferable that the bottom of the constant-concentration region 121 of the acceptor injection region 12 reaches the lower surface 112 of the n-type semiconductor layer 11, as shown in Figure 4.

[0057] If the bottom of the constant concentration region 121 does not reach the lower surface 112 of the n-type semiconductor layer 11, the acceptor injection region 12 has a transition concentration region 124 below the constant concentration region 121 where the acceptor concentration decreases as it moves away from the constant concentration region 121.

[0058] In that case, in order to more effectively mitigate the concentration of the electric field near the outer edge 200 of the anode electrode 20, the width W in the depth direction of the constant concentration region 121 is ４ (cm) represents the width in the depth direction of the transition concentration region 124, W. ５ (cm), the carrier concentration and dielectric constant of the central region of the n-type semiconductor layer 11 (the region surrounded by the acceptor injection region 12 where acceptor impurities have not been injected) are set to N, respectively. Ｄ (cm ―３ ) and ε (F / cm), and the dielectric breakdown voltage of SBD2 is V ＢＲ (V), the dielectric breakdown field of the n-type semiconductor layer 11 is E ＣWhen the voltage is (V / cm) and the elementary charge is q (C), it is preferable that the relationship expressed by equation (1) above is satisfied.

[0059] The anode electrode 20 is made of, for example, Pt, Ni, Mo, Fe, Co, Pd, Au, Cr, Cu, Rh, Ir, W, etc.

[0060] (Effects of the second embodiment) In the SBD2 according to the second embodiment of the present invention, the acceptor injection region 12 effectively mitigates the concentration of the electric field near the outer edge 200 of the anode electrode 20 in the n-type semiconductor layer 11 when a reverse voltage is applied, thereby suppressing a decrease in breakdown voltage.

[0061] [Third Embodiment] As a third embodiment of the present invention, a MOS-Schottky barrier diode (MOS-SBD) 3, which is an example of a semiconductor device according to the present invention, will be described. Note that the same points as in the first embodiment described above may be omitted or simplified in the description.

[0062] Figure 5 is a vertical cross-sectional view of a MOSBD3 according to a third embodiment of the present invention. The MOSBD3 is a vertical Schottky barrier diode having a trench MOS structure.

[0063] The MOS SBD3 comprises an n-type semiconductor layer 11 made of a gallium oxide-based semiconductor, an anode electrode 31 provided on the n-type semiconductor layer 11 and forming a Schottky junction with the n-type semiconductor layer 11, a cathode electrode 15 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, and an annular acceptor injection region 12 provided within the n-type semiconductor layer 11 so as to be in contact with the anode electrode 31.

[0064] In the MOS SBD3, a trench 113 opening to the upper surface 111 is formed in the n-type semiconductor layer 11, an insulating film 30 covers the inner surface of the trench 113, and the anode electrode 31 is connected to the mesa portion 114 between the trenches 113 of the n-type semiconductor layer 11 and is located inside the insulating film 30 within the trench 113. A pad electrode 32 is also formed on the anode electrode 31.

[0065] In MOS SBD3, when a reverse voltage (positive voltage on the cathode electrode 15 side and negative voltage on the anode electrode 31 side) is applied, the electric field concentrates near the outer edge 310 of the anode electrode 31 in the n-type semiconductor layer 11. However, in the acceptor injection region 12, the injection of acceptor impurities reduces or eliminates effective donors, and the intensity of the electric field generated by these ionized effective donors decreases or disappears. Therefore, compared to the case where the acceptor injection region 12 is not formed, the electric field concentration near the outer edge 310 of the anode electrode 31 in the n-type semiconductor layer 11 is greatly mitigated, and the decrease in breakdown voltage of MOS SBD3 is suppressed.

[0066] In MOS SBD3, the n-type semiconductor layer 11 contains donor impurities such as Si, Sn, Ge, and Cl. Furthermore, the donor concentration of the n-type semiconductor layer 11 is, for example, 5 × 10⁻⁶. １５ ~1 x 10 １７ cm －３ Furthermore, the thickness of the n-type semiconductor layer 11 is, for example, 1 to 50 μm.

[0067] The n-type semiconductor layer 11 is typically laminated on the substrate 10, as shown in Figure 5, similar to that of the pn diode 1 in the first embodiment. The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. １８ ~1 x 10 ２０ cm －３ , has . When the substrate 10 is used, the cathode electrode 15 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via the substrate 10.

[0068] The configuration of the acceptor injection region 12 is the same as that of the pn diode 1 according to the first embodiment.

[0069] The outer edge 310 of the anode electrode 31 is located above the constant concentration region 121 of the acceptor injection region 12, and the overlap width W is the overlap width between the constant concentration region 121 and the anode electrode 31 when viewed from above (i.e., when viewed from above in Figure 5). １However, it is 50 μm or more. This effectively mitigates the concentration of the electric field near the outer edge 310 of the anode electrode 31 in the n-type semiconductor layer 11. Note that the overlap width W １ Typically, it is constant, but if it is not constant, its minimum width is 50 μm or more.

[0070] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 310 of the anode electrode 31, the overlap width W １ (m) and the width W of the transition concentration regions 122 and 123. ２ (m) is W ２ ≤3W １ -10 x 10 －６ It is preferable that the relationship is satisfied.

[0071] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 310 of the anode electrode 31, the donor concentration N of the n-type semiconductor layer 11 is increased. Ｄ (m －３ ) and the acceptor concentration N of the constant concentration region 121 of the acceptor injection region 12 Ａ (m －３ ) but, N Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field E of the n-type semiconductor layer 11 Ｃ (V / m), dielectric breakdown voltage V of MOS SBD3 ＢＲ (V) The width W of the constant concentration region 121 that extends outside the anode electrode 31 in a top view. ３ (m), that is, the width (m) of the constant concentration region 121 and the overlap width W. １ The difference in (m) is V ＢＲ / W ３ > E Ｃ It is preferable that the relationship is satisfied.

[0072] To more effectively mitigate the concentration of the electric field near the outer edge 310 of the anode electrode 31, it is preferable that the bottom of the constant-concentration region 121 of the acceptor injection region 12 reaches the lower surface 112 of the n-type semiconductor layer 11, as shown in Figure 5.

[0073] If the bottom of the constant concentration region 121 does not reach the lower surface 112 of the n-type semiconductor layer 11, the acceptor injection region 12 has a transition concentration region 124 below the constant concentration region 121 where the acceptor concentration decreases as it moves away from the constant concentration region 121.

[0074] In that case, in order to more effectively mitigate the concentration of the electric field near the outer edge 310 of the anode electrode 31, the width W in the depth direction of the constant concentration region 121 is ４ (cm) represents the width in the depth direction of the transition concentration region 124, W. ５ (cm), the carrier concentration in the central region of the n-type semiconductor layer 11 (the region surrounded by the acceptor injection region 12 where acceptor impurities have not been injected) is N Ｄ (cm ―３ ), the dielectric constant is ε (F / cm), and the dielectric breakdown voltage of MOS SBD3 is V ＢＲ (V), the dielectric breakdown field of the n-type semiconductor layer 11 is E Ｃ When the voltage is (V / cm) and the elementary charge is q (C), it is preferable that the relationship expressed by equation (1) above is satisfied.

[0075] The insulating film 30 is, for example, SiO ２ Al ２ O ３ , HfO ２ The components consist of the following: The anode electrode 31 consists of, for example, Pt, Ni, Mo, Fe, Co, Pd, Au, Cr, Cu, Rh, Ir, W, etc. The pad electrode 32 consists of, for example, Al, Au, Cu, etc.

[0076] (Effects of the third embodiment) In the MOSBD3 according to the third embodiment of the present invention, the acceptor injection region 12 effectively mitigates the concentration of the electric field near the outer edge 310 of the anode electrode 31 in the n-type semiconductor layer 11 when a reverse voltage is applied, thereby suppressing a decrease in breakdown voltage.

[0077] [Fourth Embodiment] As a fourth embodiment of the present invention, a JBS (Junction Barrier Schottky Barrier Diode) 4, which is an example of a semiconductor device according to the present invention, will be described. Note that the same points as in the first embodiment described above may be omitted or simplified.

[0078] Figure 6 is a vertical cross-sectional view of a JBS4 according to a fourth embodiment of the present invention. The JBS4 is a vertical Schottky barrier diode having a junction barrier Schottky structure.

[0079] JBS4 comprises an n-type semiconductor layer 11 made of a gallium oxide semiconductor, a p-type semiconductor layer 40 provided on the n-type semiconductor layer 11 and forming a pn junction with the n-type semiconductor layer 11, an anode electrode 41 provided on the p-type semiconductor layer 40, a cathode electrode 15 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, and an annular acceptor injection region 12 provided in the n-type semiconductor layer 11 so as to be in contact with the p-type semiconductor layer 13.

[0080] In JBS4, the p-type semiconductor layer 40 is embedded in a plurality of trenches 113 that open to the upper surface 111 formed in the n-type semiconductor layer 11, and the anode electrode 41 is connected to the mesa portion 114 between the trenches 113 of the n-type semiconductor layer 11, so that the anode electrode 41 and the mesa portion 114 form a Schottky junction.

[0081] In JBS4, when a reverse voltage (positive voltage on the cathode electrode 15 side and negative voltage on the anode electrode 41 side) is applied, the electric field concentrates near the outer edge 400 of the p-type semiconductor layer 40 in the n-type semiconductor layer 11. However, in the acceptor injection region 12, the effective donors are reduced or eliminated by the injection of acceptor impurities, and the strength of the electric field generated by these ionized effective donors decreases or disappears. Therefore, compared to the case where the acceptor injection region 12 is not formed, the electric field concentration near the outer edge 400 of the p-type semiconductor layer 40 in the n-type semiconductor layer 11 is greatly mitigated, and the decrease in the breakdown voltage of JBS4 is suppressed.

[0082] In JBS4, the n-type semiconductor layer 11 contains donor impurities such as Si, Sn, Ge, and Cl. Furthermore, the donor concentration of the n-type semiconductor layer 11 is, for example, 5 × 10⁻⁶. １５ ~1 x 10 １７ cm －３ Furthermore, the thickness of the n-type semiconductor layer 11 is, for example, 1 to 50 μm.

[0083] The n-type semiconductor layer 11 is typically laminated on the substrate 10, as shown in Figure 6, similar to that of the pn diode 1 in the first embodiment. The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. １８ ~1 x 10 ２０ cm －３ , has . When the substrate 10 is used, the cathode electrode 15 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via the substrate 10.

[0084] The configuration of the acceptor injection region 12 is the same as that of the pn diode 1 according to the first embodiment.

[0085] The outer edge 400 of the p-type semiconductor layer 40 is located above the constant-concentration region 121 of the acceptor injection region 12, and the overlap width W is the overlap width between the constant-concentration region 121 and the p-type semiconductor layer 40 when viewed from above (i.e., when viewed from above in Figure 6). １ However, it is 50 μm or more. This effectively mitigates the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40. Note that the overlap width W １ Typically, it is constant, but if it is not constant, its minimum width is 50 μm or more.

[0086] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40, the overlap width W １ (m) and the width W of the transition concentration regions 122 and 123. ２ (m) is W ２ ≤3W １ -10 x 10 －６ It is preferable that the relationship is satisfied.

[0087] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40, the donor concentration N of the n-type semiconductor layer 11 is increased. Ｄ (m －３ ) and the acceptor concentration N of the constant concentration region 121 of the acceptor injection region 12 Ａ (m －３ ) but, N Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field E of the n-type semiconductor layer 11 Ｃ(V / m), Dielectric breakdown voltage of JBS4 V ＢＲ (V) Width W of the constant concentration region 121 extending outside the p-type semiconductor layer 40 in a top view. ３ (m), that is, the width (m) of the constant concentration region 121 and the overlap width W. １ The difference in (m) is V ＢＲ / W ３ > E Ｃ It is preferable that the relationship is satisfied.

[0088] To more effectively mitigate the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40, it is preferable that the bottom of the constant-concentration region 121 of the acceptor injection region 12 reaches the lower surface 112 of the n-type semiconductor layer 11, as shown in Figure 6.

[0089] If the bottom of the constant concentration region 121 does not reach the lower surface 112 of the n-type semiconductor layer 11, the acceptor injection region 12 has a transition concentration region 124 below the constant concentration region 121 where the acceptor concentration decreases as it moves away from the constant concentration region 121.

[0090] In that case, in order to more effectively mitigate the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40, the width W in the depth direction of the constant concentration region 121 is ４ (cm) represents the width in the depth direction of the transition concentration region 124, W. ５ (cm), the carrier concentration in the central region of the n-type semiconductor layer 11 (the region surrounded by the acceptor injection region 12 where acceptor impurities have not been injected) is N Ｄ (cm ―３ ), the dielectric constant is ε (F / cm), and the dielectric breakdown voltage of JBS4 is V ＢＲ (V), the dielectric breakdown field of the n-type semiconductor layer 11 is E Ｃ When the voltage is (V / cm) and the elementary charge is q (C), it is preferable that the relationship expressed by equation (1) above is satisfied.

[0091] The p-type semiconductor layer 40 is, for example, NiO, Cu ２ O, CuO, Ir ２ O ３ , Rh ２ O ３ , Si, Ge, GeO ２It consists of a p-type semiconductor such as GaN or diamond. The p-type semiconductor layer 40 may be single crystal, polycrystalline, or amorphous. Note that as the p-type semiconductor layer 40, Ga ２ O ３ Gallium oxide-based semiconductors such as (Ga Ｘ Ir １－Ｘ ) ２ O ３ (0 < X ​​< 1), (Ga Ｘ Rh １－Ｘ ) ２ O ３ A layer consisting of a gallium oxide mixed crystal such as (0 < X ​​< 1) can be used. The anode electrode 41 is made of, for example, Pt, Ni, Mo, Fe, Co, Pd, Au, Cr, Cu, Rh, Ir, W, etc.

[0092] Figures 7A and 7B are vertical cross-sectional views of JBS4a and 4b, which are modified versions of JBS4, respectively.

[0093] In JBS4a shown in Figure 7A, the p-type semiconductor layer 40 is formed on the upper surface 111 of the n-type semiconductor layer 11. Then, a Schottky junction is formed between the anode electrode 41 and a mesa-shaped n-type semiconductor portion 42, which is provided as part of the n-type semiconductor layer 11, in the gap of the p-type semiconductor layer 40.

[0094] This structure allows for a smaller capacitance between the anode electrode 41 and the cathode electrode 15 compared to JBS4, resulting in superior electrical characteristics.

[0095] JBS4b, shown in Figure 7B, uses a p-type semiconductor layer 43 made of a film-like p-type semiconductor instead of the p-type semiconductor layer 40 in JBS4a.

[0096] Since the p-type semiconductor layer 43 is composed of a film-like p-type semiconductor, it has lower electrical resistance than the p-type semiconductor layer 40 in JBS4a, and is more resistant to surge currents that occur when an excessive forward voltage is applied between the anode electrode 41 and the cathode electrode 15. In other words, JBS4b has better surge current resistance than JBS4a.

[0097] In JBS4a and 4b, the same conditions as in JBS4 (W １、 W ２ , W３ , N Ｄ , N Ａ By satisfying conditions such as the depth of the bottom of the acceptor injection region 12, the acceptor injection region 12 can effectively mitigate the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40 or near the outer edge 430 of the p-type semiconductor layer 43.

[0098] (Effects of the fourth embodiment) In the JBS4, 4a, and 4b according to the fourth embodiment of the present invention, the acceptor injection region 12 effectively mitigates the concentration of the electric field near the outer edge 400 of the p-type semiconductor layer 40 or near the outer edge 430 of the p-type semiconductor layer 43 in the n-type semiconductor layer 11 when a reverse voltage is applied, thereby suppressing a decrease in breakdown voltage.

[0099] [Fifth Embodiment] As a fifth embodiment of the present invention, a MOSFET (MOS field-effect transistor) 5, which is an example of a semiconductor device according to the present invention, will be described. Note that the same points as in the first embodiment described above may be omitted or simplified.

[0100] Figure 8 is a vertical cross-sectional view of a MOSFET 5 according to a fifth embodiment of the present invention. The MOSFET 5 is a vertical field-effect transistor having a planar structure. The MOSFET 5 shown in Figure 8 is a MOSFET that includes a plurality of unit cell structures.

[0101] The MOSFET 5 comprises an n-type semiconductor layer 11 made of a gallium oxide semiconductor, a source region 51 containing donor impurities provided in the surface layer of the n-type semiconductor layer 11, an acceptor-containing region 50 containing acceptor impurities provided in the surface layer of the n-type semiconductor layer 11 surrounding the source region 51, a source electrode 56 provided on the n-type semiconductor layer 11 and connected to the source region 51, a gate electrode 53 provided on the n-type semiconductor layer 11 via an insulating film 54, a drain electrode 57 directly or indirectly connected to the lower surface 112 of the n-type semiconductor layer 11, and an annular acceptor injection region 12 provided in the n-type semiconductor layer 11 so as to be in contact with the acceptor-containing region 50.

[0102] The source region 51 is a region in the n-type semiconductor layer 11 into which donor impurities such as Si, Sn, Ge, and Cl are implanted, and it functions as a contact region with the source electrode 56.

[0103] The acceptor-containing region 50 is a region in the n-type semiconductor layer 11 into which acceptor impurities such as N, Mg, Zn, and P are implanted, and functions as a well surrounding the source region 51. When a voltage is applied to the gate electrode 53, a channel is formed in the acceptor-containing region 50 near the gate electrode 53.

[0104] The acceptor-containing region 50 preferably contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities. Multiple acceptor ions interact with each other in the gallium oxide crystal, modulating the acceptor levels and improving the controllability of the electrical properties.

[0105] The acceptor-containing region 52, like the acceptor-containing region 50, functions to block the current flowing between the source electrode 56 and the n-type semiconductor region, or to reduce the contact resistance with the source electrode 56, thereby facilitating the transmission of the source potential to the acceptor-containing region 50.

[0106] The gate electrode 53 is insulated from the n-type semiconductor layer 11 and the source electrode 56 by being surrounded by an insulating film 54. In addition, the upper surface 111 of the outer n-type semiconductor layer 11 of multiple MOSFET cells is covered with an insulating film 55.

[0107] In MOSFET 5, when a drain voltage (a positive voltage on the drain electrode 57 side) is applied, the electric field concentrates near the outer edge 500 of the acceptor-containing region 50 in the n-type semiconductor layer 11 (the outer edge of the outermost acceptor-containing region 50 if there are multiple MOSFET cells as shown in Figure 8) 500. However, in the acceptor-injection region 12, the injection of acceptor impurities reduces or eliminates effective donors, and the intensity of the electric field generated by these ionized effective donors decreases or disappears. Therefore, compared to the case where the acceptor-injection region 12 is not formed, the electric field concentration near the outer edge 500 of the acceptor-containing region 50 in the n-type semiconductor layer 11 is greatly mitigated, and the decrease in the breakdown voltage of MOSFET 5 is suppressed.

[0108] In MOSFET 5, the n-type semiconductor layer 11 contains donor impurities such as Si, Sn, Ge, and Cl. The donor concentration of the n-type semiconductor layer 11 is, for example, 5 × 10⁻¹⁰ １５ ~1 x 10 １７ cm －３ Furthermore, the thickness of the n-type semiconductor layer 11 is, for example, 1 to 50 μm.

[0109] The n-type semiconductor layer 11 is typically laminated on the substrate 10, as shown in Figure 8, similar to that of the pn diode 1 in the first embodiment. The substrate 10 has a higher donor concentration than the n-type semiconductor layer 11, for example, 1 × 10⁻¹⁶. １８ ~1 x 10 ２０ cm －３ , has . When substrate 10 is used, the drain electrode 57 is indirectly connected to the lower surface 112 of the n-type semiconductor layer 11 via substrate 10.

[0110] The configuration of the acceptor injection region 12 is the same as that of the pn diode 1 according to the first embodiment. Normally, when forming the acceptor injection region 12, the region in which impurities are injected overlaps with a portion of the region in which impurities are injected when forming the acceptor-containing region 50. Therefore, a portion of the acceptor injection region 12 overlaps with the acceptor-containing region 50. Furthermore, the acceptor injection region 12 may overlap not only with the outermost acceptor-containing region 50, but with multiple acceptor-containing regions 50.

[0111] The outer edge 500 of the acceptor-containing region 50 is located above the constant-concentration region 121 of the acceptor injection region 12, and the overlap width W is the overlap width between the constant-concentration region 121 and the acceptor-containing region 50 when viewed from above (i.e., when viewed from above in Figure 8). １ However, it is 50 μm or more. This effectively mitigates the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50. Note that the overlap width W １ Typically, it is constant, but if it is not constant, its minimum width is 50 μm or more.

[0112] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50, the overlap width W １ (m) and the width W of the transition concentration regions 122 and 123. ２ (m) is W ２ ≤3W １ -10 x 10 －６ It is preferable that the relationship is satisfied.

[0113] Furthermore, in order to more effectively mitigate the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50, the donor concentration N of the n-type semiconductor layer 11 is increased. Ｄ (m －３ ) and the acceptor concentration N of the constant concentration region 121 of the acceptor injection region 12 Ａ (m －３ ) but, N Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field E of the n-type semiconductor layer 11 Ｃ (V / m), dielectric breakdown voltage V of MOSFET 5 ＢＲ(V) Width W of the constant concentration region 121 that extends outside the acceptor-containing region 50 in a top view. ３ (m), that is, the width (m) of the constant concentration region 121 and the overlap width W. １ The difference in (m) is V ＢＲ / W ３ > E Ｃ It is preferable that the relationship is satisfied.

[0114] To more effectively mitigate the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50, it is preferable that the bottom of the constant-concentration region 121 of the acceptor-injection region 12 reaches the lower surface 112 of the n-type semiconductor layer 11, as shown in Figure 8.

[0115] If the bottom of the constant concentration region 121 does not reach the lower surface 112 of the n-type semiconductor layer 11, the acceptor injection region 12 has a transition concentration region 124 below the constant concentration region 121 where the acceptor concentration decreases as it moves away from the constant concentration region 121.

[0116] In that case, in order to more effectively mitigate the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50, the width W in the depth direction of the constant concentration region 121 is ４ (cm) represents the width in the depth direction of the transition concentration region 124, W. ５ (cm), the carrier concentration in the central region of the n-type semiconductor layer 11 (the region surrounded by the acceptor injection region 12 where acceptor impurities have not been injected) is N Ｄ (cm －３ ), the dielectric constant is ε (F / cm), and the dielectric breakdown voltage of MOSFET 5 is V ＢＲ (V), the dielectric breakdown field of the n-type semiconductor layer 11 is E Ｃ When the voltage is (V / cm) and the elementary charge is q (C), it is preferable that the relationship expressed by equation (1) above is satisfied.

[0117] Figures 9A and 9B are vertical cross-sectional views of MOSFETs 5a and 5b, which are modified versions of MOSFET 5, respectively.

[0118] In the MOSFET 5a shown in Figure 9A, acceptor-containing regions 52 are formed outside the cells of the multiple MOSFETs, and the source electrode 56 is in contact with these regions. Furthermore, in the MOSFET 5a, the gate electrode 53 is insulated from the n-type semiconductor layer 11 by an insulating film 58 covering its lower surface, and insulated from the source electrode 56 by an insulating film 59 covering its upper and side surfaces.

[0119] In the MOSFET 5b shown in Figure 9B, a gate electrode 60 is formed on the outside of a cell of multiple MOSFETs including a gate electrode 53, and a source electrode 63 that contacts an acceptor-containing region 52 is provided further outside of the gate electrode 60. The gate electrode 60 includes a first portion 61 formed simultaneously with the gate electrode 53 from the same material, and a second portion 62 above it.

[0120] In MOSFETs 5a and 5b, the same conditions as in MOSFET 5 (W １、 W ２ , W ３ , N Ｄ , N Ａ By satisfying conditions such as the depth of the bottom of the acceptor injection region 12, the acceptor injection region 12 can effectively mitigate the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50.

[0121] (Effects of the Fifth Embodiment) In the MOSFETs 5, 5a, and 5b according to the fifth embodiment of the present invention, the acceptor injection region 12 effectively mitigates the concentration of the electric field near the outer edge 500 of the acceptor-containing region 50 in the n-type semiconductor layer 11 when a reverse voltage is applied, thereby suppressing a decrease in breakdown voltage.

[0122] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Furthermore, the components of the above embodiments can be arbitrarily combined without departing from the spirit of the invention. Moreover, the embodiments described above do not limit the invention as claimed. It should also be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention.

[0123] The present invention provides a semiconductor device using a semiconductor layer made of a gallium oxide-based semiconductor, which has a termination structure that can effectively suppress the concentration of electric fields that reduce breakdown voltage.

[0124] 1…pn diode, 11…n-type semiconductor layer, 12…acceptor injection region, 121…constant concentration region, 122, 123…transition concentration region, 13…p-type semiconductor layer, 130…outer edge, 14…anode electrode, 15…cathode electrode, 2…SBD, 20…anode electrode, 200…outer edge, 3…MOS SBD, 31…anode electrode, 310…outer edge, 4, 4a, 4b…JBS, 40, 43…p-type semiconductor layer, 400, 430…outer edge, 5, 5a, 5b…MOSFET, 50…acceptor-containing region, 500…outer edge

Claims

1. A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide-based semiconductor; a p-type semiconductor layer provided on the n-type semiconductor layer and forming a pn junction with the n-type semiconductor layer; an anode electrode provided on the p-type semiconductor layer; a cathode electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided within the n-type semiconductor layer so as to be in contact with the p-type semiconductor layer, wherein the outer edge of the p-type semiconductor layer is located on a constant-concentration region in which the acceptor concentration in the acceptor injection region is constant, and the overlap width, which is the overlap width between the constant-concentration region and the p-type semiconductor layer in a top view, is 50 μm or more.

2. A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide-based semiconductor; an anode electrode provided on the n-type semiconductor layer and forming a Schottky junction with the n-type semiconductor layer; a cathode electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided in the n-type semiconductor layer so as to be in contact with the anode electrode, wherein the outer edge of the anode electrode is located on a constant-concentration region in the acceptor injection region where the acceptor concentration is constant, and the overlap width, which is the overlap width between the constant-concentration region and the anode electrode in a top view, is 50 μm or more.

3. A semiconductor device comprising: an n-type semiconductor layer made of a gallium oxide semiconductor; a source region containing donor impurities provided in the surface layer of the n-type semiconductor layer; an acceptor-containing region containing acceptor impurities provided in the surface layer of the n-type semiconductor layer surrounding the source region; a source electrode provided on the n-type semiconductor layer and connected to the source region; a gate electrode provided on the n-type semiconductor layer via an insulating film; a drain electrode directly or indirectly connected to the lower surface of the n-type semiconductor layer; and an annular acceptor injection region provided in the n-type semiconductor layer so as to be in contact with the acceptor-containing region, wherein the outer edge of the acceptor-containing region is located on a constant-concentration region in which the acceptor concentration in the acceptor injection region is constant, and the overlap width, which is the overlap width between the constant-concentration region and the acceptor-containing region when viewed from above, is 50 μm or more.

4. The acceptor injection region has a transition concentration region below the constant concentration region, where the acceptor concentration decreases as it moves away from the constant concentration region, and the width W in the depth direction of the constant concentration region. ４ (cm) is the width in the depth direction of the transition concentration region W ５ (cm), the carrier concentration and dielectric constant of the region in the n-type semiconductor layer surrounded by the acceptor injection region where acceptor impurities have not been injected are N, respectively. Ｄ (cm ―３ ) and ε (F / cm), the dielectric breakdown voltage V of the semiconductor device ＢＲ (V) and the dielectric breakdown field of the n-type semiconductor layer 11 is E Ｃ A semiconductor device according to any one of claims 1 to 3, wherein the voltage (V / cm) and the elementary charge q (C) satisfy the relationship expressed by the following equation (1).

5. The semiconductor device according to any one of claims 1 to 3, wherein the bottom of the acceptor injection region reaches the lower surface of the n-type semiconductor layer.

6. The acceptor implantation region has transition concentration regions on the inner and outer sides of the constant concentration region, where the acceptor concentration decreases as the distance from the constant concentration region increases. Let the overlap width be W １ (m), and the width of the transition concentration region be W ２ (m). When this is the case, W ２ ≦ 3W １ −10 × 10 －６ satisfies the relationship. The semiconductor device according to any one of claims 1 to 3.

7. The donor concentration of the n-type semiconductor layer is set to N Ｄ (m －３ ), the acceptor concentration in the constant concentration region of the acceptor injection region is N Ａ (m －３ When N is set to ), Ａ >N Ｄ The relationship is satisfied, and the dielectric breakdown field of the n-type semiconductor layer is E Ｃ (V / m), the dielectric breakdown voltage of the semiconductor device is V ＢＲ (V) The difference between the width of the constant concentration region and the overlap width is W ３ If we let (m), then V ＢＲ / W ３ > E Ｃ A semiconductor device according to any one of claims 1 to 3 that satisfies the relationship.

8. The semiconductor device according to claim 1 or 2, wherein the acceptor injection region contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities.

9. The semiconductor device according to claim 3, wherein at least one of the acceptor injection region and the acceptor containing region contains two or more elements selected from the group consisting of N, Mg, Zn, and P as acceptor impurities.

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