Laminated structure, semiconductor device, electronic equipment, and system

Abstract

[Problem] The purpose of the present invention is to provide a laminated structure that has excellent crystallinity useful for a semiconductor device and the like. [Solution] Provided is a laminated structure in which a crystal film is laminated directly or via another layer on a crystal substrate containing, on part or all of a surface, a crystal having a diamond structure, wherein the crystal film contains SnO2 or a mixed crystal thereof as a main component, the crystal film has a rutile structure, and the crystal film is a mixed crystal of SnO2 and GeO2. This laminated structure is applied to, for example, a semiconductor device.

Description

Stacked Structure, Semiconductor Device, Electronic Apparatus, and System

[0001] The present invention relates to a stacked structure useful for semiconductor devices.

[0002] Conventionally, the industrial use of SnO ２ , ２ ,

[0004] films has been expected to expand. For example, Non-Patent Document 1 describes SnO ２ films on Si substrates. However, the SnO ２ films described in Non-Patent Document 1 are polycrystalline films and cannot fully exhibit the original functions of the SnO ２ films.

[0003] In recent years, rutile-type oxides such as r-SnO ２ have attracted attention as wide-bandgap semiconductors promising for power electronics devices such as wide bandgaps and breakdown electric fields. As an n-type oxide, r-SnO ２ has mainly been studied for transparent electrodes, sensors, and transistors in solar cells and flat panel displays. Among them, r-SnO ２ is regarded as promising as a drift layer of power electronics devices. In recent years, for example, a stacked structure in which an r-SnO ２ crystal film is laminated on an r-TiO ２ (001) substrate has been studied (Non-Patent Document 2). However, the r-TiO ２ (001) substrate has problems such as high price and poor heat dissipation, and has not been satisfactory yet. Therefore, a method capable of manufacturing r-SnO ２ crystals on a substrate with better heat dissipation and lower price than a TiO ２ substrate has been awaited.

[0004] Further, rutile-structured germanium dioxide (r-GeO <00000​​Because it has a band gap of 4.68 eV, allows for the creation of n-type and p-type semiconductors, and can be manufactured inexpensively, it is also expected to be a next-generation semiconductor material.

[0005] Non-patent document 3, patent document 1, patent document 2, and patent document 3 contain r-TiO ２ (001) r-GeO ２ A stacked structure with stacked crystalline films is described. However, Non-Patent Document 3 states that Non-Patent Document 4 was submitted as Erratum after the peer review of Non-Patent Document 3 (Non-Patent Document 4), and that the crystal grains (abnormal grains) described in Non-Patent Document 3 and Patent Document 1 are rutile-type germanium dioxide crystals (r-GeO ２ It was found that the crystalline phase was the one described above, and the rest was the amorphous phase. In other words, the amorphous phase was formed in most of the material, and even when a crystalline phase was formed, only a portion of the crystal grains were formed. Therefore, r-GeO, as described in Non-Patent Document 3, was not formed. ２ GeO with scattered crystal grains ２ Rather than amorphous films, r-GeO has excellent crystallinity and is industrially useful as a semiconductor. ２ A method for manufacturing crystalline films was eagerly awaited.

[0006] Furthermore, Non-Patent Document 5 contains r-TiO ２ r-Sn ｘ Ge １－ｘ O ２ After changing the composition of the thin film and stacking seven layers as an intermediate layer, r-GeO ２ A laminated structure in which thin films are stacked is described. However, r-Sn ｘ Ge １－ｘ O ２ Controlling the composition was difficult, and even when a crystalline phase was formed, only a portion of the crystal grains were formed. In addition, r-TiO ２ (001) There were problems such as the high cost of the substrate, and it was still not satisfactory. Therefore, r-GeO ２ r-SnO that can be used to produce crystalline films ２ The interlayer was eagerly awaited.

[0007] Alexander Nikiforova et al., “Formation of SnO and SnO2 phases during the annealing of SnO(x) filmsobtained by molecular beam epitaxy”, Applied Surface Science 512 (2020) 145735Yui Takahashi1 et al., “Carrier density control of Sb-doped rutile-type SnO2 thin films and fabrication of a vertical Schottky barrier diode”, Applied Physics Express 17, 041002 (2024)H.Takane, K. Kaneko., “Establishment of a growth route of crystallized rutile GeO2 thin film (≧ 1 mm / h) and its structural properties”, Applied Physics Letters Vol.119, pp.062104(1-6) (2021).H.Takane, K. Kaneko., Erratum: “Establishment of a growth route of crystallized rutile GeO2 thin film (≧1 μm / h) and its structural properties”, Applied Physics Letters Vol.120, 099903(1-3) (2022).Kazuki Shimazoe et al., “Growth of water-insoluble rutile GeO2 thin films on (001) TiO2 substrates with graded GexSn1-xO2 buffer layers”, The Japan Society of Applied Physics, Express 17 105501 (2024).

[0008] International Publication No. 2023 / 008452, International Publication No. 2023 / 008453, International Publication No. 2023 / 008454

[0009] The present invention aims to provide a laminated structure having excellent crystallinity that is useful for semiconductor devices and the like.

[0010] As a result of diligent research to achieve the above objective, the present inventors have newly developed a mist CVD apparatus using guide partitions, and have used the mist CVD apparatus using guide partitions to construct a laminated structure in which a crystalline film is laminated directly or via other layers on a crystalline substrate whose surface part or all of the surface contains silicon or a silicon-containing compound as the main component, wherein the crystalline film is made of SnO ２ Alternatively, the inventors succeeded in creating a laminated structure mainly composed of single crystals of the mixed crystal, and found that the resulting laminated structure can be easily manufactured at low cost, possesses excellent crystallinity, and is useful for semiconductor devices, etc. They also found that such a laminated structure can solve the above-mentioned conventional problems all at once. Furthermore, after obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0011] In other words, the present invention relates to the following invention: [1] A laminated structure in which a crystalline film is laminated directly or via another layer on a crystalline substrate containing a crystal having a diamond structure on part or all of its surface, wherein the crystalline film is SnO ２ or a laminated structure characterized by containing a single crystal of the mixed crystal as the main component. [2] The laminated structure according to [1], wherein the crystalline film has a rutile-type structure. [3] The crystalline film is SnO ２ and GeO ２ The laminated structure described in [1] above, which is a mixed crystal of [4] the crystal film is 100 mm ２[1] The laminated structure according to [1] having the above area. [5] The laminated structure according to [1], wherein the thickness of the crystalline film is 300 nm or more. [6] The laminated structure according to [1], wherein the full width at half maximum of the rocking curve measured by X-ray diffraction of the crystalline film is 5300 arcsec or less. [7] The laminated structure according to [1], wherein the surface roughness of the crystalline film is 300 nm or less. [8] The laminated structure according to [1], wherein the crystalline substrate is a Si substrate. [9] The laminated structure according to [1], further comprising a crystalline film mainly composed of a metal oxide containing Ge.

[10] A semiconductor device comprising a laminated structure, characterized in that the laminated structure is the laminated structure according to [1].

[11] The semiconductor device according to

[10] , which is a power device.

[12] The semiconductor device described in

[10] , which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor field-effect transistor (MESFET), an electrostatic induction transistor (SIT), a high electron-mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), or a light-emitting diode (LED).

[13] An electronic device including a semiconductor device, characterized in that the semiconductor device is the semiconductor device described in

[10] .

[14] A system including an electronic device, characterized in that the electronic device is the electronic device described in

[13] .

[0012] The laminated structure of the present invention is useful for semiconductor devices and the like, and exhibits excellent crystallinity.

[0013] This is an example of a schematic configuration diagram of a film deposition apparatus suitably used in the present invention. This is a schematic diagram showing an atomizing apparatus suitably used in the present invention. This is a schematic diagram showing a cross-sectional view of an atomizing apparatus suitably used in the present invention, viewed from the side. This is a diagram showing the XRD diffraction results in Example 1. This is a diagram showing an enlarged view of the XRD analysis results in Figure 4 in Example 1. This is a diagram showing the ω scan in the X-ray diffraction measurement in Example 1. This is a diagram showing the SEM image in Example 1. This is a diagram showing the EDS image in Example 1. This is a diagram showing the AFM image in Example 1. This is a diagram showing the XRD diffraction results in Comparative Example 1. This is a schematic diagram showing a suitable example of the Schottky barrier diode (SBD) of the present invention. This is a schematic diagram showing a suitable example of the high electron mobility transistor (HEMT) of the present invention. This is a schematic diagram showing a suitable example of the metal oxide semiconductor field-effect transistor (MOSFET) of the present invention. This is a schematic diagram showing a suitable example of the junction field-effect transistor (JFET) of the present invention. This is a schematic diagram showing a suitable example of the insulated gate bipolar transistor (IGBT) of the present invention. This figure schematically shows a preferred example of a light-emitting element (LED) of the present invention. This figure schematically shows a preferred example of a junction barrier Schottky diode (JBS) of the present invention. This figure schematically shows a preferred example of a metal-semiconductor field-effect transistor (MESFET) of the present invention. This figure schematically shows a preferred example of an electrostatic induction transistor (SIT) of the present invention. This is a schematic diagram for explaining part of the manufacturing process of the SIT in Figure 19. This figure schematically shows a preferred example of a power supply system device according to the present invention. This figure schematically shows a preferred example of a system device according to the present invention. This figure schematically shows a preferred example of a power supply circuit diagram of a power supply device according to the present invention.

[0014] The present invention relates to a laminated structure in which a crystalline film is laminated directly or via another layer on a crystalline substrate containing a crystal having a diamond structure on part or all of its surface, wherein the crystalline film is SnO ２Alternatively, it is characterized by containing a mixed crystal thereof as the main component. In this specification, "film" can be read as "layer". A "laminated structure" is a structure that includes one or more crystalline layers, and may also include layers other than crystalline layers (e.g., amorphous layers).

[0015] In this invention, the "main component" refers to SnO in the crystalline film. ２ Alternatively, it means that the single crystal content of the mixed crystal is 50 at% or more in terms of composition ratio (atomic ratio) in the crystalline film. In the embodiment of the present invention, the crystalline film contains SnO ２ Alternatively, the single crystal content of the mixed crystal is preferably 70 at% or more in terms of composition ratio (atomic ratio) in the crystal film, and more preferably 90 at% or more. ２ Alternatively, it is not particularly limited as long as it is a compound of oxygen and tin. Furthermore, the crystalline film is the SnO ２ Other metal elements may be included. Examples of these other metal elements include Group 14 metals of the periodic table (such as germanium or silicon) or Group 4 metals of the periodic table (such as titanium, zirconium, or hafnium). The atomic ratio of tin in the metal elements in the crystal film is not particularly limited, as long as it is greater than 0.5. In the embodiments of the present invention, it is preferable that the atomic ratio of tin in the metal elements in the crystal film is 0.7 or more, and more preferably 0.9 or more. Furthermore, the crystal film may be SnO ２ and GeO ２ It is also preferable that it be a mixed crystal with GeO. The crystal structure of the crystalline film in the present invention is preferably a rutile-type structure which is tetragonal. The mixed crystal is GeO. ２ MnO ２ PtO ２ , TiO ２ IrO ２ , OsO ２ , PbO ２ NbO ２ , TaO ２ , VO ２ RuO ２ , RhO ２ ,CrO ２ or SiO ２ and SnO ２Examples include mixed crystals, but according to the present invention, the crystal film is SnO ２ and GeO ２ It is preferable that it be a mixed crystal. Within such a preferred range, better crystallinity can be achieved, and electrical properties such as voltage resistance can be improved.

[0016] Furthermore, in the present invention, it is preferable that a crystalline film mainly composed of a metal oxide containing Ge is laminated on the crystalline film. Within this preferred range, a crystalline film with even greater crystallinity can be produced. Examples of the metal oxide include Group 14 metals of the periodic table (germanium or silicon, etc.) or Group 4 metals of the periodic table (titanium, zirconium or hafnium, etc.). In the embodiments of the present invention, it is preferable that the Ge content in the metal oxide is 70 at% or more in terms of composition ratio (atomic ratio) in the metal oxide, and more preferably 90 at% or more. Furthermore, the crystal structure of the crystalline film is not particularly limited as long as it does not hinder the objective of the present invention, and may be a tetragonal rutile-type crystal structure or a trigonal α-quartz-type structure. Orthorhombic CaCl ２ It may also be a type crystal structure, or α-PbO ２ The crystal structure may be a type crystal structure, or a tetragonal pyrite crystal structure, but in the present invention, a tetragonal rutile structure is preferred. Within this preferred range, a semiconductor device with better semiconductor properties can be realized.

[0017] In the present invention, the film may be formed directly on the crystal substrate, or other layers such as a layer different from the crystal layer consisting of the crystal film (for example, an n-type semiconductor layer, an n+-type semiconductor layer, an n--type semiconductor layer, etc.), an insulating layer (including a semi-insulating layer), a buffer layer, etc., may be laminated on the crystal substrate, and then the film may be formed on the crystal substrate via the other layers. In particular, a buffer layer can be suitably used to relieve stress between the crystal substrate and the single crystal layer. For example, SnO can be used as the constituent material of the buffer layer. ２ , TiO ２ , VO ２ , MnO ２ RuO ２, CsO ２ IrO ２ , GeO ２ CuO ２ , PbO ２ AgO ２ ,CrO ２ SiO ２ Examples include SiC, GaN, and mixed crystals thereof.

[0018] Furthermore, in the present invention, the area of ​​the crystal film is 100 mm². ２ It is preferable that the crystalline film has the above-mentioned area. A crystalline film with such a preferred area can be easily obtained by using the preferred mist CVD apparatus described above. Furthermore, the thickness of the crystalline film is not particularly limited as long as it does not hinder the objective of the present invention, but in the present invention, it is preferable that it is 300 nm or more, and more preferably 1 μm or more. Within these preferred ranges, the semiconductor film can have better breakdown voltage. Furthermore, when the crystalline film is used as an intermediate layer, it is preferable that the thickness is 1 μm or less.

[0019] Furthermore, the surface roughness (RMS) of the crystalline film is preferably 300 nm or less. Also, the half-width of the rocking curve measured by X-ray diffraction in the oriented crystal axis direction is preferably 5300 arcsec or less. According to these preferred ranges, when the laminated structure is applied to a semiconductor device, it is possible to impart superior electrical properties such as better breakdown voltage or better rectification to the semiconductor device. Note that the surface roughness (RMS) refers to the value obtained by calculating it in accordance with JIS B0601 using the surface shape measurement results for a 10 μm square region by atomic force microscopy (AFM). The above-described preferred crystalline film can be easily obtained by using the above-described preferred mist CVD apparatus.

[0020] The preferred laminated structure described above can be more easily obtained by using the preferred mist CVD apparatus described above, for example, the film-forming apparatus shown in Figure 1. Doping can also be appropriately performed using the film-forming apparatus. The doped crystalline film can be suitably used as a semiconductor film or semiconductor layer, and n-type dopants or p-type dopants can be applied to conventional doping methods in oxide semiconductors. Examples of n-type dopants include antimony (Sb), arsenic (As), bismuth (Bi), phosphorus (P), fluorine (F), niobium (Nb), vanadium (V), tantalum (Ta), or tungsten (W). Examples of p-type dopants include aluminum (Al), gallium (Ga), or indium (In). In this invention, laminated structures containing dopants are also included.

[0021] Furthermore, the crystalline substrate is not particularly limited as long as it does not hinder the objectives of the present invention, and may be an insulator, a conductor, or a semiconductor. The crystalline substrate may also be a single-crystal substrate or a polycrystalline substrate. The crystalline substrate may be a substrate having a metal film on its surface. When the crystalline substrate is a conductive substrate, a vertical device can be manufactured without removing the substrate. The crystal structure of the crystalline substrate is also not particularly limited as long as it does not hinder the objectives of the present invention. Examples of the crystal structure of the crystalline substrate include a hexagonal structure, a cubic structure, a tetragonal structure, and the like. Examples of crystalline substrates containing crystals having a diamond structure on part or all of their surface include a Si substrate or a diamond substrate. The Si substrate may be a conductive substrate containing dopants such as boron (B), aluminum (Al), phosphorus (P), arsenic (As), and antimony (Sb). The diamond substrate may be a conductive substrate containing dopants such as boron (B). Such a favorable range allows for improved ease of manufacturing, better crystallinity, better heat dissipation, and easier application to semiconductor devices and the like.

[0022] The film formation conditions may be set as appropriate, as long as they do not hinder the objective of the present invention. In the present invention, the film formation temperature is preferably 450°C to 1300°C. The film formation time is not particularly limited, but for example, it can be from 1 minute to 20 hours. In the present invention, the carrier gas used for film formation may be set as appropriate, as long as it does not hinder the objective of the present invention. The carrier gas is not particularly limited, but for example, it can be oxygen gas, nitrogen gas, argon gas, foaming gas, etc. The means for introducing the dopant may be a known introduction means, for example, a means for implanting impurity ions or a means for producing a crystalline film containing impurities. The ion implantation may be a known ion implantation means. The means for producing the crystalline film may be a known film formation means. It is preferable to subject the film to an annealing treatment such as recovery annealing after ion implantation. The processing temperature for the annealing treatment is not particularly limited, but for example, it is preferably 400°C to 1300°C. The processing time for the annealing treatment is not particularly limited, but for example, it is preferably 1 second to 10 hours. The atmosphere for the annealing treatment is not particularly limited, but examples include a non-oxygen atmosphere such as nitrogen, foaming gas, or argon, or an oxygen atmosphere. In this invention, the ion implantation angle is the inclination between the ion beam and a line perpendicular to the surface of the crystal film or the crystal substrate. A smaller ion implantation angle results in deeper implantation, while a larger ion implantation angle results in shallower implantation. The ion implantation angle may be set as appropriate, as long as it does not hinder the objectives of this invention. In this invention, it is preferable that the ion implantation angle is 0.5° or more and 60° or less. Such a preferred range allows for easier manufacturing and easier control of electrical properties.

[0023] The laminated structure can be used, for example, in a semiconductor device, either as is or after being subjected to known processing methods such as substrate peeling, using known means. Examples of semiconductor devices include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), metal-semiconductor field-effect transistors (MESFETs), electrostatic induction transistors (SITs), high electron-mobility transistors (HEMTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), or light-emitting diodes (LEDs). Furthermore, the invention is applicable to modules on which these semiconductor devices are mounted, and to electronic devices and their components equipped with these semiconductor devices, making it useful for a variety of applications, and is particularly preferred for use in power devices. The semiconductor devices can be classified into horizontal devices, where electrodes are formed on one side of the semiconductor layer, and vertical devices, where electrodes are formed on both the front and back sides of the semiconductor layer. In the present invention, the semiconductor devices can be suitably used as both horizontal and vertical devices. In particular, their use as vertical devices is more preferable.

[0024] The following describes examples of semiconductor devices preferably used in the present invention with reference to the drawings, but the present invention is not limited to these examples. Note that, among the examples of semiconductor devices described below, examples other than HEMT and LED refer to the SnO in the laminated structure. ２ Alternatively, a crystalline layer containing a single crystal of the mixed crystal as the main component is used as an intermediate layer, r-GeO ２ A semiconductor film is stacked, then the crystal substrate and the crystal layer are removed, and the r-GeO ２ The following are preferred examples of how the semiconductor film can be used as a semiconductor layer in the semiconductor device. However, the present invention is not limited to these preferred examples.

[0025] (SBD) Figure 11 shows a preferred example of a Schottky barrier diode (SBD) comprising an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a metal layer 103, an insulating layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The metal layer 103 is made of a metal such as Al and covers the Schottky electrode 105a.

[0026] (HEMT) Figure 12 shows a preferred example of a high electron mobility transistor (HEMT) comprising a wide bandgap n-type semiconductor layer 121a, a narrow bandgap n-type semiconductor layer 121b, an n+-type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, and a substrate 129.

[0027] (MOSFET) Figure 13 shows a preferred example of a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+-type semiconductor layer 132a may be a p-type semiconductor layer, or it may be the same as the p-type semiconductor layer 132.

[0028] (JFET) Figure 14 shows a preferred example of a junction field-effect transistor (JFET) comprising an n-type semiconductor layer 141a, a first n+-type semiconductor layer 141b, a second n+-type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0029] (IGBT) Figure 15 shows a preferred example of an insulated-gate bipolar transistor (IGBT) comprising an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n+-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0030] (LED) Figure 16 shows an example of a semiconductor device of the present invention when the semiconductor device is a light-emitting diode (LED). The semiconductor light-emitting device in Figure 16 has an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is laminated on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is laminated on the light-emitting layer 163. A translucent electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is laminated on the translucent electrode 167. Note that the semiconductor light-emitting device in Figure 16 may be covered with a protective layer except for the electrode portion.

[0031] Examples of materials for translucent electrodes include conductive materials such as oxides containing indium (In) or titanium (Ti). More specifically, for example, In ２ O ３ ZnO, SnO ２ Ga ２ O ３ , TiO ２ , CEO ２ Alternatively, these may include mixed crystals of two or more of these materials, or materials doped therewith. Translucent electrodes can be formed by providing these materials by known means such as sputtering. Furthermore, after forming the translucent electrodes, thermal annealing may be performed to make the translucent electrodes transparent.

[0032] In the semiconductor light-emitting element shown in Figure 16, the first electrode 165a is the positive electrode and the second electrode 165b is the negative electrode. By passing current through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 via these electrodes, the light-emitting layer 163 emits light.

[0033] Examples of materials for the first electrode 165a and the second electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof. The electrode deposition method is not particularly limited and can be formed on the substrate according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration the suitability with the material.

[0034] (JBS) Figure 17 shows the main part of a junction barrier Schottky diode (JBS), which is one of the preferred embodiments of the present invention. The JBS in Figure 17 comprises an ohmic electrode 1020, an n-type semiconductor layer 1010a, an n+-type semiconductor layer 1010b, a Schottky electrode 1030, and an electric field relaxation region 1060. The Schottky electrode 1030 is composed of a metal layer 1030a, a metal layer 1030b, and a metal layer 1030c. In the semiconductor device of Figure 17, the outer ends of the metal layer 1030a and / or metal layer 1030b, which are the second electrode layers, are located outside the outer end of the metal layer 1030c, which is the first electrode layer. In addition, in the semiconductor device of Figure 17, the electric field relaxation region 1060 comprises at least a portion of the second electrode layer located outside the outer end of the first electrode layer, and the outer end of the second electrode, with at least two electric field relaxation regions 1060 arranged in a planar manner. Furthermore, in the semiconductor device shown in Figure 17, the electric field relaxation region 1060 is made of a p-type semiconductor and forms a PN junction with the n-type semiconductor layer 1010a.

[0035] The means for forming each layer in Figure 17 are not particularly limited and may be known means, as long as they do not hinder the objective of the present invention. Examples include means of forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or means of directly patterning using printing technology.

[0036] (MESFET) Figure 18 shows an example of a metal-semiconductor field-effect transistor (MESFET) according to the present invention. The MESFET in Figure 18 comprises an n-type semiconductor layer 111a, an n+-type semiconductor layer 111b, a buffer layer 118, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0037] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrol; or mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0038] The semi-insulating layer 114 only needs to be composed of a semi-insulating material. Examples of such semi-insulating materials include those containing semi-insulating dopants such as magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium (Cs), strontium (Sr), and barium (Ba), as well as those that have not undergone doping treatment.

[0039] In the MESFET shown in Figure 18, a good depletion layer is formed beneath the gate electrode, allowing for efficient control of the current flowing from the drain electrode to the source electrode.

[0040] (SIT) Figure 19 shows an example where the semiconductor device of the present invention is an electrostatic induction transistor (SIT). The SIT in Figure 19 comprises an n-type semiconductor layer 241a, n+-type semiconductor layers 241b and 241c, a gate electrode 245a, a source electrode 245b, and a drain electrode 245c.

[0041] On the drain electrode 245c, for example, an n+ type semiconductor layer 241b with a thickness of 100 nm to 100 μm is formed, and on the n+ type semiconductor layer 241b, for example, an n- type semiconductor layer 241a with a thickness of 100 nm to 100 μm is formed. Furthermore, on the n- type semiconductor layer 241a, an n+ type semiconductor layer 241c is formed, and on the n+ type semiconductor layer 241c, the source electrode 245b is formed.

[0042] Furthermore, within the n-type semiconductor layer 241a, a plurality of trench grooves are formed that penetrate the n+ semiconductor layer 241c and reach a depth partway through the n-semiconductor layer 241a. A gate electrode 245a is formed on the n-type semiconductor layer 241a within the trench grooves.

[0043] In the ON state of the SIT in Figure 19, when a voltage is applied between the source electrode 245b and the drain electrode 245c, and a positive voltage is applied to the gate electrode 245a relative to the source electrode 245b, a channel layer is formed in the n-type semiconductor layer 241a, electrons are injected into the n-type semiconductor layer 241a, and the device turns on. In the OFF state, the voltage of the gate electrode is set to 0V, which prevents the formation of the channel layer, filling the n-type semiconductor layer with a depletion layer, and the device turns off.

[0044] Figure 20 shows a part of the manufacturing process of the SIT shown in Figure 19. For example, using a laminate as shown in Figure 20(a), an etching mask is provided in a predetermined area of ​​the n-type semiconductor layer 241a and the n+-type semiconductor layer 241c. Using the etching mask as a mask, anisotropic etching is performed, for example, by reactive ion etching, to form a trench groove with a depth that reaches from the surface of the n+-type semiconductor layer 241c to partway down the n-type semiconductor layer 241a, as shown in Figure 20(b). Next, a gate electrode material, such as polysilicon, is formed in the trench groove with a thickness less than or equal to the thickness of the n-type semiconductor layer 241a by CVD, vacuum deposition, sputtering, etc. Furthermore, the SIT can be manufactured by forming a source electrode 245b on the n+-type semiconductor layer 241c and a drain electrode 245c on the n+-type semiconductor layer 241b using known means such as vacuum deposition, sputtering, and CVD. The electrode materials for the source electrode and drain electrode may be known electrode materials, and examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, or polypyrrole; or mixtures thereof.

[0045] The above example shows an example in which a p-type semiconductor is not used, but the present invention is not limited to this and may use a p-type semiconductor. The p-type semiconductor may be the same material as the n-type semiconductor and contain a p-type dopant, or it may be a different p-type semiconductor.

[0046] (Semiconductor System) The semiconductor devices described above are used in semiconductor systems, such as systems using power supply devices. The power supply device can be manufactured by connecting the semiconductor devices to wiring patterns, etc., using known means. Figure 21 shows an example of a power supply system. In the example shown in Figure 21, a power supply system is configured using a plurality of the power supply devices and control circuits. The power supply system can be used in combination with electronic circuits to form a system device, as shown in Figure 22. An example of a power supply circuit diagram for a power supply device is shown in Figure 23. Figure 23 shows the power supply circuit of a power supply device consisting of a power circuit and a control circuit. In this power supply circuit, the DC voltage is switched at high frequency by an inverter (composed of MOSFETs A to D) and converted to AC, then isolation and voltage transformation are performed by a transformer, rectification is performed by rectifier MOSFETs (A to B), and then smoothing is performed by DCL (smoothing coils L1, L2) and capacitors to output a DC voltage. At this time, the output voltage is compared with a reference voltage by a voltage comparator, and the inverter and rectifier MOSFETs are controlled by a PWM control circuit to obtain the desired output voltage.

[0047] (Example 1) Figure 1 shows an example of a preferred embodiment of the film-forming apparatus used in this embodiment. The film-forming apparatus 19 consists of a film-forming sample 20, a sample stage 21, a carrier gas source 22a, a carrier gas source 22b, a flow rate control valve 23a, a flow rate control valve 23b, a film-forming chamber 27, a heater 28, and an atomizing device 30. The atomizing device 30 consists of a raw material partition 24, a raw material liquid for atomization 24a, an ultrasonically transparent substrate 24b, a stage 24c, an ultrasonic transducer 26, a guide partition 31, an ultrasonic transmission liquid tank 35, and an ultrasonic transmission liquid 36. Figure 2 shows an example of another preferred embodiment of the film-forming apparatus when the atomizing device of the present invention is used as a film-forming atomizing stage. The atomizing device 30 consists of a raw material partition 24, a raw material liquid for atomization 24a, an ultrasonically transparent substrate 24b, a stage 24c, an ultrasonic transducer 26, a guide partition 31, an ultrasonic transmission liquid tank 35, and an ultrasonic transmission liquid 36. The sample stage 21 is made of quartz, and the surface on which the film-forming sample 20 is placed is inclined from the horizontal plane. By making both the film-forming chamber 27 and the sample stage 21 out of quartz, the contamination of the crystalline film formed on the film-forming sample 20 with impurities originating from the apparatus is suppressed. The atomizing raw material liquid 24a is contained in the mist generation source 24. The guide partition 31 is in contact with the ultrasonic-transmitting substrate 24b. Figure 3 is a schematic cross-sectional view of the atomizing apparatus used in the present invention, viewed from the side. The atomizing apparatus 30 in Figure 3 consists of a raw material partition 24, an ultrasonic-transmitting substrate 24b, a stage 24c, an ultrasonic transducer 26, a guide partition 31, and an ultrasonic transmission liquid tank 35. The guide partition 31 is in contact with the ultrasonic transmission liquid tank 35. By using the guide partition 31, the ultrasonic waves emitted from the ultrasonic transducer 26 are transmitted to the raw material partition 24 more efficiently.

[0048] The concentration of tin chloride pentahydrate in the atomizing raw material solution 24a was set to 0.02 mol / L, and when adjusting the concentration of bis-[2-carboxyethynylgermanium]sesquidide to a 0.01 mol / L aqueous solution, hydrochloric acid was prepared to be 20% by volume.

[0049] Next, as the film-forming sample 20, a Si(100) substrate having a diamond structure with a side length of 10 mm and a thickness of 500 μm was placed on the sample stage 21, and the heater 28 was operated to raise the temperature in the film-forming chamber 27 to 650°C. Next, the flow rate control valve 23 was opened to supply carrier gas from the carrier gas source 22 into the film-forming chamber 27. After sufficiently replacing the atmosphere in the film-forming chamber 27 with the carrier gas, the flow rate of the carrier gas was adjusted to 1.2 L / min. Forming gas was used as the carrier gas.

[0050] Next, the ultrasonic oscillator 26 was vibrated, and the vibration was propagated through the water 25a to the raw material solution 24a to atomize the raw material solution 24a and generate raw material fine particles. These raw material fine particles were introduced into the film-forming chamber 27 by the carrier gas, reacted in the film-forming chamber 27, and a thin film was formed on the film-forming sample 20 by CVD reaction on the film-forming surface of the film-forming sample 20. The film thickness was 1.2 μm.

[0051] The obtained thin film was measured using an X-ray diffractometer. The XRD analysis results are shown in FIG. 4. As is clear from FIG. 4, the obtained thin film has a rutile structure type that is tetragonal and is a (111)-oriented SnO ２ single crystal film and a rutile-type structure (111)-oriented SnGeO ２ single crystal film. Further, FIG. 5 shows an enlarged view of the XRD analysis results in FIG. 4. From FIG. 5, the SnGeO ２ (111) crystal film was Sn:Ge = 80:20 according to Vegard's law. Also, the result of the ω scan in the X-ray diffraction measurement is shown in FIG. 6. From FIG. 6, the rocking curve half-width at the 200 diffraction peak was 5210 arcsec, and a SnO ２ single crystal with good crystallinity was formed on the Si(100) substrate.

[0052] Further, the surface of the obtained thin film was observed using SEM. The SEM image is shown in FIG. 7. As is clear from FIG. 7, it has excellent surface smoothness and has r-Sn ８０ Ge ２０ O ２A crystal film was formed. Also, the surface of the obtained thin film was observed using EDS. The measurement results by EDS are shown in FIG. 8. As is clear from FIG. 8, r-Sn is uniformly distributed on the entire surface. ８０ Ge ２０ O ２ It can be seen that a single crystal film is formed.

[0053] Also, the surface of the obtained r-Sn ８０ Ge ２０ O ２ single crystal film was observed using an atomic force microscope (AFM). As shown in FIG. 9, the surface roughness (RMS) based on JIS B0601 was 40.2 nm, and it was found that the surface smoothness was excellent.

[0054] (Comparative Example 1) As Comparative Example 1, an r-SnO film was formed in the same manner as in Example 1, except that bis-[2-carboxyethynylgermanium] sesquide was not used in the atomizing raw material liquid 24a. The results of analyzing the obtained crystal film by XRD measurement are shown in FIG. 10. It was found from FIG. 10 that a polycrystalline rutile-type structure SnO film was formed. Therefore, an r-SnO single crystal film could not be obtained. ２ film was formed. The results of analyzing the obtained crystal film by XRD measurement are shown in FIG. 10. It was found from FIG. 10 that a polycrystalline rutile-type structure SnO ２ film was formed. Therefore, an r-SnO ２ single crystal film could not be obtained.

[0055] From the results of the examples and comparative examples, it can be seen that the laminated structure of the present invention has excellent crystallinity.

[0056] The laminated structure of the present invention is suitably used, for example, in semiconductor devices and the like.

[0057] 19 CVD apparatus 20 Sample to be fabricated 21 Sample stage 22 Carrier gas source 23 Flow control valve 24 Mist source 24a Raw material solution 24b Ultrasonic-transmitting substrate 25 Container 25a Water 26 Ultrasonic transducer 27 Fabrication chamber 28 Heater 30 Atomizer 31 Guide partition 33 Dilution gas supply pipe 34 Carrier gas supply pipe 35 Ultrasonic transmission liquid tank 36 Ultrasonic transmission liquid 101a n-type semiconductor layer 101b n+-type semiconductor layer 102 p-type semiconductor layer 103 Metal layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 111a n-type semiconductor layer 111b n+-type semiconductor layer 114 Semi-insulator layer 115a Gate electrode 115b Source electrode 115c Drain electrode 118 Buffer layer 121a Wide bandgap n-type semiconductor layer 121b Narrow bandgap n-type semiconductor layer 121c n+-type semiconductor layer 123 p-type semiconductor layer 124 Semi-insulating layer 125a Token electrode 125b Source electrode 125c Drain electrode 129 Substrate 131a n--type semiconductor layer 131b First n+-type semiconductor layer 131c Second n+-type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a Token electrode 135b Source electrode 135c Drain electrode 141a n--type semiconductor layer 141b First n+-type semiconductor layer 141c Second n+-type semiconductor layer 142 p-type semiconductor layer 145a Token electrode 145b Source electrode 145c Drain electrode 151 n-type semiconductor layer 151a n-type semiconductor layer 151b n+-type semiconductor layer 152 p-type semiconductor layer 154 Gate insulating film 155a Token electrode 155b Emitter electrode 155c Collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 Light-emitting layer 165a First electrode 165b Second electrode 167 Translucent electrode 169 Substrate 241a n-type semiconductor layer 241b n+-type semiconductor layer 241c n+-type semiconductor layer 245a Token electrode 245b Source electrode 245c Drain electrode 1010a n-type semiconductor 1010b n+-type semiconductor 1020 Ohmic electrode 1030 Schottky electrode 1030a Metal layer 1030b Metal layer1030c metal layer 1060 electrolytic tempering zone

Claims

1. A laminated structure in which a crystalline film is laminated directly or via another layer on a crystalline substrate containing a crystal having a diamond structure on part or all of its surface, wherein the crystalline film is SnO ２ A laminated structure characterized by containing, as a main component, a single crystal of the mixed crystal.

2. The laminated structure according to claim 1, wherein the crystalline film has a rutile-type structure.

3. The crystalline film is SnO ２ and GeO ２ The laminated structure according to claim 1, which is a mixed crystal of the above.

4. The crystalline film is 100 mm ２ A laminated structure according to claim 1 having the above area.

5. The laminated structure according to claim 1, wherein the thickness of the crystalline film is 300 nm or more.

6. The laminated structure according to claim 1, wherein the full width at half maximum of the rocking curve measured by X-ray diffraction of the crystalline film is 5300 arcsec or less.

7. The laminated structure according to claim 1, wherein the surface roughness of the crystalline film is 300 nm or less.

8. The laminated structure according to claim 1, wherein the crystal substrate is a Si substrate.

9. The laminated structure according to claim 1, further comprising a crystalline film mainly composed of a metal oxide containing Ge.

10. A semiconductor device comprising a stacked structure, wherein the stacked structure is the stacked structure described in claim 1.

11. The semiconductor device according to claim 10, which is a power device.

12. The semiconductor device according to claim 10, which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor field-effect transistor (MESFET), an electrostatic induction transistor (SIT), a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light-emitting diode (LED).

13. Electronic equipment including a semiconductor device, characterized in that the semiconductor device is the semiconductor device described in claim 10.

14. A system including an electronic device, wherein the electronic device is the electronic device described in claim 13.

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