Semiconductor device using edge contact between two-dimensional material and semimetallic material, and method for manufacturing same

Abstract

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may comprise the steps of: preparing a substrate; forming, on the substrate, a first dielectric layer including a two-dimensional insulator; forming, on the first dielectric layer, a channel layer including a two-dimensional material; forming, on the channel layer, a second dielectric layer including a two-dimensional insulator; etching the first dielectric layer, the channel layer, and the second dielectric layer to expose a region on the substrate; and forming, on the exposed substrate, an electrode including a semimetallic material, wherein the electrode is formed so as to contact etched surfaces of the first dielectric layer, the channel layer, and the second dielectric layer.

Description

Semiconductor device using edge contact between a two-dimensional material and a semimetal material and method for manufacturing the same

[0001] The present invention relates to a semiconductor device using edge contact between a two-dimensional material and a semimetal material, and a method for manufacturing the same.

[0002] At a time when we are approaching the limitations of Moore's Law, two-dimensional materials are attracting attention as a next-generation material to overcome this. Semiconductor devices using two-dimensional materials have the advantage of enabling ultra-miniaturization and multidimensional heterojunctions. In addition, since heterojunction stacking is much easier compared to conventional semiconductors, it is advantageous for fabricating various structures such as multi-gates.

[0003] In surface contact methods where a two-dimensional material and a metal are in contact, high contact resistance is caused by the formation of Schottky barriers or van der Waals gaps between the interfaces, which significantly degrades electrical performance. To address this, an edge contact method has been introduced in which a metal contacts the side of a two-dimensional material, unlike conventional contact methods. This allows for a reduction in the physical distance of the contact interface, thereby easily eliminating unnecessary elements that hinder the flow of charge and improving the performance of semiconductor devices.

[0004] One technical problem that the present invention aims to solve is to provide a semiconductor device using edge contact between a two-dimensional material and a semimetal material, and a method for manufacturing the same.

[0005] Another technical problem that the present invention aims to solve is to provide a semiconductor device in which the contact resistance between the channel layer and the electrode is reduced, and a method for manufacturing the same.

[0006] Another technical problem that the present invention aims to solve is to provide a semiconductor device with improved stability and a method for manufacturing the same.

[0007] Another technical problem that the present invention aims to solve is to provide a semiconductor device with improved reliability and a method for manufacturing the same.

[0008] Another technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and a method for manufacturing the same.

[0009] The technical problems that the present invention aims to solve are not limited to those described above.

[0010] To solve the technical problems described above, the present invention provides a method for manufacturing a semiconductor device.

[0011] According to one embodiment, the method for manufacturing the semiconductor device comprises the steps of: preparing a substrate; forming a first dielectric layer including a two-dimensional insulator on the substrate; forming a channel layer including a two-dimensional material on the first dielectric layer; forming a second dielectric layer including a two-dimensional insulator on the channel layer; etching the first dielectric layer, the channel layer, and the second dielectric layer to expose a region on the substrate; and forming an electrode including a semimetal on the exposed substrate, wherein the electrode may be formed to be in contact with the etched surfaces of the first dielectric layer, the channel layer, and the second dielectric layer.

[0012] According to one embodiment, the first dielectric layer, the channel layer, and the second dielectric layer may be etched simultaneously so that the etched surface of the first dielectric layer, the etched surface of the channel layer, and the etched surface of the second dielectric layer form a co-plane.

[0013] According to one embodiment, the etching may include an angle between the co-plane of the first dielectric layer, the channel layer, and the second dielectric layer and the upper plane of the substrate such that the angle is greater or less than 90°.

[0014] According to one embodiment, the first dielectric layer, the channel layer, and the second dielectric layer may be simultaneously etched by providing an etching gas mixed with a first gas containing fluorine (F) and a second gas containing oxygen (O) and performing plasma treatment.

[0015] According to one embodiment, the ratio of the first gas and the second gas in the etching gas may be controlled so that the first dielectric layer, the channel layer, and the second dielectric layer are etched at the same etching rate.

[0016] According to one embodiment, the ratio of the first gas and the second gas in the etching gas may be controlled differently so that the first dielectric layer, the channel layer, and the second dielectric layer are etched at the same etching rate depending on the type of two-dimensional material included in the channel layer.

[0017] According to one embodiment, the first gas may include either SF6 or CF4, and the second gas may include O2.

[0018] According to one embodiment, the step of etching the first dielectric layer, the channel layer, and the second dielectric layer to expose a region on the substrate may include the step of etching one side of the first dielectric layer, the channel layer, and the second dielectric layer to expose a first region on the substrate, and the step of etching the other side of the first dielectric layer, the channel layer, and the second dielectric layer to expose a second region on the substrate.

[0019] According to one embodiment, the step of forming an electrode containing a semimetal on the exposed substrate may include the step of forming a source electrode containing a semimetal on the first region and the step of forming a drain electrode containing a semimetal on the second region.

[0020]

[0021] To solve the technical problems described above, the present invention provides a semiconductor device.

[0022] According to one embodiment, the semiconductor device may include a first dielectric layer disposed on a substrate and comprising a two-dimensional insulator, a channel layer disposed on the first dielectric layer and comprising a two-dimensional material, a second dielectric layer disposed on the channel layer and comprising a two-dimensional insulator, a source electrode disposed on the substrate and comprising a semimetal so as to be in contact with one side of each of the first dielectric layer, the channel layer, and the second dielectric layer, and a drain electrode disposed on the substrate and comprising a semimetal so as to be in contact with the other side of each of the first dielectric layer, the channel layer, and the second dielectric layer.

[0023] According to one embodiment, the contact surface between the first dielectric layer and the source electrode, the contact surface between the channel layer and the source electrode, and the contact surface between the second dielectric layer and the source electrode form a first co-surface, and the contact surface between the first dielectric layer and the drain electrode, the contact surface between the channel layer and the drain electrode, and the contact surface between the second dielectric layer and the drain electrode form a second co-surface, and the angle between the first co-surface and the upper surface of the substrate and the angle between the second co-surface and the upper surface of the substrate may be greater than or less than 90°.

[0024] According to one embodiment, the two-dimensional material may include either molybdenum disulfide (MoS2) or graphene.

[0025] According to one embodiment, when the two-dimensional material comprises molybdenum disulfide (MoS2), it may include molybdenum atoms (Mo) and sulfur atoms (S) that are bonded to the semimetal included in the source electrode and the semimetal included in the drain electrode.

[0026] According to one embodiment, the two-dimensional insulator comprising the first dielectric layer and the two-dimensional insulator comprising the second dielectric layer are identical, provided that the two-dimensional insulator comprising the first dielectric layer and the second dielectric layer may comprise hexagonal boron nitride (h-BN).

[0027] According to one embodiment, the semimetal included in the source electrode and the semimetal included in the drain electrode are the same, provided that the semimetal included in the source electrode and the drain electrode may include antimony (Sb).

[0028] A semiconductor device according to an embodiment of the present invention may include a first dielectric layer disposed on a substrate and comprising a two-dimensional insulator (e.g., h-BN), a channel layer disposed on the first dielectric layer and comprising a two-dimensional material (e.g., MoS2 or Graphene), a second dielectric layer disposed on the channel layer and comprising a two-dimensional insulator (e.g., h-BN), a source electrode disposed on the substrate and comprising a semimetal (e.g., Sb) so as to be in contact with one side of each of the first dielectric layer, the channel layer, and the second dielectric layer, and a drain electrode disposed on the substrate and comprising a semimetal (e.g., Sb) so as to be in contact with the other side of each of the first dielectric layer, the channel layer, and the second dielectric layer.

[0029] Additionally, the contact surface between the first dielectric layer and the source electrode, the contact surface between the channel layer and the source electrode, and the contact surface between the second dielectric layer and the source electrode form a first co-surface, and the contact surface between the first dielectric layer and the drain electrode, the contact surface between the channel layer and the drain electrode, and the contact surface between the second dielectric layer and the drain electrode form a second co-surface, and the angle between the first co-surface and the upper surface of the substrate and the angle between the second co-surface and the upper surface of the substrate may be greater than or less than 90°. Accordingly, a semiconductor device having high performance, high reliability, and high stability can be provided.

[0030] FIG. 1 is a flowchart for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] FIG. 2 is a schematic diagram illustrating step S110 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] FIG. 3 is a schematic diagram illustrating step S120 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0033] FIG. 4 is a schematic diagram illustrating step S130 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] FIG. 5 is a schematic diagram illustrating step S140 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0035] FIG. 6 is a schematic diagram illustrating step S150 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0036] FIG. 7 is a schematic diagram illustrating step S160 of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0037] FIG. 8 is a diagram illustrating the bonding state between a two-dimensional material contained in a channel layer and a semimetal material contained in an electrode when the side of the channel layer is etched vertically and comes into contact with the electrode.

[0038] FIG. 9 is a diagram illustrating the bonding state between a two-dimensional material contained in a channel layer and a semimetal material contained in an electrode when the side of the channel layer is etched to have a slope and comes into contact with the electrode.

[0039] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0040] FIG. 11 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

[0041] Figure 12 is a TEM image of a semiconductor device according to Experimental Example 1 of the present invention.

[0042] Figure 13 is a diagram illustrating the density of states between metal and MoS2.

[0043] Figure 14 is a diagram illustrating the density of states between semimetals and MoS2.

[0044] Figure 15 is a diagram illustrating the density of states of MoS2 through a simulation according to Experimental Example 2 of the present invention.

[0045] Figure 16 is a diagram illustrating the atomic structure and electrostatic potential profile of the MoS23 layer and Sb in edge contact state.

[0046] FIG. 17 is an optical image of a semiconductor device according to Experimental Example 3 of the present invention.

[0047] FIG. 18 is a diagram illustrating the transfer characteristics according to the channel layer length of a semiconductor device according to Experimental Example 3 of the present invention.

[0048] FIG. 19 is a diagram illustrating the output characteristics of a semiconductor device according to Experimental Example 3 of the present invention.

[0049] FIG. 20 is a diagram illustrating the contact characteristics of a semiconductor device according to Experimental Example 3 of the present invention.

[0050] FIG. 21 is a diagram showing the transfer curve and output curve of a semiconductor device according to Experimental Example 4 of the present invention.

[0051] FIG. 22 is a diagram illustrating the field-effect mobility of a semiconductor device according to Experimental Example 4 of the present invention.

[0052] FIG. 23 is a diagram illustrating the Schottky barrier height of a semiconductor device according to Experimental Example 4 of the present invention.

[0053] FIG. 24 is a diagram illustrating the contact resistance extracted through 4PP measurement of a semiconductor device according to Experimental Example 4 of the present invention.

[0054] FIG. 25 is a diagram illustrating the change in resistance according to the gate voltage of a semiconductor device according to Experimental Example 4 of the present invention.

[0055] Figure 26 is a diagram illustrating the output curve of a Pd-MoS2 edge contact semiconductor device.

[0056] Figure 27 is a diagram illustrating the output curve of a Ti-MoS2 edge contact semiconductor device.

[0057] Figure 28 is a diagram illustrating the output curve of a Cr-MoS2 edge contact semiconductor device.

[0058] Figure 29 is a diagram illustrating the output curve of a Bi-MoS2 edge contact semiconductor device.

[0059] Figure 30 is a diagram illustrating the output curve of an Sb-MoS2 edge contact semiconductor device.

[0060] Figure 31 is a diagram for comparing the electrical behavior of different types of metals in edge contact with MoS2.

[0061] FIG. 32 is a TEM image of a semiconductor device according to Experimental Example 6-1 of the present invention.

[0062] FIG. 33 is a TEM image of a semiconductor device according to Experimental Example 6-2 of the present invention.

[0063] FIGS. 34 to 36 are drawings for explaining the etching rate of the dielectric layer and channel layer of a semiconductor device according to Experimental Example 6-1 of the present invention.

[0064] FIG. 37 is a diagram illustrating the change in etching rate of a WSe2 / hBN structure according to Experimental Example 7 of the present invention.

[0065] FIG. 38 is a diagram illustrating the change in etching rate of a Graphene / hBN structure according to Experimental Example 8 of the present invention.

[0066] Figure 39 is a TEM image of a graphene / hBN structure etched under conditions where 3 sccm of CF4 gas and 100 sccm of O2 gas were used.

[0067] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0068] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0069] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0070] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0071] Furthermore, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0072]

[0073] FIG. 1 is a flowchart for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 2 is a schematic diagram for explaining step S110 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 3 is a schematic diagram for explaining step S120 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 4 is a schematic diagram for explaining step S130 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 5 is a schematic diagram for explaining step S140 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 6 is a schematic diagram for explaining step S150 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 7 is a schematic diagram for explaining step S160 of a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 8 is a diagram for explaining the bonding state of a two-dimensional material included in a channel layer and a semimetal material included in an electrode when the side of the channel layer is etched vertically and contacted with an electrode; FIG. 9 is a state in which the side of the channel layer is etched to have an inclination FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 11 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

[0074] Referring to FIGS. 1 and FIGS. 2, a substrate (100) may be prepared (S110). According to one embodiment, the substrate (100) may include a base substrate (110) and an insulating layer (120) formed on the base substrate (100). For example, the base substrate (110) may include silicon (Si), and the insulating layer (120) may include silicon oxide (SiO2). That is, the substrate (100) may be a Si / SiO2 substrate.

[0075] Referring to FIGS. 1 and 3, a first dielectric layer (200) including a two-dimensional insulator can be formed on the substrate (100) (S120). For example, the two-dimensional insulator included in the first dielectric layer (200) may include hexagonal-boron nitride (h-BN). In the case of hexagonal-boron nitride (h-BN), as a two-dimensional insulating material with a hexagonal atomic structure having a band gap of around 5 eV and a high dielectric constant, it can improve the efficiency of forming a one-dimensional metal contact between the channel layer (300) described later, the source electrode (S), and the drain electrode (D).

[0076] Referring to FIGS. 1 and 4, a channel layer (300) including a two-dimensional material may be formed on the first dielectric layer (200) (S130). According to one embodiment, the two-dimensional material may include transition metal dichalcogenides (TMDs). For example, the transition metal dichalcogenides may include molybdenum disulfide (MoS2). Transition metal dichalcogenides (TMDs) are representative two-dimensional semiconductor materials that have the advantages of enabling the formation of thin channels, being advantageous for preventing short channel effects, and being able to operate as low-power devices. Alternatively, according to another embodiment, the two-dimensional material may include graphene.

[0077] Referring to FIGS. 1 and 5, a second dielectric layer (400) including a two-dimensional insulator may be formed on the channel layer (300) (S140). For example, the two-dimensional insulator included in the second dielectric layer (400) may include hexagonal-boron nitride (h-BN). In the case of hexagonal-boron nitride (h-BN), as a two-dimensional insulating material with a hexagonal atomic structure having a band gap of around 5 eV and a high dielectric constant, it can improve the efficiency of forming a one-dimensional metal contact between the channel layer (300) and the source electrode (S) and drain electrode (D) described later.

[0078] Referring to FIGS. 1 and 6, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) can be etched to expose regions (A1, A2) on the substrate (100) (S150). According to one embodiment, the step of etching the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) to expose regions on the substrate (100) may include the step of etching one side of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) to expose a first region (A1) on the substrate (100), and the step of etching the other side of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) to expose a second region (A2) on the substrate (100).

[0079] The first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) can be etched simultaneously. According to one embodiment, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) can be etched simultaneously by providing an etching gas mixed with a first gas containing fluorine (F) and a second gas containing oxygen (O) and performing plasma treatment. For example, the first gas may include either SF6 or CF4, and the second gas may include O2. More specifically, SF6 gas may be used as the first gas when the channel layer (300) contains molybdenum disulfide (MoS2), whereas CF4 gas may be used as the first gas when the channel layer (300) contains graphene.

[0080] Additionally, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) can be etched at the same etching rate. That is, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) can be etched simultaneously at the same etching rate. Accordingly, the etched surface of the first dielectric layer (200), the etched surface of the channel layer (300), and the etched surface of the second dielectric layer (400) can be coplanar. For example, one etched surface (200a) of the first dielectric layer (200), one etched surface (300a) of the channel layer (300), and one etched surface (400a) of the second dielectric layer (400) may form a first etched surface (CP1), and the other etched surface (200b) of the first dielectric layer (200), the other etched surface (300b) of the channel layer (300), and the other etched surface (400b) of the second dielectric layer (400) may form a second etched surface (CP2).

[0081] As described above, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are etched simultaneously at the same etching rate so that the etched surfaces form a co-surface, thereby improving the one-dimensional metal contact reliability between the channel layer (300) and the source electrode (S) and drain electrode (D) described later. Conversely, if the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are not etched simultaneously at different etching rates, a mismatch between the etched surfaces may be formed, and as a result, the one-dimensional metal contact reliability between the channel layer (300) and the source electrode (S) and drain electrode (D) described later may be reduced.

[0082] According to one embodiment, the ratio of the first gas and the second gas in the etching gas can be controlled so that the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are etched at the same etching rate. Additionally, depending on the type of two-dimensional material included in the channel layer (300), the ratio of the first gas and the second gas in the etching gas can be controlled differently so that the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are etched at the same etching rate. For example, if the channel layer (300) includes molybdenum disulfide (MoS2), the etching gas mixed with SF6 gas and O2 gas can be controlled such that the ratio of SF6 gas to O2 gas is greater than 1:1 vol% and less than or equal to 1:3 vol%. In contrast, as another example, when the channel layer (300) includes graphene, the ratio of CF4 gas in the etching gas mixed with O2 gas can be controlled to be greater than 3 vol% and less than 4 vol%.

[0083] The first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) may not only be etched simultaneously, but may also be etched such that the angle between the co-plane (CP1, CP2) of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) and the upper surface of the substrate (100) is greater or less than 90°. That is, the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) may be etched at an angle rather than vertically. When the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are etched at an angle, the reliability of the one-dimensional metal contact between the channel layer (300) and the source electrode (S) and drain electrode (D) described later can be further improved compared to when they are etched vertically.

[0084] Referring to FIGS. 1 and 7, an electrode containing a semimetal may be formed on the exposed substrate (100) (S160). According to one embodiment, the step of forming an electrode containing a semimetal on the exposed substrate (100) may include the step of forming a source electrode (S) containing a semimetal on the first region (A1), and the step of forming a drain electrode (D) containing a semimetal on the second region (A2). The source electrode (S) may be formed to contact one etched surface of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400), i.e., the first co-surface (CP1). Alternatively, the drain electrode (D) may be formed to contact the other etched surface of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400), i.e., the second co-surface (CP2). That is, the channel layer (300) can form a one-dimensional metal contact with the source electrode (S) and the drain electrode (D).

[0085] One-dimensional metal contact is a process in which another metal is deposited and contacted on an etched area of ​​a metal, and is also called edge contact because the side edge of the etched metal and one side of the deposited metal are in contact. In contrast, two-dimensional metal contact is a process in which another metal is deposited and contacted on the surface of a metal, and is also called surface contact because the surfaces of different metals are in contact.

[0086] When the channel layer (300), the source electrode (S), and the drain electrode (D) form a two-dimensional metal contact, a problem may arise in which the electrical characteristics of the semiconductor device are degraded by Schottky barriers and van der Waals gaps that hinder the flow of charge. However, as described above, when the channel layer (300), the source electrode (S), and the drain electrode (D) form a one-dimensional metal contact, Schottky barriers and van der Waals gaps can be suppressed, and the bonding strength between the two-dimensional material and the metal can also be improved, so the electrical characteristics of the semiconductor device can be improved.

[0087] According to one embodiment, the semimetal included in the source electrode (S) and the drain electrode (D) may include antimony (Sb). When a metal (e.g., Pd, Ti, etc.) and a two-dimensional material (e.g., MoS2, graphene, etc.) come into contact, a mismatch in the density of states between the metal and the two-dimensional material occurs, causing an increase in contact resistance, which may result in a problem of reduced contact reliability between the channel layer and the electrode. However, since antimony (Sb), which is a semimetal, has a density of states close to zero near the Fermi level, the increase in contact resistance can be minimized due to the similarity of the density of states even when contact is made with the two-dimensional material (e.g., MoS2, graphene, etc.), and thus the contact reliability between the channel layer and the electrode can be relatively improved.

[0088] In addition, the present invention enables the realization of a high-reliability semiconductor device by improving the bonding force between the channel layer (300), the source electrode (S), and the drain electrode (D) as the source electrode (S) and the drain electrode (D) are formed while the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400) are etched to have a slope.

[0089] More specifically, as shown in FIG. 8, when the side of the channel layer (300) is etched vertically and comes into contact with the source electrode (S), only one of the molybdenum atoms (Mo) and sulfur atoms (S) constituting molybdenum disulfide (MoS2) forms a bond with antimony (Sb), so a problem may arise in which the bonding force between the channel layer (300) and the source electrode (S) becomes relatively weak. However, as shown in FIG. 9, when the side of the channel layer (300) is etched at an angle and comes into contact with the source electrode (S), both the molybdenum atoms (Mo) and sulfur atoms (S) constituting molybdenum disulfide (MoS2) form a bond with antimony (Sb), so the bonding force between the channel layer (300) and the source electrode (S) can become relatively strong.

[0090] Consequently, a semiconductor device according to an embodiment of the present invention may comprise a first dielectric layer (200) disposed on a substrate (100) and comprising a two-dimensional insulator (e.g., h-BN), a channel layer (300) disposed on the first dielectric layer (200) and comprising a two-dimensional material (e.g., MoS2 or Graphene), a second dielectric layer (400) disposed on the channel layer (300) and comprising a two-dimensional insulator (e.g., h-BN), a source electrode (S) disposed on the substrate (100) and comprising a semimetal (e.g., Sb) so as to be in contact with one side of each of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400), and a drain electrode (D) disposed on the substrate (100) and comprising a semimetal (e.g., Sb) so as to be in contact with the other side of each of the first dielectric layer (200), the channel layer (300), and the second dielectric layer (400). there is.

[0091] Additionally, the contact surface between the first dielectric layer (200) and the source electrode (S), the contact surface between the channel layer (300) and the source electrode (S), and the contact surface between the second dielectric layer (400) and the source electrode (S) form a first co-surface (CP1), and the contact surface between the first dielectric layer (200) and the drain electrode (D), the contact surface between the channel layer (300) and the drain electrode (D), and the contact surface between the second dielectric layer (400) and the drain electrode (D) form a second co-surface (CP2), and the angle between the first co-surface (CP1) and the upper surface of the substrate (100) and the angle between the second co-surface (CP2) and the upper surface of the substrate (100) may be greater than or less than 90°. Accordingly, a semiconductor device having high performance and high reliability can be provided.

[0092] According to one embodiment, the semiconductor device can be applied as a field effect transistor (TFT) using the base substrate (110) as a gate electrode.

[0093]

[0094] For the above, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention have been described. Below, specific experimental examples of the semiconductor device and the method for manufacturing the same according to an embodiment of the present invention are described.

[0095] Experimental Example 1: Structural Analysis of Edge-Contacted Semiconductor Devices

[0096] A MoS2 channel layer and an hBN dielectric layer were sequentially formed on a Si / SiO2 substrate, and then the channel layer and the dielectric layer were etched using plasma etching. Subsequently, an electrode was deposited on the substrate exposed by etching to fabricate a semiconductor device according to Experimental Example 1. More specifically, plasma etching was performed using an etching gas mixture of SF6 gas and O2 gas in a 1:3 vol% ratio under conditions of 30 W power, 30 mTorr pressure, and 20 seconds etching time. Additionally, one of Pd, Cr, Ti, Bi, and Sb was used as the electrode.

[0097] Figure 12 is a TEM image of a semiconductor device according to Experimental Example 1 of the present invention.

[0098] Referring to Figures 12 (a) and (b), a Transmission Electron Microscopy (TEM) image of the semiconductor device according to Experimental Example 1 is shown. As can be seen in Figures 12 (a) and (b), a distinct interface is formed between the metal deposited in the etched area and the two-dimensional material (MoS2, hBN). In addition, the etched surface of MoS2 and the etched surface of hBN form a co-plane, and it can be seen that the co-plane is formed with a slope.

[0099] Figure 13 is a diagram illustrating the density of states between metal and MoS2, and Figure 14 is a diagram illustrating the density of states between metal and MoS2.

[0100] Figure 13 shows the density of states (DOS) between Pd and MoS2 when the metal (Pd) electrode and the MoS2 channel layer are in edge contact, and Figure 14 shows the density of states between Sb and MoS2 when the semimetal (Sb) electrode and the MoS2 channel layer are in edge contact.

[0101] As can be seen in Figures 13 and 14, the density of states of MoS2 remained relatively similar to that of Sb, but in the case of Pd, a significant difference was observed. In particular, near the Fermi level, the density of states of MoS2 is close to zero, and when in contact with Sb, the density of aligned gap states increases as it moves further away from the Fermi level.

[0102]

[0103] Experimental Example 2: Analysis of the Electronic Structure of the MoS2-Sb Interface

[0104] In Experimental Example 2, Density Functional Theory (DFT) simulations were performed to analyze the electronic structure of the MoS2 / Sb interface through the calculation of Partial Density of Sates (PDOS).

[0105] FIG. 15 is a diagram illustrating the density of states of MoS2 through a simulation according to Experimental Example 2 of the present invention, and FIG. 16 is a diagram illustrating the atomic structure and electrostatic potential profile of the MoS23 layer and Sb in edge contact state.

[0106] Referring to Fig. 15, the density of states (DOS) for edge contact of the trilayer MoS2 is shown. More specifically, the partial density of states (PDOS) of MoS2 was calculated before contact with Sb (top panel), after contact (middle panel), and with Sb (bottom panel), respectively.

[0107] As can be seen in Fig. 15, it is evident that Mo 4d orbitals and S 5p orbitals play dominant roles in the valence band and conduction band of MoS2, respectively. In the case of edge contact, the three Mo-S atoms closest to the Sb-MoS2 interface are denoted by the subscript "b," while the others are denoted by the subscript "nb." Compared to surface contact, this indicates that only some atoms of MoS2 are bonded to the Sb interface. This can be confirmed through PDOS analysis of the adsorbed MoS2. In the case of non-binding MoS2, the positions of the valence and conduction bands can be clearly identified, and the gap states within the band gap are found to be negligibly small. Furthermore, it is observed that the band gap size of non-binding MoS2 remains similar to that of the original MoS2. Meanwhile, the reason a high density of states (DOS) is observed at the original band gap is due to the formation of strong covalent bonds between the metal and MoS2, which reduces the Schottky barrier and band gap to a nearly negligible level. The wave function of the Sb 5p orbital resonates with the Mo 4d and S 5p orbitals, and accordingly, it can be seen that the bonded DOS of MoS2 exhibits the same trend as the Sb 5p DOS. This can be confirmed in the area highlighted by the vertical black dashed line.

[0108] Referring to Fig. 16 (a), the atomic structure of a trilayer MoS2 using semimetal Sb is shown, and referring to Fig. 16 (b), the electrostatic potential profile of the heterostructure is shown.

[0109] As can be seen in Fig. 16, the positive potential at the Sb / Mo2 interface is lower than the Fermi level, and accordingly, it can be confirmed that there is no interfacial tunneling barrier. This characteristic acts as an important factor in significantly improving the electron transmission probability.

[0110]

[0111] Experimental Example 3: Analysis of Electrical Performance and Contact Resistance of Edge Contact Semiconductor Devices Using TLM Structure

[0112] A semiconductor device was prepared according to the method described in Experimental Example 1, but using Sb as the electrode, and a semiconductor device according to Experimental Example 3 having a TLM structure was prepared.

[0113] FIG. 17 is an optical image of a semiconductor device according to Experimental Example 3 of the present invention.

[0114] Referring to Fig. 17, it can be seen that contact between the MoS2 channel layer and the Sb electrode was easily made.

[0115] FIG. 18 is a diagram illustrating the transfer characteristics according to the channel layer length of a semiconductor device according to Experimental Example 3 of the present invention.

[0116] Referring to FIG. 18, the gate bias (V G Drain current (I) according to ) D ) represents the measurement results (transfer characteristics). The measurement is based on the drain bias (V D Under = 1 V), different lengths (L ch The study was performed on MoS2 channels with values ​​of ≠ 3, 4.5, 7.5, and 12.43 μm, and analyzed on linear and logarithmic scales (measured at room temperature). The typical n-type semiconductor characteristics of MoS2 can be confirmed from the transfer curves, and I ON / IOFF The ratio is 10 7 As shown above, it can be seen that it possesses excellent semiconductor properties.

[0117] FIG. 19 is a diagram illustrating the output characteristics of a semiconductor device according to Experimental Example 3 of the present invention.

[0118] Referring to FIG. 19, the channel layer length (L ch Gate voltage (V) at = 3 μm) G Drain-source voltage (V) according to change D ) relative to drain current (I D ) represents the output characteristics. Linear and symmetric behavior is observed in the output curve, which means that strong ohmic contact characteristics appear between the Sb electrode and the MoS2 channel layer. In other words, the semiconductor device with edge contact between Sb and MoS2 exhibits strong ohmic characteristics without separate pre-treatment or post-treatment, suggesting that Sb plays an important role as a contact electrode when MoS2 is used as a channel layer.

[0119] FIG. 20 is a diagram illustrating the contact characteristics of a semiconductor device according to Experimental Example 3 of the present invention.

[0120] Referring to FIG. 20, to analyze the contact characteristics of the semiconductor device according to Experimental Example 3, the contact resistance (R) is calculated using a TLM equation. c ) was extracted. Total resistance (R) in TLM T ) can be expressed as in <Mathematical Equation 1> below, and the channel resistance (R ch ) can be expressed as shown in <Mathematical Formula 2> below.

[0121] <Mathematical Formula 1>

[0122]

[0123] (R c : Contact resistance, R T : Total resistance, Rch : Channel resistance, R sh : Sheet resistance)

[0124] <Mathematical Formula 2>

[0125]

[0126] (Rch: Channel resistance, Rsh: Sheet resistance, W: Channel layer width, Lch: Channel layer length)

[0127] Referring to FIG. 20(a), the gate voltage (V G Total resistance (R) measured in the range of 0~60 V (5 V intervals) T Represents the value of ). Total resistance (R T ) is the channel layer length (L ch It shows a tendency to vary linearly with respect to ), which means it represents an ideal TLM structure. The intercept of the linear fitting result represents the 2Rc value at various VG values.

[0128] Referring to FIG. 20(b), the gate voltage (V G Represents the contact resistance (Rc) value according to ). Minimum contact resistance (R) in Sb-MoS2 contact c The ) value is 6.14 kΩ·μm (V G It can be seen that it appears as (measured at 60 V).

[0129] Referring to Fig. 20 (c), the gate voltage (V G Channel resistance (R) according to ) ch Represents the value of ). Minimum channel resistance (R ch The value is 7.79 kΩ / sq (V G It can be seen that it appears as (measured at 60 V). Contact resistance (R c ) channel resistance (R ch It was measured to be smaller than ), which means that the channel plays a more dominant role than contact in carrier transport.

[0130]

[0131] Experimental Example 4: Analysis of Temperature-Dependent Electrical Characteristics of Edge Contact Semiconductor Devices Using a 4PP (4 Point Probe) Structure

[0132] A semiconductor device was prepared according to the method described in Experimental Example 1, but using Sb as the electrode, and a semiconductor device according to Experimental Example 4 having a 4PP structure was prepared.

[0133] FIG. 21 is a diagram showing the transfer curve and output curve of a semiconductor device according to Experimental Example 4 of the present invention.

[0134] Referring to FIG. 21 (a), transfer curves measured in the temperature range from 10 K to 310 K are shown, and referring to FIG. 21 (b), output curves measured in the temperature range from 10 K to 310 K are shown. More specifically, data extracted from the channel indicated by the red rectangle in the image inserted in FIG. 21 (a) and measurement results are provided. The scale bar is set to 10 μm.

[0135] FIG. 22 is a diagram illustrating the field-effect mobility of a semiconductor device according to Experimental Example 4 of the present invention.

[0136] Referring to Fig. 22, the change in field-effect mobility with temperature is shown. V D It represents the mobility measured at =1 V and was calculated through <Equation 3> below.

[0137] <Mathematical Formula 3>

[0138]

[0139] (μ: field-effect mobility, I D : Source-drain current, V G : Gate voltage, V D : Drain voltage, C ox : Capacitance of the SiO2 insulating layer, L ch: Length of channel layer, W: Width of channel layer)

[0140] As can be seen in Figure 22, mobility decreases as temperature increases.

[0141] FIG. 23 is a diagram illustrating the Schottky barrier height of a semiconductor device according to Experimental Example 4 of the present invention.

[0142] Referring to Figure 23, the Schottky barrier height (SBH) measured at various gate voltages is shown. As can be seen in Figure 23, the gate voltage has almost no effect on the Schottky barrier height (SBH) and maintains a level of approximately 0 meV. In other words, it can be seen that barrier-free charge injection occurs in the Sb-MoS2 edge contact semiconductor device.

[0143] FIG. 24 is a diagram illustrating the contact resistance extracted through 4PP measurement of a semiconductor device according to Experimental Example 4 of the present invention.

[0144] As can be seen in Fig. 24, the lowest contact resistance (R) at 10 K was obtained through 4PP measurements. c It can be seen that the value is 600 Ω·μm. Contact resistance (R c Since the phenomenon where the value decreases as the temperature decreases is related to ohmic contact, it can be seen that Sb-MoS2 forms ohmic contact.

[0145] FIG. 25 is a diagram illustrating the change in resistance according to the gate voltage of a semiconductor device according to Experimental Example 4 of the present invention.

[0146] Referring to Fig. 25, various resistance changes according to the gate voltage at 10 K are shown. As can be seen in Fig. 25, the contact resistance shows a decreasing trend with increasing gate voltage, and at VG=60 V, the contact resistance (R c It can be seen that ) was measured as 676 Ω·μm.

[0147]

[0148] Experimental Example 5: Characterization of Semiconductor Devices with Edge Contacts Between Various Metals and MoS2

[0149] After preparing a semiconductor device according to Experimental Example 1, output curves were measured in a temperature range of 77 K to 373 K.

[0150] FIG. 26 is a diagram illustrating the output curve of a Pd-MoS2 edge contact semiconductor device, FIG. 27 is a diagram illustrating the output curve of a Ti-MoS2 edge contact semiconductor device, FIG. 28 is a diagram illustrating the output curve of a Cr-MoS2 edge contact semiconductor device, FIG. 29 is a diagram illustrating the output curve of a Bi-MoS2 edge contact semiconductor device, FIG. 30 is a diagram illustrating the output curve of an Sb-MoS2 edge contact semiconductor device, and FIG. 31 is a diagram for comparing the electrical behavior of MoS2 and the metal edge-contacted with each type.

[0151] Referring to Figures 26 and 27, it can be seen that the palladium (Pd) and titanium (Ti) contact MoS2 device exhibits nonlinear Schottky behavior. This occurred despite the application of a gate bias favorable for the n-type saturation current.

[0152] Referring to Figures 28 and 29, it can be seen that nonlinear Schottky behavior still appears in the chromium (Cr) and bismuth (Bi) contact MoS2 devices. However, it can be seen that the linearity of the current-voltage (IV) output curve is improved compared to Pd and Ti, and the ohmic characteristics are more distinct.

[0153] Referring to Fig. 30, it can be seen that the antimony (Sb) contact MoS2 device exhibits clear ohmic characteristics at all measurement temperatures. In other words, it can be seen that Sb is an effective contact metal that provides barrier-free charge transfer to MoS2.

[0154] Referring to Fig. 31, to more clearly compare the electrical behavior of metals at MoS2 edge contacts, the ohmic characteristics with linearity (L) as an indicator were analyzed using the data from Figs. 26 to 30. The linearity of the output curve was normalized to the maximum dI / dV value measured within the experimental range according to <Equation 4> below and plotted on the y-axis.

[0155] <Mathematical Formula 4>

[0156]

[0157] As can be seen in Fig. 31, Pd exhibits the lowest linearity, showing the strongest Schottky behavior, and the ohmic properties increase in the order of Ti, Cr, and Br. Cr and Bi show similar levels of linearity, but it can be observed that Bi has slightly higher ohmic properties (Cr: 0.4–0.6, Bi: 0.6–0.8). This implies that Bi, being a semimetal, is more advantageous than Cr for forming ohmic contacts. Sb exhibits stronger ohmic properties than Bi, and it can be seen that its linearity is close to 1.

[0158] To quantitatively analyze the difference between the metalloids Bi and Sb, the contact resistances were compared. The results showed that the contact resistance of Bi was 49 kΩ·μm, while the contact resistance of Sb was 6.14 kΩ·μm, indicating a significantly lower contact resistance. In other words, while metalloids are more advantageous than metals for forming edge contact with MoS2, it can be seen that among metalloids, the organic bonding characteristics with Sb are significantly higher.

[0159]

[0160] Experimental Example 6: Analysis of the Influence of Etching Gas Used in the Fabrication of Sb-MoS2 Edge Contact Semiconductor Devices

[0161] A semiconductor device was prepared according to Experimental Example 6 by using the method described in Experimental Example 1, but using Sb as the electrode and varying the plasma etching conditions. More specifically, a semiconductor device according to Experimental Example 6-1 (Ex 6-1) was prepared by etching at 20 W and 20 mTorr using an etching gas mixture of SF6 gas and O2 gas in a ratio of 1:3 vol%, and a semiconductor device according to Experimental Example 6-2 (Ex 6-2) was prepared by etching at 20 W and 20 mTorr using an etching gas mixture of SF6 gas and O2 gas in a ratio of 1:1 vol%.

[0162] Classification SF6 Gas:O2 Gas Ratio (vol%) Ex 6-11:3 Ex 6-21:1

[0163] FIG. 32 is a TEM image of a semiconductor device according to Experimental Example 6-1 of the present invention, and FIG. 33 is a TEM image of a semiconductor device according to Experimental Example 6-2 of the present invention.

[0164] As can be seen in Fig. 32, when the ratio of SF6 gas to O2 gas is 1:3 (Ex 6-1), uniform etching occurs and the etched surfaces of h-BN and MoS2 form a co-plane; however, as can be seen in Fig. 33, when the ratio of SF6 gas to O2 gas is 1:1 (Ex 6-2), non-uniform etching occurs and the etched surfaces of h-BN and MoS2 do not form a co-plane. In other words, when etching h-BN and MoS2 using an etching gas mixture of SF6 gas and O2 gas, it can be seen that the ratio of SF6 gas to O2 gas must be controlled to be greater than 1:1 vol% and less than or equal to 1:3 vol% in order for the etched surfaces of h-BN and MoS2 to form a co-plane.

[0165] FIGS. 34 to 36 are drawings for explaining the etching rate of the dielectric layer and channel layer of a semiconductor device according to Experimental Example 6-1 of the present invention.

[0166] Referring to FIG. 34, the change in thickness (nm) of the h-BN dielectric layer according to the plasma etching time (S) is shown, and referring to FIG. 35, the change in thickness (nm) of the MoS2 channel layer according to the plasma etching time (S) is shown, and referring to FIG. 36, the results of FIG. 34 and FIG. 35 are shown overlaid. As can be seen in FIG. 34 to FIG. 36, it can be observed that a distinct decrease in thickness occurs as the plasma etching time increases.

[0167]

[0168] Experimental Example 7: Analysis of Changes in Etching Rate of WSe2 / hBN Structures According to Changes in Ratio of SF6 / O2 in Etching Gas

[0169] FIG. 37 is a diagram illustrating the change in etching rate of a WSe2 / hBN structure according to Experimental Example 7 of the present invention.

[0170] Referring to Fig. 37, a structure in which hBN is stacked on WSe2 was prepared, and then plasma etching was performed using an etching gas mixture of SF6 gas and O2 gas, under conditions where the ratio of O2 gas was different. More specifically, plasma etching was performed under conditions of 30 W and 30 m Torr, and etching was performed while maintaining the SF6 gas at 30 sccm and varying the O2 gas from 0 to 10 sccm.

[0171] As can be seen in Fig. 37, it can be observed that the etching rate (nm / s) of WSe2 and hBN changes differently as the proportion of O2 gas increases. In other words, it can be seen that the etching rate of WSe2 and hBN can be controlled by controlling the ratio of SF6 gas and O2 gas in the etching gas.

[0172]

[0173] Experimental Example 8: Analysis of Changes in Etching Rate of Graphene / hBN Structures According to Changes in Ratio of CF4 / O2 Etching Gas

[0174] FIG. 38 is a diagram illustrating the change in etching rate of a graphene / hBN structure according to Experimental Example 8 of the present invention, and FIG. 39 is a TEM image of a graphene / hBN structure etched under conditions where CF4 gas is used at 3 sccm and O2 gas is used at 100 sccm.

[0175] Referring to FIG. 38, a structure in which hBN is stacked on graphene (Gr) is prepared, and then plasma etching is performed using an etching gas mixture of CF4 gas and O2 gas, wherein the ratio of CF4 gas in the etching gas (CF4 in CF4 / O2) is different (2~10 vol%), and the etching rate (nm / s) is measured and shown for graphene and hBN, respectively.

[0176] As can be seen in Fig. 38, as the ratio of CF4 gas in the etching gas is controlled to be greater than 3 vol% and less than 4 vol%, it can be seen that the etching rate (nm / s) of Graphene and the etching rate (nm / s) of hBN can be controlled to be the same.

[0177] Referring to Fig. 39, a TEM image of a graphene / hBN structure etched under conditions where 3 sccm of CF4 gas and 100 sccm of O2 gas were used is shown.

[0178] As can be seen in Fig. 39, when the ratio of CF4 gas in the etching gas is 2.9 vol% (CF4: 3 sccm, O2: 100 sccm), it can be seen that the etching plane slope of Graphene and the etching plane slope of hBN are different.

[0179]

[0180] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention.

[0181] The present invention can be used in the semiconductor industry.

Claims

1. Step of preparing the substrate; A step of forming a first dielectric layer comprising a two-dimensional insulator on the substrate; A step of forming a channel layer comprising a two-dimensional material on the first dielectric layer; A step of forming a second dielectric layer comprising a two-dimensional insulator on the above channel layer; A step of etching the first dielectric layer, the channel layer, and the second dielectric layer to expose a region on the substrate; and The method includes the step of forming an electrode containing a semimetal on the exposed substrate, wherein A method for manufacturing a semiconductor device comprising forming the electrode to contact the etched surface of the first dielectric layer, the channel layer, and the second dielectric layer.

2. In Paragraph 1, A method for manufacturing a semiconductor device comprising etching the first dielectric layer, the channel layer, and the second dielectric layer simultaneously so that the etched surface of the first dielectric layer, the etched surface of the channel layer, and the etched surface of the second dielectric layer form a co-plane.

3. In Paragraph 2, A method for manufacturing a semiconductor device comprising etching such that the angle between the co-plane of the first dielectric layer, the channel layer, and the second dielectric layer and the upper plane of the substrate is greater than or less than 90°.

4. In Paragraph 1, By providing an etching gas mixed with a first gas containing fluorine (F) and a second gas containing oxygen (O) and performing plasma treatment, A method for manufacturing a semiconductor device comprising simultaneously etching the first dielectric layer, the channel layer, and the second dielectric layer.

5. In Paragraph 4, A method for manufacturing a semiconductor device comprising controlling the ratio of the first gas and the second gas in the etching gas so that the first dielectric layer, the channel layer, and the second dielectric layer are etched at the same etching rate.

6. In Paragraph 5, A method for manufacturing a semiconductor device comprising controlling the ratio of the first gas and the second gas in the etching gas differently so that the first dielectric layer, the channel layer, and the second dielectric layer are etched at the same etching rate according to the type of two-dimensional material included in the channel layer.

7. In Paragraph 4, A method for manufacturing a semiconductor device in which the first gas comprises either SF6 or CF4, and the second gas comprises O2.

8. In Paragraph 1, The step of etching the first dielectric layer, the channel layer, and the second dielectric layer to expose a region on the substrate is: A step of etching one side of the first dielectric layer, the channel layer, and the second dielectric layer to expose a first region on the substrate; and A method for manufacturing a semiconductor device comprising the step of etching the other side of the first dielectric layer, the channel layer, and the second dielectric layer to expose a second region on the substrate.

9. In Paragraph 8, The step of forming an electrode containing a semimetal on the exposed substrate is: A step of forming a source electrode comprising a semimetal on the first region; and A method for manufacturing a semiconductor device comprising the step of forming a drain electrode containing a semimetal on the second region.

10. A first dielectric layer disposed on a substrate and comprising a two-dimensional insulator; A channel layer disposed on the first dielectric layer and comprising a two-dimensional material; A second dielectric layer disposed on the above channel layer and comprising a two-dimensional insulator; A source electrode comprising a semimetal disposed on the substrate to be in contact with one side of each of the first dielectric layer, the channel layer, and the second dielectric layer; and A semiconductor device comprising a drain electrode comprising a semimetal, disposed on the substrate to be in contact with the other side of each of the first dielectric layer, the channel layer, and the second dielectric layer.

11. In Paragraph 10, The contact surface between the first dielectric layer and the source electrode, the contact surface between the channel layer and the source electrode, and the contact surface between the second dielectric layer and the source electrode form a first co-surface. The contact surface between the first dielectric layer and the drain electrode, the contact surface between the channel layer and the drain electrode, and the contact surface between the second dielectric layer and the drain electrode form a second co-surface. A semiconductor device comprising an angle between the first joint surface and the upper surface of the substrate and an angle between the second joint surface and the upper surface of the substrate that is greater than or less than 90°.

12. In Paragraph 10, The above two-dimensional material is a semiconductor device comprising either molybdenum disulfide (MoS2) or graphene.

13. In Paragraph 12, When the above two-dimensional material contains molybdenum disulfide (MoS2), A semiconductor device comprising molybdenum atoms (Mo) and sulfur atoms (S), both of which are combined with the semimetal included in the source electrode and the semimetal included in the drain electrode.

14. In Paragraph 13, The two-dimensional insulator comprising the first dielectric layer and the two-dimensional insulator comprising the second dielectric layer are identical, but, A semiconductor device comprising a two-dimensional insulator including the first dielectric layer and the second dielectric layer, comprising hexagonal boron nitride (h-BN).

15. In Paragraph 10, The semimetal included in the source electrode and the semimetal included in the drain electrode are the same, but, A semiconductor device in which the source electrode and the drain electrode comprise a semimetal comprising antimony (Sb).

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