Method for manufacturing metal bit line below transistor having vertical channel
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-12-04
- Publication Date
- 2026-08-13
Smart Images
Figure KR2025020662_13082026_PF_FP_ABST
Abstract
Description
Method for manufacturing metal bit lines on the lower part of a transistor with a vertical channel
[0001] The present invention relates to a manufacturing technology for a semiconductor device including a transistor having a vertical channel, and more specifically, to a technology for manufacturing a bit line below the vertical channel of a transistor.
[0002] This project (result) is the result of the Regional Innovation-Centered University Support System (RISE) carried out with funding from the Ministry of Education and Busan Metropolitan City and supported by the Busan RISE Innovation Center in 2025 (2025-RISE-02-004-244-45).
[0003] Transistors with vertical channel structures are attracting significant interest for the development of high-density chips. In particular, 4F 2 In DRAMs of this structure, MOSFETs with vertical channels must be used as access transistors, so vertical channel transistor technology is very important.
[0004] However, MOSFETs with a vertical channel structure have a problem in that it is very difficult to form metal interconnects at the bottom part of the vertical channel. The 4F published so far 2 According to research results on DRAM, since it is difficult to form a metal bit line at the bottom of the source / drain channel, the content discloses using highly doped silicon as a bit line or using two wafers to form a metal bit line.
[0005] Existing technologies using highly doped silicon as bit lines have a limitation in that their resistance is relatively higher compared to metal bit lines, because even if the silicon is highly doped, it cannot have a resistivity lower than that of metal.
[0006] The existing technology for forming metal bit lines using two wafers has the problem of requiring a lot of manufacturing time and cost, as it involves forming a metal bit line on the top, attaching a dummy wafer on top of it, flipping it over, polishing the substrate, and then forming a metal bit line.
[0007] The objective of the present invention is to solve the above problem by manufacturing a metal bit line on the lower part of a transistor having a vertical channel on a single wafer.
[0008] The objectives of the present invention are not limited to those mentioned above, and other unmentioned objectives will be clearly understood from the description below.
[0009] A method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to one aspect of the present invention for achieving the aforementioned purpose comprises the steps of forming a space for forming a metal bit line at the bottom of a vertical channel surrounded by an insulating material, filling the space with metal to form a metal bit line, and filling the top of the metal bit line with an insulating material.
[0010] According to the present invention, it is possible to manufacture a metal bit line on the lower part of a transistor having a vertical channel on a single wafer using existing CMOS process technology.
[0011] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims.
[0012] FIG. 1 is a flowchart of a method for manufacturing a metal bit line on the lower part of a transistor having a vertical channel according to one embodiment of the present invention.
[0013] FIG. 2 is a flowchart illustrating the process of isolating a vertical channel and a substrate in a method for manufacturing a metal bit line on the lower part of a transistor having a vertical channel according to one embodiment of the present invention.
[0014] FIGS. 3 to 22 are drawings for illustrating a method of manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to one embodiment of the present invention.
[0015] FIGS. 23 to 24 are drawings illustrating a method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to another embodiment of the present invention.
[0016] FIG. 25 is a drawing illustrating a method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to another embodiment of the present invention.
[0017] A method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to one aspect of the present invention for achieving the aforementioned purpose comprises the steps of: forming a space for forming a metal bit line at the bottom of a vertical channel surrounded by an insulating material; filling the space with metal to form a metal bit line; and filling the top of the metal bit line with an insulating material.
[0018] The step of forming a space for forming a metal bit line in the lower part of the vertical channel comprises: forming an insulating layer of a predetermined height for insulating a substrate with a first insulating material in the lower part of a trench formed on at least one side of the vertical channel surrounded by a first insulating material and exposing one side of the vertical channel; forming a guide film comprising a second insulating material that prevents the vertical channel from being etched along the side of the trench and an etching material formed in a strip shape in the lower part of the second insulating material to provide a passage for etching the lower part of the vertical channel; isotropically etching the etching material of the guide film to form a groove for forming a metal bit line in the lower part of the vertical channel; and removing a portion of the insulating layer through anisotropic etching so that the height of the lower end of the groove matches the height of the insulating layer.
[0019] The step of forming a space for forming a metal bit line in the lower part of the vertical channel further includes the step of removing a second insulating material of the guide film by selective etching after the step of removing a part of the insulating layer.
[0020] The step of forming a space for forming the metal bit line involves forming trenches on both sides of a vertical channel, and the step of filling the space with metal to form the metal bit line involves filling the trenches with metal to a predetermined height to form the metal bit line, and forming silicide in the intersection area where the vertical channel and the metal bit line meet through an annealing process.
[0021] The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the claims. Meanwhile, the terms used in this specification are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text.
[0022] Referring to FIG. 1, a method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to one embodiment of the present invention involves forming a space for forming a metal bit line at the bottom of a vertical channel surrounded by an insulating material (S100), filling the space with metal to form a metal bit line (S200), filling the top of the metal bit line with an insulating material (S300), and isolating the metal bit line from the substrate (S400).
[0023] Step S100, which forms a space for forming a metal bit line, may first form a trench in a vertical channel that is formed vertically on a semiconductor substrate and has both sides filled with a first insulating material (S110).
[0024] Here, the first insulating material may be SiO2, but is not limited thereto.
[0025] Although the metal bit line manufacturing process is illustrated in the attached drawings based on a single transistor, the actual transistors forming the metal bit line can be arranged in a form where multiple transistors are connected in all four directions: front, back, left, and right.
[0026] In addition, the attached drawings illustrate the formation of a rectangular channel structure and the formation of a pillar-shaped vertical channel through a process, but are not limited thereto.
[0027] For example, a metal bit line can be formed during the process of forming a pillar-shaped vertical channel from the beginning.
[0028] Specifically, with reference to FIGS. 3 to 6, a hard mask (301) is applied to a vertical channel (102) that is formed vertically on a semiconductor substrate (101) and has both sides filled with a first insulating material (201), a hard mask pattern (302) is formed so that one side of the vertical channel (102) is exposed, and a trench (401) is formed by anisotropic etching on the one side of the vertical channel (102) exposed through the hard mask pattern (302) (S110).
[0029] Through step S110 of forming a trench (401), the shape of the vertical channel (102) can be changed into a column shape, and space can be secured to form a metal bit line at the bottom of the vertical channel (102).
[0030] Referring to FIG. 1 and FIG. 7, an insulating layer (402) of a predetermined height for insulating the substrate can be formed with a first insulating material at the bottom of the trench (401) (S120).
[0031] At this time, the trench (401) can be filled with a first insulating material and anisotropically etched to create an insulating layer (402) of a predetermined height to electrically separate the metal bit line and the substrate at the bottom.
[0032] Afterwards, a guide film can be formed comprising a second insulating material formed at different heights along the side of the trench (401) to prevent the vertical channel from being etched, and an etching material formed in a strip shape on the lower part of the second insulating material to provide a passage for etching the lower part of the vertical channel (S130).
[0033] Here, the second insulating material is a material with a different etching rate from the vertical channel, and the etching rate is lower than the etching rate of the vertical channel by more than a predetermined range, and the etching material is a material with a similar etching rate to the vertical channel, and the etching rate may fall within a predetermined range based on the etching rate of the vertical channel.
[0034] For example, the second insulating material may be silicon nitride (Si3N4 or SiN) and the etching material may be polysilicon, but is not limited thereto.
[0035] Specifically, referring to FIG. 1 and FIG. 8, an etching material (403) can be formed at a predetermined height on the upper part of the insulating layer (402) in the trench (401) (S131).
[0036] At this time, the upper part of the insulating layer (402) in the trench (401) can be filled with an etching material through deposition and CMP processes and anisotropic etched to form an etching material (403) of a predetermined height on the upper part of the insulating layer (402) (S131).
[0037] The etching material (403) is used as a passage for etching the lower part of the vertical channel, and the thickness of the metal bit line can be controlled by controlling the thickness of the etching material (403).
[0038] Referring to FIGS. 9 to 11, a second insulating material (404) is isotropically deposited on a trench (401) in which an etching material (403) is formed (S133), the second insulating material (404) is anisotropically etched to expose the upper surface of the etching material (403) (S135), and the etching material (403) is anisotropically etched to leave only a strip-shaped etching material (403) and the second insulating material (404) on the side surface of the trench (S137).
[0039] By forming a guide film (405) containing a strip-shaped etching material (403) and a second insulating material (404) on the side of the trench (401), the guide film (405) can be used to guide the etching of only the lower part of the vertical channel (102).
[0040] Referring to FIG. 12, the etching material (403) of the guide film (405) is selectively isotropically etched to etch the etching material (403) and the lower surface of the vertical channel (102) in contact with the etching material (403), thereby forming a groove (103) for forming a metal bit line in the lower surface of the vertical channel (102) (S140).
[0041] Since the lower part of the etching material (403) is not etched because an insulating layer (402) is formed therein, a height difference (h1) occurs between the bottom of the groove (103) and the upper surface of the insulating layer (402).
[0042] Accordingly, to form a metal bit line of constant height, the insulating layer (402) is partially removed by a predetermined height (h1) through anisotropic etching as shown in FIGS. 12 and 13 so that the bottom of the groove (103) and the height of the insulating layer match (S150), and the second insulating material (404) remaining on the side is also removed through selective etching (S160).
[0043] According to the above configuration, a space (104) for forming a metal bit line can be formed in the lower part of the vertical channel (102).
[0044] Referring to FIGS. 14 and 15, a space (104) for forming a metal bit line is formed in the lower part of a vertical channel (102) by leaving only the height difference (h2) between the top and bottom of the groove through metal deposition and anisotropic etching processes (S200), and the upper part (406) of the metal bit line (110) can be filled with a first insulating material (S300).
[0045] Referring to FIGS. 16 and 17, a hard mask pattern (303) is formed so that the side opposite to the side where the metal bit line (110) is formed in the vertical channel (102) is exposed, and the steps S100 (forming a space), S200 (forming a metal bit line), and S300 (filling the upper part of the metal bit line with an insulating material) are repeated so that a metal bit line (110) can also be formed on the other side of the vertical channel (102).
[0046] Then, referring to FIG. 2 and FIG. 18 to 20, a patterned hard mask pattern (304) is applied so that a first insulating material (201) formed on one side of a vertical channel (102) is exposed, and the first insulating material (201) on one side is anisotropically etched through the hard mask pattern (304) to form a trench (S410), an etching material (501) of a predetermined height is formed in the trench (S420), a second insulating material (502) isotropically deposited (S430), the second insulating material (502) is anisotropically etched so that the upper surface of the etching material (501) is exposed (S440), and the etching material (501) is anisotropically etched so that only the edge in contact with the second insulating material (502) remains (S450).
[0047] When using a PN junction structure, the process of isolating the vertical channel and the substrate as illustrated in FIG. 2 and FIG. 18 to 20 can be omitted.
[0048] Then, as shown in FIG. 21, a strip-shaped etching material (501) is isotropically etched to remove the lower part of the vertical channel (101) in contact with the etching material (501) to form a groove (503) in the vertical channel (101) at the lower part of the metal bit line (110) (S460), the second insulating material (502) is removed (S470), and the first insulating material can be filled (S480).
[0049] In FIG. 21, the first insulating material surrounding the vertical channel (102) is not shown so that the positional relationship of the substrate (101), vertical channel (102), metal bit line (110), second insulating material (502), and groove (503) can be easily identified, but in reality, the periphery of the vertical channel (102) may be surrounded by the first insulating material.
[0050] And, the above process can be performed once more on the first insulating material (201) formed on the other side of the vertical channel (102) to isolate the vertical channel (102) and the substrate (101) as shown in FIG. 22.
[0051] Referring to FIG. 23, a method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to another embodiment of the present invention may be to form a space for forming a metal bit line by forming trenches on both sides of a vertical channel (603) that is formed vertically on a semiconductor substrate (601) and surrounded by a first insulating material (602), wherein the lower part of the first insulating material (602) is deposited to a predetermined height, and to fill the space with metal to a predetermined height to form a metal bit line (604) in which one end is in contact with the vertical channel (603) and the other end is exposed, and to form silicide in an intersection area (605) where the vertical channel (603) and the metal bit line (604) meet as in FIG. 24 through an annealing process, and to fill the upper part of the metal bit line (604) in which silicide is formed in the intersection area (605) with an insulating material.
[0052] Here, the statement that the other end of the metal bit line is exposed is explained based on the region containing a single transistor; however, in an actual structure where the connection between multiple transistors and the metal bit line is repeated, the other end of the metal bit line can be connected to the vertical channel of an adjacent transistor.
[0053] Since silicide is a metal formed when a vertical channel meets a metal, the material formed may vary depending on the type of material constituting the vertical channel.
[0054] And, the lower part of the cross region (605) can be isolated through a PN junction instead of the first insulating material (602). In this structure, since the vertical channel (603) and the substrate (601) are connected below the cross region (605) by a material with relatively high thermal conductivity, the vertical channel (603) and the substrate (601) can be electrically isolated, while allowing heat generated in the channel to escape to the bottom of the substrate (601).
[0055] In a method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel according to another embodiment, after forming silicide in the intersection region (605), the lower vertical channel (603) of the intersection region (605) where the silicide is formed is removed in the manner described with reference to FIG. 2 and FIG. 18 to 21, and then a first insulating material (602) is filled to electrically isolate the intersection region (605) where the silicide is formed and the substrate (601).
[0056] The embodiments shown in the present invention can be applied interchangeably.
[0057] According to the present invention, a metal bit line can be formed on the lower part of a transistor having a vertical channel with a single wafer.
[0058] Accordingly, it can reduce manufacturing costs and time compared to existing metal bit line manufacturing technology, and has the advantage of having less resistance loss compared to silicon bit lines.
[0059] Meanwhile, the steps of the attached flowchart may be implemented as computer instructions that perform specified functions by being loaded into the processor or memory of an electronic device capable of data processing (e.g., a general-purpose computer, a specialized computer, a portable notebook computer, or a network computer). Since these computer program instructions can be stored in computer-readable memory, the functions described in the blocks of the block diagram or the steps of the flowchart may be produced as manufactured products containing means of instruction to perform them.
[0060] A person skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the claims and their equivalents should be interpreted as being included within the scope of the present invention.
[0061] The present invention relates to a manufacturing technology for a semiconductor device including a transistor having a vertical channel, and more specifically, to a technology for manufacturing a bit line below the vertical channel of a transistor.
Claims
1. A step of forming a space for forming a metal bit line in the lower part of a vertical channel surrounded by an insulating material; Step of filling the above space with metal to form a metal bit line; and A method for manufacturing a metal bit line in the lower part of a transistor having a vertical channel, comprising the step of filling the upper part of the metal bit line with an insulating material.
2. In Paragraph 1, The step of forming a space for forming a metal bit line in the lower part of the vertical channel is A step of forming an insulating layer of a predetermined height for insulating a substrate with a first insulating material at the bottom of a trench formed on at least one side of a vertical channel surrounded by a first insulating material and exposing one side of the vertical channel; A step of forming a guide film comprising a second insulating material that prevents a vertical channel from being etched along the side surface of the trench, and an etching material formed in a strip shape on the lower part of the second insulating material to provide a passage for etching the lower part of the vertical channel; A step of isotropically etching the etching material of the guide membrane to form a groove for forming a metal bit line in the lower part of a vertical channel; and The method includes the step of removing a portion of the insulating layer through anisotropic etching so that the height of the bottom of the groove matches the height of the insulating layer. Method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel.
3. In Paragraph 2, The step of forming a space for forming a metal bit line in the lower part of the vertical channel is The method further comprises the step of removing a second insulating material of the guide film by selective etching after the step of removing a portion of the insulating layer. Method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel.
4. In Paragraph 1, The step of forming a space for forming the metal bit line above It is to form trenches on both sides of the vertical channel, and The step of filling the above space with metal to form a metal bit line Filling the above trench with metal to a predetermined height to form a metal bit line, and forming silicide in the intersection area where the vertical channel and the metal bit line meet through an annealing process. Method for manufacturing a metal bit line at the bottom of a transistor having a vertical channel.