Nuclear battery and manufacturing method therefor

Abstract

According to exemplary embodiments, a nuclear battery is provided. The nuclear battery comprises: a first semiconductor layer including a plurality of semiconductor rods; a second semiconductor layer on the plurality of semiconductor rods; a radiation source layer on the second semiconductor layer; and a third semiconductor layer on the radiation source layer.

Description

Nuclear battery and method of manufacturing the same

[0001] The present invention relates to a nuclear battery and a method for manufacturing the same. The present application claims the benefit of Korean application No. 10-2025-0013543, filed on February 4, 2025, which is incorporated herein by reference in its entirety.

[0002] A nuclear battery is a device that generates electricity by converting the energy released as radioactive isotopes decay into electrical energy. It is also called a radioisotope battery.

[0003] Since radioactive decay occurs regularly over a considerable period of time, nuclear batteries can produce stable power for a much longer duration compared to conventional chemical batteries.

[0004] Nuclear batteries power probes and satellites in the deep space environment where sunlight is scarce, and are utilized to support long-term space missions. They are applied to medical devices, such as pacemakers, to reduce the burden of repetitive surgeries on patients. Furthermore, in the military sector, nuclear batteries provide stable power to small electronic equipment and long-range aircraft like drones, while in deep-sea exploration, they are used for deep-sea robots and communication relay devices. In polar environments like the Arctic and Antarctic, nuclear batteries power scientific research bases and communication equipment, and in disaster zones, they provide stable power to communication devices even when the power grid has collapsed. In research and commercial fields, nuclear batteries are utilized as small power sources for sensor networks, IoT devices, and telemetry. Additionally, because nuclear batteries can operate in extreme environments involving high temperatures, high pressures, and strong radiation, they are used for special purposes such as volcanic exploration and underground excavation.

[0005] The problem that the technical concept of the present invention aims to solve is to provide a nuclear battery having enhanced output and energy efficiency and a method for manufacturing the same.

[0006] According to exemplary embodiments of the present invention for solving the above-described problem, a nuclear battery is provided. The nuclear battery comprises: a first semiconductor layer including a plurality of semiconductor rods; a second semiconductor layer on the plurality of semiconductor rods; a radiation source layer on the second semiconductor layer; and a third semiconductor layer on the radiation source layer.

[0007] The second semiconductor layer has a uniform thickness.

[0008] The above radiation source layer has a uniform thickness.

[0009] The third semiconductor layer has a uniform thickness.

[0010] The above nuclear battery further includes a fourth semiconductor layer on the third semiconductor layer.

[0011] The above-mentioned fourth semiconductor layer has a uniform thickness.

[0012] The first semiconductor layer is doped with a p-type dopant, the second semiconductor layer is doped with an n-type dopant, the third semiconductor layer is doped with a p-type dopant, and the fourth semiconductor layer is doped with an n-type dopant.

[0013] The first semiconductor layer is doped with an n-type dopant, the second semiconductor layer is doped with a p-type dopant, the third semiconductor layer is doped with a p-type dopant, and the fourth semiconductor layer is doped with an n-type dopant.

[0014] The first semiconductor layer is doped with a p-type dopant, the second semiconductor layer is doped with an n-type dopant, the third semiconductor layer is doped with an n-type dopant, and the fourth semiconductor layer is doped with a p-type dopant.

[0015] The first semiconductor layer is doped with an n-type dopant, the second semiconductor layer is doped with a p-type dopant, the third semiconductor layer is doped with an n-type dopant, and the fourth semiconductor layer is doped with a p-type dopant.

[0016] The above plurality of semiconductor rods form a hexagonal grid.

[0017] The planar shape of each of the above plurality of semiconductor rods is circular.

[0018] According to exemplary embodiments, a method for manufacturing a nuclear battery is provided. The method comprises the steps of: doping a first semiconductor layer; patterning the first semiconductor layer to form a plurality of semiconductor rods; forming a second semiconductor layer on the first semiconductor layer; forming a radiation source layer on the second semiconductor layer; and forming a third semiconductor layer on the radiation source layer.

[0019] The second semiconductor layer is formed conformally.

[0020] The above radiation source layer is formed conformally.

[0021] The above third semiconductor layer is formed conformally.

[0022] It further includes a fourth semiconductor layer on the third semiconductor layer.

[0023] The above-mentioned fourth semiconductor layer is formed conformally.

[0024] The above plurality of semiconductor rods form a hexagonal grid.

[0025] The planar shape of each of the above plurality of semiconductor rods is circular.

[0026] A nuclear battery according to exemplary embodiments of the present invention comprises a first semiconductor layer including a plurality of semiconductor rods, a second semiconductor layer on the first semiconductor layer, a radiation source layer on the second semiconductor layer, a third semiconductor layer on the radiation source layer, and a fourth semiconductor layer on the third semiconductor layer. Accordingly, the area of ​​the pn junction between the first semiconductor layer and the second semiconductor layer facing the radiation source layer and the area of ​​the pn junction between the third semiconductor layer and the fourth semiconductor layer can be increased or maximized, and the output and efficiency of the nuclear battery can be improved.

[0027] The effects obtainable from the exemplary embodiments of the present invention are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

[0028] FIG. 1 is a plan view of a nuclear battery according to exemplary embodiments.

[0029] Figure 2 is a cross-sectional view taken along the cutting line 1I-1I' of Figure 1.

[0030] FIG. 3 is a flowchart for explaining a method for manufacturing a nuclear battery according to exemplary embodiments.

[0031] FIGS. 4 to 8 are drawings for explaining a method of manufacturing a nuclear battery according to exemplary embodiments.

[0032] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Prior to this, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings. Instead, based on the principle that the inventor can appropriately define the concepts of terms to best describe his invention, they should be interpreted in a meaning and concept consistent with the technical spirit of the present invention.

[0033] Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical ideas of the present invention; thus, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0034] In addition, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the invention, such detailed description is omitted.

[0035] Since embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, the shapes and sizes of the components in the drawings may be exaggerated, omitted, or schematically depicted for clearer explanation. Accordingly, the size or proportion of each component does not entirely reflect the actual size or proportion.

[0036]

[0037] (1st embodiment)

[0038] FIG. 1 is a plan view of a nuclear battery (100) according to exemplary embodiments.

[0039] Figure 2 is a cross-sectional view taken along the cutting line 1I-1I' of Figure 1.

[0040] Referring to FIGS. 1 and 2, the nuclear battery (100) may include a first semiconductor layer (110), a second semiconductor layer (120), a radiation source layer (130), a third semiconductor layer (140), and a fourth semiconductor layer (150).

[0041] The first semiconductor layer (110) may include a base portion (110B) and a plurality of semiconductor rods (110R). Each of the plurality of semiconductor rods (110R) may have a rod shape. Each of the plurality of semiconductor rods (110R) may be connected to the base portion (110B). Each of the plurality of semiconductor rods (110R) may protrude from the base portion (110B).

[0042] Each of the plurality of semiconductor rods (110R) may extend in the Z direction. Each of the plurality of semiconductor rods (110R) may have a high aspect ratio. Since each of the plurality of semiconductor rods (110R) has a high aspect ratio, the area of ​​the pn junction between the first semiconductor layer (110) and the second semiconductor layer (120) facing the radiation source layer (130) and the area of ​​the pn junction between the third semiconductor layer (140) and the fourth semiconductor layer (150) may be increased or maximized.

[0043] Each of the plurality of semiconductor rods (110R) may have a circular planar shape, but is not limited thereto. The planar shape of each of the plurality of semiconductor rods (110R) may have various shapes such as polygons, elliptical stars, cross shapes, etc. Here, the planar shape of each of the plurality of semiconductor rods (110R) may be the shape of each of the plurality of semiconductor rods (110R) on a plane perpendicular to the Z direction.

[0044] Multiple semiconductor rods (110R) may be arranged in the X direction and the Y direction. The X direction, the Y direction, and the Z direction may be substantially perpendicular to each other. Multiple semiconductor rods (110R) may form a hexagonal grid. Here, the multiple semiconductor rods (110R) forming a hexagonal grid means that the multiple semiconductor rods (110R) are arranged at the vertices and centers of regular hexagons (VHG) that fill the XY plane. FIG. 1 illustrates virtual regular hexagons (VHG) in dashed lines to represent the arrangement of multiple semiconductor rods (110R).

[0045] By having multiple semiconductor rods (110R) form a hexagonal grid, the number of multiple semiconductor rods (110R) arranged within a unit area (i.e., the area density of multiple semiconductor rods (110R)) can be increased or maximized. By increasing or maximizing the area density of multiple semiconductor rods (110R), the area of ​​the pn junction between the first semiconductor layer (110) and the second semiconductor layer (120) facing the radiation source layer (130) and the area of ​​the pn junction between the third semiconductor layer (140) and the fourth semiconductor layer (150) can be increased or maximized, and the output (e.g., current or power) of the nuclear battery (100) can be enhanced.

[0046]

[0047] The first semiconductor layer (110) may be a part of the substrate or an additional semiconductor layer formed on the substrate. When the first semiconductor layer (110) is a substrate, the first semiconductor layer (110) may include any one of a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, and a sapphire substrate.

[0048] The first semiconductor layer (110) may include a III-V semiconductor material. The III-V semiconductor material may include InAlP, InGaP, InAlGaP, ZnSe, AlAs, AlAsP, and yttria-stabilized zirconia (YSZ).

[0049] According to exemplary embodiments, the first semiconductor layer (110) may have the chemical formula AMO3, where A is one of La, Ba, Sr, and K, and M is one of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr. For example, the first semiconductor layer (110) may be BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3(here 0 <x<1), Ba 1-x La x SnO3(here 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3(here 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x It may include one or more of and LaAlO3 (where 0 <x<1).

[0050]

[0051] The second semiconductor layer (120) may be on the first semiconductor layer (110). The second semiconductor layer (120) may have a uniform thickness. The second semiconductor layer (120) may have a conformal shape. That is, the shape of the first semiconductor layer (110) may be transferred to the second semiconductor layer (120).

[0052] When the first semiconductor layer (110) is a substrate, the second semiconductor layer (120) may include a metal oxide. The metal oxide is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3(here 0 <x<1), Ba 1-x La x SnO3(here 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3(here 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x It may include one or more selected from the group consisting of and LaAlO3 (where 0 <x<1).

[0053]

[0054] The first semiconductor layer (110) can be doped with a first dopant, and the second semiconductor layer (120) can be doped with a second dopant having opposite polarity to the first dopant. Accordingly, the first semiconductor layer (110) can have opposite polarity to the second semiconductor layer (120), and a pn junction and a depletion region can be formed at the interface between the first semiconductor layer (110) and the second semiconductor layer (120).

[0055] According to exemplary embodiments, the first semiconductor layer (110) comprises silicon (Si) doped with boron (B) and the second semiconductor layer (120) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As).

[0056] According to exemplary embodiments, the first semiconductor layer (110) comprises silicon (Si) doped with either phosphorus (P) or arsenic (As), and the second semiconductor layer (120) may comprise silicon (Si) doped with boron (B).

[0057] According to exemplary embodiments, the first semiconductor layer (110) may comprise gallium arsenide (GaAs) doped with zinc (Zn) and the second semiconductor layer (120) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te).

[0058] According to exemplary embodiments, the first semiconductor layer (110) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te), and the second semiconductor layer (120) may comprise gallium arsenide (GaAs) doped with zinc (Zn).

[0059] According to exemplary embodiments, the first semiconductor layer (110) may comprise germanium (Ge) doped with boron (B) and the second semiconductor layer (120) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb).

[0060] According to exemplary embodiments, the first semiconductor layer (110) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb), and the second semiconductor layer (120) may comprise germanium (Ge) doped with boron (B).

[0061] According to exemplary embodiments, the first semiconductor layer (110) may comprise gallium nitride (GaN) doped with magnesium (Mg) and the second semiconductor layer (120) may comprise gallium nitride (GaN) doped with silicon (Si).

[0062] According to exemplary embodiments, the first semiconductor layer (110) may comprise gallium nitride (GaN) doped with silicon (Si) and the second semiconductor layer (120) may comprise gallium nitride (GaN) doped with magnesium (Mg).

[0063] According to exemplary embodiments, the first semiconductor layer (110) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B), and the second semiconductor layer (120) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P).

[0064] According to exemplary embodiments, the first semiconductor layer (110) comprises silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P), and the second semiconductor layer (120) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B).

[0065] According to exemplary embodiments, the first semiconductor layer (110) may comprise indium phosphate (InP) doped with zinc (Zn) and the second semiconductor layer (120) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si).

[0066] According to exemplary embodiments, the first semiconductor layer (110) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si), and the second semiconductor layer (120) may comprise indium phosphate (InP) doped with zinc (Zn).

[0067] According to exemplary embodiments, the first semiconductor layer (110) may comprise cadmium telluride (CdTe) and the second semiconductor layer (120) may comprise cadmium sulfide (CdS).

[0068] According to exemplary embodiments, the first semiconductor layer (110) may comprise cadmium sulfide (CdS) and the second semiconductor layer (120) may comprise cadmium telluride (CdTe).

[0069] According to exemplary embodiments, the first semiconductor layer (110) may comprise tin oxide (SnO) and the second semiconductor layer (120) may comprise zinc oxide (ZnO).

[0070] According to exemplary embodiments, the first semiconductor layer (110) may comprise zinc oxide (ZnO) and the second semiconductor layer (120) may comprise tin oxide (SnO).

[0071]

[0072] The radiation source layer (130) may be on the second semiconductor layer (120). The radiation source layer (130) may have a uniform thickness. The radiation source layer (130) may have a conformal shape. That is, the shape of the second semiconductor layer (120) may be transferred to the radiation source layer (130).

[0073] The radiation source layer (130) may contain a radioactive isotope. According to exemplary embodiments, the radiation source layer (130) may be a beta ray source. According to exemplary embodiments, the radiation source layer (130) may be tritium ( 3 H, tritium), calcium-45( 45 Ca), nickel-63 63 Ni), copper-67 67 Cu), strontium-90 ( 90 Sr), promethium-147( 147 Pm), osmium-194( 194 OS), Thulium-171( 171 Tm), tantalum-179( 179 Ta), cadmium-109( 109 Cd), germanium-68 68 Ge), cerium-159( 159 Ce) and tungsten-181( 181 It may include one or more of W).

[0074] According to exemplary embodiments, the radiation source layer (130) may be an alpha source. According to exemplary embodiments, the radiation source layer (130) comprises americium-241 (241Am), americium-243 (243Am), polonium-209 (209Po), polonium-210 (210Po), plutonium-238 (238Pu), plutonium-239 (239Pu), curium-242 (242Cm), curium-244 (244Cm), curium-249 (249Cm), promethium-147 (147Pm), uranium-238 (238U), thorium-232 (232Th), It may include one or more of radium-226 (226Ra), bismuth-210 (210Bi), neptunium-237 (237Np), europium-152 (152Eu), francium-223 (223Fr), astatine-210 (210At), protactinium-231 (231Pa), einsteinium-253 (253Es), californium-252 (2520Cf), and berkelium-249 (249Bk).

[0075] According to exemplary embodiments, the radiation source layer (130) may be an alpha source and a beta source at the same time. The radiation source layer (130) may also emit radiation such as gamma rays.

[0076]

[0077] The third semiconductor layer (140) may be on the radiation source layer (130). The third semiconductor layer (140) may have a uniform thickness. The third semiconductor layer (140) may have a conformal shape. That is, the shape of the radiation source layer (130) may be transferred to the third semiconductor layer (140).

[0078] The fourth semiconductor layer (150) may be on the third semiconductor layer (140). The fourth semiconductor layer (150) may have a uniform thickness. The fourth semiconductor layer (150) may have a conformal shape. That is, the shape of the third semiconductor layer (140) may be transferred to the third semiconductor layer (140).

[0079] According to exemplary embodiments, the shape of a plurality of semiconductor rods (110R) is sequentially transferred to a second semiconductor layer (120), a radiation source layer (130), a third semiconductor layer (140), and a fourth semiconductor layer (150), thereby increasing or maximizing the area of ​​the pn junction between the third semiconductor layer (140) and the fourth semiconductor layer (150) facing the radiation source layer (130), and thereby further enhancing the output of the nuclear battery (100).

[0080] The third semiconductor layer (140) may have opposite polarity to the fourth semiconductor layer (150), and a pn junction and a depletion region may be formed at the interface between the third semiconductor layer (140) and the fourth semiconductor layer (150). The composition of the third semiconductor layer (140) and the fourth semiconductor layer (150) is generally similar to that described in relation to the first semiconductor layer (110) and the second semiconductor layer (120).

[0081] According to exemplary embodiments, the third semiconductor layer (140) comprises silicon (Si) doped with boron (B), and the fourth semiconductor layer (150) may comprise silicon (Si) doped with either phosphorus (P) or arsenic (As).

[0082] According to exemplary embodiments, the third semiconductor layer (140) comprises silicon (Si) doped with either phosphorus (P) or arsenic (As), and the fourth semiconductor layer (150) may comprise silicon (Si) doped with boron (B).

[0083] According to exemplary embodiments, the third semiconductor layer (140) may comprise gallium arsenide (GaAs) doped with zinc (Zn) and the fourth semiconductor layer (150) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te).

[0084] According to exemplary embodiments, the third semiconductor layer (140) may comprise gallium arsenide (GaAs) doped with either silicon (Si) or tellurium (Te), and the fourth semiconductor layer (150) may comprise gallium arsenide (GaAs) doped with zinc (Zn).

[0085] According to exemplary embodiments, the third semiconductor layer (140) may comprise germanium (Ge) doped with boron (B) and the fourth semiconductor layer (150) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb).

[0086] According to exemplary embodiments, the third semiconductor layer (140) may comprise germanium (Ge) doped with either phosphorus (P) or antimony (Sb), and the fourth semiconductor layer (150) may comprise germanium (Ge) doped with boron (B).

[0087] According to exemplary embodiments, the third semiconductor layer (140) may comprise gallium nitride (GaN) doped with magnesium (Mg) and the fourth semiconductor layer (150) may comprise gallium nitride (GaN) doped with silicon (Si).

[0088] According to exemplary embodiments, the third semiconductor layer (140) may comprise gallium nitride (GaN) doped with silicon (Si) and the fourth semiconductor layer (150) may comprise gallium nitride (GaN) doped with magnesium (Mg).

[0089] According to exemplary embodiments, the third semiconductor layer (140) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B), and the fourth semiconductor layer (150) may comprise silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P).

[0090] According to exemplary embodiments, the third semiconductor layer (140) comprises silicon carbide (SiC) doped with either nitrogen (N) or phosphorus (P), and the fourth semiconductor layer (150) may comprise silicon carbide (SiC) doped with either aluminum (Al) or boron (B).

[0091] According to exemplary embodiments, the third semiconductor layer (140) may comprise indium phosphate (InP) doped with zinc (Zn) and the fourth semiconductor layer (150) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si).

[0092] According to exemplary embodiments, the third semiconductor layer (140) may comprise indium phosphate (InP) doped with either sulfur (S) or silicon (Si), and the fourth semiconductor layer (150) may comprise indium phosphate (InP) doped with zinc (Zn).

[0093] According to exemplary embodiments, the third semiconductor layer (140) may comprise cadmium telluride (CdTe) and the fourth semiconductor layer (150) may comprise cadmium sulfide (CdS).

[0094] According to exemplary embodiments, the third semiconductor layer (140) may comprise cadmium sulfide (CdS) and the fourth semiconductor layer (150) may comprise cadmium telluride (CdTe).

[0095] According to exemplary embodiments, the third semiconductor layer (140) may comprise tin oxide (SnO) and the fourth semiconductor layer (150) may comprise zinc oxide (ZnO).

[0096] According to exemplary embodiments, the third semiconductor layer (140) may comprise zinc oxide (ZnO) and the fourth semiconductor layer (150) may comprise tin oxide (SnO).

[0097]

[0098] According to exemplary embodiments, the third semiconductor layer (140) may have the same conductivity type as the first semiconductor layer (110), and the fourth semiconductor layer (150) may have the same conductivity type as the second semiconductor layer (120). In one example, the third semiconductor layer (140) and the first semiconductor layer (110) may be doped with an n-type dopant, and the fourth semiconductor layer (150) and the second semiconductor layer (120) may be doped with a p-type dopant. In another example, the third semiconductor layer (140) and the first semiconductor layer (110) may be doped with a p-type dopant, and the fourth semiconductor layer (150) and the second semiconductor layer (120) may be doped with an n-type dopant.

[0099] According to other exemplary embodiments, the third semiconductor layer (140) may have the same conductivity type as the second semiconductor layer (120), and the fourth semiconductor layer (150) may have the same conductivity type as the first semiconductor layer (110). In one example, the third semiconductor layer (140) and the second semiconductor layer (120) may be doped with an n-type dopant, and the fourth semiconductor layer (150) and the first semiconductor layer (110) may be doped with a p-type dopant. In another example, the third semiconductor layer (140) and the second semiconductor layer (120) may be doped with a p-type dopant, and the fourth semiconductor layer (150) and the first semiconductor layer (110) may be doped with an n-type dopant.

[0100]

[0101] (1st and 2nd embodiments)

[0102] Figure 3 is a flowchart illustrating a method for manufacturing a nuclear battery.

[0103] FIGS. 4 to 8 are drawings for explaining a method of manufacturing a nuclear battery according to exemplary embodiments.

[0104] Referring to FIGS. 3 and 4, the first semiconductor layer (110L) can be doped. The first semiconductor layer (110L) can be processed by either ion implantation or diffusion. The first semiconductor layer (110L) can be doped. The dopant for doping the first semiconductor layer (110L) may be a p-type dopant or an n-type dopant. The composition of the first semiconductor layer (110L) and the dopant for doping the first semiconductor layer (110L) is the same as described with reference to FIGS. 1 and 2.

[0105]

[0106] Next, referring to FIGS. 3 to 5, a first semiconductor layer (110L) can be patterned to form a plurality of semiconductor rods (110R) in P120. By processing P120, a first semiconductor layer (110) comprising a base (110B) and a plurality of semiconductor rods (110R) can be formed. The first semiconductor layer (110L) can be patterned by any one of reactive ion etching (RIE) including low-temperature etching and ion beam etching. The first semiconductor layer (110L) may also be patterned by anisotropic wet etching.

[0107] Before patterning the first semiconductor layer (110L), a mask pattern may be formed on the first semiconductor layer (110L). The mask pattern may be formed by photolithography. The mask pattern may expose the etching target portion of the first semiconductor layer (110L) (i.e., the space between the plurality of semiconductor rods (110R)) and cover the non-etching portion (i.e., the portion where the plurality of semiconductor rods (110R) are to be formed). A hard mask may additionally be provided between the mask pattern and the first semiconductor layer (110L).

[0108] A plurality of semiconductor rods (110R) can be formed by patterning the first semiconductor layer (110L). According to exemplary embodiments, each of the plurality of semiconductor rods (110R) may have a circular planar shape and may be arranged in a hexagonal grid.

[0109]

[0110] Next, referring to FIGS. 3 and FIGS. 6, a second semiconductor layer (120) can be formed in P130. The second semiconductor layer (120) can be formed conformally. The second semiconductor layer (120) can have a uniform thickness. The second semiconductor layer (120) can be formed by any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and epitaxial growth, but is not limited thereto. The second semiconductor layer (120) may also be formed by an oxidation process of a metal layer formed by metal CVD.

[0111] The second semiconductor layer (120) may be doped. During the growth of the second semiconductor layer (120), a dopant may be introduced into the third semiconductor layer (140), or, after the second semiconductor layer (120) is formed, the second semiconductor layer (120) may be doped by ion implantation and diffusion.

[0112] The second semiconductor layer (120) can be doped with a dopant having a conductivity type opposite to that of the first semiconductor layer (110). For example, if the first semiconductor layer (110) is doped with a p-type dopant, the second semiconductor layer (120) can be doped with an n-type dopant. For example, if the first semiconductor layer (110) is doped with an n-type dopant, the second semiconductor layer (120) can be doped with a p-type dopant. Accordingly, a pn junction and a depletion region can be formed between the substrate (110) and the second semiconductor layer (120).

[0113]

[0114] Next, referring to FIGS. 3 and FIGS. 7, a radiation source layer (130) can be formed in P140. The radiation source layer (130) can be formed by any one of the methods of evaporation, sputtering, CVD, electroplating, or electroless plating. The radiation source layer (130) can be formed conformally, and accordingly, the radiation source layer (130) can have a uniform thickness.

[0115]

[0116] Next, referring to FIGS. 3 and FIGS. 8, a third semiconductor layer (140) can be formed in P150. The third semiconductor layer (140) can be formed conformally. The third semiconductor layer (140) can have a uniform thickness. The third semiconductor layer (140) can be formed by any one of CVD, PVD, and epitaxial growth, but is not limited thereto.

[0117] The third semiconductor layer (140) may be doped with a dopant. The dopant may be introduced into the third semiconductor layer (140) during the growth of the third semiconductor layer (140), or the third semiconductor layer (140) may be doped by ion implantation and diffusion after the third semiconductor layer (140) is formed.

[0118] According to exemplary embodiments, the third semiconductor layer (140) may be spaced apart from the second semiconductor layer (120) with the radiation source layer (130) in between. The radiation source layer (130) may be interposed between the third semiconductor layer (140) and the second semiconductor layer (120).

[0119]

[0120] Next, referring to FIGS. 1 and FIGS. 3, a fourth semiconductor layer (150) can be formed in P160. The fourth semiconductor layer (150) can be formed conformally. The fourth semiconductor layer (150) can have a uniform thickness. The fourth semiconductor layer (150) can be formed by any one of CVD, PVD, and epitaxial growth, but is not limited thereto.

[0121] The fourth semiconductor layer (150) may be doped with a dopant. The dopant may be introduced into the fourth semiconductor layer (150) during the growth of the fourth semiconductor layer (150), or the fourth semiconductor layer (150) may be doped by ion implantation and diffusion after the fourth semiconductor layer (150) is formed.

[0122]

[0123] The present invention has been described in more detail above through drawings and embodiments. However, the configurations described in the drawings or embodiments described in this specification are merely one embodiment of the present invention and do not represent all technical concepts of the present invention; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

Claims

1. A first semiconductor layer comprising a plurality of semiconductor loads; A second semiconductor layer on the plurality of semiconductor loads above; A radiation source layer on the second semiconductor layer; and A nuclear battery comprising a third semiconductor layer on the radiation source layer.

2. In Paragraph 1, A nuclear battery characterized in that the second semiconductor layer has a uniform thickness.

3. In Paragraph 1, A nuclear battery characterized in that the radiation source layer has a uniform thickness.

4. In Paragraph 1, A nuclear battery characterized in that the third semiconductor layer has a uniform thickness.

5. In Paragraph 1, A nuclear battery further comprising a fourth semiconductor layer on the third semiconductor layer.

6. In Paragraph 5, A nuclear battery characterized in that the above-mentioned fourth semiconductor layer has a uniform thickness.

7. In Paragraph 5, The first semiconductor layer is doped with a p-type dopant, and The above second semiconductor layer is doped with an n-type dopant, and The above third semiconductor layer is doped with a p-type dopant, and A nuclear battery characterized in that the above-mentioned fourth semiconductor layer is doped with an n-type dopant.

8. In Paragraph 5, The first semiconductor layer is doped with an n-type dopant, and The above second semiconductor layer is doped with a p-type dopant, and The above third semiconductor layer is doped with a p-type dopant, and A nuclear battery characterized in that the above-mentioned fourth semiconductor layer is doped with an n-type dopant.

9. In Paragraph 5, The first semiconductor layer is doped with a p-type dopant, and The above second semiconductor layer is doped with an n-type dopant, and The above third semiconductor layer is doped with an n-type dopant, and A nuclear battery characterized in that the above-mentioned fourth semiconductor layer is doped with a p-type dopant.

10. In Paragraph 5, The first semiconductor layer is doped with an n-type dopant, and The above second semiconductor layer is doped with a p-type dopant, and The above third semiconductor layer is doped with an n-type dopant, and A nuclear battery characterized in that the above-mentioned fourth semiconductor layer is doped with a p-type dopant.

11. In Paragraph 1, A nuclear battery characterized in that the above plurality of semiconductor rods form a hexagonal grid.

12. In Paragraph 1, A nuclear battery characterized in that the planar shape of each of the plurality of semiconductor rods is circular.

13. Step of doping the first semiconductor layer; A step of patterning a first semiconductor layer to form a plurality of semiconductor loads; A step of forming a second semiconductor layer on the first semiconductor layer; A step of forming a radiation source layer on the second semiconductor layer; and A method for manufacturing a nuclear battery comprising the step of forming a third semiconductor layer on the radiation source layer.

14. In Paragraph 13, A method for manufacturing a nuclear battery characterized in that the second semiconductor layer is formed conformally.

15. In Paragraph 13, A method for manufacturing a nuclear battery characterized in that the radiation source layer is formed conformally.

16. In Paragraph 13, A method for manufacturing a nuclear battery characterized in that the third semiconductor layer is formed conformally.

17. In Paragraph 13, A method for manufacturing a nuclear battery further comprising a fourth semiconductor layer on the third semiconductor layer.

18. In Paragraph 17, A method for manufacturing a nuclear battery characterized in that the above-mentioned fourth semiconductor layer is formed conformally.

19. In Paragraph 13, A method for manufacturing a nuclear battery characterized in that the plurality of semiconductor rods above form a hexagonal grid.

20. In Paragraph 13, A method for manufacturing a nuclear battery characterized in that the planar shape of each of the plurality of semiconductor rods is circular.

Images