Method and apparatus for performing data transmission using a frequency interleaver in a wireless communication system

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure discloses a method for performing data transmission by a base station in a wireless communication system. The method includes receiving one or more transport blocks (TBs); generating a plurality of codewords corresponding to the one or more TBs; applying a cyclic shift to the plurality of codewords using an offset; performing frequency-domain interleaving on modulation symbols obtained from the cyclic shifted plurality of codewords; and transmitting a plurality of interleaved modulation symbols via a physical multicast channel (PMCH).

Description

METHOD AND APPARATUS FOR PERFORMING DATA TRANSMISSION USING A FREQUENCY INTERLEAVER IN A WIRELESS COMMUNICATION SYSTEM

[0001] The present disclosure is related to the field of wireless networks. More particularly, the present disclosure is related to a method and system for performing data transmission by a base station using a frequency interleaver in a wireless communication system.

[0002] 5G mobile communication technologies define broad frequency bands such that high transmission rates and new services are possible, and can be implemented not only in "Sub 6GHz" bands such as 3.5GHz, but also in "Above 6GHz" bands referred to as mmWave including 28GHz and 39GHz. In addition, it has been considered to implement 6G mobile communication technologies (referred to as Beyond 5G systems) in terahertz bands (for example, 95GHz to 3THz bands) in order to accomplish transmission rates fifty times faster than 5G mobile communication technologies and ultra-low latencies one-tenth of 5G mobile communication technologies.

[0003] At the beginning of the development of 5G mobile communication technologies, in order to support services and to satisfy performance requirements in connection with enhanced Mobile BroadBand (eMBB), Ultra Reliable Low Latency Communications (URLLC), and massive Machine-Type Communications (mMTC), there has been ongoing standardization regarding beamforming and massive MIMO for mitigating radio-wave path loss and increasing radio-wave transmission distances in mmWave, supporting numerologies (for example, operating multiple subcarrier spacings) for efficiently utilizing mmWave resources and dynamic operation of slot formats, initial access technologies for supporting multi-beam transmission and broadbands, definition and operation of BWP (BandWidth Part), new channel coding methods such as a LDPC (Low Density Parity Check) code for large amount of data transmission and a polar code for highly reliable transmission of control information, L2 pre-processing, and network slicing for providing a dedicated network specialized to a specific service.

[0004] Currently, there are ongoing discussions regarding improvement and performance enhancement of initial 5G mobile communication technologies in view of services to be supported by 5G mobile communication technologies, and there has been physical layer standardization regarding technologies such as V2X (Vehicle-to-everything) for aiding driving determination by autonomous vehicles based on information regarding positions and states of vehicles transmitted by the vehicles and for enhancing user convenience, NR-U (New Radio Unlicensed) aimed at system operations conforming to various regulation-related requirements in unlicensed bands, NR UE Power Saving, Non-Terrestrial Network (NTN) which is UE-satellite direct communication for providing coverage in an area in which communication with terrestrial networks is unavailable, and positioning.

[0005] Moreover, there has been ongoing standardization in air interface architecture / protocol regarding technologies such as Industrial Internet of Things (IIoT) for supporting new services through interworking and convergence with other industries, IAB (Integrated Access and Backhaul) for providing a node for network service area expansion by supporting a wireless backhaul link and an access link in an integrated manner, mobility enhancement including conditional handover and DAPS (Dual Active Protocol Stack) handover, and two-step random access for simplifying random access procedures (2-step RACH for NR). There also has been ongoing standardization in system architecture / service regarding a 5G baseline architecture (for example, service based architecture or service based interface) for combining Network Functions Virtualization (NFV) and Software-Defined Networking (SDN) technologies, and Mobile Edge Computing (MEC) for receiving services based on UE positions.

[0006] As 5G mobile communication systems are commercialized, connected devices that have been exponentially increasing will be connected to communication networks, and it is accordingly expected that enhanced functions and performances of 5G mobile communication systems and integrated operations of connected devices will be necessary. To this end, new research is scheduled in connection with eXtended Reality (XR) for efficiently supporting AR (Augmented Reality), VR (Virtual Reality), MR (Mixed Reality) and the like, 5G performance improvement and complexity reduction by utilizing Artificial Intelligence (AI) and Machine Learning (ML), AI service support, metaverse service support, and drone communication.

[0007] Furthermore, such development of 5G mobile communication systems will serve as a basis for developing not only new waveforms for providing coverage in terahertz bands of 6G mobile communication technologies, multi-antenna transmission technologies such as Full Dimensional MIMO (FD-MIMO), array antennas and large-scale antennas, metamaterial-based lenses and antennas for improving coverage of terahertz band signals, high-dimensional space multiplexing technology using OAM (Orbital Angular Momentum), and RIS (Reconfigurable Intelligent Surface), but also full-duplex technology for increasing frequency efficiency of 6G mobile communication technologies and improving system networks, AI-based communication technology for implementing system optimization by utilizing satellites and AI (Artificial Intelligence) from the design stage and internalizing end-to-end AI support functions, and next-generation distributed computing technology for implementing services at levels of complexity exceeding the limit of UE operation capability by utilizing ultra-high-performance communication and computing resources.

[0008] The principal object of the embodiment disclosed herein is to provide a method and a system for a Time-frequency interleavers for 5G broadcast in the wireless communication network system.

[0009] In an aspect, the objectives are achieved by providing a method for performing data transmission by a base station using a frequency interleaver in a wireless communication system. The method includes receiving, by a network apparatus from higher layers, a transport block for baseband processing. The transport block is split into a plurality of code blocks. Each code block of the plurality of code blocks undergoes cyclic redundancy check (CRC) addition, channel coding, rate matching and code block concatenation to generate a plurality of code words. Further, the method includes processing each code word of the plurality of code words by scrambling and modulation mapping to generate modulation symbols, an optional layer mapping and precoder, frequency interleaver, a block permute and block shift processing, a resource element mapper and an OFDM signal generator. Further, the method includes dividing the modulation symbols into a plurality of sets. Each set of the plurality of sets include the modulation symbols to be mapped to orthogonal frequency division multiplexing (OFDM) symbols. Each set of the plurality of sets is further processed using the frequency interleaver, a block permute and block shift, a resource element mapper, and an OFDM signal generation associated with an OFDM symbol associated with the plurality of sets. Further, the method includes interleaving each set of the plurality of sets to be mapped to an OFDM symbol, using the frequency interleaver to obtain a plurality of interleaved modulation symbols. Further, the method includes transmitting the plurality of interleaved modulation symbols via a physical multicast channel (PMCH).

[0010] In an aspect, the objectives are achieved by providing a network apparatus for performing data transmission by a base station using a frequency interleaver in a wireless communication system. The network apparatus includes a processor, a memory coupled to the processor, and a modulation interleaving controller communicatively coupled to the processor and the memory. The modulation interleaving controller receives a transport block for baseband processing. The transport block is split into a plurality of code blocks. Each code block of the plurality of code blocks undergoes CRC addition, channel coding, rate matching and code block concatenation to generate a plurality of code words. Further, the modulation interleaving controller processes each code word of the plurality of code words by scrambling and modulation mapping to generate modulation symbols, an optional layer mapping and precoder, frequency interleaver, a block permute and block shift processing, a resource element mapper and an OFDM signal generator. Further, the modulation interleaving controller divides the modulation symbols into a plurality of sets. Each set of the plurality of sets include the modulation symbols to be mapped to orthogonal frequency division multiplexing (OFDM) symbols. Each set of the plurality of sets is further processed using the frequency interleaver, a block permute and block shift, a resource element mapper, and an OFDM signal generation associated with an OFDM symbol associated with the plurality of sets. Further, the modulation interleaving controller interleaves each set of the plurality of sets to be mapped to an OFDM symbol, using the frequency interleaver to obtain a plurality of interleaved modulation symbols. Further, the modulation interleaving controller transmits the plurality of interleaved modulation symbols via a physical multicast channel (PMCH).

[0011] These and other aspects of the embodiments will be better understood with the following description and accompanying drawings. The descriptions, while indicating preferred embodiments and specific details, are for illustration and not limitation. Many changes and modifications can be made within the scope of the embodiments.

[0012] These and other features, aspects, and advantages of the present embodiments are illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:

[0013] Fig. 1A is a flow diagram that illustrates the Transport Block Processing for Downlink Shared Channel (DL-SCH) Paging Channel (PCH) and Multicast Channel (MCH).

[0014] Fig. 1B is a flow diagram that illustrates the overview of the physical channel processing.

[0015] Fig. 2A illustrates the structure of a radio frame in the wireless communication network system.

[0016] Fig. 2B is a schematic diagram that illustrates the LTE subframe slot and Orthogonal Frequency-Division Multiplexing (OFDM) symbol structure.

[0017] Fig. 3 is a flow diagram that illustrates the Physical Multicast Channel (PMCH) transmit processing chain with the RE interleaving to provide frequency (time) interleaving to increase frequency (time) diversity.

[0018] Fig. 4 is a schematic diagram that illustrates the mapping to the RE.

[0019] Fig. 5 is a schematic diagram that illustrates the Channel Burst Errors due to deep fades in a time-frequency grid.

[0020] Fig. 6 is a schematic diagram that illustrates a schematic of a network apparatus implemented to carry out the disclosed subject matter according to an embodiment as disclosed herein.

[0021] Fig. 7 is a schematic diagram that illustrates a frequency interleaver that uses the row-column interleaver usedin theprocess of data transmission, according to an embodiment as disclosed herein.

[0022] Fig. 8 is a schematic diagram that illustrates the occurrence of deep fade errors in the modulated symbols off the time-frequency RE grid, according to an embodiment as disclosed herein.

[0023] Fig. 9 is a schematic diagram that illustrates the effect of frequency interleaver at the transmitter and the deinterleaver at the receiver, according to an embodiment as disclosed herein.

[0024] Fig. 10 is a schematic diagram that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=2N and the deep fades correspond to same OFDM symbol, according to an embodiment as disclosed herein.

[0025] Fig. 11 is a schematic diagram that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=N and the deep fades correspond to two adjacent OFDM symbols, according to an embodiment as disclosed herein.

[0026] Fig. 12 is a schematic diagram that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=N and the deep fades correspond to same OFDM symbols but adjacent DFR, according to an embodiment as disclosed herein.

[0027] Fig. 13A is a schematic diagram that illustrates depicts a scenario where the LLRs from two different instances of the same transmission blocks, TB LLRs and TB LLRs, are combined without offset, in the context of chase combining, according to an embodiment as disclosed herein.

[0028] Fig. 13B is a schematic diagram that illustrates depicts a scenario where the LLRs from two different instances of the same transmission blocks, TB LLRs and TB LLRs, are combined with offset, in t, according to an embodiment as disclosed herein.

[0029] Fig. 14 is a schematic diagram that illustrates the proposed Offset-frequency interleaver with offset of 5, according to an embodiment as disclosed herein.

[0030] Fig. 15 is a schematic diagram that illustrates how different RVs are formed for retransmission and read from a circular buffer, according to an embodiment as disclosed herein.

[0031] Fig. 16 is a schematic diagram that illustrates modulated symbols per subframe of two RVs, RV1 and RV3, according to an embodiment as disclosed herein.

[0032] Fig. 17 is a schematic diagram that illustrates the transmission and reception of Multiple Transport Blocks and Multiple RVs of a transport block, according to an embodiment as disclosed herein.

[0033] Fig. 18 is a schematic diagram that illustrates the decimated Time-frequency interleaver, according to an embodiment as disclosed herein.

[0034] Fig. 19 is a schematic diagram that illustrates the decimated Time-frequency interleaver (with TSBI), according to an embodiment as disclosed herein.

[0035] Fig. 20 is a schematic diagram that illustrates the diagonal Time-frequency interleaver, according to an embodiment as disclosed herein.

[0036] Fig. 21 is a schematic diagram that illustrates decimated frequency interleaver, according to an embodiment as disclosed herein.

[0037] Fig. 22 is a schematic diagram that illustrates decimated frequency interleaver (with TSBI), according to an embodiment as disclosed herein.

[0038] Fig. 23 is a schematic diagram that illustrates frequency interleaver, according to an embodiment as disclosed herein.

[0039] Fig. 24 is a schematic diagram that illustrates a transmit chain as per legacy and another transmit chain that uses offset-frequency interleaver and block permute block shift features. according to an embodiment as disclosed herein.

[0040] Fig. 25 is a schematic diagram that illustrates a block permute and block shift according to an embodiment as disclosed herein.

[0041] Fig. 26 is a flow diagram that illustrates a method for performing data transmission by a base station using a frequency interleaver in a wireless communication system according to an embodiment as disclosed herein.

[0042] Fig. 27 illustrates a method 2700 performed by a base station (BS) according to various embodiments of the present disclosure.

[0043] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0044] In describing the embodiments, descriptions related to technical contents well-known in the art and not associated directly with the disclosure will be omitted. Such an omission of unnecessary descriptions is intended to prevent obscuring of the main idea of the disclosure and more clearly transfer the main idea.

[0045] For the same reason, in the accompanying drawings, some elements may be exaggerated, omitted, or schematically illustrated. Further, the size of each element does not completely reflect the actual size. In the drawings, identical or corresponding elements are provided with identical reference numerals or different reference numerals.

[0046] The advantages and features of the disclosure and ways to achieve them will be apparent by making reference to embodiments as described below in detail in conjunction with the accompanying drawings. However, the disclosure is not limited to the embodiments set forth below, but may be implemented in various different forms. The following embodiments are provided only to completely disclose the disclosure and inform those skilled in the art of the scope of the disclosure, and the disclosure is defined only by the scope of the appended claims. Throughout the specification, the same or like reference numerals designate the same or like elements. Furthermore, in describing the disclosure, a detailed description of known functions or constitution incorporated herein will be omitted in the case that it is determined that the description may make the subject matter of the disclosure unnecessarily unclear. The terms which will be described below are terms defined in consideration of the functions in the disclosure, and may be different according to users, intentions of the operators, or customs. Therefore, the definitions of the terms should be made based on the contents throughout the specification.

[0047] Herein, it will be understood that each block of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, may be performed based on computer program instructions. These computer program instructions may be loaded collectively onto at least one processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which perform through any one of, or in any combination of, the at least one processor of the computer or other programmable data processing apparatus, create means for performing the functions specified in the flowchart block(s). These computer program instructions may also be stored in a non-transitory computer usable or computer-readable memory that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer usable or computer-readable memory produce an article of manufacture including instruction means that perform the function specified in the flowchart block(s). The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable data processing apparatus to produce a computer executed process such that the instructions that perform on the computer or other programmable data processing apparatus provide steps for executing the functions specified in the flowchart block(s).

[0048] Further, each block may represent a module, segment, or portion of code, which includes one or more executable instructions for executing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks(or functions) shown in succession may in fact be performed substantially concurrently or the blocks may sometimes be performed in the reverse order, depending upon the functionality involved.

[0049] As used in embodiments of the disclosure, a "~unit" may refer to a software element or a hardware element, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), which performs a predetermined function. However, the term including the word "~unit" does not always have a meaning limited to software or hardware. The "~unit" may be constructed either to be stored in an addressable storage medium or to execute one or more processors. Therefore, the "~unit" includes, for example, software elements, object-oriented software elements, components such as class elements and task elements, processes, functions, properties, procedures, sub-routines, segments of a program code, drivers, firmware, micro-codes, circuits, data, database, data structures, tables, arrays, and parameters. The components and functions provided by the "~unit" may be either combined into a smaller number of components and a "~unit," or divided into additional components and a "~unit." Moreover, the components and "~units" may be implemented to reproduce one or more central processing units (CPUs) within a device or a security multimedia card. Further, in the embodiments, the "~unit" may include one or more processors.

[0050] It should be appreciated that the blocks in each flowchart and combinations of the flowcharts may be performed by one or more computer programs which include instructions. The entirety of the one or more computer programs may be stored in a single memory device or the one or more computer programs may be divided with different portions stored in different multiple memory devices.

[0051] Any of the functions or operations described herein can be processed by one processor or a combination of processors. The one processor or the combination of processors is circuitry performing processing and includes circuitry like an application processor (AP, e.g. a CPU), a communication processor (CP, e.g., a modem), a graphics processing unit (GPU), a neural processing unit (NPU) (e.g., an artificial intelligence (AI) chip), a Wi-Fi chip, a Bluetooth® chip, a global positioning system (GPS) chip, a near field communication (NFC) chip, connectivity chips, a sensor controller, a touch controller, a finger-print sensor controller, a display driver integrated circuit (IC), an audio CODEC chip, a universal serial bus (USB) controller, a camera controller, an image processing IC, a microprocessor unit (MPU), a system on chip (SoC), an IC, or the like.

[0052] It will be appreciated that various embodiments of the disclosure according to the claims and description in the specification can be realized in the form of hardware, software or a combination of hardware and software.

[0053] Any such software may be stored in non-transitory computer readable storage media. The non-transitory computer readable storage media store one or more computer programs (software modules), the one or more computer programs include computer-executable instructions that, when executed by one or more processors of an electronic device individually or collectively, cause the electronic device to perform a method of the disclosure.

[0054] Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like read only memory (ROM), whether erasable or rewritable or not, or in the form of memory such as, for example, random access memory (RAM), memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a compact disk (CD), digital versatile disc (DVD), magnetic disk or magnetic tape or the like. It will be appreciated that the storage devices and storage media are various embodiments of non-transitory machine-readable storage that are suitable for storing a computer program or computer programs comprising instructions that, when executed, implement various embodiments of the disclosure. Accordingly, various embodiments of the present disclosure may provide a program comprising code for implementing apparatus or a method as claimed in any one of the claims of this specification and a non-transitory machine-readable storage storing such a program.

[0055] Hereinafter, the determination of priority between A and B in the present disclosure may refer to various actions such as selecting the one having a higher priority based on a predefined priority rule and performing an operation corresponding thereto, or omitting or dropping an operation corresponding to the one having a lower priority.

[0056] Hereinafter, "A or B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0057] In addition, "at least one of A, B, and C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0058] In addition, "at least one of A, B, or C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0059] Furthermore, "A / B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0060] Furthermore, "A, B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0061] Furthermore, "A and B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0062] Furthermore, "if condition A and condition B are satisfied," as described in the present disclosure, may not be limited to a case where both condition A and condition B are satisfied, but may be understood to include a case where either condition A or condition B is individually satisfied, both condition A and condition B are satisfied, or one or more additional conditions are satisfied in combination.

[0063] Furthermore, throughout this disclosure, ordinal terms such as "first," "second," "third," etc., (and similar qualifiers) are used merely to distinguish between different instances, occurrences, configurations, messages, stages, or aspects of elements, operations, or information as described herein. Unless the context clearly dictates otherwise, the use of such ordinal terms does not itself require that the elements, operations, or information distinguished by these terms be structurally different, numerically distinct, or substantively dissimilar. For example, a "first signal" and a "second signal" may refer to instances of the same signal transmitted at different times or containing the same core information despite minor variations, or they may refer to signals with different content or characteristics, depending on the specific context. Similarly, a "first value" and a "second value" may represent the same magnitude but measured or applied in different circumstances, or they may represent different magnitudes. The interpretation should be guided by the specific technical context, function, and relationship described in the relevant portion of the specification and claims.

[0064] Furthermore, the terms "first ~", "second ~", etc., as described in the present disclosure with respect to various elements (e.g., information, objects, operation, sequences, or the like), should not limit those elements. These terms may only be intended to distinguish one element from another, and may not be intended to indicate a specific order. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element.

[0065] Furthermore, even if "first ~" and "second ~" are described in the present disclosure, it may be understood that element(s) referred to by "first ~" and "second ~" may be the same or different. For example, in case of element(s) being information, first information and second information may both be same information and, in some cases, are separate and different information.

[0066] In addition, the terms "if ~" and "in case that ~" as used in the disclosure or claims may be interpreted to include the meanings of "when (or upon) ~," "in response to ~," "based on ~," or "according to ~," and may be used interchangeably with these expressions. In addition, expressions other than those exemplified herein may also be used, as long as they have substantially the same meaning and do not impair the technical features of the present disclosure.

[0067] For example, the physical layer signaling may be referred to as Layer 1 (L1) signaling and may include downlink control information (DCI). In addition, the higher layer signaling may include a medium access control (MAC) control message, a radio resource control (RRC) signaling message, a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as L3 (layer 3) signaling. It should be noted, however, that the higher layer signaling is not limited to the aforementioned examples.

[0068] In addition, the term "not perform" as used in the present disclosure or claims may, in context, be understood to mean that the corresponding step is omitted or skipped. Such a term may be replaced with other terms having the same or substantially equivalent meaning.

[0069] In addition, "transmitting a message including A and B" as described in the present disclosure, may be understood as encompassing both (i) transmitting A and B in a single message, and (ii) transmitting A and B separately via multiple messages (e.g., transmitting a first message including A and a second message including B). This interpretation may also apply to messages that include two or more items (e.g., A, B, C), transmitted either together or separately.

[0070] In addition, "transmitting a message including A and transmitting a message including B" may also be interpreted as transmitting a message including A and B in a single message.

[0071] In the specific embodiments of the present disclosure described below, terms or components included in the disclosure may be expressed in singular or plural form depending on the specific embodiments presented. However, such singular or plural expressions are selected appropriately for convenience of description, and the present disclosure is not limited to a singular or plural number of components. A component expressed in the plural form may be implemented as a single component, and a component expressed in the singular form may be implemented as multiple components.

[0072] The drawings or flowcharts described below illustrate exemplary methods that may be implemented according to the principles of the present disclosure, and various modifications may be made to the methods illustrated in the flowcharts of the present disclosure. For example, although illustrated as a series of steps, various steps in each drawing or flowchart may overlap, occur in parallel, occur in a different order, or be repeated. In other examples, any step may be omitted or replaced with another step.

[0073] The methods and apparatuses proposed in the embodiments of the present disclosure are not limited to each embodiment individually, but may also be applied in combination of all or some of the embodiments proposed in the disclosure. Therefore, the embodiments of the present disclosure may be modified and applied without significantly departing from the scope of the present disclosure, as would be understood by those skilled in the art.

[0074] In this case, even if certain wordings are described differently across embodiments, they may be used interchangeably or in substitution or in combination if their underlying concepts are equivalent. For example, for the same or equivalent concept, even if one embodiment uses the expression "A" and another embodiment uses the expression "B", such expressions may be understood interchangeably, in substitution, or in combination.

[0075] The terms used in the following description to refer to access nodes, network entities, messages, interfaces between network entities, various types of identification information, and the like, are provided merely for the convenience of explanation by way of example. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may also be used. Such terms may also be interchangeable with terms defined in any 3rd generation partnership project (3GPP) technical specifications (TS) where appropriate.

[0076] Hereinafter, a base station is an entity that allocates resources to terminals, and may be at least one of a gNode B, an eNode B, a Node B, a base station (BS), a wireless access unit, a BS controller, or a node on a network.

[0077] Furthermore, the base station of the present disclosure may include a split architecture comprising a central unit (CU) and a distributed unit (DU). In this structure, the CU is configured to process the higher layers of the control and user planes, while the DU is configured to process lower-layer radio resource functions. The embodiments of the present disclosure may be equally applicable to 5G base station architectures in which such CU and DU functional splits are implemented.

[0078] A terminal may include a UE, a mobile station (MS), a cellular phone, a smartphone, a computer, or a multimedia system capable of performing communication functions.

[0079] In the disclosure, a downlink (DL) refers to a radio link through which a BS transmits a signal to a UE, and an uplink (UL) refers to a radio link through which a UE transmits a signal to a BS.

[0080] Furthermore, hereinafter, 5th generation (5G) mobile communication technologies (e.g., 5G new radio (NR)), 6th generation (6G) mobile communication technologies may be described by way of example, but the embodiments of the present disclosure may also be applied to other communication systems having similar technical backgrounds or channel types. For example, newly evolved mobile communication systems developed after 5G and 6G may be included. Furthermore, based on determinations by those skilled in the art, the embodiments of the present disclosure may also be applied to other communication systems (e.g., Wi-Fi systems) through some modifications without significantly departing from the scope of the present disclosure

[0081] In the following description, the terms physical channel and signal may be used interchangeably with data or control signal. For example, the term physical downlink shared channel (PDSCH) refers to a physical channel through which data is transmitted, but the term PDSCH may also be used to refer to the data itself. That is, in the present disclosure, the expression "transmit a physical channel" may be interpreted as being equivalent to the expression "transmit data or a signal via a physical channel."

[0082] Hereinafter, in the context of the present disclosure, higher layer signaling may refer to signaling corresponding to at least one or any combination of the following: master information block (MIB), system information block (SIB) or SIB M (M = 1, 2, ...), radio resource control (RRC), or medium access control (MAC) control element (CE), or a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as L3 (layer 3) signaling.

[0083] In addition, L1 signaling may refer to signaling corresponding to at least one or any combination of signaling techniques using the at least one or any combination of the following physical layer channels or signaling: physical downlink control channel (PDCCH), downlink control information (DCI), user equipment (UE)-specific DCI, group-common DCI, common DCI, scheduling DCI (e.g., DCI used for scheduling downlink or uplink data), non-scheduling DCI (e.g., DCI not used for scheduling downlink or uplink data) physical uplink control channel (PUCCH), or uplink control information (UCI). The L1 signaling message may be referred to as a physical layer signaling.

[0084] Hereinafter, the expression that information is configured by the BS, as used in the present disclosure or claims, may, in context, be understood to mean that the terminal receives the corresponding information from the BS via a physical layer signaling or a higher layer signaling. Such an expression may be replaced with other terms having the same or substantially equivalent meaning.

[0085] Hereinafter, the operational principle of the present disclosure will be described in detail with reference to the accompanying drawings.

[0086] The advances in wireless communication technologies have made it possible for the development of Long-Term Evolution (LTE)-based 5G broadcast services. These services are intended to deliver the data to many people at the same time through the Physical Multicast Channel (PMCH). The transport block processing in this context involves several steps such as Cyclic Redundancy Check (CRC), channel coding, code block concatenation, and rate matching. However, a challenge arises due to the absence of time and frequency interleaving parts in the current processing mechanisms. The time and frequency interleaving be used for data transmission against burst error, which are caused by deep fades in the channel. Deep fades refer to significant drops in signal strength over short periods, leading to a higher likelihood of burst errors. These errors effects the quality of broadcast services. Existing mechanisms for frequency interleaving include two primary types: Inter-Column Bit Interleaving (ICBI) and Time-Slot Bit Interleaving (TSBI). In general, a frequency interleaver works as follows: 1. Data is written into a row-column interleaver in a column way. 2. The rows are optionally permuted as seen in TSBI. 3. Data is then read out in a row-wise manner.

[0087] The principle of the interleaver will depend on its minimum span, which is the separation of data before and after permutation by the interleaver. In the case of ICBI, the minimum span is N + 1 for a M x N interleaver where M is the number of rows of the row-column interleaver and N is the no. of columns of the row-column interleaver. For TSBI, the minimum span is chosen as k for a given N and M, such that minimum span is maximized.

[0088] Consider M x N interleaver for ICBI, If minimum span (S) is N+1, and for example considering one region of deep fade and minim span, if DFis K times S then there will be K consecutive symbols with a burst error after deinterleaving, for every M values. If S is greater than DFthere are no consecutive burst errors.

[0089] Given the importance of minimizing burst errors and enhancing data robustness, there is a need of interleavers with a minimum span (S) that is greater than the deep fade (DF) or S being dependent on DF.

[0090] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with a plurality of other embodiments to form new embodiments. The term "or" as used herein, refers to a non-exclusive or, unless otherwise indicated. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein can be practiced and to further enable those skilled in the art to practice the embodiments herein. Accordingly, the examples are not be construed as limiting the scope of the embodiments herein.

[0091] As is existing in the field, embodiments are described and illustrated in terms of blocks that carry out a described function or functions.　These blocks, which referred to herein as managers, units, modules, hardware components or the like, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and the like, and optionally be driven by firmware and software. The circuits, for example, be embodied in a plurality of semiconductor chips, or on substrate supports such as printed circuit boards, and the like.　The circuits constituting a block be implemented by dedicated hardware, or by a processor (e.g., a plurality of programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments be physically separated into two or more interacting and discrete blocks without departing from the scope of the proposed method.　Likewise, the blocks of the embodiments be physically combined into more complex blocks without departing from the scope of the proposed method.

[0092] The drawings help explain the technical features, but the embodiments are not limited to them. The proposed method includes any modifications, equivalents, and substitutes beyond those shown. Terms like first, second, etc., are used to distinguish elements and do not limit them. Referring now to the drawings, and more particularly to FIGS. 1 through 27, where similar reference characters denote corresponding features consistently throughout the figures, there are shown embodiments.

[0093] Fig. 1A is a flow diagram that illustrates a Transport Block Processing for DL-SCH, PCH and MCH. The Transport Block Processing illustrated here is taken from 36.212 titled "Multiplexing and channel coding for LTE". At step 102, the method includes a0, a1, ...., aA-1is given as an input to the Transport block CRC attachment. At step 104, the method includes the inputs b0, b1, ...., bB-1is sent to the Code block segmentation Code block CRC attachment. At step 106, the method includes the inputs is sent to the Channel coding block. At step 108, the method includes the is given as an input to the Rate matching block. At step 110, the method includes the inputs is sent to the Code block concatenation and f0,f1,...,fG-1is received as codeword.

[0094] Fig. 1B is a flow diagram that illustrates the overview of the physical channel processing. The codewords generated after Transport Block Processing illustrated in Fig. 1A is taken as an input for the Waveform generation. The Fig. 1B illustrated here is taken from 36.211 titled "Physical channels and modulation".

[0095] Fig. 2A illustrates the structure (200A) of a radio frame in the wireless communication network system. One radio frame has a duration of 10 milliseconds and includes 20 slots, each with a duration of 0.5 milliseconds. The slots are indexed from 0 to 19. A subframe includes two consecutive slots, and thus, one radio frame includes 10 subframes. Each subframe has a duration of 1 millisecond. For example, the LTE frame where Tf=307200Ts=10ms which includes slots where one slot, Tslot=15360Tg=0.5ms and two slots equals one subframe.

[0096] Fig. 2B provides a more detailed view of the structure (200B) of a subframe and its constituent slots. Each subframe includes two slots, and each slot includes 7 OFDM (Orthogonal Frequency Division Multiplexing) symbols when a short cyclic prefix is used. The OFDM symbols within a slot are indexed from 0 to 6. The cyclic prefixes are inserted before each OFDM symbol to mitigate inter-symbol interference and to provide robustness against multipath propagation. As shown in the Fig. 2B, one Frame equals 10 msec including 20 slots where each slot equals 0.5msec and one subframe includes two slots which makes one sub-frame equals 1.0msec. Each slot includes 7 OFDM symbols which is a short cyclic prefix. One transport block illustrated in the FIG 1A is mapped to one subframe.

[0097] Fig. 3 is a flow diagram (300) that illustrates the PMCH transmit processing chain with the RE interleaving to provide frequency (time) interleaving to increase frequency (time) diversity. The process begins with multiplexing and channel coding, where the data from the PMCH is multiplexed and encoded to protect against errors. The encoded data is then scrambled using a scrambling sequence to randomize the data and reduce the likelihood of burst errors. The scrambled data is mapped to Quadrature Amplitude Modulation (QAM) symbols in the QAM Mapper, which modulates the data onto carriers. The modulated data is then interleaved using a RE interleaver to spread the data across the frequency-time grid, providing additional robustness against errors. Reference signals are inserted into the interleaved data to assist with channel estimation at the receiver. Further, the data is processed through OFDM generation, where it is converted into an OFDM signal for transmission over the wireless channel.

[0098] The output of code block concatenation as illustrated in the Fig. 1A is passed through time / frequency interleaver before further processing by elements of 36.211. For reference, the Fig. 3 is taken from 3GPP document R1-1910979 titled "Time and Frequency Interleaving for LTE-based 5G Terrestrial Broadcast".

[0099] Fig. 4 is a schematic diagram (400) that illustrates the mapping to the REs. Structure of subcarriers in an OFDM symbol, where the number of subcarriers is denoted as NOFDMand is equal to 10. The figure shows a grid where the horizontal axis represents time and the vertical axis represents frequency. Each cell within the grid is marked with a unique identifier, indicating a RE (resource element). The symbols are first written across REs in a given OFDM symbol, then to REs in the next OFDM symbol and so on. NOFDMis referred to as the number of subcarriers dedicated to PMCH channel (after accounting for other RE like reference signals etc) in one OFDM symbol.

[0100] Fig. 5 is a schematic diagram (500) that illustrates the Channel Burst Errors due to deep fades in a time-frequency grid. The horizontal axis represents time in terms of OFDM symbols, while the vertical axis represents frequency. A contiguous region of subcarriers and OFDM symbols suffer deep fades resulting in burst errors. So, time and frequency interleaving are employed to distribute these errors in time and frequency. DFis the duration of a deep fade region (DFR) in frequency while DTis the duration in time. SFis the separation of two DFR regions in frequency. The DFdepends on delay spread or cell-size. If cell size is high DFwill be lesser but there could be more deep fade regions close to each other. DTdepends on the speed of the mobile and is inversely proportional to speed. For Speed =0., DTcan tend to infinity, so a maximum value of DTcan correspond to speeds of 3-4 km / hr. Working with maximum values of DTand DFwill help design the interleavers and associated minimum span.

[0101] According to an existing mechanism, there are two types of frequency interleavers, the ICBI and TSBI, as given in H. Ju, Y. Xu, D. He and W. Zhang, "A Frequency Interleaver Scheme with Cyclic Shift for LTE-based 5G Terrestrial Broadcasting,"　2021 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB), Chengdu, China, 2021 . A general frequency interleaver has the following steps: 1) Write data into a row-column interleaver column-wise, 2) Optionally permute the different rows (like in TSBI), 3) Read out the data row wise.

[0102] The Interleaver is characterized by a minimum span, which is the separation of data before and after permutation by the interleaver. In case of the ICBI, for the minimum span is N+1. For a M x N interleaver where M is the number of rows of the row-column interleaver and N is the number of columns of the row-column interleaver. For TSBI, choose a k for a given N and M, such that minimum span is maximized. Consider M x N interleaver for ICBI, If minimum span (S) is N+1, and for example considering one region of deep fade and minim span, if DFis K times S then there will be K consecutive symbols with a burst error after deinterleaving, for every M values. If S is greater than DFthere are no consecutive burst errors. Hence, design the interleaver with minimum span S > DF(or) S being dependent on DF.

[0103] Fig. 6 is a schematic diagram that illustrates a schematic of a network apparatus (600) implemented to carry out the disclosed subject matter according to an embodiment as disclosed herein. The network apparatus (600) may be implemented as, or form part of, a radio access network (RAN) node and / or a core network node. By way of example, the network apparatus (600) may include a base station (such as a macro cell, small cell, femtocell, or picocell), a gNB / eNB component (including a distributed unit (DU) and / or a centralized unit (CU)), an access and mobility management function (AMF), a user plane function (UPF), or other network entity included in providing connectivity and signaling for user equipment. The network apparatus (600) may further include, or be coupled to, antennas and radio-frequency (RF) units (including MIMO and beamforming circuitry), edge computing nodes (such as MEC servers), backhaul and transport equipment, network management systems, and security elements. These examples are illustrative and do not limit the scope of the network apparatus (600).

[0104] As shown in Fig. 6, the network apparatus (600) includes a processor (602), a memory (604), an input / output (I / O) interface (606), and a modulation interleaving controller (608). The modulation interleaving controller (608) is operatively coupled to the processor (602) and the memory (604). The components are described below.

[0105] The processor (602) is operatively coupled to the memory (604), the I / O interface (606), and the modulation interleaving controller (608). The processor (602) is configured to execute instructions stored in the memory (604) to perform one or more operations of the network apparatus (600). In various implementations, the processor (602) includes one or more processing units, such as a central processing unit (CPU), an application processor (AP), a general-purpose processing unit, or other processing circuitry available within the network apparatus architecture. The specific processor type may vary based on whether the network apparatus (600) is implemented as a RAN node, a core network node, or a computing platform executing one or more network functions.

[0106] The memory (604) stores information used for operation of the network apparatus (600). In an implementations, the memory (604) stores the transport block, modulation symbols, a plurality of sets, a plurality of interleaved modulation symbols, and the like. The memory (604) may include volatile memory and non-volatile memory, and may be implemented using one or more computer-readable storage media, including flash memory, EEPROM, EPROM, and other suitable storage technologies. In an implementations, the memory (604) may include error detection and / or correction features.

[0107] The memory 604 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 604 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof. The memory 604 may be electrically, operatively, or communicatively coupled to the processor 602 and may be accessed by the processor 602. The memory 604 may store a computer program, codes, or instructions executable by the processor 602. According to an embodiment, a computer program, codes, or instructions executable by the processor 602 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 604, the processor 602 may perform various functions according to an embodiment of the disclosure. According to an embodiment of the disclosure, operations of the network apparatus 600 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 604 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0108] The processor 602 may control general operations of the network apparatus 600 according to embodiments of the disclosure. The processor 602 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processings. The processor 602 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 604, individually, collectively or in any combination thereof. Further, the processor 602 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme. Further, it should be noted that, according to another embodiment, in a case where NF is implemented in the form of an instance, the network function may be not necessarily configured by physical hardware. According to an embodiment, the processor 602 may be electrically, operatively, or communicatively coupled to the network interface to control the network interface. The processor 602 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. In a specific embodiment, at least a part of the processor 602 may be included in one chip and the other part of the processor 602 may be included in another chip. Otherwise, at least one processor may be included in another component, for example, the network interface or the memory 604. The processor 602 may perform or control or cause an operation of the network apparatus 600 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 602 may control operations of the network apparatus 600 for exchanging a control plane message or a user plane message with a UE, a BS, or other core network entities through wireless or wired communication, using various protocols (e.g., NAS protocol). To this end, the processor 602 may execute a computer program, codes, or instructions stored in the memory 604, so as to control other components of the network apparatus 600 to enable execution of various operations.

[0109] The I / O interface (606) provides communication between internal components of the network apparatus (600) and one or more external devices and / or network elements. The I / O interface (606) may include one or more buses, ports, fronthaul / backhaul interfaces, and / or interface circuitry for data transfer. The modulation interleaving controller (608) is operatively coupled to the I / O interface (606) and the memory (604). This arrangement enables the modulation interleaving controller (608) for performing data transmission by a base station using a frequency interleaver in a wireless communication system.

[0110] In an embodiment, the modulation interleaving controller (608) may be a hardware element implemented as dedicated electronic circuitry within the network apparatus (600). In an implementations, the modulation interleaving controller (608) is realized as an integrated circuit (IC), an application-specific integrated circuit (ASIC), a system-on-chip (SoC) hardware block, or a field-programmable gate array (FPGA) configuration. The modulation interleaving controller (608) may include dedicated hardware logic configured to perform data transmission by a base station using a frequency interleaver in a wireless communication system as described herein.The modulation interleaving controller (608) receives a transport block for baseband processing. The transport block is split into a plurality of code blocks. Each code block of the plurality of code blocks undergoes CRC addition, channel coding, rate matching and code block concatenation to generate a plurality of code words. Further, the modulation interleaving controller (608) processes each code word of the plurality of code words by scrambling and modulation mapping to generate modulation symbols, an optional layer mapping and precoder, frequency interleaver, a block permute and block shift processing, a resource element mapper and an OFDM signal generator. Further, the modulation interleaving controller (608) divides the modulation symbols into a plurality of sets. Each set of the plurality of sets include the modulation symbols to be mapped to orthogonal frequency division multiplexing (OFDM) symbols. Each set of the plurality of sets is further processed using the frequency interleaver, a block permute and block shift, a resource element mapper, and an OFDM signal generation associated with an OFDM symbol associated with the plurality of sets. Further, the modulation interleaving controller (608) interleaves each set of the plurality of sets to be mapped to an OFDM symbol, using the frequency interleaver to obtain a plurality of interleaved modulation symbols. Further, the modulation interleaving controller (608) transmits the plurality of interleaved modulation symbols via a physical multicast channel (PMCH).

[0111] In an embodiment, the modulation interleaving controller (608) may be implemented as software executed by the processor (602) and rely on execution of program instructions by the processor (602). The modulation interleaving controller (608) may be configured, via execution of the program instructions, to perform data transmission by a base station using a frequency interleaver in a wireless communication system as described herein.

[0112] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to receive one or more transport blocks (TBs). In an embodiment, the insttruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to generate a plurality of codewords corresponding to the one or more TBs. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to apply a cyclic shift to the plurality of codewords using an offset. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to perform frequency-domain interleaving on modulation symbols obtained from the cyclic shifted plurality of codewords. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to transmit a plurality of interleaved modulation symbols via a physical multicast channel (PMCH).

[0113] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to set a number of columns (K) of a frequency interleaver and set a number of rows (R) of the frequency interleaver. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to write the modulation symbols into the frequency interleaver column-wise, in increasing index of the modulation symbols, starting with row '0' and column '0', and in increasing order of first a row number and then a column number. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to read the interleaved modulation symbols of the frequency interleaver row-wise from the frequency interleaver, in an increasing order of index of the interleaved modulation symbols, and in an increasing order of first the column number and then the row number.

[0114] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to append one or more <NULL> elements to a frequency interleaver when a number of the modulation symbols is smaller than a size of the block interleaver. In an embodiment, the insttruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to discard the <NULL> elements.

[0115] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to read the interleaved modulation symbols row-wise from the frequency interleaver starting with column 'A' and row 'B'. In an embodiment, the A is determined as a floor of a ratio of the offset to R, and the B is determined as the offset modulo R.

[0116] In an embodiment, the offset is determined as a function of: a deep fade duration (DF), the number of columns of the frequency interleaver, and a minimum span of the frequency interleaver.

[0117] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to determine whether a last element of the frequency interleaver, corresponding to Row R-1 and Column K-1, is reached upon reading each interleaved modulation symbol of the plurality of modulation symbols. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to continue reading from row '0' and column '0' of the frequency interleaver in an increasing order of the column number and then the row number until an element with column 'A' and row 'B' of the frequency interleaver is reached.

[0118] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to divide the modulation symbols into a plurality of sets, wherein each set of the plurality of sets include the modulation symbols to be mapped to an orthogonal frequency division multiplexing (OFDM) symbol. In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to perform the frequency-domain interleaving for each set of the plurality of sets.

[0119] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to: to perform the frequency-domain interleaving, process the modulation symbols by a block processing and block shifting (BPBS) operation. In an embodiment, the BPBS operation processes the modulation symbols as R segments, each segment including K modulation symbols. In an embodiment, the BPBS operation comprises: a right shift operation, a first block shift (BS1) operation, a block permutation (BP) operation, and a second block shift (BS2) operation. In an embodiment, an output of the BPBS operation is provided to a resource element mapping operation and an orthogonal frequency division multiplexing (OFDM) signal generation operation for mapping to an OFDM symbol.

[0120] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to: for the right shift operation, cyclically right-shift the modulation symbols by a c1 elements, wherein the c1 is equal to A, and wherein the A is determined as a floor of a ratio of the offset to R.

[0121] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to: for the BS1 operation, obtain R shift values, wherein an i-th shift value of the R shift values is denoted by ti; and cyclically right-shift an i-th input segment by timodulation symbols to generate an i-th output segment.

[0122] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to: for the BP operation, permute R segments output from the BS1 operation, wherein an i-th output segment of the BP operation corresponds to a qi-th input segment of the BP operation, and wherein qiis determined during the BP operation.

[0123] In an embodiment, the instruction stored in the memory (604) executable by the at least one processor (602) individually or in any combination to cause the BS (600) to: for the BS2 operation, right-shift an i-th segment of R segments output from the BP operation by a value Sito generate an i-th output segment of the BS2 operation, wherein the Siis calculated during the BS2 operation; and discard all <NULL> elements from an output of the BS2 operation prior to resource element mapping.

[0124] Fig. 7 is a schematic diagram (700) that illustrates a frequency interleaver that uses the row-column interleaver used in the process of data transmission, according to an embodiment as disclosed herein. The frequency interleaver basically is a row-column interleaver where the modulated symbols to be written to RE is written column-wise and then read out row-wise. The output is then mapped to REs as per existing rules.

[0125] Fig. 8 is a schematic diagram (800) that illustrates the occurrence of deep fade errors in the modulated symbols off the time-frequency RE grid, according to an embodiment as disclosed herein. The output of code block concatenation, after modulation and other processing, is mapped to all RE in the first OFDM symbol and then to all RE in the second OFDM symbol and so on. If the modulated symbols off the time-frequency RE grid is observed, it looks likes the illustrated Fig. 8. Burst of DFerrors separated by SFsymbols.

[0126] Fig. 9 is a schematic diagram (900) that illustrates the effect of frequency interleaver at the transmitter and the deinterleaver at the receiver, according to an embodiment as disclosed herein.

[0127] In an embodiment, a M x N row-column interleaver is assumed as the frequency interleaver. At reference numeral 902, the modulated symbols of a subframe at the receiver after deinterleaving is illustrated. At reference numeral 904, the modulated symbols of a subframe at the receiver after channel is illustrated.

[0128] Fig. 10 is a schematic diagram (1000) that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=2N and the deep fades correspond to same OFDM symbol, according to an embodiment as disclosed herein.

[0129] In an embodiment, without loss of generality, let DF= KN, where K is an integer. This means that at the receiver, after deinterleaving channel errors due to deep fades of a DFR in the same OFDM symbol manifest as a burst of K (= 2 in the figure) continuous errors repeated every M modulated symbols and this happens DTtimes.

[0130] Fig. 11 is a schematic diagram (1100) that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=N and the deep fades correspond to two adjacent OFDM symbols, according to an embodiment as disclosed herein.

[0131] In an embodiment, without loss of generality, let NOFDM= AN, whereAis an integer. Two adjacent deep fades belonging to adjacent OFDM symbols on the same subcarrier manifestAmodulation symbols apart at the receiver after the deinterleaver.

[0132] Fig. 12 is a schematic diagram (1200) that illustrates the distribution of deep fade channel errors of Modulated symbols of a subframe at the receiver after deinterleaving which corresponds to DF=N and the deep fades correspond to same OFDM symbols but adjacent DFR, according to an embodiment as disclosed herein.

[0133] In an embodiment, without loss of generality, let SF= BN, where B is an integer. Two adjacent deep fades belonging to adjacent DFRs in the same OFDM symbol manifest B modulation symbols apart at the receiver after the deinterleaver.

[0134] Fig. 13A is a schematic diagram (1300A) that illustrates depicts a scenario where the LLRs from two different instances (RVs or redundancy versions) of the same transmission blocks, TB LLRs and TB LLRs, are combined without offset, in the context of chase combining (in one embodiment), according to an embodiment as disclosed herein.

[0135] Fig. 13A is a schematic diagram (1300A) showing two vertical bars representing the LLRs for two different instances (RVs) of the same TB (transport block) instances. Each bar is divided into segments, with certain segments shaded to indicate areas affected by the deep fades or burst errors. The combination process is represented by a plus sign between the two bars and an equal sign leading to a third bar. The third bar represents the combined LLRs, where the shaded segments from both instances of the same TB are aggregated. This combined bar shows the cumulative effect of the errors from both RVs of same transmission blocks . The LLRs of REs in both instances are affected by deep fades in the same location, so combining does not give benefits.

[0136] Fig. 13B depicts a scenario where the LLRs from two different instances (RV) of the same transmission blocks, TB LLRs and TB LLRs, are combined with offset, in the context of chase combining(in one embodiment or example), according to an embodiment as disclosed herein.

[0137] In an embodiment, the retransmitted RV of the TB is given a cyclic shift offset at the transmitter so deep fade locations of affected Res occur in different positions, there by combining has at least one clean LLR. Similar to Fig. 13A, the figure shows two vertical bars representing the LLRs for two different instances (RVs) of same TB. However, in this case, the bar for one instance of TB LLRs is vertically offset relative to the bar for another instance of TB LLRs as illustrated. This offset is indicated by an arrow labeled "offset." The combination process is again represented by a plus sign between the two bars and an equal sign leading to a third bar. The third bar represents the combined LLRs with the offset taken into account. The combined bar shows the regions labeled with reference numeral 1302 which are unaffected by deep fades, as there is at least one clean LLR unaffected by deep fades is used in combining. This is ensured due to the cyclic shift offset at the transmitter.

[0138] In an embodiment, the TB can be frequency interleaved or not. It is to be noted that unlike a time-interleaver, where these TBs fill a row-column interleaver column wise and then output row-wise, this method has no memory requirements like a row-column interleaver.

[0139] Fig. 14 is a schematic diagram (1400) that illustrates the proposed Offset-frequency interleaver with offset of 5, according to an embodiment as disclosed herein. The offset value may be denoted as O, and the example illustrated in Fig. 14 corresponds to a case where O = 5. The offset value of 5 is merely an exemplary value and the offset value is not limited to 5 and may be variously configured.

[0140] In an embodiment, for a M x N row-column interleaver, if the offset is O, the first value output is at (O%M, floor(O / M)), where (i,j) denotes the element in the i-th row and j-th column. All row and column indices start from 0. Here % denotes modulo operation. The offset determines the starting position to be read from the row-column interleaver and is a function of DFand N (of the M x N row-column interleaver), minimum span of the interleaver. After reading the last element (M-1, N-1) from the row-column interleaver reading resumes at (0,0) until all unread elements are read. M can be represented by R and N, by K.

[0141] Fig. 15 is a schematic diagram (1500) that illustrates how different RVs are formed for retransmission and read from a circular buffer, according to an embodiment as disclosed herein.

[0142] In an embodiment, the figure depicts how different RVs (redundancy versions), in the context of incremental redundancy (IR) are formed for retransmission and read from a circular buffer.

[0143] Fig. 16 is a schematic diagram (1600) that illustrates modulated symbols per subframe of two RVs of a same TB, RV1 and RV3, in the context of incremental redundancy (IR) according to an embodiment as disclosed herein.

[0144] In an embodiment, the modulated symbols per subframe of two RVs, RV1 and RV3. RV3 has a rate matching offset RMO w.r.t RV1 in the circular buffer. The burst errors are of length X and occur every Y modulated symbols. X and Y depend on frequency interleaver parameters M, N, DF, NOFDM, and SF. Where they overlap, they are soft combined, so there is a need to design RMO so that the deep fade errors do not overlap. The modulated symbols in the subframe of a RV are optionally frequency interleaved and the frequency interleaved subframe can have a cyclic offset O. Each RV of a transport block is cyclically shifted before transmission and after it is read from circular buffer, denoted by O, which is unique for that RV. It is to be noted that as per the embodiments disclosed before Y can be A, B or K.

[0145] In an embodiment, assume O is zero, for deep fade errors to overlap in both subframes it is required to have RMO+W+X+k'Y = W+X+K''Y where K' and K'' are integers, which means RMO should be a multiple of Y. So possible values for deep fade errors not to overlap is RMO = K'''Y + / - X where K''' is an integer.

[0146] In an embodiment, if RMO is fixed, O is designed such that the deep fade errors do not overlap. For deep fade errors to overlap RMO+W+X+k'Y= O+W+X+K''Y. RMO-O should be a multiple of Y for overlap. RMO-O+ / - X should be a multiple of Y for no overlap. RMO+W+X+k'Y =O+W+X+K''Y. One could also have RMO-O + / - Y / 2 to be a multiple of Y to avoid overlap. In general, the modulated symbols of a transport blocks' s RVs in IR scheme that are transmitted (whether they are frequency interleaved or not) should have a cyclic shift offset, which is unique to that RV.

[0147] Fig. 17 is a schematic diagram (1700) that illustrates the transmission and reception of Multiple Transport Blocks and Multiple RVs of a transport block, according to an embodiment as disclosed herein. In the Fig. 17, two methods for managing resources in the wireless communication network system are depicted as Method 1 and Method 2. In each method, M transport blocks, each with n RVs, are sent over the air.

[0148] In the Method 1, first send RV0 of all transport blocks, then RV1 of all transport blocks, and so non and so forth.

[0149] In the Method 2, first send all RVs of transport block1, followed by RVs of transport block 2, so on and so forth.

[0150] Further, the below Table 1 illustrates the comparison of the method 1 and the method 2. Let DTbe the duration of a deep fade for a given speed in terms of number of subframes, T the length of

[0151] time-interleaver across T subframes and N the number of transport blocks. Generally, T > DTto get time interleaver benefits, V be the number of RVs.

[0152]

[0153] Table 1

[0154] In an embodiment, many input streams (say, N) are concatenated together, fill-up a row-column interleaver column-wise, then optionally the rows are permuted, optionally each permuted row is cyclically shifted or each permuted row is permuted as per a rule, and then data is read row-wise, optionally an cyclic offset can be added before reading row-wise (the first element to be read is in the ith row and jth column) and filling up N output streams. Each input and output stream has the same number of elements.

[0155] In an embodiment, the following for time interleavers is proposed in this solution.

[0156] 1) Each input stream is the set of modulated symbols of an OFDM symbol and many such streams are concatenated. All input streams can pertain to a subframes of same or different transport blocks. The input stream can be frequency interleaved or not.

[0157] 2) Each input stream is a subframe of modulated symbols of a particular TB and a particular RV of that TB. Many such input streams are concatenated. One can have all RVs of a particular TB as input streams or a mix of various TBs and their RVs as input streams. The input stream can be frequency interleaved or not.

[0158] Fig. 18 is a schematic diagram (1800) that illustrates the decimated Time-frequency interleaver, according to an embodiment as disclosed herein.

[0159] In an embodiment, the illustrated Fig. 18 includes a M x N row-column time-frequency interleaver. M is a number of modulated symbols / REs in an OFDM symbol and N is one or more contiguous OFDM symbols / subframes of the same or different transport blocks. Consider a subblock of size m x n, such that M=k1m, N=k2n and k1, k2being integers (without loss of generality). The row-column interleaver is filled column-wise. Then to read, (0,0) elements from all subblocks is read, then (0,1) element from all subblocks and so on until the (0, n-1) elements of all subblocks is read. Then (1,0) elements of all subblocks (next row in the subblock) are read and so on. This way while reading n positions in time and m positions in frequency is skipped. The continuous burst errors are distributed across many subblocks now at the receiver after deinterleaving. The values ofm around DF and n around DTis recommended in one embodiment. Note that the minimum span is k1k2n+1.

[0160] Fig. 19 is a schematic diagram (1900) that illustrates the decimated Time-frequency interleaver (with TSBI), according to an embodiment as disclosed herein. In an embodiment, the illustrated Fig.19 includes a M x N row-column time-frequency interleaver. M is a number of modulated symbols / REs in an OFDM symbol and N is one or more contiguous OFDM symbols / subframes of the same or different transport blocks. Consider a subblock of size m x n, such that M=k1m, N=k2n and k1, k2being integers (without loss of generality). The row-column interleaver is filled column-wise. Then to read, (0,0) elements from all subblocks is read, then (0,1) elements from all subblocks and so on until the (0, n-1) elements of all subblocks is read. Then (g,0) elements of all subblocks are read where g < m, g>1 as in TSBI, followed by (g,1) elements of all subblocks and so on.

[0161] Fig. 20 is a schematic diagram (2000) that illustrates the Diagonal Time-frequency interleaver, according to an embodiment as disclosed herein. The illustrated FIG.19 includes a M x N row-column time-frequency interleaver. M is the no. of modulated symbols / REs in an OFDM symbol and N is one or more contiguous OFDM symbols / subframes of the same or different transport blocks. The input is written column-wise into a row-column interleaver and outputs are read diagonal-wise. If (i, j) denotes the position in ithrow and jthcolumn (all indices start from 0), each diagonal has a constant value for i-j. Firstly, a diagonal for the lowest i-j is taken, read out all elements, permute them optionally as per some rule and then output them. Further, the next diagonal is read with the next lowest value of (i-j), read all the elements, optionally permute them as per a rule, and output them. This process is continued until the diagonal with maximum value of (i-j) is processed.

[0162] In an embodiment, a Forney convolutional Time interleaver can also be used. This is given in "Physical layer time interleaving for the ATSC 3.0 system", IEEE Trans. On Broadcasting, vol. 62, no. 1, March 2016 and G Forney, "Burst correcting codes for the classic bursty channel," IEEE Trans. Comm. Technology., vol. 19, no. 5, Oct. 1971.

[0163] Fig. 21 is a schematic diagram (2100) illustrating a decimated frequency interleaver according to embodiments disclosed herein. This interleaver is structured as an M x N row-column frequency interleaver. The input consists of a set of modulated symbols that are to be mapped across a subframe of OFDM symbols.

[0164] Consider a subblock of size m x n such that M = k1m and N = k2n, with k1 and k2 being integers (without loss of generality). The row-column interleaver is filled column-wise. To read from the interleaver, (0,0) elements from all subblocks are read first, followed by (0,1) elements from all subblocks, and so on, until the (0,n-1) elements of all subblocks are read. Subsequently, (1,0) elements of all subblocks (next row in the subblock) are read, and this process continues accordingly.

[0165] It is important to note that the minimum span is k1k2n + 1. A special case where n = 1 (where the subblock is a vector and not a matrix) is supported. If the input is insufficient to fill the row-column interleaver, nulls are used, which are then discarded while reading from the row-column interleaver.

[0166] Fig. 22 is a schematic diagram (2200) illustrating a decimated frequency interleaver with Time-Space Block Interleaving (TSBI) according to embodiments disclosed herein. This interleaver is an M x N row-column frequency interleaver. The input consists of a set of modulated symbols that are to be mapped across a subframe of OFDM symbols.

[0167] Consider a subblock of size m x n such that M = k1m and N = k2n, with k1 and k2 being integers (without loss of generality). The row-column interleaver is filled column-wise. Reading is performed by first reading (0,0) elements from all subblocks, then (0,1) elements from all subblocks, and so on until the (0,n-1) elements of all subblocks are read. Subsequently, (g,0) elements of all subblocks are read where g < m and g > 1, as in TSBI, followed by (g,1) elements of all subblocks, and so on.

[0168] A special case where n=1 (the subblock is a vector and not a matrix) is supported. If the input is insufficient to fill the row-column interleaver, nulls are used, which are then discarded while reading from the row-column interleaver.

[0169] Fig. 23 is a schematic diagram (2300) illustrating a frequency interleaver according to embodiments disclosed herein. The input comprises a set of modulated symbols that are to be mapped across a subframe of OFDM symbols. The frequency interleaver performs the following steps:

[0170] Nulls are appended if the number of modulated symbols cannot completely fit the row-column interleaver. The modulated symbols are written column-wise. Intermediate operations, referred to as row or column operations, are then performed. The output is read row-wise while ignoring the nulls.

[0171] A frequency interleaver can include one or more of the following steps (row operations): the rows are permuted according to a specific rule, and the elements of each row are shifted or permuted according to another rule. Similar operations can be performed for columns, known as column operations, where columns are permuted and elements of each column can be shifted. One or both of the column operations can be included.

[0172] Row operations can be followed by column operations, or column operations can be followed by row operations. Alternatively, only row operations or only column operations can be performed as part of the intermediate operations.

[0173] Fig. 24 is a schematic diagram (2400) that illustrates a proposed offset frequency interleaver according to an embodiment as disclosed herein.

[0174] In an embodiment, the The number of rows, R and number of columns K, of the O-FIL are determined in the same way as Sec. 6.5.2 in 36.211 v19.1.0, corresponding to the frequency interleaver. Write the input stream of modulation symbols in th set (to be mapped to the th OFDM symbol) column-wise into row-column interleaver of O-FIL in increasing order of , starting with column 0 and row 0 and in increasing order of first the row number and then the column number. If the number of inputs is not enough to fill the row-column interleaver of, append <NULL> elements to fill the remaining elements of the row-column interleaver. The output of the O-FIL is read our row-wise, in increasing order of the output index, starting with column and row and in increasing order of first the column number and then the row number. The O-FIL output is read from location ( , ) of the row-column interleaver where it corresponds to a delay or offset associated with the th set input to O-FIL. In an embodiment where OFDM symbol only is mapped to entire codeword, corresponds to the delay introduced by the cyclic shift block in the upper Tx chain of 36.211.

[0175] The proposed Tx chain using the offset-based frequency interleaver (O-FIL) is shown in the bottom Tx chain of the figure 24. The upper Tx chain is as per 36.211. The proposed Tx chain has no cyclic shift of 36.211 as it is absorbed in the O-FIL. Recall that O-FIL reads out from an offset that is equivalent to the cyclic shift offset introduced in the upper Tx chain.

[0176] The proposed Tx chain at the bottom, we have a new block, called as block permute and block shift (BPBS) , which will be discussed later. The input to the O-FIL is broken into L sets such that and th set is mapped to the th OFDM symbol. We assume that the entire codeword is mapped to L OFDM symbols.

[0177] As per 36.211 the th set is processed by O-FIL, block permute and block shift (BPBS) before the resource mapper maps it to resource elements of the th OFDM symbol as per 36.211 and the OFDM signal generation block Tx signal as per 36.211 block.

[0178] Fig. 25 is a schematic diagram (2500) that illustrates a block permute and block shift according to an embodiment as disclosed herein. The output of O-FIL is fed to BPBS. This consists of blocks of elements each. An element is a modulation symbol. The BPBS consists of:

[0179] - A right shifter that right-shifts the input by a fixed amount. In an embodiment it is .

[0180] - A block shift 1 (BS1). Here we have shift values for each of the blocks. Each of blocks is right shifted by a specific value to give the corresponding block of output.

[0181] - A block permutation. The order of the blocks is permuted among themselves and they are output.

[0182] - A block shift 2 (BS2). Here we have shift values for each of the blocks. Each of the blocks is right shifted by a specific value to give the corresponding output block. After this NULL values are discarded at the output.

[0183] All indices start from zero. where is the floor operation. All mention of input blocks / segments is of R blocks / segments of elements or modulation symbols.

[0184] The right shifter uses a right shift value of .

[0185] Let be the right shift value associated with the th block of BS1. is calculated as follows.

[0186]

[0187] Now cyclically right shift by to get the updated value of .

[0188] In the block permutation step, these input blocks are permuted among themselves as per a rule. This permutation to occur, only if . Construct a vector, whose th element is which is computed as

[0189]

[0190] Construct a vector, whose th element is which is computed as . The th block at the input is repositioned or permuted to be the th block of the output of block permutation step. .

[0191] For BS2, the right shift value corresponding to the th block is denoted by , where the offset

[0192]

[0193] At the output of BS2 / BPBS the <NULL> elements are deleted and the stream of modulation symbols for the th OFDM symbol passes to the resource element mapper.

[0194] Fig. 26 is a flow diagram that illustrates a method for performing data transmission by a base station using a frequency interleaver in a wireless communication system according to an embodiment as disclosed herein. The method includes steps (2602-2610). Each step is explained in further detail below.

[0195] At step (2602), the method includes receiving by the network apparatus (600) from higher layers, one or more transport blocks for baseband processing. The transport block is split into a plurality of code blocks. Each code block of the plurality of code blocks undergoes cyclic redundancy check (CRC) addition, channel coding, rate matching and code block concatenation to generate a code word.

[0196] At step (2604), the method includes processing by the network apparatus (600) the code word by scrambling and modulation mapping to generate modulation symbols, an optional layer mapping and precoder, frequency interleaver, a block permute and block shift (BPBS), a resource element mapper and an OFDM signal generator.

[0197] At step (2606), the method includes dividing by the network apparatus (600) the modulation symbols into a plurality of sets. Each set of the plurality of sets include the modulation symbols to be mapped to orthogonal frequency division multiplexing (OFDM) symbols. Each set is further processed using the frequency interleaver, the BPBS, a resource element mapper, and an OFDM signal generation associated with an OFDM symbol associated with the plurality of sets.

[0198] At step (2608), the method includes interleaving by the network apparatus (600) each set to be mapped to an OFDM symbol, using the frequency interleaver to obtain a plurality of interleaved modulation symbols.

[0199] At step (2610), the method includes transmitting by the network apparatus (600), the interleaved modulation symbols via a PMCH.

[0200] In an embodiment, an output of the frequency interleaver is an input to the BPBS. An output of the block BPBS is passed to a resource element mapper and an OFDM signal generation unit, which maps the output to an OFDM symbol. The BPBS processes the input as R segments of K modulation symbols each, and comprises of a right shift block, a block shift 1 (BS1), a block permutation (BP), and a block shift2 (BS2).

[0201] In an embodiment, the right shifter block right shifts the input by 'c1' elements, and wherein 'c1' is equal to 'A'.

[0202] In an embodiment, R values are obtained, where an 'ith value of R values is denoted by ti, The input and output of the BS1 are R segments of K modulation symbols each. An 'ith' input segment of the BS1 is right-shifted by timodulation symbols. After the right shift of the input segment, it it output

[0203] In an embodiment, the output of the BS1 is input to the BP. TheTheinput is R segments of K modulation symbols and the output is a permuted version of input segments. An 'ith' output segment of K modulation symbols is a 'qith' input segment of K modulation symbols, wherein qiis obtained by the BP.

[0204] In an embodiment, the output of the BP is fed as input to the BS2. The BS2 treats the input and output as R segments of K modulation symbols each. The BS2 right-shifts an ith input segment by a value Si, where Siis calculated in the BS2.,and then outputs it as the ith output segment..all NULL elements are discarded from the output of the BS2 prior to resource element mapping.

[0205] In an example: [Table 2]

[0206]

[0207] Table 2

[0208] An input of 24 modulation symbols is considered with an offset of 10 introduced by cyclic shift block in upper Tx chain. The case of L=1 OFDM symbol is considered. For the lower Tx chain of Fig. 24, there is no offset as there is no cyclic shift block but the o-FIL does not read the output from (0,0) location. Rather it reads the output from (4,1) position corresponding to offset of 10. The various outputs are shown in the figure. It can be seen that both Tx chains have the same output.

[0209] In an example: [Table 3]

[0210]

[0211] Table 3

[0212] An input of 40 modulation symbols is considered with an offset of 16 introduced by cyclic shift block in upper Tx chain of Fig. 24. The frequency interleaver has 8 rows and 5 columns. We consider the case of L=1 OFDM symbol. For the lower Tx chain of Fig. 24, there is no offset as there is no cyclic shift block but the o-FIL does not read the output from (0,0) location. Rather it reads the output from (0,2) position corresponding to offset of 16. The various outputs are shown in Fig. 24. It can be seen that both Tx chains have the same output.

[0213] Fig. 27 illustrates a method 2700 performed by a base station according to various embodiments of the disclosure. In FIG. 27, descriptions of contents overlapping with Fig. 27 is omitted.

[0214] In step 2710, the base station receives one or more transport blocks (TBs).

[0215] In step 2720, the base station generates a plurality of codewords corresponding to the one or more TBs.

[0216] In step 2730, the base station applys a cyclic shift to the plurality of codewords using an offset.

[0217] In step 2740, the base station performs frequency-domain interleaving on modulation symbols obtained from the cyclic shifted plurality of codewords.

[0218] In an embodiment, the base station sets a number of columns (K) of a frequency interleaver and sets a number of rows (R) of the frequency interleaver. In an embodiment, the base station writes the modulation symbols into the frequency interleaver column-wise, in increasing index of the modulation symbols, starting with row '0' and column '0', and in increasing order of first a row number and then a column number. In an embodiment, the base station reads the interleaved modulation symbols row-wise from the frequency interleaver, in an increasing order of index of the interleaved modulation symbols, and in an increasing order of first the column number and then the row number.

[0219] In an embodiment, the base station appends one or more <NULL> elements to a frequency interleaver when a number of the modulation symbols is smaller than a size of the block interleaver. The base station discards the <NULL> elements.

[0220] In an embodiment, the base station reads the interleaved modulation symbols row-wise from the frequency interleaver starting with column 'A' and row 'B'. In an embodiment, the A is determined as a floor of a ratio of the offset to R, and the B is determined as the offset modulo R.

[0221] In an embodiment, the offset is determined as a function of: a deep fade duration (DF), the number of columns of the frequency interleaver, and a minimum span of the frequency interleaver.

[0222] In an embodiment, the base station determines whether a last element of the frequency interleaver, corresponding to Row R-1 and Column K-1, is reached upon reading each interleaved modulation symbol of the plurality of modulation symbols. In an embodiment, the base station continues reading from row '0' and column '0' of the frequency interleaver in an increasing order of the column number and then the row number until an element with column 'A' and row 'B' of the frequency interleaver is reached.

[0223] In an embodiment, the base station divides the modulation symbols into a plurality of sets, wherein each set of the plurality of sets include the modulation symbols to be mapped to an orthogonal frequency division multiplexing (OFDM) symbol. In an embodiment, the base station performs the frequency-domain interleaving for each set of the plurality of sets.

[0224] In an embodiment, the base station, to perform the frequency-domain interleaving, processes the modulation symbols by a block processing and block shifting (BPBS) operation. In an embodiment, the BPBS operation processes the modulation symbols as R segments, each segment including K modulation symbols. In an embodiment, the BPBS operation comprises: a right shift operation, a first block shift (BS1) operation, a block permutation (BP) operation, and a second block shift (BS2) operation. In an embodiment, an output of the BPBS operation is provided to a resource element mapping operation and an orthogonal frequency division multiplexing (OFDM) signal generation operation for mapping to an OFDM symbol.

[0225] In an embodiment, the base station, for the right shift operation, cyclically right-shifts the modulation symbols by a c1 elements, wherein the c1 is equal to A, and wherein the A is determined as a floor of a ratio of the offset to R.

[0226] In an embodiment, the base station, for the BS1 operation, obtains R shift values, wherein an i-th shift value of the R shift values is denoted by ti; and cyclically right-shift an i-th input segment by timodulation symbols to generate an i-th output segment.

[0227] In an embodiment, the base station, for the BP operation, permutes R segments output from the BS1 operation, wherein an i-th output segment of the BP operation corresponds to a qi-th input segment of the BP operation, and wherein qiis determined during the BP operation.

[0228] In an embodiment, the base station, for the BS2 operation, right-shifts an i-th segment of R segments output from the BP operation by a value Sito generate an i-th output segment of the BS2 operation, wherein the Siis calculated during the BS2 operation; and discards all <NULL> elements from an output of the BS2 operation prior to resource element mapping.

[0229] In step 2750, the base station transmits a plurality of interleaved modulation symbols via a physical multicast channel (PMCH).The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the scope of the embodiments as described herein.

[0230] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available media that can be accessed by a general purpose or special purpose computer. I n addition, computer-readable storage media may be provided in the form of non-transitory storage media. The 'non-transitory storage medium' is a tangible device and only means that it does not contain a signal (e.g., electromagnetic waves). This term does not distinguish a case in which data is stored semi-permanently in a storage medium from a case in which data is temporarily stored. For example, the non-transitory recording medium may include a buffer in which data is temporarily stored.

[0231] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Any of the above variation embodiments can be utilized independently or in combination with at least one other variation embodiment. The above flowchart(s) illustrate example methods that can be implemented in accordance with the principles of the present disclosure and various changes could be made to the methods illustrated in the flowcharts herein. For example, while shown as a series of steps, various steps in each figure could overlap, occur in parallel, occur in a different order, or occur multiple times. In another example, steps may be omitted or replaced by other steps.

[0232] Meanwhile, although specific embodiments of the present disclosure have been described in detail, various modifications may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the described embodiments, but should be defined by the claims and equivalents thereof.

Claims

1.A method performed by a base station (BS) in a wireless communication system, comprising:receiving one or more transport blocks (TBs);generating a plurality of codewords corresponding to the one or more TBs;applying a cyclic shift to the plurality of codewords using an offset;performing frequency-domain interleaving on modulation symbols obtained from the cyclic shifted plurality of codewords; andtransmitting a plurality of interleaved modulation symbols via a physical multicast channel (PMCH).2.The method of claim 1, wherein performing the frequency-domain interleaving comprises:setting a number of columns (K) of a frequency interleaver;setting a number of rows (R) of the frequency interleaver;writing the modulation symbols into the frequency interleaver column-wise, in increasing index of the modulation symbols, starting with row '0' and column '0', and in increasing order of first a row number and then a column number; andreading the interleaved modulation symbols row-wise from the frequency interleaver, in an increasing order of index of the interleaved modulation symbols, and in an increasing order of first the column number and then the row number.3.The method of claim 1, wherein performing the frequency-domain interleaving further comprises:appending one or more <NULL> elements to a frequency interleaver when a number of the modulation symbols is smaller than a size of a frequency interleaver; anddiscarding the <NULL> elements.4.The method of claim 2, wherein reading the interleaved modulation symbols row-wise from the frequency interleaver further comprises:reading the interleaved modulation symbols row-wise from the frequency interleaver starting with column 'A' and row 'B',wherein the A is determined as a floor of a ratio of the offset to R, andwherein the B is determined as the offset modulo R.5.The method of claim 4, wherein the offset is determined as a function of: a deep fade duration (DF), the number of columns of the frequency interleaver, and a minimum span of the frequency interleaver.6.The method of claim 4, wherein reading the interleaved modulation symbols row-wise from the frequency interleaver further comprises:determining whether a last element of the frequency interleaver, corresponding to Row R-1 and Column K-1, is reached upon reading each interleaved modulation symbol of the plurality of modulation symbols; andcontinuing reading from row '0' and column '0' of the frequency interleaver in an increasing order of the column number and then the row number until an element with column 'A' and row 'B' of the frequency interleaver is reached.7.The method of claim 1, further comprising:dividing the modulation symbols into a plurality of sets, wherein each set of the plurality of sets include the modulation symbols to be mapped to an orthogonal frequency division multiplexing (OFDM) symbol; andperforming the frequency-domain interleaving for each set of the plurality of sets.8.The method of claim 2, wherein performing the frequency-domain interleaving comprises:processing the modulation symbols by a block processing and block shifting (BPBS) operation,wherein the BPBS operation processes the modulation symbols as R segments, each segment including K modulation symbols, andwherein the the BPBS operation comprises: a right shift operation, a first block shift (BS1) operation, a block permutation (BP) operation, and a second block shift (BS2) operation, andwherein an output of the BPBS operation is provided to a resource element mapping operation and an orthogonal frequency division multiplexing (OFDM) signal generation operation for mapping to an OFDM symbol.9.The method of claim 8, wherein the right shift operation comprises:cyclically right-shifting the modulation symbols by a c1 elements, wherein the c1 is equal to A, and wherein the A is determined as a floor of a ratio of the offset to R.10.The method of claim 8, wherein the BS1 operation comprises:obtaining R shift values, wherein an i-th shift value of the R shift values is denoted by ti; andcyclically right-shifting an i-th input segment by timodulation symbols to generate an i-th output segment.11.The method of claim 8, wherein the BP operation comprises:permuting R segments output from the BS1 operation,wherein an i-th output segment of the BP operation corresponds to a qi-th input segment of the BP operation, andwherein qiis determined during the BP operation.12.The method of claim 8, wherein the BS2 operation comprises:right-shifting an i-th segment of R segments output from the BP operation by a value Sito generate an i-th output segment of the BS2 operation,wherein the Siis calculated during the BS2 operation; anddiscarding all <NULL> elements from an output of the BS2 operation prior to resource element mapping.13.A base station (BS) in a wireless communication system, comprising:at least one transceiver;at least one processor communicatively coupled to the at least one transceiver; andat least one memory, communicatively coupled to the at least one processor, storing instructions executable by the at least one processor individually or in any combination to cause the BS to:receive one or more transport blocks (TBs);generate a plurality of codewords corresponding to the one or more TBs;apply a cyclic shift to the plurality of codewords using an offset;perform frequency-domain interleaving on modulation symbols obtained from the cyclic shifted plurality of codewords; andtransmit a plurality of interleaved modulation symbols via a physical multicast channel (PMCH).14.The BS of claim 13, wherein, to perform the frequency-domain interleaving, the instructions further executable by the at least one processor individually or in any combination to cause the BS to:set a number of columns (K) of a frequency interleaver;set a number of rows (R) of the frequency interleaver;write the modulation symbols into the frequency interleaver column-wise, in increasing index of the modulation symbols, starting with row '0' and column '0', and in increasing order of first a row number and then a column number; andread the interleaved modulation symbols row-wise from the frequency interleaver, in an increasing order of index of the interleaved modulation symbols, and in an increasing order of first the column number and then the row number.15.The BS of claim 13, wherein to perform the frequency-domain interleaving, the instructions further executable by the at least one processor individually or in any combination to cause the BS to:append one or more <NULL> elements to a frequency interleaver when a number of the modulation symbols is smaller than a size of a frequency interleaver; anddiscard the <NULL> elements.

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