Embedded noise management device for managing noise caused by radiated electromagnetic waves, electronic system including same, and noise management system using embedded noise management device

Abstract

Embodiments of the present disclosure provide an embedded noise management device for managing noise caused by radiated electromagnetic waves. The embedded noise management device comprises: a noise sampling circuit configured to detect and sample a noise signal corresponding to the radiated electromagnetic waves in real time, convert the sampled noise signal into digital data, and then sequentially store the digital data through a data shift operation; an event detection circuit configured to determine an event when a noise signal exceeding a threshold value is detected, and stop the data shift operation of the noise sampling circuit; and a noise waveform restoration circuit configured to sequentially read the digital data corresponding to time before and after occurrence of the event, the digital data being stored in the noise sampling circuit, so as to generate restoration data for restoring the digital data into an analog noise waveform.

Description

An embedded noise management device for managing noise caused by radiated electromagnetic waves, an electronic system including the same, and a noise management system using the embedded noise management device

[0001] The embodiments of the present disclosure relate to an embedded noise management device for managing noise caused by radiated electromagnetic waves, an electronic system including the same, and a noise management system using the embedded noise management device.

[0002] Radiated electromagnetic waves, such as those caused by electrostatic discharge (ESD) or high-power electromagnetic waves (HPEM), can cause malfunctions in electronic systems. However, due to issues such as common mode (CM) noise, direct radiation coupling, or the inaccessibility of external equipment, it is difficult to accurately measure noise waveforms induced within electronic systems. Furthermore, since radiated electromagnetic waves propagate through space in the form of electromagnetic waves, there is a problem in designing compensation because their phase, direction, and path are intricately intertwined in the high-frequency band.

[0003] To address these issues, active research is being conducted on electronic system-embedded noise management devices capable of accurate noise measurement and recording without external interference, and effectively compensating for radiated electromagnetic waves.

[0004] Embodiments according to one aspect of the present disclosure provide an embedded noise management device for accurately measuring and recording noise waveforms induced inside an electronic system by electromagnetic waves.

[0005] Embodiments according to another aspect of the present disclosure provide an embedded noise management device for effectively compensating for radiated electromagnetic waves.

[0006] Embodiments according to other aspects of the present disclosure provide an electronic system including the aforementioned built-in noise management device.

[0007] Embodiments according to another aspect of the present disclosure provide a noise management system capable of monitoring at least one built-in noise management device.

[0008] The problems that the present disclosure aims to solve are not limited to those mentioned above, and other problems and advantages of the present disclosure not mentioned can be understood from the following description and will be more clearly understood by the embodiments of the present disclosure. Furthermore, it will be seen that the problems and advantages that the present disclosure aims to solve can be realized by the means and combinations thereof set forth in the claims.

[0009] According to one embodiment of the present disclosure, an embedded noise management device is provided for managing noise induced in the electronic system by radiated electromagnetic waves generated by an electrical stress event, wherein the embedded noise management device comprises: a noise sampling circuit that detects and samples a noise signal corresponding to the radiated electromagnetic waves in real time, converts it into digital data, and then sequentially stores the digital data through a data shift operation; an event detection circuit that determines an event when a noise signal exceeding a threshold is detected and performs the data shift operation of the noise sampling circuit; and a noise waveform restoration circuit that sequentially reads the digital data before and after the occurrence of the event stored in the noise sampling circuit and generates restoration data for restoring it into an analog noise waveform.

[0010] Here, the built-in noise management device is mounted on a printed circuit board on which at least one computer chip controlling the electronic system is mounted.

[0011] Here, the built-in noise management device receives the radiated electromagnetic waves through the printed circuit board.

[0012] Here, the built-in noise management device is electrically connected to the computer chip and manages the noise signal induced in the computer chip in response to the radiated electromagnetic waves.

[0013] Here, the built-in noise management device receives the radiated electromagnetic waves through a frame that fixes or supports the internal components of the electronic system.

[0014] Here, the device further includes an antenna electrically connected to the built-in noise management device and receiving the radiated electromagnetic waves.

[0015] Here, the noise sampling circuit includes a sensing input that detects the noise signal corresponding to the radiated electromagnetic wave in real time, an input buffer circuit that attenuates the detected noise signal, an analog-to-digital conversion circuit that samples the attenuated noise signal in real time and converts it into digital data, and a shift register that sequentially stores the converted digital data through a data shift operation.

[0016] Here, the event detection circuit includes an event detector that determines the event based on whether a noise signal detected in real time at the sensing input has exceeded a threshold value, and a hold circuit that generates a hold signal to stop the data shift operation of the shift register when the event occurs as a result of the determination.

[0017] Here, the noise waveform restoration circuit includes a counter circuit that sequentially reads digital data before and after the occurrence of the event stored in the shift register and generates restoration data to restore the digital data into an analog noise waveform.

[0018] Here, the built-in noise management device further includes a power circuit that receives power from an external source and generates at least internal power to operate the built-in noise management device.

[0019] Here, the built-in noise management device further includes a noise compensation circuit that detects the radiated electromagnetic waves and generates and provides a compensation signal corresponding to the detected radiated electromagnetic waves.

[0020] Here, the noise compensation circuit includes one or more magnetic loops through which at least a portion of the radiated electromagnetic waves pass, and a compensation circuit connected to the magnetic loops and generating a compensation signal for generating a cancellation electromagnetic wave that cancels out the radiated electromagnetic waves.

[0021] According to another aspect of the present disclosure, an electronic system including an embedded noise management device is provided.

[0022] According to another aspect of the present disclosure, a noise management system is provided comprising at least one built-in noise management device and a computing device that receives data for restoration from the built-in noise management device via a network, converts the data into a noise waveform, and monitors it.

[0023] According to one embodiment of the present disclosure, an embedded noise management device can accurately measure and record a noise waveform induced inside an electronic system by radiated electromagnetic waves.

[0024] According to another embodiment of the present disclosure, an embedded noise management device can effectively compensate for radiated electromagnetic waves.

[0025] According to another embodiment of the present disclosure, an electronic system can accurately measure, record, and compensate for noise waveforms caused by radiated electromagnetic waves.

[0026] According to other embodiments of the present disclosure, at least one built-in noise management device can be effectively monitored.

[0027] FIG. 1 is a schematic diagram disclosing an electronic system including an embedded noise management device according to one embodiment of the present disclosure.

[0028] Figure 2 is an explanatory diagram showing the configuration of the built-in noise management device of Figure 1.

[0029] Figure 3 is an explanatory diagram showing the configuration of the built-in noise management device of Figure 2 in more detail.

[0030] Figure 4 is an explanatory diagram showing the configuration of the built-in noise management device of Figure 3 in more detail.

[0031] FIG. 5 is a circuit diagram illustrating a voltage drop regulator according to one embodiment.

[0032] FIG. 6 is a circuit diagram illustrating an input buffer circuit according to one embodiment.

[0033] FIG. 7 is a circuit diagram showing an ADC circuit and a shift register according to one embodiment.

[0034] FIGS. 8a to 8c are circuit diagrams showing a first event detector and a second event detector according to one embodiment.

[0035] Figure 9 is a graph showing the noise signal measurement performance of an embedded noise management device according to the embodiment of Figure 1 when an electrostatic discharge (ESD) occurs.

[0036] FIG. 10 is a schematic diagram disclosing an electronic system including an embedded noise management device according to another embodiment of the present disclosure.

[0037] Figure 11 is an explanatory diagram showing the configuration of the built-in noise management device of Figure 10.

[0038] FIG. 12 is a graph showing the noise signal measurement performance of an embedded noise management device according to the embodiment of FIG. 11 when high-power electromagnetic waves (HPEM) are generated.

[0039] FIG. 13 is an explanatory diagram showing the configuration of an embedded noise management device according to another embodiment of the present disclosure.

[0040] FIG. 14 is a block diagram showing an example of the compensation circuit of FIG. 13.

[0041] FIG. 15 is a circuit diagram showing a part of an embodiment of the compensation circuit of FIG. 14.

[0042] FIG. 16 is a circuit diagram showing an embedded noise management device according to another embodiment including two or more magnetic loops.

[0043] FIG. 17 is a schematic diagram illustrating a noise management system according to an embodiment of the present disclosure.

[0044] FIG. 18 is a block diagram of a computing device according to one embodiment.

[0045] According to one embodiment of the present disclosure, an embedded noise management device is provided for managing noise induced in the electronic system by radiated electromagnetic waves generated by an electrical stress event, wherein the embedded noise management device comprises: a noise sampling circuit that detects and samples a noise signal corresponding to the radiated electromagnetic waves in real time, converts it into digital data, and then sequentially stores the digital data through a data shift operation; an event detection circuit that determines an event when a noise signal exceeding a threshold is detected and performs the data shift operation of the noise sampling circuit; and a noise waveform restoration circuit that sequentially reads the digital data before and after the occurrence of the event stored in the noise sampling circuit and generates restoration data for restoring it into an analog noise waveform.

[0046] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments presented below, but can be implemented in various different forms and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and scope of the present disclosure.

[0047] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the disclosure. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0048] Some embodiments of the present disclosure may be represented by functional block configurations and various processing steps. Some or all of these functional blocks may be implemented by various numbers of hardware and / or software configurations that execute specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors or by circuit configurations for a specific function. Additionally, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages. The functional blocks may be implemented as algorithms executed on one or more processors. Furthermore, the present disclosure may employ prior art for electronic configuration, signal processing, and / or data processing, etc. Terms such as “mechanism,” “element,” “means,” and “configuration,” etc., may be used broadly and are not limited to mechanical and physical configurations.

[0049] Furthermore, the connecting lines or connecting members between the components depicted in the drawings are merely illustrative of functional connections and / or physical or circuit connections. In the actual device, connections between components may be represented by various alternative or added functional connections, physical connections, or circuit connections.

[0050] The present disclosure will be described in detail below with reference to the attached drawings.

[0051] FIG. 1 is a schematic diagram disclosing an electronic system (1000) including an embedded noise management device (100) according to one embodiment of the present disclosure. FIG. 2 is an explanatory diagram showing the configuration of the embedded noise management device (100) of FIG. 1. FIG. 3 is an explanatory diagram showing the configuration of the embedded noise management device (100) of FIG. 2 in more detail. FIG. 4 is an explanatory diagram showing the configuration of the embedded noise management device (100) of FIG. 3 in more detail.

[0052] Referring to FIG. 1, the electronic system (1000) includes a built-in noise management device (100).

[0053] The electronic system (1000) refers to any electronic device that may be affected by Radiated Electromagnetic Waves (REW). For example, the electronic system (1000) may include at least one of a drone system, a wearable device, a smartphone, a tablet, a laptop, a Wi-Fi router, a communication relay, a server, data center equipment, an electronic system for vehicles, an electric vehicle battery management system, communication equipment, a satellite communication system, a radar device, a high-speed computing system, home appliances (smart TV, air conditioner, refrigerator, washing machine, electric rice cooker, microwave oven, etc.), an industrial control system, or medical electronic equipment, but is not limited to those exemplified.

[0054] An embedded noise management device (100) is placed inside an electronic system (1000). The embedded noise management device (100) can measure and record noise induced in the electronic system (1000) by radiated electromagnetic waves (REW). Here, radiated electromagnetic waves (REW) may be generated by an Electrical Stress Event (ESE). An Electrical Stress Event (ESE) may include various electrical interferences such as electrostatic discharge (ESD), high-power electromagnetic waves (HPEM), electrical fast transients (EFT), surges, or electromagnetic pulses (EMP), but is not limited to those exemplified. Radiated electromagnetic waves (REW) may be electromagnetic energy emitted into space in the form of radio waves. Radiated electromagnetic waves (REW) may cause soft and hard failures in the electronic system (1000). Management of radiated electromagnetic waves (REW) is required to compensate for user safety of the electronic system (1000) and to save costs and time. To verify the impact of radiated electromagnetic waves (REW) on the electronic system (1000), a manual measurement method can generally be used, which involves measuring the oscilloscope power noise voltage waveform through an external oscilloscope using a cable. However, this manual measurement method is not feasible for electronic systems (1000) that have a small size and high integration density. Furthermore, the differential-mode voltage waveform measured through the external oscilloscope may be distorted due to common-mode noise generated by the radiated electromagnetic waves (REW). Additionally, as the electromagnetic field of the radiated electromagnetic waves (REW) combines with wire bonding, the measurement cable, and the oscilloscope equipment, the noise waveform generated in the actual electronic system (1000) and the measured noise waveform may be distorted.The built-in noise management device (100) according to the embodiments of the present disclosure overcomes the limitations of such manual measurement methods and can directly monitor noise signals within the electronic system (1000) in the form of waveforms. Accordingly, the impact of radiated electromagnetic waves (REW) in the electronic system (1000) can be analyzed effectively, without distortion, and quickly.

[0055] The built-in noise management device (100) may be in the form of an integrated circuit chip or a semiconductor package in which the integrated circuit chip is packaged.

[0056] An embedded noise management device (100) may be mounted on a printed circuit board (1000P) on which at least one computer chip (CIC) is mounted. The computer chip (CIC) may be a computer chip (CIC) involved in controlling an electronic system (1000). For example, the computer chip (CIC) may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), an I / O interface chip, or a power management chip (PMIC).

[0057] The built-in noise management device (100) can be electrically connected to a computer chip (CIC) through a printed circuit board (1000P), power lines, signal lines, etc. For example, the built-in noise management device (100) can be electrically connected to a power management chip (PMIC) through a power line, and can be electrically connected to a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), or an I / O interface chip through a signal line. However, it is not limited to this, and the built-in noise management device (100) can be electrically connected directly to a computer chip (CIC) through a printed circuit board (1000P) without passing through power lines and signal lines. The built-in noise management device (100) is electrically connected to the computer chip (CIC) and can manage noise signals induced in the computer chip (CIC) in response to radiated electromagnetic waves (REW).

[0058] In one embodiment, the built-in noise management device (100) can receive radiated electromagnetic waves (REW) through a printed circuit board (1000P). In another embodiment, the built-in noise management device (100) can receive the radiated electromagnetic waves (REW) through a frame (1000F) that fixes or supports internal components of an electronic system (1000). The printed circuit board (1000P) or the frame (1000F) acts as a type of antenna, and the radiated electromagnetic waves (REW) received therefrom can cause voltage disturbances in internal systems, including computer chips (CIC), thereby inducing noise signals.

[0059] For reference, in FIG. 1, VSS means ground, VDD means external power from a power management chip (PMIC), and SIG means a control signal from a computer chip (CIC). In this specification, VDD may sometimes mean a power line corresponding to an external power source, and SIG may mean a signal line corresponding to a control signal.

[0060] Referring to FIG. 2, the built-in noise management device (100) may include at least a noise sampling circuit (110), an event detection circuit (120), a noise waveform restoration circuit (130), and an output interface (140). In addition to the configuration shown in FIG. 2, the built-in noise management device (100) may further include known additional configurations required for operation.

[0061] The built-in noise management device (100) detects a noise signal corresponding to the radiated electromagnetic waves (REW). Specifically, an electrical stress event (ESE) emits radiated electromagnetic waves (REW) into space. The radiated electromagnetic waves (REW) are induced (conducted or radiated) into the electronic system (1000). Accordingly, a noise signal is generated in the computer chip (CIC), printed circuit board (1000P), power line, signal line, etc., within the electronic system (1000). The noise signal may be an unintended noise voltage (noise voltage). The noise voltage may range from several mV to several thousand volts. The noise signal may contain high-frequency components. The noise signal is generated in real time, and the built-in noise management device (100) detects the noise signal in real time.

[0062] The noise sampling circuit (110) detects a noise signal as described above. The noise sampling circuit (110) samples the detected noise signal, converts it into digital data, and then sequentially stores the digital data through a data shift operation. That is, the noise sampling circuit (110) continuously samples the noise signal in real time, and the sampled digital data is sequentially stored in a FIFO (First In First Out) manner.

[0063] The event detection circuit (120) determines that a noise signal exceeding a threshold is an event when detected, and stops (holds) the data shift operation of the noise sampling circuit (110). An event refers to the case where a noise signal having a voltage exceeding a threshold or a noise signal having a high frequency exceeding a threshold is detected. For example, if a rapid voltage / current spike of several nanometers is generated by electrostatic discharge (ESD) or if a powerful electromagnetic wave (HPEM) is applied, a noise signal exceeding a threshold may be generated. When the event detection circuit (120) determines an event, it stops the data shift operation of the noise sampling circuit (110), thereby allowing digital data before and after the event time to be stored in a fixed (stick) state without being pushed out by the FIFO method. Here, before and after the event time may be a preset time, for example, a time window of several hundred nanoseconds (ns) to several tens of milliseconds (ms) in the past from the event time, and a time window of several hundred nanoseconds (ns) to several tens of milliseconds (ms) in the future from the event time. Specifically, digital data immediately prior to the event is preserved by stopping the data shift operation. Additionally, digital data immediately prior to the event may be included by a delayed storage method. A delayed storage method refers to a method in which a data shift operation is performed for a predetermined time (hundreds of nanoseconds (ns) to tens of milliseconds (ms)) immediately after the event occurs, and then stopped.

[0064] The noise waveform restoration circuit (130) sequentially reads digital data before and after the event occurrence stored in the noise sampling circuit (110) to generate restoration data for restoring it into an analog noise waveform. The restoration data may be modulated digital data at an intermediate stage for restoration into an analog noise waveform. Additionally, the noise waveform restoration circuit (130) may sequentially read digital data before and after the event occurrence stored in the noise sampling circuit (110) to restore it into an analog noise waveform. The analog noise waveform may include noise voltage over time. Unlike cases where noise is simply detected, the analog noise waveform allows for verification of temporal characteristics such as the time of noise occurrence, duration, change in amplitude, and oscillation period, and allows for estimation of the type of cause of the noise through the shape of the waveform. Furthermore, it is useful that the noise can be easily visually identified and can be reused as an input signal for testing or simulation.

[0065] The output interface (140) outputs data for restoration or a restored noise waveform. The output interface (140) may be an output terminal, for example, at least one of an I / O pin (Input / Output Pin), a pad, or a package terminal (Leads, Balls, or Bumps). The output interface (140) may be connected to a computing device (500 in FIG. 17) inside or outside the electronic system (1000). The data for restoration or the restored noise waveform may be transmitted to the computing device (500 in FIG. 17). The computing device (500 in FIG. 17) may convert the transmitted data for restoration into an analog noise waveform or perform noise measurement, analysis, and management through the transmitted noise waveform. Meanwhile, the built-in noise management device (100) may further include a power circuit (150) that generates the internal power (VDDA) required for the built-in noise management device (100).

[0066] With reference to FIGS. 3 and 4, the power circuit (150), the noise sampling circuit (110), the event detection circuit (120), and the noise waveform restoration circuit (130) will be described in detail.

[0067] The power circuit (150) receives power from an external source and generates an internal power supply (VDDA) for operating at least the built-in noise management device (100). The power from the external source may be an external power supply (VDD) provided by a power management chip (PMIC). The power circuit (150) may include a low drop-out regulator (LDO). The low drop-out regulator (LDO) can convert the external power supply (VDD) into a stable, low-voltage internal power supply (VDDA).

[0068] FIG. 5 is a circuit diagram illustrating a voltage drop regulator (LDO) according to one embodiment.

[0069] The voltage drop regulator (LDO) includes an error amplifier (151), a booster buffer (152), a compensation capacitor (154), and a power switch (153).

[0070] The error amplifier (151) is placed at the input terminal where the external power supply (VDD) is input. The error amplifier (151) is intended to output a stable internal power supply (VDDA). The error amplifier (151) takes the target output voltage (VBGR) and the actual output voltage, which is the internal power supply (VDDA), as inputs and transmits the output to the booster buffer (152) to be used for controlling the power switch (153). The error amplifier (151) compares the target output voltage (VBGR) and the actual output voltage, which is the internal power supply (VDDA), and amplifies the error to control the power switch (153). When an error occurs when comparing the feedback between the target output voltage (VBGR) and the actual output voltage, the error amplifier (151) amplifies the voltage difference. The amplified error signal passes through the booster buffer (152) to control the power switch (153).

[0071] A booster buffer (152) is placed between the error amplifier (151) and the power switch (153). If the actual output voltage from the error amplifier (151) is directly transmitted to the power switch (153), the response speed is slow and stability is reduced. Therefore, by placing a booster buffer (152), a fast response and the loop gain of the entire voltage drop regulator (LDO) can be improved. The booster buffer (152) takes the actual output voltage from the error amplifier (151) as input and outputs a signal necessary to regulate the gate voltage of the power switch (153). The booster buffer (152) operates in the form of an amplifier with current gain to amplify the signal applied to the gate of the power switch (153).

[0072] A power switch (153) is positioned at an output terminal where the internal power supply (VDDA) is output. The power switch (153) outputs the internal power supply (VDDA) by adjusting the drain-source current according to the gate voltage.

[0073] The compensation capacitor (154) provides phase compensation to the feedback loop inside the voltage drop regulator (LDO) to prevent oscillation or unstable response. The compensation capacitor (154) may be a Metal-Insulator-Metal (MIM) capacitor. The compensation capacitor (154) is designed to have sufficient gain margin (GM) and phase margin (PM) for stable operation of the voltage drop regulator (LDO).

[0074] For reference, Vbias in FIG. 5 is a reference voltage for setting the bias current required for the circuit of the error amplifier (151) or booster buffer (152).

[0075] Referring again to FIGS. 3 and FIGS. 4, the noise sampling circuit (110) may include at least a sensing input (111), an input buffer circuit (112), an analog-to-digital converter (ADC) circuit (113), and a shift register (114).

[0076] The sensing input (111) may be an input terminal. The sensing input (111) may be at least one of, for example, an I / O pin (Input / Output Pin), a pad, or a package terminal (Leads, Balls, or Bumps).

[0077] The sensing input (111) detects and receives noise signals corresponding to radiated electromagnetic waves (REW) in real time. The sensing input (111) detects noise signals from the power line as well as noise signals from the signal line. By detecting noise signals from the signal line as well, the sensing input (111) can measure all various noise signals generated within the electronic system (1000) by radiated electromagnetic waves (REW). The noise signals detected through the sensing input (111) are transmitted to the input buffer circuit (112). Additionally, the noise signals detected through the sensing input (111) are also transmitted to the event detector (121) of the event detection circuit (120).

[0078] The input buffer circuit (112) attenuates and / or amplifies the detected noise signal. The input buffer circuit (112) adjusts the DC offset and AC swing included in the noise signal due to radiated electromagnetic waves (REW). In one embodiment, the input buffer circuit (112) may include an attenuation circuit (112a in FIG. 6). In another embodiment, the input buffer circuit (112) may further include an attenuation circuit (112a) and an input amplifier (112b in FIG. 6) connected to the output terminal of the attenuation circuit (112a).

[0079] The attenuation circuit (112a) can reduce the noise signal to within a predetermined voltage range. Accordingly, the attenuation circuit (112a) resolves the problem of the ADC circuit (113) being damaged by overvoltage. Here, the predetermined voltage range can be set based on the median value of the input range of the ADC circuit (113) (e.g., 0.4V, 0.6V, 0.8V, 1.0V, 1.2V, etc.). By adjusting the voltage of the noise signal based on the median value of the input range of the ADC circuit (113), the DC offset included in the noise signal is removed, and the allowable range of positive (+) and negative (-) AC swings can be set equally. For example, the attenuation circuit (112a) can adjust the voltage of the noise signal to within the range of 0.3V to 1.3V based on 0.8V, which is the median value of the input range of the ADC circuit (113). The attenuation circuit (112a) may include at least one resistor and at least one capacitor, etc. Noise signal (V) attenuated by the attenuation circuit (112a) IN ) is input to the ADC circuit (113).

[0080] FIG. 6 is a circuit diagram illustrating an input buffer circuit (112) according to one embodiment.

[0081] The input buffer circuit (112) is placed between the sensing input (111) and the ADC circuit (113). As shown in FIG. 6(a), the input buffer circuit (112) may include an attenuation circuit (112a).

[0082] The attenuation circuit (112a) includes a resistor voltage divider (112R) that attenuates the DC component and a capacitor voltage divider (112C) that attenuates the AC component.

[0083] The resistor voltage divider (112R) includes a first resistor (R1) connected between the internal power supply (VDDA) and the input of the ADC circuit (113), a second resistor (R2) connected between the input of the ADC circuit (113) and ground (VSS), and a third resistor (R3) connected in parallel with the second resistor (R2) and connected between the input of the ADC circuit (113) and ground (VSS). The second resistor (R2) and the third resistor (R3) form a DC bias. A first switch element (M1) is connected between the second resistor (R2) and ground (VSS), and a second switch element (M2) is connected between the third resistor (R3) and ground (VSS) to form a DC offset selection logic, thereby allowing the voltage division ratio to be adjusted and the DC offset voltage of the noise signal input to the ADC circuit (113) to be adjusted.

[0084] The capacitor voltage divider (112C) includes a first capacitor (C1) connected between the sensing input (111) and the input of the ADC circuit (113), and a second capacitor (C2) connected between the input of the ADC circuit (113) and ground (VSS). The first capacitor (C1) transmits the high-frequency component of the noise signal to the input of the ADC circuit (113) and does not transmit DC or low-frequency components. The second capacitor (C2) bypasses the high-frequency component of the input of the ADC circuit (113) to ground (VSS) to remove it. The capacitor voltage divider (112C) can control the attenuation of the high-frequency component of the AC signal according to the ratio of the capacitances of the first capacitor (C1) and the second capacitor (C2). As a result, only the attenuated high-frequency component of the noise signal remains at the input of the ADC circuit (113), allowing the ADC circuit (113) to operate stably.

[0085] Meanwhile, ground (VSS) is the local ground of the electronic system (1000) and can be set to 0V, but is not limited thereto. V IN represents an attenuated noise signal.

[0086] As shown in FIG. 6(b), the input buffer circuit (112) may further include an input amplifier (112b) in addition to the attenuation circuit (112a).

[0087] The description related to the damping circuit (112a) is the same as that described in FIG. 6(a), so refer to it.

[0088] The input amplifier (112b) can be placed between the output terminal of the attenuation circuit (112a) and the input terminal of the ADC circuit (113). The input amplifier (112b) serves to minimize distortion of the original noise signal by providing high input impedance. Additionally, the input amplifier (112b) can perform the function of amplifying when the magnitude of the target event-driven electromagnetic noise signal is small. The input amplifier (112b) may employ an Op-Amp, but is not limited thereto and may use an amplifier designed to provide high impedance.

[0089] Referring again to FIGS. 3 and 4, the ADC circuit (113) samples an analog noise signal and converts it into digital data. The ADC circuit (113) may include multiple ADCs. For example, the ADC circuit (113) may include 4, 6, 8, 10, or 12 ADCs, but is not limited thereto. The ADC may be a flash ADC having a fast sampling rate. Since a flash ADC has a fast sampling rate, it is useful for capturing noise signals containing high-frequency components. In particular, noise signals caused by radiated electromagnetic waves (REW) generated by electrostatic discharge (ESD) or high-power electromagnetic waves (HPEM) may contain high-frequency components.

[0090] The ADC circuit (113) is attenuated noise signal (V INThe noise signal is sampled in parallel through multiple ADCs. Each ADC converts the voltage of the noise signal into a digital value of a specific resolution. Here, the specific resolution can be the number of bits, for example, 5 bits, but is not limited to this. The ADC cuts the noise voltage into short time intervals, quantizes (converts into numbers) according to the ADC resolution, and converts each voltage value into a binary number.

[0091] The ADC can operate through multiple multiphase clocks. The multiphase clocks may be 4, 6, 8, 10, or 12, equal to the number of ADCs, but are not limited thereto. The multiphase clocks may be generated by a delay-locked loop (DLL). Therefore, the ADC circuit (113) may further include a delay-locked loop (DLL). The delay-locked loop (DLL) receives an external reference clock and precisely delays it to generate multiple multiphase clocks with different phases.

[0092] The shift register (114) is placed at the output terminal of the ADC circuit (113). The shift register (114) stores converted digital data sequentially through a data shift operation. A data shift operation refers to an operation in which digital data moves sequentially in one direction within a register that stores digital data. In other words, the data shift operation is a process in which existing data is pushed out and moved as new data enters. In this way, the shift register (114) stores digital data in a FIFO (First-In First-Out) manner. Therefore, when new digital data enters, the oldest digital data is pushed out and deleted. Since the shift register (114) stores data through a data shift operation, it can be advantageous for real-time analysis of noise signals.

[0093] FIG. 7 is a circuit diagram showing an ADC circuit (113) and a shift register (114) according to one embodiment.

[0094] FIG. 7 shows an embodiment in which the ADC circuit (113) includes eight flash ADCs (ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8) and uses eight multi-phase clocks (CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8).

[0095] Attenuated noise signal (V IN ) is input to each of the 8 ADCs (ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8), and through the 8 multi-phase clocks (CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8), each ADC generates a total of 8 5-bit digital data.

[0096] The ADC circuit (113) may further include a data alignment circuit (113D). The data alignment circuit (113D) may be placed between a plurality of ADCs (ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8) and a shift register (114). The data alignment circuit (113D) aligns and synchronizes a plurality of digital data generated by different phase clocks. The data alignment circuit (113D) transmits eight aligned 5-bit digital data (ADC1_OUT, ADC2_OUT, ADC3_OUT, ADC4_OUT, ADC5_OUT, ADC6_OUT, ADC7_OUT, ADC8_OUT) to the shift register (114).

[0097] The shift register (114) stores digital data of the ADC circuit (113) in chronological order in a FIFO manner. The shift register (114) includes a shift register control circuit (114C).

[0098] The shift register control circuit (114C) controls the timing of storing sampled digital data in the shift register (114) via the DFF driving clock (CLK_dff). The shift register control circuit (114C) includes a clock selector (114C1), an AND gate (114C2), and a buffer (114C3).

[0099] The clock selector (114C1) selects one of eight multi-phase clocks. The clock selector (114C1) selects one clock by the clock select signal (CLK_sel). The clock select signal can be preset. The clock selector (114C1) selects one clock and outputs it as the selected clock (Selected_CLK).

[0100] The AND gate (114C2) is placed between the clock selector (114C1) and the shift register (114). The AND gate (114C2) is also associated with the event detection circuit (120). The AND gate (114C2) can receive a select clock (Selected_CLK) and / or a hold signal (S_hold) from the event detection circuit (120). If the hold signal (S_hold) is not received from the event detection circuit (120), that is, if no event occurs, the select clock (Selected_CLK) passes through as is and the DFF driving clock (CLK_dff) is generated. Accordingly, the shift register (114) stores digital data through a data shift operation. However, if the hold signal (S_hold) is received from the event detection circuit (120), that is, if an event occurs, the output of the AND gate (114C2) becomes 0 and the DFF driving clock (CLK_dff) is not generated. Accordingly, the shift register (114) stops the data shift operation.

[0101] The buffer (114C3) is intended to reliably transmit the DFF driving clock (CLK_dff) to the shift register (114). The buffer (114C3) is placed between the AND gate (114C2) and the shift register (114).

[0102] Referring again to FIGS. 3 and FIGS. 4, the event detection circuit (120) may include at least an event detector (121) and a hold circuit (122).

[0103] The event detector (121) receives a noise signal from the sensing input (111). The event detector (121) determines whether an event has occurred based on the detected noise signal. Here, an event refers to the moment when the noise signal exceeds a threshold value. For example, an event may be the moment when a noise voltage exceeding a threshold value is induced within the electronic system (1000) due to radiated electromagnetic waves (REW) generated by electrostatic discharge (ESD) or high-power electromagnetic waves (HPEM). Here, the threshold value may be a range of preset voltage values, or a high voltage value that may cause errors in the electronic system (1000). The event detector (121) may include at least two resistors, and the sensitivity of the event determination can be adjusted by adjusting the resistors. That is, the event detector (121) can adjust the aforementioned threshold value by adjusting the resistors. This will be described later in FIGS. 8a to 8c.

[0104] An event detector (121) generates a trigger signal when an event occurs. Referring to FIG. 4, the event detector (121) may include a first event detector (121V) that detects an event on a power line and a second event detector (121S) that detects an event on a signal line. The first event detector (121V) generates a first trigger signal (VDD_trigger) when an event is detected. The second event detector (121S) generates a second trigger signal (SIG_trigger) when an event is detected.

[0105] A hold circuit (122) is positioned between an event detector (121) and a shift register (114). When an event occurs as a result of the judgment of the event detector (121), the hold circuit (122) generates a hold signal (S_hold) and transmits it to the shift register (114). The hold circuit (122) takes a trigger signal as input and outputs a hold signal (S_hold).

[0106] Referring to FIG. 4, the hold circuit (122) may include a trigger signal selector (122M) and a hold signal generator (122T).

[0107] The trigger signal selector (122M) selects and outputs one of the first trigger signal (VDD_trigger) from the first event detector (121V), the second trigger signal (SIG_trigger) from the second event detector (121S), and the third trigger signal (Ext_trigger) applied from the outside. The trigger signal selector (122M) selects one trigger signal by the trigger signal selection signal (trigger_sel).

[0108] A hold signal generator (122T) is positioned between the output terminal of the trigger signal selector (122M) and the shift register (114). The hold signal generator (122T) generates a hold signal (S_hold) based on the trigger signal. The hold signal generator (122T) generates a hold signal (S_hold) to preserve digital data immediately after an event occurs through a delayed storage method. A delayed storage method refers to a method of performing a data shift operation for a predetermined time (hundreds of nanoseconds (ns) to several milliseconds (ms)) immediately after an event occurs, and then stopping. Accordingly, digital data immediately after an event occurs can also be preserved in the shift register (114). That is, the hold signal generator (122T) generates a hold signal (S_hold) that stops the storage of sampling data, and outputs the hold signal (S_hold) after a predetermined delayed time following the input of the trigger signal. The hold signal generator (122T) outputs a hold signal (S_hold) by the delay time control signal (Time_cont).

[0109] The shift register (114) stops the data shift operation by the hold signal (S_hold). When the shift operation is stopped, the digital data is fixed and stored without being pushed out by the FIFO method. That is, digital data is stored before and after the time of the event occurrence. Specifically, digital data immediately before the event is preserved by stopping the data shift operation. In addition, digital data immediately after the event can be included by the delayed storage method described above.

[0110] FIGS. 8a to 8c are circuit diagrams showing a first event detector (121V) and a second event detector (121S) according to one embodiment. FIG. 8a shows a first event detector (121V) according to one embodiment, and FIGS. 8b and FIGS. 8c each show a second event detector (121S) of a different type.

[0111] Referring to FIG. 8a, the first event detector (121V) detects a noise signal induced on the power line and, if the noise signal exceeds a threshold value, determines that an event has occurred and generates a first trigger signal (VDD_trigger). The first event detector (121V) generates a reference voltage (VREF) which is a threshold value from an external power source (VDD) and detects an event in which the noise voltage exceeds the reference voltage (VREF) through an RC circuit including a capacitor (C) and a transistor (MN1). The reference voltage (VREF) which is a threshold value is determined by the voltage division of resistors a (Ra) and b (Rb). Therefore, the threshold value can be set by adjusting the resistance values.

[0112] The second event detector (121S) detects a noise signal induced on a signal line and, when the noise signal exceeds a threshold value, determines that an event has occurred and generates a second trigger signal (SIG_trigger). The second event detector (121S) may include a second positive event detector (121Sp) that detects a positive direction noise signal event (positive event) and generates a second positive trigger signal (SIG_trigger-p), and a second negative event detector (121Sn) that detects a negative direction noise signal event (negative event) and generates a second negative trigger signal (SIG_trigger-n). A positive direction (overshoot) signal event is when the noise signal becomes higher than the maximum threshold value and can be referred to as a positive event. A negative direction (undershoot) signal event is when the noise signal becomes lower than the minimum threshold value and can be referred to as a negative event. Both cases correspond to events because the noise signal exceeds the threshold value. The second event detector (121S) performs event detection in the positive and negative directions, respectively, enabling separate detection based on the polarity direction of the noise signal.

[0113] Referring to FIG. 8b, the second positive event detector (121Sp) employs an internal power supply (VDDA) and a first PMOS transistor (M) that operates when the noise signal is greater than the maximum threshold value. p1 ), cross-coupled first bias PMOS transistor (M pb1 ) and second bias PMOS transistor (M pb2 A PMOS cross-coupled inverter block (121Sp1) including ), and an NMOS reset switch (M) that initializes the PMOS cross-coupled inverter block (121Sp1) by a reset signal (reset) from an external source. nrIt may include a positive trigger output inverter chain (121Sp2) that generates and outputs a second positive trigger signal (SIG_trigger-p).

[0114] The PMOS cross-coupled inverter block (121Sp1) is the first PMOS transistor (M p1 When a positive event is detected through ), the state is latched and the state is output. Then, the positive trigger output inverter chain (121Sp2) buffers and level-shifts the output node to generate a second positive trigger signal (SIG_trigger-p) with a logically stable output.

[0115] V in Fig. 8b B is a bias voltage that provides a potential at which the components in the circuit operate stably, and Bias-p refers to the PMOS bias voltage.

[0116] Referring to FIG. 8c, the second negative event detector (121Sn) employs ground (VSS) and a first NMOS transistor (M) that operates when the noise signal is smaller than a minimum threshold value. n1 ), cross-coupled first bias NMOS transistor (M nb1 ) and second bias NMOS transistor (M nb2 An NMOS cross-coupled inverter block (121Sn1) including ), and a PMOS reset switch (M) that initializes the NMOS cross-coupled inverter block (121Sn1) by an inverted reset signal (reset_b) from the outside. pr It may include a negative trigger output inverter chain (121Sn2) that generates and outputs a second negative trigger signal (SIG_trigger-n).

[0117] The NMOS cross-coupled inverter block (121Sn1) is the first NMOS transistor (M n1When a negative event is detected through ), the state is latched and the state is output. Then, the negative trigger output inverter chain (121Sn2) buffers and level-shifts the output node to generate a second negative trigger signal (SIG_trigger-n) with a logically stable output.

[0118] V in Fig. 8c C is a bias voltage that provides a potential at which the components in the circuit operate stably, and Bias-n refers to the NMOS bias voltage.

[0119] Referring again to FIGS. 3 and FIGS. 4, the noise waveform recovery circuit (130) may include at least a counter circuit (131).

[0120] The counter circuit (131) sequentially reads digital data before and after an event stored in the shift register (114) and converts the digital data into data for restoration to restore the analog noise waveform. The counter circuit (131) reassembles the stored digital data according to the sampling time interval to generate data for restoration. The counter circuit (131) receives a Read Clock and reads the digital data stored in the shift register (114) in order, and may use a method of reading data sequentially one by one for each Read Clock cycle.

[0121] The noise waveform recovery circuit (130) may further include a waveform recovery circuit (not shown) for generating an analog noise waveform based on recovery data generated in the counter circuit (131). The waveform recovery circuit may be implemented as an integrated circuit chip or implemented to be included in the counter circuit (131), and generates an analog noise waveform using recovery data as input.

[0122] FIG. 9 is a graph showing the noise signal measurement performance of an embedded noise management device (100) according to the embodiment of FIG. 1 when an electrostatic discharge (ESD) occurs.

[0123] FIG. 9 shows the results of measuring the noise signal induced by generating an electrostatic discharge (ESD) as an electrical stress event (ESE) in the drone system through an electronic system (1000) and a comparative example. Specifically, the noise signal was measured by an embedded noise management device (100) according to an embodiment, which is mounted on an APM board (ArduPilot Mega Board) embedded in the drone system, and as a comparative example, the noise signal was also measured by an external oscilloscope. FIG. 9(a) is the case where the drone system has no separate ground connection, and is significantly affected by disturbances when measured with an external oscilloscope due to the influence of common mode current, etc. FIG. 9(b) is the case where the drone system is connected to ground, preventing unwanted common mode current from going to the external oscilloscope.

[0124] As can be seen in FIG. 9(b), when the drone system is connected to ground, the embodiment and the comparative example can measure very similar noise waveforms. Because the common mode noise is reduced due to the ground connection, both the embodiment and the comparative example can accurately measure the noise waveform. However, the drone system is an electronic system (1000) that flies in the air, and ground connection is not possible during flight.

[0125] As can be seen in FIG. 9(a), when the drone system is not connected to ground, there is a significant difference in the noise waveform between the embodiment and the comparative example. In other words, when the drone system is not connected to ground, it indicates that there is an error in the measurement of the noise waveform by the external oscilloscope equipment. This is because when the external oscilloscope equipment is not grounded, the common mode noise increases, and the resulting noise signal distortion is severe. Therefore, the noise waveform of a flying drone system cannot be accurately measured by the external oscilloscope equipment. However, it is confirmed that the built-in noise management device (100) according to the embodiment can accurately measure the noise waveform regardless of grounding.

[0126] FIG. 10 is a schematic diagram disclosing an electronic system (1000) including an embedded noise management device (100a) according to another embodiment of the present disclosure. FIG. 11 is an explanatory diagram showing the configuration of the embedded noise management device (100a) of FIG. 10.

[0127] Referring to FIG. 10, the electronic system (1000) includes a built-in noise management device (100a).

[0128] An embedded noise management device (100a) is placed inside an electronic system (1000). The embedded noise management device (100a) can measure and record noise induced in the electronic system (1000) by radiated electromagnetic waves (REW). The embedded noise management device (100a) may be in the form of an integrated circuit chip or a semiconductor package in which an integrated circuit chip is packaged.

[0129] An embedded noise management device (100a) may be mounted on a printed circuit board (1000P) on which at least one computer chip (CIC) is mounted. The computer chip (CIC) may be a computer chip (CIC) involved in controlling an electronic system (1000). For example, the computer chip (CIC) may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), an I / O interface chip, or a power management chip (PMIC).

[0130] The built-in noise management device (100a) can be electrically connected to a computer chip (CIC) through a printed circuit board (1000P), power lines, signal lines, etc. For example, the built-in noise management device (100a) can be electrically connected to a power management chip (PMIC) through a power line, and can be electrically connected to a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), or an I / O interface chip through a signal line. However, it is not limited to this, and the built-in noise management device (100a) can be electrically connected directly to a computer chip (CIC) through a printed circuit board (1000P) without passing through power lines and signal lines. The built-in noise management device (100a) is electrically connected to the computer chip (CIC) and can manage noise signals induced in the computer chip (CIC) in response to radiated electromagnetic waves (REW).

[0131] In the embodiment of FIG. 1, the built-in noise management device (100) could receive radiated electromagnetic waves (REW) through a printed circuit board (1000P) or a frame (1000F). In contrast, the built-in noise management device (100a) according to the embodiment of FIG. 10 further includes an antenna (160) and can receive radiated electromagnetic waves (REW) from the antenna (160). The antenna (160) can be connected to the built-in noise management device (100a) via a signal line, or it can be connected via a printed circuit board (1000P). Since the built-in noise management device (100a) according to the embodiment of FIG. 10 can receive radiated electromagnetic waves (REW) more easily from the antenna (160), it can accurately measure the noise signal caused by the radiated electromagnetic waves (REW).

[0132] Referring to FIG. 11, the built-in noise management device (100a) may include at least a noise sampling circuit (110), an event detection circuit (120), a noise waveform restoration circuit (130), and an output interface (140). In addition to the configuration shown in FIG. 11, the built-in noise management device (100a) may further include known additional configurations required for operation.

[0133] The built-in noise management device (100a) detects a noise signal corresponding to the radiated electromagnetic waves (REW). Specifically, an electrical stress event (ESE) emits radiated electromagnetic waves (REW) into space. The radiated electromagnetic waves (REW) are more easily induced (conducted or radiated) into the electronic system (1000) by the antenna (160). Accordingly, a noise signal is generated in the computer chip (CIC), printed circuit board (1000P), power line, signal line, etc., within the electronic system (1000). The noise signal may be an unintended noise voltage (noise voltage). The noise voltage may range from several mV to several thousand volts. The noise signal may contain high-frequency components. The noise signal is generated in real time, and the built-in noise management device (100) detects the noise signal in real time.

[0134] The noise sampling circuit (110) detects a noise signal as described above. The noise sampling circuit (110) samples the detected noise signal, converts it into digital data, and then sequentially stores the digital data through a data shift operation. That is, the noise sampling circuit (110) continuously samples the noise signal in real time, and the sampled digital data is sequentially stored in a FIFO (First In First Out) manner.

[0135] The event detection circuit (120) determines that a noise signal exceeding a threshold is an event when detected, and stops (holds) the data shift operation of the noise sampling circuit (110). An event refers to the case where a noise signal having a voltage exceeding a threshold or a noise signal having a high frequency exceeding a threshold is detected. For example, if a rapid voltage / current spike of several nanometers is generated by electrostatic discharge (ESD) or if a powerful electromagnetic wave (HPEM) is applied, a noise signal exceeding a threshold may be generated. When the event detection circuit (120) determines an event, it stops the data shift operation of the noise sampling circuit (110), thereby allowing digital data before and after the event time to be stored in a fixed (stick) state without being pushed out by the FIFO method. Here, before and after the event time may be a preset time, for example, a time window of several hundred nanoseconds (ns) to several tens of milliseconds (ms) in the past from the event time, and a time window of several hundred nanoseconds (ns) to several milliseconds (ms) in the future from the event time. Specifically, digital data immediately prior to the event is preserved by stopping the data shift operation. Additionally, digital data immediately prior to the event may be included by a delayed storage method. A delayed storage method refers to a method of performing a data shift operation for a predetermined time (several nanoseconds (ns) to several milliseconds (ms)) immediately after the event occurs, and then stopping.

[0136] The noise waveform restoration circuit (130) sequentially reads digital data before and after the occurrence of an event stored in the noise sampling circuit (110) to generate restoration data for restoring to an analog noise waveform or to restore to an analog noise waveform. The analog noise waveform includes noise voltage over time. Unlike cases where noise is simply detected, the analog noise waveform allows for verification of temporal characteristics such as the time of noise occurrence, duration, change in amplitude, and oscillation period, and allows for estimation of the type of cause of the noise through the shape of the waveform. Additionally, it is useful that the noise can be easily visually identified and can be reused as an input signal for testing or simulation.

[0137] The output interface (140) outputs the restored noise waveform. The output interface (140) may be an output terminal, for example, at least one of an I / O pin (Input / Output Pin), a pad, or a package terminal (Leads, Balls, or Bumps). The output interface (140) may be connected to a computing device (500 in FIG. 17) inside or outside the electronic system (1000). The noise waveform may be transmitted to the computing device (500 in FIG. 17). The computing device (500 in FIG. 17) may perform noise measurement, analysis, and management through the transmitted noise waveform.

[0138] Since the specific configuration of the built-in noise management device (100a) according to the embodiment of FIG. 11 is similar to that described in FIG. 3 to FIG. 8a to FIG. 3, we will refer to FIG. 3 to FIG. 8a to FIG. 3.

[0139] FIG. 12 is a graph showing the noise signal measurement performance of the built-in noise management device (100a) according to the embodiment of FIG. 11 when high-power electromagnetic waves (HPEM) are generated.

[0140] FIG. 12 shows the results of measuring the noise signal induced by generating a high-power electromagnetic wave (HPEM) as an electrical stress event (ESE) in an electronic system (1000) and measuring the resulting noise signal through an embodiment and a comparative example. Here, the GTEM cell is a grounded metal chamber to provide an experimental environment for the electrical stress event (ESE). The noise signal was measured by an embedded noise management device (100a) according to an embodiment mounted on an APM board embedded in the GTEM cell, and as a comparative example, the noise signal was also measured by an external oscilloscope. FIG. 12(a) shows the noise waveform when the sampling rate is 100 MHz, and FIG. 12(b) shows the noise waveform when the sampling rate is 5 MHz.

[0141] As can be seen in FIG. 12(a) and FIG. 12(b), the embodiment can measure a noise waveform that is very similar to that measured with an external oscilloscope. That is, it can be confirmed that the built-in noise management device (100a) according to the embodiment is capable of measuring a noise waveform at an accurate level similar to that measured with an external oscilloscope.

[0142] FIG. 13 is an explanatory diagram showing the configuration of an embedded noise management device (100b) according to another embodiment of the present disclosure.

[0143] Referring to FIG. 13, the built-in noise management device (100b) can compensate for noise induced in the electronic system (1000) by radiated electromagnetic waves (REW), in addition to measuring and recording. The built-in noise management device (100b) may be in the form of an integrated circuit chip or a semiconductor package in which an integrated circuit chip is packaged.

[0144] The built-in noise management device (100b) may be mounted on a printed circuit board (1000P) on which at least one computer chip (CIC) is mounted. The computer chip (CIC) may be a computer chip (CIC) involved in controlling an electronic system (1000). For example, the computer chip (CIC) may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), an I / O interface chip, or a power management chip (PMIC).

[0145] The built-in noise management device (100b) can be electrically connected to a computer chip (CIC) through a printed circuit board (1000P), power lines, signal lines, etc. For example, the built-in noise management device (100b) can be electrically connected to a power management chip (PMIC) through power lines, and can be electrically connected to a central processing unit (CPU), a graphics processing unit (GPU), a memory chip (DRAM, SRAM, Flash, etc.), a chipset, a system on chip (SoC), a microcontroller unit (MCU), a field programmable gate array (FPGA), an application specific IC (ASIC), or an I / O interface chip through signal lines. However, it is not limited to this, and the built-in noise management device (100b) can be electrically connected directly to a computer chip (CIC) through a printed circuit board (1000P) without passing through power lines and signal lines. The built-in noise management device (100b) is electrically connected to the computer chip (CIC) and can manage noise signals induced in the computer chip (CIC) in response to radiated electromagnetic waves (REW).

[0146] In the embodiment of FIG. 13, the built-in noise management device (100b) further includes a noise compensation circuit (180) that detects radiated electromagnetic waves (REW) and generates and provides a compensation signal corresponding to the detected radiated electromagnetic waves (REW), compared to the built-in noise management device (100, 100a) according to the embodiments of FIG. 1 and FIG. 10. Through this, the built-in noise management device (100b) can perform compensation in addition to measuring and recording noise.

[0147] Referring to FIG. 13, the built-in noise management device (100b) may include at least a noise sampling circuit (110), an event detection circuit (120), a noise waveform restoration circuit (130), an output interface (140), and a noise compensation circuit (180). In addition to the configuration shown in FIG. 13, the built-in noise management device (100b) may further include known additional configurations required for operation.

[0148] The built-in noise management device (100b) detects a noise signal corresponding to the radiated electromagnetic waves (REW). Specifically, an electrical stress event (ESE) emits radiated electromagnetic waves (REW) into space. The radiated electromagnetic waves (REW) are induced (conducted or radiated) into the electronic system (1000). Accordingly, a noise signal is generated in the computer chip (CIC), printed circuit board (1000P), power line, signal line, etc., within the electronic system (1000). The noise signal may be an unintended noise voltage (noise voltage). The noise voltage may range from several mV to several thousand volts. The noise signal may contain high-frequency components. The noise signal is generated in real time, and the built-in noise management device (100b) detects the noise signal in real time.

[0149] The noise sampling circuit (110) detects a noise signal as described above. The noise sampling circuit (110) samples the detected noise signal, converts it into digital data, and then sequentially stores the digital data through a data shift operation. That is, the noise sampling circuit (110) continuously samples the noise signal in real time, and the sampled digital data is sequentially stored in a FIFO (First In First Out) manner.

[0150] The event detection circuit (120) determines that a noise signal exceeding a threshold is an event when detected, and stops (holds) the data shift operation of the noise sampling circuit (110). An event refers to the case where a noise signal having a voltage exceeding a threshold or a noise signal having a high frequency exceeding a threshold is detected. For example, if a rapid voltage / current spike of several nanometers is generated by electrostatic discharge (ESD) or if a powerful electromagnetic wave (HPEM) is applied, a noise signal exceeding a threshold may be generated. When the event detection circuit (120) determines an event, it stops the data shift operation of the noise sampling circuit (110), thereby allowing digital data before and after the event time to be stored in a fixed (stick) state without being pushed out by the FIFO method. Here, before and after the event time may be a preset time, for example, a time window of several hundred nanoseconds (ns) to several tens of milliseconds (ms) in the past from the event time, and a time window of several nanoseconds (ns) to several milliseconds (ms) in the future from the event time. Specifically, digital data immediately prior to the event is preserved by stopping the data shift operation. Additionally, digital data immediately prior to the event may be included by a delayed storage method. A delayed storage method refers to a method of performing a data shift operation for a predetermined time (several nanoseconds (ns) to several milliseconds (ms)) immediately after the event occurs, and then stopping.

[0151] The noise waveform restoration circuit (130) sequentially reads digital data before and after the occurrence of an event stored in the noise sampling circuit (110) to generate restoration data for restoring to an analog noise waveform or to restore to an analog noise waveform. The analog noise waveform includes noise voltage over time. Unlike cases where noise is simply detected, the analog noise waveform allows for verification of temporal characteristics such as the time of noise occurrence, duration, change in amplitude, and oscillation period, and allows for estimation of the type of cause of the noise through the shape of the waveform. Additionally, it is useful that the noise can be easily visually identified and can be reused as an input signal for testing or simulation.

[0152] The output interface (140) outputs the restored noise waveform. The output interface (140) may be an output terminal, for example, at least one of an I / O pin (Input / Output Pin), a pad, or a package terminal (Leads, Balls, or Bumps). The output interface (140) may be connected to a computing device (500 in FIG. 17) inside or outside the electronic system (1000). The noise waveform may be transmitted to the computing device (500 in FIG. 17). The computing device (500 in FIG. 17) may perform noise measurement, analysis, and management through the transmitted noise waveform.

[0153] Since the specific configuration of the built-in noise management device (100b) according to the embodiment of FIG. 13 is similar to that described in FIG. 3 to FIG. 8, we will refer to FIG. 3 to FIG. 8.

[0154] The noise compensation circuit (180) detects radiated electromagnetic waves (REW) and generates a compensation signal corresponding to the detected radiated electromagnetic waves (REW). In one embodiment, the noise compensation circuit (180) can activate a self-loop (181) using a trigger signal generated by an event detection circuit (120) as an input. When an event occurs, the event detection circuit (120) detects it. The event detection circuit (120) (specifically, the event detector (121)) generates a trigger signal as a result of the event detection. The generated trigger signal is applied to the noise compensation circuit (180), thereby activating the noise compensation circuit (180). The activated noise compensation circuit (180) can generate a compensation signal to perform cancellation and reduction of radiated electromagnetic waves (REW).

[0155] The noise compensation circuit (180) may include a magnetic loop (181) through which at least a portion of the radiated electromagnetic waves (REW) pass, and a compensation circuit (182) connected to the magnetic loop (181) and generating a compensation signal to generate a cancellation electromagnetic wave that cancels out the radiated electromagnetic waves (REW).

[0156] At least one magnetic loop (181) may be provided. Two or more magnetic loops (181) may be provided. The magnetic loop (181) may be circular, but is not limited thereto, and may exist in various shapes as long as it forms a loop when points A and B are connected. In FIG. 13, the magnetic loop (181) is wound once, but is not limited thereto, and the magnetic loop (181) may be wound multiple times.

[0157] The magnetic loop (181) may be a loop through which all or part of the radiated electromagnetic waves (REW) pass. The planar or solid space inside the loop formed by the magnetic loop (181) may be formed so that at least part of the radiated electromagnetic waves (REW) pass through. The magnetic loop (181) is connected to a compensation circuit (182).

[0158] The compensation circuit (182) generates a compensation signal to generate a cancellation electromagnetic wave that cancels out the radiated electromagnetic wave (REW). The compensation circuit (182) may include a negative impedance converter. That is, if the impedance of the short loop is sL, the impedance of the compensation circuit (182) can be set to -sL. Since the cancellation electromagnetic wave generated by the compensation signal is opposite in direction to the radiated electromagnetic wave (REW), the radiated electromagnetic wave (REW) is compensated. That is, since the impedance of the magnetic loop (181) is sL, when the impedance of the compensation circuit (182) is -sL, the total impedance of the noise compensation circuit (180) becomes 0. The current (Iemf') flowing through the noise compensation circuit (180) and the voltage (Vemf') across points A and B can be expressed by the formula Iemf' = Vemf' / (sL - sL). Accordingly, as the current Iemf' flowing through the noise compensation circuit (180) is maximized, the canceling magnetic field is also maximized, so that the radiated electromagnetic waves (REW) can be canceled or reduced.

[0159] FIG. 14 is a block diagram showing an example of the compensation circuit (182) of FIG. 13.

[0160] Referring to FIG. 14, the compensation circuit (182) may include an impedance sensing unit (182L) including one or more inductors, an amplifier circuit (182A) connecting the magnetic loop (181) and the impedance sensing unit (182L) and including one or more amplifiers, and an activation switch (182S) for activating the compensation circuit (182).

[0161] The compensation circuit (182) converts the impedance of the magnetic loop (181) into a negative value. The impedance (-sL) of the compensation circuit (182) as viewed from the magnetic loop (181) may be the negatively inverted value of the impedance (sL) of the magnetic loop (181). Accordingly, the value amplified by the amplification circuit (182A) of the impedance of the impedance sensing unit (182L) including one or more inductors may be the negatively inverted value of the impedance of the magnetic loop (181). The compensation circuit (182) may include a negative impedance converter circuit that senses the impedance of the magnetic loop (181) and simultaneously performs inversion compensation. Alternatively, in the case of an embodiment using two or more magnetic loops (181), the amplification circuit (182A) of the compensation circuit (182) may include at least one of an inverting amplifier circuit, a non-inverting amplifier circuit, or a current amplifier circuit.

[0162] The activation switch (182S) may be connected to an amplification circuit (182A) and / or an impedance detection unit (182L). The activation switch (182S) may be composed of a transistor. The activation switch (182S) receives a trigger signal (VDD_trigger and / or SIG_trigger) from the event detection circuit (120) and activates the compensation circuit (182). The activation switch (182S) may be automatically deactivated after a predetermined compensation holding time has elapsed following the receipt of the trigger signal (VDD_trigger and / or SIG_trigger).

[0163] As such, the built-in noise management device (100b) according to the embodiment of FIG. 13 can not only accurately measure and record the noise waveform induced inside the electronic system (1000) by the radiated electromagnetic waves (REW), but also compensates by effectively canceling or reducing the radiated electromagnetic waves (REW), thereby having the effect of preventing damage to the electronic system (1000) caused by the radiated electromagnetic waves (REW).

[0164] FIG. 15 is a circuit diagram showing part of an embodiment of the compensation circuit (182) of FIG. 14.

[0165] The compensation circuit (182) may include a magnetic loop (181), an impedance sensing unit (182L), an amplification circuit (182A), and an activation switch (182S). FIG. 15 shows an example of the impedance sensing unit (182L) and the amplification circuit (182A) among the compensation circuit (182). FIG. 15 is exemplary, and the impedance sensing unit (182L) and the amplification circuit (182A) can be varied in many ways.

[0166] Additionally, the amplifier circuit (182A) may include a first amplifier circuit (182Aa) and a second amplifier circuit (182Ab). The first amplifier circuit (182Aa) may include an Op-amp (Opa) and two resistors (Rf1, Rf2). More specifically, the positive input terminal of the Op-amp (Opa) is connected to the resistor (Rf1) and the impedance sensing unit (182L) described above. Additionally, the negative input terminal of the Op-amp (Opa) is connected in parallel with point A of the magnetic loop (181) and the resistor (Rf2). Additionally, the output terminal (Vao) of the Op-amp (Opa) is connected in parallel with the resistor (Rf1) and the resistor (Rf2). That is, the output terminal (Vao) of the Op-amp (Opa) is fed back to the negative input terminal through the resistor (Rf2). Additionally, one end of the resistor (Rf1) is connected to the impedance sensing unit (182L), and the other end is connected to the output terminal (Vao). One end of the resistor (Rf2) is connected in parallel with point A and the negative input terminal of the magnetic loop (181), and the other end is connected to the output terminal (Vao).

[0167] Likewise, the second amplifier circuit (182Ab) may include an Op-amp (Opb) and two resistors (Rf1, Rf2). More specifically, the positive input terminal of the Op-amp (Opb) is connected to resistor (Rf1) and the impedance sensing unit (182L). Additionally, the negative input terminal of the Op-amp (Opb) is connected to point B of the magnetic loop (181) and resistor (Rf2). Additionally, the output terminal (vout) of the Op-amp (Opb) is connected to resistor (Rf1) and resistor (Rf2). Furthermore, one end of resistor (Rf1) is connected to the impedance sensing unit (182L), and the other end is connected to the output terminal (Vbo). Additionally, one end of resistor (Rf2) is connected to point B of the magnetic loop (181) and the output terminal (Vbo).

[0168] The input impedance (Zin) viewed from the impedance detection unit (182L), that is, the impedance of the impedance detection unit (182L) and the amplification circuit (182A), is the negatively inverted value obtained by multiplying Zt by Rf2 / Rf1, where Zt is the impedance of the impedance detection unit (182L) including the resistor (Rt) and the inductor (Lt).

[0169] Accordingly, if an inductor is provided in the impedance sensing unit (182L), the impedance value (Zt) of the impedance sensing unit (182L) and the values ​​of resistance (Rf1) and resistance (Rf2) can be adjusted so that the input impedance (Zin) becomes Zin = -sL.

[0170] FIG. 16 is a circuit diagram showing an embedded noise management device (100c) according to another embodiment including two or more magnetic loops (181).

[0171] Since the specific configuration of the built-in noise management device (100c) according to the embodiment of FIG. 16, excluding the noise compensation circuit (180c), is similar to that described in FIG. 13 for the built-in noise management device (100b) according to the embodiment of FIG. 13, we will refer to FIG. 13. Below, the noise compensation circuit (180c) will be described in detail.

[0172] The noise compensation circuit (180c) includes a magnetic loop (181c) and a compensation circuit (182c). The magnetic loop (181c) may include at least a sensing loop (181s) and a compensation loop (181i).

[0173] The sensing loop (181s) is connected to the noise sampling circuit (110) and the event detection circuit (120) to receive a noise signal from the noise sampling circuit (110) and a trigger signal from the event detection circuit (120). Additionally, the sensing loop (181s) is also connected to the input terminal of the compensation circuit (182).

[0174] The compensation circuit (182c) may include an amplifier (182a). The amplifier may be a non-inverting amplifier, but is not limited thereto, and may also utilize an inverting amplifier or a current-type amplifier. The compensation circuit may further include resistors (Rf3, Rf4) connected to the amplifier. The resistors can adjust the gain of the compensation current generated in the compensation circuit. The compensation current flows through the compensation loop (181i) to generate a compensation magnetic field, which can cancel out radiated noise.

[0175] The compensation loop (181i) is connected to the output terminal of the compensation circuit (182c) and can receive compensation current from the compensation circuit (182c). The compensation loop (181i) may be a loop through which all or part of the radiated electromagnetic waves (REW) pass. The planar or three-dimensional space inside the loop formed by the compensation loop (181i) may be formed so that at least part of the radiated electromagnetic waves (REW) pass through. The compensation loop (181i) may be arranged to overlap with the sensing loop (181s).

[0176] The built-in noise management devices (100, 100a, 100b) according to the embodiments disclosed in FIGS. 1 to 14 can all be mounted inside an electronic system (1000).

[0177] FIG. 17 is a schematic diagram illustrating a noise management system (900) according to an embodiment of the present disclosure.

[0178] Referring to FIG. 17, the noise management system (900) may include at least one built-in noise management device (100, 100a, 100b) according to an embodiment or at least one electronic system (1000) according to an embodiment (including the built-in noise management device (100, 100a, 100b)), and a computing device (500) connected thereto via a network (300). FIG. 17 illustrates first to fifth built-in noise management devices (101, 102, 103, 104, 105), but the number thereof is not limited thereto.

[0179] As the built-in noise management device (100, 100a, 100b) and the electronic system (1000) including the same have been described in FIGS. 1 to 14, please refer to them.

[0180] The network (300) may include a Local Area Network (LAN), a Wide Area Network (WAN), a Value Added Network (VAN), a mobile radio communication network, a satellite communication network, and combinations thereof. Additionally, the network (300) is a data communication network in a comprehensive sense that enables each network constituent entity to communicate smoothly with one another, and may include wired internet, wireless internet, and mobile wireless communication networks. Furthermore, wireless communication may include, for example, wireless LAN (Wi-Fi), Bluetooth, Bluetooth Low Energy, Zigbee, WFD (Wi-Fi Direct), UWB (ultra wideband), infrared communication (IrDA, infrared Data Association), NFC (Near Field Communication), but is not limited thereto.

[0181] The computing device (500) receives data for restoration and / or noise waveforms from the built-in noise management device (100) via the network (300) and monitors them. When the computing device (500) receives data for restoration from the noise management device (100), it can convert it into an analog noise waveform. The computing device (500) is not limited to any specific implementation form as long as it is a device capable of receiving and monitoring data from the built-in noise management device (100) via the network (300). For example, the computing device (500) can be implemented as a desktop computer, laptop, tablet, smartphone, server, etc.

[0182] The computing device (500) may include an artificial intelligence (AI) algorithm. The computing device (500) can analyze in real time data for restoration and / or noise waveforms received from at least one built-in noise management device (101, 102, 103, 104, 105) through the AI ​​algorithm, and distinguish between abnormal waveforms and normal waveforms or determine the cause of an event. The AI ​​algorithm can distinguish between abnormal waveforms and normal waveforms or determine the cause of an event by analyzing feature values ​​including the rise time of the noise waveform, voltage magnitude, amplitude of the waveform, frequency components, high voltage duration, etc. For example, the computing device (500) can distinguish between an abnormal waveform where an event has occurred and a normal waveform where no event has occurred through the analysis of the feature values ​​of the noise waveform. As another example, the computing device (500) can automatically determine whether the event is caused by electrostatic discharge (ESD), high-power electromagnetic waves (HPEM), or a power surge.

[0183] Artificial intelligence algorithms can apply Convolutional Neural Networks (CNN) models, Recurrent Neural Networks (RNN) models, Long Short-Term Memory (LSTM) network models, Transformer-based models, etc., which are suitable for waveform analysis. For example, based on time-series data of received noise waveforms, the AI ​​algorithm analyzes the local shape of the noise waveform using a CNN model and learns the noise occurrence pattern over time using an LSTM network model. Through this, it is possible to automatically distinguish events caused by other factors.

[0184] FIG. 18 is a block diagram of a computing device (500) according to one embodiment.

[0185] Referring to FIG. 18, the computing device (500) may include a communication unit (510), a processor (520), and a DB (530). Only the components related to the embodiment are shown in the computing device (500) of FIG. 18. Therefore, a person skilled in the art will understand that other general-purpose components may be included in addition to the components shown in FIG. 18.

[0186] The communication unit (510) may include one or more components that enable wired / wireless communication with other nodes. For example, the communication unit (510) may include at least one of a short-range communication unit (not shown), a mobile communication unit (not shown), and a broadcast receiving unit (not shown).

[0187] DB (530) is hardware that stores various data processed within the computing device (500) and can store programs for processing and controlling the processor (520). DB (530) can store payment information, user information, etc.

[0188] DB (530) may include RAM (random access memory), such as DRAM (dynamic random access memory) and SRAM (static random access memory), ROM (read-only memory), EEPROM (electrically erasable programmable read-only memory), CD-ROM, Blu-ray or other optical disc storage, HDD (hard disk drive), SSD (solid state drive), or flash memory.

[0189] The processor (520) controls the overall operation of the computing device (500). For example, the processor (520) can control the input unit (not shown), display (not shown), communication unit (510), DB (530), etc., by executing programs stored in the DB (530). The processor (520) can control the operation of the computing device (500) by executing programs stored in the DB (530).

[0190] The processor (520) may be implemented using at least one of ASICs (application specific integrated circuits), DSPs (digital signal processors), DSPDs (digital signal processing devices), PLDs (programmable logic devices), FPGAs (field programmable gate arrays), controllers, microcontrollers, microprocessors, and other electrical units for performing functions.

[0191] Although the present disclosure has been described with reference to an embodiment illustrated in the drawings, this is merely illustrative and those skilled in the art will understand that various modifications and variations of the embodiment are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

[0192] This invention is embedded within an electronic system to measure, record, and analyze noise induced by radiated electromagnetic waves in real time, and can even perform compensation as needed, making it applicable to various electronic devices and systems. In particular, it can be usefully utilized for improving reliability and analyzing the causes of failures across industries requiring electromagnetic immunity, such as drones, automotive electronic systems, communication equipment, data centers, industrial control systems, and medical electronic equipment. Furthermore, when combined with network-based monitoring and artificial intelligence analysis, it holds significant industrial value in the fields of maintenance, quality control, and safety assurance for large-scale electronic systems.

Claims

1. An embedded noise management device disposed inside an electronic system and managing noise induced in the electronic system by radiated electromagnetic waves generated by an electrical stress event, The above-mentioned built-in noise management device A noise sampling circuit that detects and samples a noise signal corresponding to the above-mentioned radiated electromagnetic waves in real time, converts it into digital data, and then sequentially stores the digital data through a data shift operation; An event detection circuit that determines an event when a noise signal exceeding a threshold is detected and stops the data shift operation of the noise sampling circuit; and A noise waveform restoration circuit that sequentially reads digital data before and after the occurrence of the event stored in the noise sampling circuit and generates restoration data for restoring it into an analog noise waveform; An embedded noise management device including 2. In Paragraph 1, The above-mentioned built-in noise management device An embedded noise management device mounted on a printed circuit board having at least one computer chip that controls the above electronic system.

3. In Paragraph 2, The above-described built-in noise management device is electrically connected to the computer chip and manages a noise signal induced in the computer chip in response to the radiated electromagnetic waves.

4. In Paragraph 2, The above-described built-in noise management device is a built-in noise management device that receives the radiated electromagnetic waves through the printed circuit board.

5. In Paragraph 1, The above-described built-in noise management device is a built-in noise management device that receives the radiated electromagnetic waves through a frame that fixes or supports the internal components of the electronic system.

6. In Paragraph 1, An antenna electrically connected to the above-mentioned built-in noise management device and receiving the above-mentioned radiated electromagnetic waves; An integrated noise management device further including 7. In Paragraph 1, The above noise sampling circuit is, A sensing input that detects the noise signal corresponding to the above-mentioned radiated electromagnetic waves in real time; Input buffer circuit that attenuates the detected noise signal; An analog-to-digital conversion circuit that samples an attenuated noise signal in real time and converts it into digital data; and A shift register that sequentially stores converted digital data through a data shift operation; An embedded noise management device including 8. In Paragraph 7, The above event detection circuit is An event detector that determines the event based on whether a noise signal detected in real time from the above sensing input has exceeded a threshold value; and A hold circuit that generates a hold signal to stop the data shift operation of the shift register when the above event occurs as a result of judgment; An embedded noise management device including 9. In Paragraph 8, The above noise waveform recovery circuit is A counter circuit that sequentially reads digital data before and after the occurrence of the event stored in the shift register and generates restoration data to restore the digital data into an analog noise waveform; An embedded noise management device including 10. In Paragraph 7, The above-mentioned built-in noise management device A power circuit that receives power from an external source and generates internal power to operate at least the above-mentioned built-in noise management device; An integrated noise management device further including 11. In Paragraph 1, The above-mentioned built-in noise management device A noise compensation circuit that detects the above-mentioned radiated electromagnetic waves and generates and provides a compensation signal corresponding to the detected radiated electromagnetic waves; An integrated noise management device further including 12. In Paragraph 11, The above noise compensation circuit is One or more magnetic loops through which at least a portion of the above-mentioned radiated electromagnetic waves pass; and A compensation circuit connected to the above magnetic loop and generating a compensation signal for generating a cancellation electromagnetic wave to cancel out the above radiated electromagnetic wave; An embedded noise management device including 13. An electronic system comprising an embedded noise management device according to any one of paragraphs 1 to 12.

14. At least one built-in noise management device according to any one of claims 1 to 12; and A computing device that receives the restoration data from the built-in noise management device via a network, converts it into a noise waveform, and monitors it; A noise management system including

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