Superconducting digital circuit synthesizer for pulse conservative logic

Abstract

An example digital circuit includes a plurality of Josephson junctions interconnected according to a netlist that defines one or more logic gates. The digital circuit also includes a clock source connected to each of the plurality of Josephson junctions and configured to generate a multiphase bias signal used to bias each of the plurality of Josephson junctions. Each of the Josephson junctions is biased by an assigned phase within the multiphase bias signal based on a logical position of a respective Josephson junction within the netlist. For each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal.

Description

Superconducting Digital Circuit Synthesizer for Pulse Conservative Logic FIELD OF THE DISCLOSURE

[0001] This disclosure relates to superconducting circuits. In particular, this disclosure relates to a digital circuit synthesizer for superconducting digital (SCD) technology, including pulse conservative logic (PCL)-based circuits.BACKGROUND

[0002] Conventional digital circuits make use of complementary metal-oxide semiconductor (CMOS) technology to provide digital logic functionality. Recent developments have provided a more power efficient, higher-bandwidth, and denser solution: SCD technology, including PCL, which makes use of Josephson single flux quantum (SFQ) pulses, while retaining compatibility with existing electronic design automation (EDA) tools, such as those used for circuit design and fabrication.

[0003] However, SCD circuits, such as those implementing PCL, are often wave-pipelined using a multiphase alternating current (AC) clock signal. Therefore, additional processing is required during the EDA process to synthesize an SCD netlist (i.e. list of components in the circuit and their connections) from a hardware description.SUMMARY

[0004] The embodiments herein relate to a process for the conversion of a CMOSbased gate-level netlist to an SCD netlist, which bridges a gap in the standard EDA flow when applied to SCD circuits.

[0005] In a first aspect, a digital circuit is provided. The digital circuit includes a plurality of Josephson junctions interconnected according to a netlist that defines one or more logic gates. The digital circuit also includes a clock source connected to each of the plurality of Josephson junctions and configured to generate a multiphase bias signal used to bias each of the plurality of Josephson junctions. Each of the Josephson junctions is biased by anassigned phase within the multiphase bias signal based on a logical position of a respective Josephson junction within the netlist. For each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal.

[0006] In a second aspect, a method for electronic design automation (EDA) of a digital circuit is provided. The method includes receiving a netlist defining one or more logic gates. The digital circuit includes a plurality of Josephson junctions interconnected according to the netlist. The method also includes determining an assigned phase within a multiphase bias signal for each of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions. A clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephson junctions. For each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal. The method also includes associating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.

[0007] In a third aspect, anon-transitory machine-readable medium is provided. The non-transitory machine-readable medium stores instructions which when executed by at least one processor of at least one computing system, causes the system to perform operations. The operations include receiving a netlist defining one or more logic gates. The digital circuit includes a plurality of Josephson junctions interconnected according to the netlist. The operations also include determining an assigned phase within a multiphase bias signal foreach of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions. A clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephson junctions. For each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal. The operations also include associating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.BRIEF DESCRIPTION OF THE FIGURES

[0008] The above, as well as additional features, will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0009] Figure 1 illustrates an overview of the design flow for SCD circuits, in accordance with example embodiments.

[0010] Figure 2A illustrates several phases of an AC bias signal, in accordance with example embodiments.

[0011] Figure 2B illustrates several groups of Josephson junctions, each associated with a phase of the AC bias signal of Figure 2A, in accordance with example embodiments.

[0012] Figure 3 illustrates an example process for phase assignment for a netlist, in accordance with example embodiments.

[0013] Figure 4A illustrates an example circuit netlist, in accordance with example embodiments.

[0014] Figure 4B illustrates the circuit netlist of Figure 4A after phase assignment has been performed, in accordance with example embodiments.

[0015] Figure 4C illustrates the circuit netlist of Figure 4B after phase matching has been performed, in accordance with example embodiments.

[0016] Figure 4D illustrates the circuit netlist of Figure 4C as an SCD netlist, in accordance with example embodiments.

[0017] Figure 5A illustrates an example of a dual-rail signal, in accordance with example embodiments.

[0018] Figure 5B illustrates an example dual-rail circuit, in accordance with example embodiments.

[0019] Figure 5C illustrates a further example dual-rail circuit, in accordance with example embodiments.

[0020] All the figures are schematic, not necessarily to scale, and generally only show parts that are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.DETAILED DESCRIPTION

[0021] Various examples of systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as being an example is not necessarily to be construed as preferred or advantageous over any other embodiment, implementation, and / or feature unless stated as such. Thus, other embodiments, implementations, and / or features may be utilized, and other changes may be made without departing from the scope of the subject matter presented herein.

[0022] Accordingly, the examples described herein are not meant to be limiting. It will be readily understood that the aspects of the present disclosure, as generally describedherein, and illustrated in the figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0023] Further, unless the context suggests otherwise, the features illustrated in each of the figures may be used in combination with one another. Thus, the figures should be generally viewed as component aspects of one or more overall embodiments, with the understanding that not all illustrated features are necessary for each embodiment.

[0024] Additionally, any enumeration of elements, blocks, or steps in this specification or the claims is for purposes of clarity. Thus, such enumeration should not be interpreted to require or imply that these elements, blocks, or steps adhere to a particular arrangement or are carried out in a particular order.

[0025] Moreover, terms such as “substantially” or “about” that may be used herein are meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those skilled in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0026] Further, terms such as “A coupled to B,” “A electrically coupled to B,” “A connected to B,” “A electrically connected to B” etc., do not necessarily mean that items A and B are directly coupled to one another. For example, a first component electrically coupled to a second component is interpreted to mean that the components are either directly coupled (e.g., via a conductor) or coupled to one another via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0027] The potential of superconducting digital technology as a beyond-CMOS technology derives from high energy efficiency, high computational density, and high interconnect bandwidth. Some forms of the technology are based on the SFQ pulse, which is fast, low power, and low-dispersion / low-loss on superconductor transmission lines. Exampleembodiments involve various combinations of fabrication materials, density, power / clock distribution, logic and memory design, packaging, interfaces, and architecture.Electronic Design Automation (EDA) for Superconducting Digital Circuits

[0028] One part of the EDA process is logic synthesis. In the context of digital integrated circuits (ICs), logic synthesis may include generating a gate-level netlist (i.e. a description of all of the electronic components in a circuit and their interconnections) based on a behavioral or structural description of the circuit written in a hardware description language (HDL), such as Verilog or VHDL.

[0029] In some design flows, logic synthesis may use a cell library described in a Liberty (.lib) fde format in combination with a design constraints fde, in addition to the HDL input.

[0030] figure 1 is a flowchart depicting several steps in an EDA process 100 for SCD circuits, including logic synthesis.

[0031] The process 100 begins with a design specification 102 for a circuit. The design specification 102 is then written in a hardware description language (HDL) 104, such as Verilog or VHDL, which produces a register-transfer level (RTL) design 106.

[0032] Following RTL design 106, logic synthesis may be performed. Digital synthesis 108 occurs first to produce a gate-level netlist 110 from the RTL design 106. This gate-level netlist 110 is similar to a netlist generated using CMOS or other common digital circuit components. Then, to convert this design into an SCD circuit, SCD synthesis 112 is performed on the gate-level netlist 110. SCD synthesis 112 may involve constructing logic gates and other components using SCD components (e.g., Josephson junctions). This results in an SCD netlist 114.

[0033] As noted above, however, SCD circuits are often wave-pipelined using a multiphase AC clock signal. Thus, to assign proper phases to the components within the SCDnetlist 114, additional processing may occur as part of SCD synthesis 112. It is with this processing that this disclosure is primarily concerned, and methods for efficient phase assignment and phase matching as part of the SCD synthesis 112 process will be described in further detail below.

[0034] Following the production of an SCD netlist 114 containing assigned phases for each of the Josephson junctions or other SCD components, an SCD placer 116 may recommend locations on a chip where a component may be placed during fabrication (e.g., to maintain appropriate phase relationships). This produces a cell placement 118.

[0035] Following the placement step, fixed inductance routing 120 may be performed to route wires between the components placed in the previous step, which produces a routing 122.

[0036] After the aforementioned steps, the EDA process 100 may provide a layout 124, which may be utilized for the manufacturing of a physical SCD-based circuit.Phase Assignment and Matching in Logic Synthesis for Superconducting Digital Circuits

[0037] As noted above, SCD circuits, including those that implement PCL and Josephson junctions, are often wave-pipelined using a multiphase AC clock signal. In effect, this means that changes in the state of circuit components may be based off of changes in the clock signal. For instance, a Josephson junction may only output a signal on the leading or trailing edge of the clock signal.

[0038] Some Josephson junctions are biased using eight phases of a 30 GHz clock at a 45° phase angle. For instance, such an eight-phase setup may result in Josephson junctions biased at 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°. However, this is just one example of the clock frequency, number of phases, and phase angles. Different values of each, and different combinations thereof, may also be used in some embodiments.

[0039] In the SCD synthesis process, phase assignment determines which phase of the clock signal is used to drive each Josephson junction in the circuit. In general, an input signal will only trigger a Josephson junction if the waveform of the signal is near peak amplitude. This phenomenon imposes a limit on the number of consecutive Josephson junctions that may use the same clock phase, as Josephson junctions at the end of the sequence may receive the input signal when the peak of the waveform has already passed, and thus the amplitude may be too small to trigger the Josephson junction. Further, when too many Josephson junctions are assigned to the same clock phase, undesired backaction within linear circuits and timing issues may result.

[0040] This phenomenon is illustrated in Figure 2A. From left to right in Figure 2A, several waveforms are depicted: 0°, 45°, 90°, 135°, and 180°. As shown, using a 45° phase angle, phases begin to overlap at around five junctions (represented by the dots on each waveform). The solid horizontal line across the middle of Figure 2A represents a positive switching threshold (e.g., a positive AC bias level corresponding to the threshold at which a Josephson junction will be triggered).

[0041] Figure 2B depicts a series of five Josephson junctions (components with the “X”) associated with each of the first three phases depicted in Figure 2A. From left to right, the first five Josephson junctions are associated with 0°, the next five are associated with 45°, and the last five are associated with 90°.

[0042] To mitigate the issues described above, a limit is set on the number of consecutive Josephson junctions that are powered by the same phase. For instance, if there is a sequence of five Josephson junctions powered by a 0° clock, the sixth Josephson junction would be powered by the next phase (e.g., 45°).

[0043] These parameters, including operating frequency, number of phases, and Josephson junctions per phase may vary based on different circuit conditions, including butnot limited to wire inductance and resistance within the circuit; the values above are merely given as examples.

[0044] Assigning these phases to each Josephson junction in a complex digital circuit is a challenging issue. To address this, methods disclosed herein for phase assignment take in a netlist (e.g., a gate-level netlist 110 produced by digital synthesis 108) and output a netlist with phase mapping (e.g., an SCD netlist 114). Essentially, example methods may assign phases based on the logical position of a particular Josephson junction within the netlist. The assignment may also be based on the phase values of Josephson junctions “nearby” within the netlist that are within a predetermined number of consecutive logical positions. For instance, a Josephson junction may only be assigned a phase that is the same as the phase of a connected Josephson junction, unless the predetermined number of Josephson junctions being biased by the same phase would be exceeded, as discussed above. Other connection rules may also be implemented. For instance, each input to a Josephson-junction implemented logic gate or other component may be matched with a phase that is capable of triggering such a Josephson junction.

[0045] An example block diagram of one example method for performing phase assignment is depicted in Figure 3. Block 302 may involve creating a priority queue (Q) that is empty. Block 304 may involve creating a map (i.e. a map, hash table, or other similar data structure) to store the delay value (i.e., the logical position within the netlist) for each pin of each component within the netlist. During setup, this delay value for each pin is set to a small value, for instance negative infinity.

[0046] Block 306 may involve creating a start pin that logically connects to every input pin of the circuit within the netlist. The delay value of the start pin is initially set to zero, and this pin (represented as a node with its associated delay value) is inserted into Q.

[0047] After these setup steps, block 308 may involve determining whether Q is empty. If Q is not empty, the process may proceed to block 310, which may involve selecting the node in Q with the largest delay value and removing this node from Q.

[0048] Block 312 may involve recalculating the delay for neighboring pins to the selected node. The process for doing so may differ depending on if the node represents an input or output pin.

[0049] Block 314 may involve updating the delay value within the delay map for each of the neighboring pins as recalculated at block 312. If the recalculated delay value is larger than the existing delay value for a particular neighboring pin, the delay value in the map may be overwritten with the larger value. This neighboring pin and its corresponding value are then inserted into Q as a node.

[0050] At this point, the process returns to block 308 to again determine if Q is empty, and proceeds as above.

[0051] If, at block 308, it is determined that Q is empty, the process may proceed to block 318. Block 318 may involve calculating the phase for each pin within the netlist. In some embodiments, the calculated phase may be the delay value for a pin divided by a predetermined number.

[0052] Block 320 relates to adjusting the assigned phases based on ensuring that each Josephson junction is matched with a phase that is capable of triggering the Josephson junction. For instance, if, during assignment, a two sequential Josephson junctions have a 0° phase and a 90° phase, and additional Josephson junction component (e.g., a buffer), may be added between them with a 45° phase to ensure compliance with the phase assignment rules.

[0053] Pseudocode implementing the example method of performing phase assignment depicted in Figure 3 is recited below:Algorithm Phase_Assignment (Netlist) :Input : Netlist, a gate-level hardware description of digital circuitOutput : Phase_map denotes the phase to use for every cell pin in the NetlistCreate a priority queue Q to hold all pins , initially emptyCreate a map di s t where each cell pin v has a distance value, initially set to negative INFINITYCreate an empty cell with one input pin (start_pin) that connects to every input of the circuit .Add start_pin to Q with a distance of 0dist [start_pin] = 0While Q is not empty:u = node in Q with the largest delay in dist [ ]Remove u from QFor each recipient v of u:If v is an input pin:alt = dist fu] + wire_delay (u, v)If v is an output pin:alt = dist fu] + cell_delay (u, v)If alt > dist [v] :dist [v] = altadd v to QFor each cell in Netlist :For each pin of cell :phase = dist [pin] / / j j s_per_phaseclicks = (dist [pin] % j j s_per_phase )Phase_map [pin] = (phase, clicks )Return Phase_map

[0054] Further, pseudocode for performing the phase matching process discussed above with regard to block 320 of Figure 3 is provided below:Algorithm Phase_Match (Netlist, Phase_map) :Input : Netlist, a gate-level hardware description of a digital circuit with initial phase assignmentOutput : Modified Netlist with phase assignmentFor each cell in Netlist :Max_phase, Max_click = max (Phase_map [cell_input_pins] )For each input_pin in cell :Pin_phase, Pin_click = Phase_map [input_pin]If Pin_phase + 1 < Max_phase :Add JJs before input_pin until phase equal to Max_phase Return the modified Netlist

[0055] Figures 4A-4D depict an example netlist as it goes through the phase assignment and matching process described above.

[0056] Figure 4A depicts an unmodified gate-level netlist of a CMOS-type circuit. This circuit has five input pins (402A, 402B, 402C, 402D, and 402E), three buffers (404A, 404B, and 404C), two AND gates (406A and 406B), and one OR gate (408), all interconnected as shown in Figure 4A.

[0057] Figure 4B depicts the netlist after phase assignment. The numbers in each of the logic gates and buffers represent the number of Josephson junctions from input to output within that particular component. A start pin 410 is shown as connected to each of the input pins 402A, 402B, 402C, 402D, and 402E.

[0058] Figure 4C depicts the netlist after phase matching, where an additional buffer (404D) has been added between buffer 404A and AND gate 406B in order to ensure the correct arrangement of phases and that all phase assignment rules have been followed, as discussed above.

[0059] The inputs and outputs of each component in Figures 4B and 4C are labeled with a pair of numbers, for example 0-0 in the case of input pin 402D. The two numbers represent the phase and index of a Josephson junction within the phase. For example, using the example above with eight phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, a value of 0-0 would represent a 0° phase and the first sequential Josephson junction of that phase. Both values use a zero-based index (i.e., the count starts at zero). Thus, a value of 2-1 would represent a 90° phase (the third phase) and the second sequential Josephson junction of that phase. Continuing the above example, if a maximum of five sequential Josephson junctions are allowed, the second value would increment from 0 to 4, again using zero-based indexing.

[0060] Figure 4D depicts the final SCD netlist, with each component (buffer and logic gate) expanded into its equivalent Josephson junction implementation. As shown, some components may be implemented as groups of parallelized, interconnected Josephson junctions. Additionally, sequential Josephson junctions are numbered to demonstrate that,following the example above, no more than five (5) sequential Josephson junctions are biased using the same phase. The numbering (using a zero-based index) for the expanded components represent the count of sequential Josephson junctions per phase - an asterisk (*) represents a 0° phase, a caret (A) represents a 45° phase, and a plus (+) represents a 90° phase.

[0061] Additionally, in the final SCD netlist as depicted in Figure 4D, the start pin 410 is removed, as it functions as a logical starting position for the phase assignment process and is not intended for actual use in the final circuit.Dual-Rail Conversion for Superconducting Digital Circuits

[0062] PCL-based SCD circuits generally represent signals using SFQ pulses. Logical ‘ 1 ’ is represented using a positive SFQ that transitions the superconducting phase high, and Logical ‘0’ is represented by a negative SFQ that transitions the superconducting phase low.

[0063] Positive and negative transitions are generally separated by half a clock cycle due to AC power, and this phenomenon can make logic inversion more challenging compared to conventional voltage level-based representation. Therefore, PCL implements dual-rail signaling to efficiently implement logical inversion. This involves a process where each single-ended signal (A) is converted to two signals which represent the signal (A) and inverted (or complementary) signal (A).

[0064] This relationship is illustrated in Figure 5A, where the solid line represents an AC power waveform P, the dotted line represents A, and the dashed line represents A. As shown, each contains two rails that are inverses of the main signal.

[0065] Figure 5B represents an example dual-rail circuit, in particular a full adder cell.

[0066] Converting a circuit from single to dual-rail requires duplicating each pin within the netlist. An example of this duplication is depicted in Figure 5C, duplicating each component of the circuit discussed above with regards to Figure 4A-4D. For instance, inputpins 402A, 402B, 402C, 402D, and 402E each have a duplicated input pin 402F, 402G, 402H, 4021, and 402J, respectively, while each buffer and logic gate has its inputs and outputs duplicated as well.

[0067] Pseudocode implementing an example method of single to dual-rail conversion is provided below, by taking as input a netlist and returning a modified netlist: Algorithm Single_to_dual_rail (Netlist) :Input : Netlist, a gate-level hardware description of digital circuit Output : Modfied NetlistFor each net in Netlist :Create a new net Inv_net in NetlistInv_net . setlnvNet (net )Net . setlnvNet ( Inv_net )For each cell in Netlist :For each pin of cell :Create a new pin Inv_pin in CellInv_net = pin . get_connected_net ( ) . getlnvNet ( )If pin is an input pin:Inv_net. add_load ( Inv_pin)Else if pin is an output pin:Inv_net . add_driver ( Inv_pin)For each port in Netlist :Create a new port Inv_port in NetlistInv_net = port . get_connected_net ( ) . getlnvNet ( )If port is an input port :Inv_net . addDriver ( Inv_port )Else if port is an output port :Inv_net . addLoad ( Inv_port )Return the modified NetlistEnumerated Example Embodiments

[0068] Embodiments of the present disclosure may thus relate to one of the enumerated example embodiments (EEEs) listed below.

[0069] EEE 1 includes a digital circuit comprising:a plurality of Josephson junctions interconnected according to a netlist that defines one or more logic gates; anda clock source connected to each of the plurality of Josephson junctions and configured to generate a multiphase bias signal used to bias each of the plurality of Josephson junctions, wherein each of the Josephson junctions is biased by an assigned phase within themultiphase bias signal based on a logical position of a respective Josephson junction within the netlist, and wherein for each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal.

[0070] EEE 2 includes the digital circuit of EEE 1, wherein the multiphase bias signal has an operational frequency of 20-40 GHz.

[0071] EEE 3 includes the digital circuit of either EEE 1 or EEE 2, wherein the predetermined number of consecutive logical positions is five (5).

[0072] EEE 4 includes the digital circuit of any of EEEs 1-3, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

[0073] EEE 5 includes the digital circuit of EEE 4, wherein the dual -rail configuration is configured to transmit a signal along a first rail and complementary signal of the signal along a second rail.

[0074] EEE 6 includes a method for electronic design automation (EDA) of a digital circuit comprising:receiving a netlist defining one or more logic gates, wherein the digital circuit comprises a plurality of Josephson junctions interconnected according to the netlist;determining an assigned phase within a multiphase bias signal for each of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions, wherein a clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephson junctions, and wherein foreach phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal; andassociating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.

[0075] EEE 7 includes the method of EEE 6, further comprising:determining an initial delay value of the respective Josephson junction based on the interconnections defined within the netlist;determining a revised delay value for the respective Josephson junction based on the assigned phase within the multiphase bias signal associated with the respective Josephson junction; andinserting one or more additional Josephson junctions into the netlist at positions logically adjacent to the respective Josephson junction based on a difference between the revised delay value and the initial delay value.

[0076] EEE 8 includes the method of either of EEE 6 or EEE 7, wherein the multiphase bias signal has an operational frequency of 20-40 GHz, and wherein the predetermined number of consecutive logical positions is five (5).

[0077] EEE 9 includes the method of any of EEEs 6-8, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

[0078] EEE 10 includes the method of EEE 9, wherein the dual -rail configuration is configured to transmit a signal along a first rail and a complementary signal of the signal along a second rail.

[0079] EEE 11 includes a non-transitory machine-readable medium storing instructions, which when executed by at least one processor of at least one computing system, causes the system to perform operations comprising:receiving a netlist defining one or more logic gates of a digital circuit, wherein the digital circuit comprises a plurality of Josephson junctions interconnected according to the netlist;determining an assigned phase within a multiphase bias signal for each of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions, wherein a clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephson junctions, and wherein for each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal; andassociating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.

[0080] EEE 12 includes the non-transitory machine-readable medium of EEE 11, wherein the operations further comprise, for each of the plurality of Josephson junctions: determining an initial delay value of the respective Josephson junction based on the interconnections defined within the netlist;determining a revised delay value for the respective Josephson junction based on the assigned phase within the multiphase bias signal associated with the respective Josephson junction; andinserting one or more additional Josephson junctions into the netlist at positions logically adjacent to the respective Josephson junction based on a difference between the revised delay value and the initial delay value.

[0081] EEE 13 includes the non-transitory machine-readable medium of either EEE 11 or EEE 12, wherein the multiphase bias signal has an operational frequency of 30 GHz, and wherein the predetermined number of consecutive logical positions is five (5).

[0082] EEE 14 includes the non-transitory machine-readable medium of any of EEEs 11-13, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

[0083] EEE 15 includes the non-transitory machine-readable medium of EEE 14, wherein the dual-rail configuration is configured to transmit a signal along a first rail and an inverse of the signal along a second rail.

[0084] The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those described herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims.

[0085] The above detailed description describes various features and operations of the disclosed systems, devices, and methods with reference to the accompanying figures. The example embodiments described herein and in the figures are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can bearranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0086] With respect to any or all of the message flow diagrams, scenarios, and flow charts in the figures and as discussed herein, each step, block, operation, and / or communication can represent a processing of information and / or a transmission of information in accordance with example embodiments. Alternative embodiments are included within the scope of these example embodiments. In these alternative embodiments, for example, operations described as method steps, blocks, transmissions, communications, requests, responses, and / or messages can be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved. Further, more or fewer blocks and / or operations can be used with any of the message flow diagrams, scenarios, and flow charts discussed herein, and these message flow diagrams, scenarios, and flow charts can be combined with one another, in part or in whole.

[0087] A step, block, or operation that represents a processing of information can correspond to circuitry that can be configured to perform the specific logical functions of a herein-described method or technique. Alternatively or additionally, a step or block that represents a processing of information can correspond to a module, a segment, or a portion of program code (including related data). The program code can include one or more instructions executable by a processor for implementing specific logical operations or actions in the method or technique. The program code and / or related data can be stored on any type of computer-readable medium (or machine-readable medium) such as a storage device including RAM, a disk drive, a solid state drive, or another storage medium.

[0088] The computer-readable medium (or machine -readable medium) can also include non-transitory computer-readable media such as computer-readable media that storedata for short periods of time like register memory and processor cache. The computer-readable media can further include non-transitory computer-readable media that store program code and / or data for longer periods of time. Thus, the computer-readable media may include secondary or persistent long term storage, like ROM, optical or magnetic disks, solid state drives, compact-disc read-only memory (CD-ROM), for example. The computer-readable media can also be any other volatile or non-volatile storage systems. A computer-readable medium can be considered a computer-readable storage medium, for example, or a tangible storage device.

[0089] Moreover, a step, block, or operation that represents one or more information transmissions can correspond to information transmissions between software and / or hardware modules in the same physical device. However, other information transmissions can be between software modules and / or hardware modules in different physical devices.

[0090] The particular arrangements shown in the figures should not be viewed as limiting. It should be understood that other embodiments can include more or less of each element shown in a given figure. Further, some of the illustrated elements can be combined or omitted. Yet further, an example embodiment can include elements that are not illustrated in the figures.

[0091] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purpose of illustration and are not intended to be limiting, with the true scope being indicated by the following claims.

Claims

CLAIMSWhat is claimed is:

1. A digital circuit comprising:a plurality of Josephson junctions interconnected according to a netlist that defines one or more logic gates; anda clock source connected to each of the plurality of Josephson junctions and configured to generate a multiphase bias signal used to bias each of the plurality of Josephson junctions, wherein each of the Josephson junctions is biased by an assigned phase within the multiphase bias signal based on a logical position of a respective Josephson junction within the netlist, and wherein for each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal.

2. The digital circuit of claim 1, wherein the multiphase bias signal has an operational frequency of 20-40 GHz.

3. The digital circuit of claim 1, wherein the predetermined number of consecutive logical positions is five (5).

4. The digital circuit of claim 1, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

5. The digital circuit of claim 4, wherein the dual -rail configuration is configured to transmit a signal along a first rail and complementary signal of the signal along a second rail.

6. A method for electronic design automation (EDA) of a digital circuit comprising: receiving a netlist defining one or more logic gates, wherein the digital circuit comprises a plurality of Josephson junctions interconnected according to the netlist; determining an assigned phase within a multiphase bias signal for each of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions, wherein a clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephson junctions, and wherein for each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal; andassociating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.

7. The method of claim 6, further comprising:determining an initial delay value of the respective Josephson junction based on the interconnections defined within the netlist;determining a revised delay value for the respective Josephson junction based on the assigned phase within the multiphase bias signal associated with the respective Josephson junction; andinserting one or more additional Josephson junctions into the netlist at positions logically adjacent to the respective Josephson junction based on a difference between the revised delay value and the initial delay value.

8. The method of claim 6. wherein the multiphase bias signal has an operational frequency of 20-40 GHz, and wherein the predetermined number of consecutive logical positions is five (5).

9. The method of claim 6, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

10. The method of claim 9, wherein the dual -rail configuration is configured to transmit a signal along a first rail and a complementary signal of the signal along a second rail.

11. A non-transitory machine-readable medium storing instructions, which when executed by at least one processor of at least one computing system, causes the at least one computing system to perform operations comprising:receiving a netlist defining one or more logic gates of a digital circuit, wherein the digital circuit comprises a plurality of Josephson junctions interconnected according to the netlist;determining an assigned phase within a multiphase bias signal for each of the plurality of Josephson junctions based on a logical position of a respective Josephson junction within the netlist and phase values for other Josephson junctions within the plurality of Josephson junctions that are logically separate from the respective Josephson junction within the netlist by at most a predetermined number of consecutive logical positions, wherein a clock source is configured to generate the multiphase bias signal to bias the plurality of Josephson junctions when connected to each of the plurality of Josephsonjunctions, and wherein for each phase of the multiphase bias signal, at most a predetermined number of consecutive logical positions within the netlist are configured to be biased by the phase of the multiphase bias signal; andassociating each of the plurality of Josephson junctions with the respective assigned phase within the multiphase bias signal.

12. The non-transitory machine-readable medium of claim 11, wherein the operations further comprise, for each of the plurality of Josephson junctions:determining an initial delay value of the respective Josephson junction based on the interconnections defined within the netlist;determining a revised delay value for the respective Josephson junction based on the assigned phase within the multiphase bias signal associated with the respective Josephson junction; andinserting one or more additional Josephson junctions into the netlist at positions logically adjacent to the respective Josephson junction based on a difference between the revised delay value and the initial delay value.

13. The non-transitory machine-readable medium of claim 11, wherein the multiphase bias signal has an operational frequency of 30 GHz, and wherein the predetermined number of consecutive logical positions is five (5).

14. The non-transitory machine-readable medium of claim 11, wherein each input interconnection and output interconnection within the digital circuit is duplicated such as to support a dual-rail configuration.

15. The non-transitory machine-readable medium of claim 14, wherein the dual-rail configuration is configured to transmit a signal along a first rail and an inverse of the signal along a second rail.

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