Systems, devices, and methods for digital antenna switching for internet of things gateways and end-nodes and other wireless communication devices

Abstract

A receiver is disclosed. The receiver includes a first receiver path including a first antenna and a first ADC, and a second receiver path including a second antenna and a second ADC. The first receiver path receives a first RF signal and generates a first digital signal from the first RF signal as an output of the first ADC during a first time period. The second receiver path receives a second RF signal and generates a second digital signal from the second RF signal as an output of the second ADC during the first time period. A digital switch selects one of the first receiver path and the second receiver path for connection to a processor, where the processor controls the switch based on the first digital signal and the second digital signal.

Description

Docket No. 62306.224WO01 (P251707-WO-UTL)SYSTEMS, DEVICES, AND METHODS FOR DIGITAL ANTENNA SWITCHING FOR INTERNET OF THINGS GATEWAYS AND END-NODES AND OTHER WIRELESS COMMUNICATION DEVICES RELATED APPLICATIONS

[0001] The present application claims the benefit of U.S. Provisional Application No. 63 / 815,074, filed May 30, 2025 and U.S. Provisional application no. 63 / 753,837, filed February 04, 2025, which are hereby expressly incorporated by reference herein in their entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to systems, devices, and methods for implementing antenna diversity in radio frequency receivers, such as antenna switching in Internet of Things devices.BACKGROUND

[0003] An application-layer connectivity standard known as “Matter” is an example of an important emerging technology for the Internet of Things (loT) and home automation. To improve the range and robustness of conventional Matter-based and other similar devices, low-power and low-cost antenna diversity features may be created. Unfortunately, previous antenna diversity strategies may cause impedance changes that interfere with the correct operation of Wi-Fi chipsets or other chipsets on the same board, particularly in the context of loT gateway and other devices. This has made it difficult to incorporate antenna diversity in many products. Thus, there remains a need for effective ways for implementing antenna diversity to take advantage of potential performance gains while mitigating the aforementioned and other drawbacks in wireless communication devices, such as loT gateways or other loT devices as examples.SUMMARY

[0004] Embodiments of the present disclosure include systems, devices, and methods of digital antenna switching for internet of things gateways and / or end-nodes.

[0005] One inventive aspect is a receiver including a first receiver path including a first antenna and a first analog-to-digital converter (ADC), where the first receiver path is configured to receive a first radio frequency (RF) signal and to generate a first digital signal from the first RF signal as an output of the first ADC during a first time period, a secondDocket No. 62306.224WO01 (P251707-WO-UTL)receiver path including a second antenna and a second ADC, where the second receiver path is configured to receive a second RF signal and to generate a second digital signal from the second RF signal as an output of the second ADC during the first time period, a processor, and a digital switch configured to select one of the first receiver path and the second receiver path for connection to the processor, where the processor is configured to control the switch to select between the first receiver path and the second receiver path for receiving data during a second time period based on the first digital signal and the second digital signal.

[0006] In some embodiments, the first time period is a multiple of the preamble period, and where the processor is further configured to perform a cyclic correlation of the first digital signal to generate a first output, and perform a cyclic correlation of the second digital signal to generate a second output, where the selecting between the first receiver path and the second receiver path is based on the first output and the second output.

[0007] In some embodiments the first receiver path further includes first analog front-end circuitry, where the first antenna, the first analog front-end circuitry, and the first ADC are connected in series, and the second receiver path further includes second analog front-end circuitry, where the second antenna, the second analog front-end circuitry and the second ADC are connected in series.

[0008] In some embodiments, a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry is configured to be toggled on and off in alternating time slots of a plurality of time slots, where the first time period is a first time slot in the plurality of time slots, and where the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal, where the receiver further includes at least one memory, where the at least one memory is configured to store the second digital signal, and where the processor is configured to retrieve the second digital signal and process the second digital signal after processing the first digital signal.

[0009] In some embodiments, the first time period includes a plurality of time slots including a first time slot and a second time slot, where the first digital signal is obtained by tuning the first receiver path to a first channel during the first time slot, where the second digital signal is obtained by tuning the second receiver path to the first channel during the second time slot, and where the first receiver path and the second receiver path are furtherDocket No. 62306.224WO01 (P251707-WO-UTL)configured to tune to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals, and where the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

[0010] In some embodiments, the first analog front-end circuitry includes a first mixer and a first phase lock loop configured to control a first frequency of the first mixer, where the second analog front-end circuitry includes a second mixer and a second phase lock loop configured to control a second frequency of the first mixer, where first receiver path is tuned to a channel by tuning the first frequency, and where the second receiver path is tuned to a channel by tuning the second frequency.

[0011] In some embodiments, the first analog front-end circuitry includes first radio frequency (RF) circuitry, a first mixer, and first intermediate frequency (IF) circuitry connected in series with the first antenna, and where the second analog front-end circuitry includes second RF circuitry, a second mixer, and second IF circuitry connected in series with the second antenna.

[0012] Another inventive aspect is a wireless communication device including a transmitter, and a receiver including a first receiver path including a first antenna and configured to receive a first radio frequency (RF) signal and to generate a first digital signal from the first RF signal during a first time period, a second receiver path including a second antenna and configured to receive a second RF signal and to generate a second digital signal from the second RF signal during the first time period, a processor, and a switch configured to select one of the first receiver path and the second receiver path for connection to the processor, where the processor is configured to control the switch to select between the first receiver path and the second receiver path for receiving data during a second time period based on the first digital signal and the second digital signal, and where the transmitter is configured to use the first antenna and the second antenna for transmission.

[0013] In some embodiments, the wireless communication device further includes the first time period is a preamble period, and where the processor is further configured to perform a cyclic correlation of the first digital signal to generate a first output, and perform a cyclic correlation of the second digital signal to generate a second output, where the selectingDocket No. 62306.224WO01 (P251707-WO-UTL)between the first receiver path and the second receiver path is based on the first output and the second output.

[0014] In some embodiments, the wireless communication device further includes the first receiver path further includes first analog front-end circuitry and a first analog-to-digital converter (ADC), where the first antenna, the first analog front-end circuitry, and the first ADC are connected in series, and the second receiver path further includes second analog front-end circuitry and a second ADC, where the second antenna, the second analog front-end circuitry and the second ADC are connected in series, where the first digital signal is based on an output of the first ADC, and where the second digital signal is based on an output of the second ADC.

[0015] In some embodiments, a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry is configured to be toggled on and off in alternating time slots of a plurality of time slots, where the first time period is a first time slot in the plurality of time slots, and where the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal, where the receiver further includes at least one memory, where the at least one memory is configured to store the second digital signal, and where the processor is configured to retrieve the second digital signal and process the second digital signal after processing the first digital signal.

[0016] In some embodiments, the first time period includes a plurality of time slots including a first time slot and a second time slot, where the first digital signal is obtained by tuning the first receiver path to a first channel during the first time slot, where the second digital signal is obtained by turning the second receiver path to the first channel during the second time slot, and where the first receiver path and the second receiver path are further configured to tune to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals, and where the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

[0017] In some embodiments, the wireless communication device further includes the first analog front-end circuitry includes a first mixer and a first phase lock loop controlling a first frequency of the first mixer, where the second analog front-end circuitry includes aDocket No. 62306.224WO01 (P251707-WO-UTL)second mixer and a second phase lock loop controlling a second frequency of the first mixer, where first receiver path is tuned to a channel by tuning the first frequency, and where the second receiver path is tuned to a channel by tuning the second frequency.

[0018] In some embodiments, the first analog front-end circuitry includes first radio frequency (RF) circuitry, a first mixer, and first intermediate frequency (IF) circuitry connected in series with the first antenna, and where the second analog front-end circuitry includes second RF circuitry, a second mixer, and second IF circuitry connected in series with the second antenna.

[0019] Another inventive aspect is a method of operating a receiver including a first receiver path and a second receiver path, the method including receiving a first radio frequency (RF) signal during a first time period by a first antenna, where the first receiver path includes the first antenna, processing the first RF signal by the first receiver path to generate a first digital signal, receiving a second RF signal during the first time period by a second antenna, where the second receiver path includes the second antenna, processing the second RF signal by the second receiver path to generate a second digital signal, selecting between the first receiver path and the second receiver path as a selected receiver path for receiving data during a second time period based on the first digital signal and the second digital signal, and receiving the data during the second time period, by the selected receiver path.

[0020] In some embodiments, the method further includes performing a cyclic correlation of the first digital signal to generate a first output, and performing a cyclic correlation of the second digital signal to generate a second output, where the selecting between the first receiver path and the second receiver path is based on the first output and the second output.

[0021] In some embodiments, the method further includes the first receiver path further includes first analog front-end circuitry and a first analog-to-digital converter (ADC), where the first antenna, the first analog front-end circuitry, and the first ADC are connected in series, and the second receiver path further includes second analog front-end circuitry and a second ADC, where the second antenna, the second analog front-end circuitry and the second ADC are connected in series, the first digital signal is based on an output of the first ADC, and the second digital signal is based on an output of the second ADC.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0022] In some embodiments, the method further includes toggling on and off a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry in alternating time slots of a plurality of time slots, where the first time period is a first time slot in the plurality of time slots, and where the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal, storing the second digital signal, retrieving the second digital signal and processing the second digital signal after processing the first digital signal.

[0023] In some embodiments, the first time period includes a plurality of time slots including a first time slot and a second time slot, where the method further includes tuning the first receiver path to a first channel during the first time slot, tuning the second receiver path to a first channel during the second time slot, and tuning the first receiver path and the second receiver path to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals, where the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

[0024] In some embodiments, the first analog front-end circuitry includes a first mixer and a first phase lock loop configured to control a first frequency of the first mixer, where the second analog front-end circuitry includes a second mixer and a second phase lock loop configured to control a second frequency of the first mixer, where the tuning the first receiver path to the first channel includes tuning the first frequency to the first channel, and where the tuning the second receiver path to the first channel includes tuning the second frequency to the first channel.

[0025] Additional aspects, features, and advantages of the present disclosure will become apparent from the following detailed description.BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0027] Figure 1 is an example block diagram of a receiver, according to some aspects of the present disclosure.

[0028] Figure 2 is an example block diagram of another receiver, according to some aspects of the present disclosure.

[0029] Figure 3 is an example of an antenna switching method, according to some aspects of the present disclosure.

[0030] Figure 4A is an example block diagram of another receiver, and Figure 4B is an example of another antenna switching method, according to some aspects of the present disclosure.

[0031] Figure 5A is an example block diagram another receiver, and Figure 5B is an example of another antenna switching method, according to some aspects of the present disclosure.

[0032] Figure 6 is an example block diagram of an antenna switching method, according to some aspects of the present disclosure.

[0033] Figure 7 illustrates a communication device, according to aspects of the present disclosure.DETAILED DESCRIPTION

[0034] For the purposes of promoting an understanding of the principles of the present disclosure, reference will now be made to the embodiments illustrated in the drawings, and specific language will be used to describe the same. It is nevertheless understood that no limitation to the scope of the disclosure is intended. Any alterations and further modifications to the described devices, systems, and methods, and any further application of the principles of the present disclosure are fully contemplated and included within the present disclosure as would normally occur to one skilled in the art to which the disclosure relates. In particular, it is fully contemplated that the features, components, and / or steps described with respect to one embodiment may be combined with the features, components, and / or steps described with respect to other embodiments of the present disclosure. For the sake of brevity, however, the numerous iterations of these combinations will not be described separately.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0035] Disclosed herein are systems, devices, and methods for radio frequency (RF) antenna path architectures combined with digital antenna switching for, for example, improved co-existence of 802.15.4 communication, such as Zigbee and Matter, with wireless fidelity (Wi-Fi) communication on the same device. The discussed approaches provide improved co-existence, making them effective techniques for emerging devices, such as Gateway devices. In addition, extensions to the approaches are proposed which further improve the antenna diversity architecture in combination with multi-channel listening and radio power duty-cycling.

[0036] The antenna diversity architectures and switching schemes provides better performance than conventional approaches, while providing improved co-existence with, for example, Wi-Fi chipsets. The embodiments are particularly effective in Matter / Bluetooth Low Energy (BLE) Gateway products which value Wi-Fi co-existence, for example, over power efficiency.

[0037] Furthermore, lower-power embodiments are also presented that may be better-suited for battery-operated end-nodes. These embodiments allow for improved performance with similar power-efficiency as conventional loT antenna selection implementations.

[0038] Figure 1 is an example block diagram of a receiver 100, according to some aspects of the present disclosure. Receiver 100 illustrates antenna selection which may be implemented, for example, in loT end node and gateway devices. In the illustrated embodiment, the receiver 100 includes two or more antennas 110, analog circuitry 190, analog to digital converter (ADC) 160, a signal conditioning circuit 170, and a processor 180. The analog circuitry 190 is circuitry for receiving an RF signal and converting the RF signal to baseband or a low IF signal for further processing by ADC 160. In this embodiment, the analog circuity 190 includes an analog switch 120, RF front end circuitry 130, a mixer 140, an IF front end circuitry 150. The analog circuitry 190 may also be referred to as analog front-end circuitry.

[0039] Analog switch 120 receives a control signal and selectively connects one of the antennas 110 to RF front end 130. An RF signal from the connected antenna 110 is transmitted to the RF front end 130 through the analog switch 120. The RF front end 130 may include, for example, a low noise amplifier (LNA), and / or one or more gain stages as is known in the art.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0040] Mixer 140 may receive a signal from, for example, a local oscillator and may downconvert the RF signal from the RF front end 130 to an intermediate frequency (IF) signal, which is transmitted to the IF front end 150. The IF frontend may include, for example, one or more anti-aliasing filters, and / or one or more additional gain stages. ADC 160 is configured to convert the analog signal generated by the analog front-end circuitry 190 to a digital signal. In the illustrated example, the digital part of the receiver 100 is separated into two parts: the signal conditioning circuit 170 and the processor 180. The signal conditioning circuit 170 may include a number of digital blocks which interact with the analog front-end for purposes of, for example, IQ-mismatch and DC-offset calibration, and may also include, for example, one or more mixers for low-IF systems, and one or more channel select filters, for example, to aid adjacent channel suppression. The processor 180 is configured to process the resulting digital signal from signal conditioning circuit 170, for example, substantially free of interferers and analog impairments, to determine the transmitted bits received in the RF signal at the antennas 110.Dual antenna paths with digital switching

[0041] Figure 2 is an example embodiment of a receiver 200, according to some aspects of the present disclosure. The receiver 200 illustrates antenna selection that may be implemented, for example, in loT end node and gateway devices. In the illustrated embodiment, receiver 200 includes a first receiver path 201 and a second receiver path 202, switch 210, and processor 280. The switch 210 implements digital switching. Receiver path 201 includes antenna 211, RF front-end circuitry 231, a mixer 241, IF front-end circuitry 251, and analog to digital converter (ADC) 261, and a signal conditioning circuit 271. Antenna path 202 includes antenna 212, an RF front end 232, a mixer 242, an IF front end 252, and analog to digital converter (ADC) 262, and a signal conditioning circuit 272. The RF front ends 231 and 232 may each include, for example, a low noise amplifier (LNA), and / or one or more gain stages. As used herein, another term for a “receiver path” is an “antenna path.”

[0042] Mixers 241 and 242 may each receive a signal from, for example, a local oscillator and may respectively downconvert the RF signals from the RF front ends 231 and 232 to intermediate frequency (IF) signals, which are respectively transmitted to the IF front ends 251 and 252. The IF front ends 251 and 252 may each include, for example, one or more anti-aliasing filters, and / or one or more additional gain stages. ADCs 261 and 262 are eachDocket No. 62306.224WO01 (P251707-WO-UTL)configured to respectively convert the IF signal received from the IF front end 251 or 252 to digital signals.

[0043] The signal conditioning circuits 271 and 272 may each include a number of digital blocks which respectively interact with the corresponding analog front-end for purposes of, for example, IQ-mismatch and DC-offset calibration, and may also include, for example, one or more mixers for LIF systems, and one or more channel select filters, for example, to aid adjacent channel suppression.

[0044] The switch 210 is configured to receive the resulting digital signals from signal conditioning circuits 271 and 272, for example, substantially free of interferers and analog impairments, and to selectively transmit the digital signal from one of signal conditioning circuits 271 and 272 to the processor 280 according to a control signal received, for example, from a processor (not shown) or from processor 280. The processor 280 is configured to process the digital signal received from switch 210, for example, to determine the transmitted bits received in the RF signal at the antennas 211 and 212. The processor 280 may implement what is commonly referred to as modem functionality.

[0045] Receiver 200 includes two receiver paths 201 and 202 each having its own signal conditioning circuit 271 or 272. Both receiver paths 201 and 202 may be simultaneously active, where switching to control which receiver path 201 or 202 is connected to processor 280 occurs in the digital domain. In some embodiments, the processor 280 can function similar or identical to processor 180.

[0046] In some embodiments, although both receiver paths 201 and 202 consume power, the architecture of receiver 200 has important compensating advantages. For example, there is no analog antenna switching, so receiver 200 can co-exist well with other Wi-Fi chips on the same board. In addition, digital switching (using switch 210) results in no transient effects. These features make receiver 200 advantageous for, for example, gateway products which are typically mains-powered and value co-existence and sensitivity over power efficiency. In some embodiments, receiver 200 is controlled to also implement radio dutycycling to extend these benefits to low-power end-node devices, as discussed in more detail below.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0047] In the illustrated embodiment, switching between the two antenna paths occurs with switch 210 configured to connect either of a selected one of receiver paths 201, 202 to processor 280. Accordingly, switch 210 is included in each of the two antenna paths.

[0048] In alternative embodiments, switching between the two antenna paths occurs with a switch configured to connect either of ADCs 261 and 262 to a signal conditioning circuit which is connected to processor 280. Accordingly, the signal conditioning circuit and the switch are included in each of the two receiver paths.

[0049] In some embodiments, switching between the two receiver paths occurs with an analog switch configured to connect either of IF front ends 251 and 252 to an ADC connected to a signal conditioning circuit which is connected to processor 280. Accordingly, the ADC, the signal conditioning circuit, and the switch are included in each of the two antenna paths.

[0050] In alternative embodiments, switching between the two antenna paths occurs with an analog switch configured to connect either of mixers 241 and 242 to an IF frontend which is connected to an ADC connected to a signal conditioning circuit which is connected to processor 280. Accordingly, the IF frontend, the ADC, the signal conditioning circuit, and the switch are included in each of the two antenna paths.

[0051] In alternative embodiments, switching between the two antenna paths occurs with an analog switch configured to connect either of RF front ends 231 and 232 to a mixer connected to an IF frontend which is connected to an ADC connected to a signal conditioning circuit which is connected to processor 280. Accordingly, the mixer, the IF frontend, the ADC, the signal conditioning circuit, and the switch are included in each of the two antenna paths.

[0052] Accordingly, in some embodiments, one or more components of the first antenna path are also included in the second antenna path. In some embodiments, one or more components of the first antenna path are not included in the second antenna path. In some embodiments, one or more components of the second antenna path are not included in the first antenna path. In some embodiments, one or more components of the first antenna path are included in the second antenna path, and one or more components of the first antenna path are not included in the second antenna path. In some embodiments, one or more components of the second antenna path are included in the first antenna path, and one or more components of the second antenna path are not included in the first antenna path.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0053] Although two antennas 211 and 212 and two corresponding receiver paths 201 and 202, respectively, are illustrated, as would be understood by a person of ordinary skill in the art, any number of antennas and receiver paths may be included in a receiver. A switch, such as switch 210, may switch between the different receiver paths when there are more than two paths. The aspects of the present disclosure discussed herein are not limited to any specific analog or digital architecture for the receiver paths. For example, analog circuitry 291 and 292 is exemplary and other forms of analog front-end circuitry may be used to prepare a received signal for ADC conversion as was known in the art.

[0054] Figures 3 - 6 illustrate example methods which may be performed by one or more of the embodiments of the receiver discussed herein. The methods are discussed typically with reference to at least receiver 200. However, the methods may be modified by those of skill in the art, for example, to be suitable for any of the embodiments of the receivers discussed herein.Antenna Multiplexing

[0055] Figure 3 is an example of an antenna switching method, according to some aspects of the present disclosure. Method may be used, for example, in loT systems. The method may be performed, for example, by a receiver discussed herein, such as receiver 200. The signal format is illustrated according to signal timing diagram 310, and an exemplary timing diagram illustrating the method is shown in receiver timing diagram 320. The notation “A0” and “Al” denotes a corresponding antenna and its corresponding receiver path being active, and the time period that a receiver path is active may be referred to herein as an antenna data slot. For example, for the receiver in Figure 2, “A0” indicates that switch 210 selects receiver path 201 (antenna A0 may be designated as antenna 211), and “Al” indicates that switch 210 selects receiver path 202 (antenna Al may be designated as antenna 212).

[0056] To per4form the method illustrated using receiver timing diagram 320, a processor, such as processor 180 of receiver 100 or processor 280 of receiver 200 is configured to selectively receive digital data corresponding with RF signals received at one of multiple antennas, for example, as shown in receivers 100 and 200. The processor is configured to process the received digital signals for each antenna to detect preamble symbols S0-S7 indicating a communication packet.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0057] In some embodiments, the processor is configured to receive digital data corresponding with RF signals received at one of the antennas for an integer number of periods of a preamble pattern, where the preamble pattern has, for example, multiple periods. In some embodiments, each of the multiple periods has a repeated preamble data pattern. For example, the 802.15.4 PHY standard used by Zigbee and Matter has a preamble consisting of 8 repeated chip patterns each lasting 16us. In this example, the processor may be configured to receive digital data corresponding with RF signals received at one of the antennas for N*16 ps where N is an integer. The processor may be configured, for example, to use a cyclic correlation to identify 802.15.4 packets.

[0058] The method illustrated using receiver timing diagram 320 illustrates an example method which is relevant to the 802.15.4 standard where N = 1. The processor is switched back and forth between antenna paths until, for example, one or more full preamble symbols S0-S7 are received, and the cyclic correlation shows a peak indicating a preamble symbol.

[0059] In the illustrated example, a first occurrence of antenna data slot A0, for which data from a first antenna is received, is partially time aligned with preamble symbol SO. In addition, a second occurrence of antenna data slot A0, for which data for the first antenna is received, is partially time aligned with preamble symbols SI and S2. Accordingly, the processor processes a beginning portion of preamble symbol SO received at the first antenna during the first occurrence of antenna data slot A0, and processes an ending portion of preamble symbol SI received at the first antenna during the second occurrence of antenna data slot A0. Based on this data, the cyclic correlation indicates that a preamble symbol has been received at the first antenna.

[0060] Similarly, in the illustrated embodiment, a first occurrence of antenna data slot Al, for which data from a second antenna is received, is partially time aligned with preamble symbols SO and SI. In addition, a second occurrence of antenna data slot Al, for which data for the first antenna is received, is partially time aligned with preamble symbols S2 and S3. Accordingly, the processor processes beginning portions of either or both of preamble symbols SO and SI received at the first antenna during the first occurrence of antenna data slot Al, and processes an ending portion of either or both of preamble symbols S2 and S3 received at the first antenna during the second occurrence of antenna data slot Al. Based on this data, the cyclic correlation indicates that a preamble symbol has been received at the second antenna.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0061] In some embodiments, the processor determines which of the two antennas provided a signal having the better SNR and selects the antenna having the better SNR to use for receiving the remainder of the packet.

[0062] An advantage of this approach using receiver 100 is that antenna diversity can be achieved with only a single antenna front-end which reduces the power of the device. This is helpful for battery-powered end-node loT devices. However, the receiver 100 may suffer from antenna switching which creates impedance changes that interfere with other wireless systems co-existing on the same board, such as a Wi-Fi system. Another disadvantage is that analog antenna switching may introduce transient effects in the signal which degrade sensitivity.

[0063] An advantage of this approach using receiver 200 is that antenna diversity can be achieved without antenna impedance changes or switching transient effects because the switching between antenna signals is done digitally. Accordingly, receiver 200 and similar receivers may be used well with other wireless systems co-existing on the same board, such as Wi-Fi systems.Duty-cycled dual antenna paths with digital switching

[0064] Figure 4A is an example block diagram of another receiver 450, and Figure 4B illustrates an example of another antenna switching method, according to some aspects of the present disclosure. The method may be used, for example, in loT systems. The method may be performed, for example, by a receiver, such as receiver 200. The receiver 450 includes many of the same components as receiver 200, and the same components are numbered the same. In receiver 450, one or more memory devices 281 and 282 are added to respective receiver paths 401 and 402, respectively. A exemplary signal format is illustrated according to signal timing diagram 410, and an exemplary receiver timing diagram illustrating the method is shown in diagram 420.

[0065] In this embodiment, during active antenna slots (denoted as “A0 + Al”, which indicates signals are being received on both antennas), all or both receiver paths 401, 402 of the receiver 450 are simultaneously active such that an RF signal is received at all or both antennas, and data for each antenna is generated and stored in memory devices 281, 282. The data is processed by the processor to detect preamble packets and, in some embodiments, to select an antenna. The memory devices 281, 282 may be buffers or other known memoryDocket No. 62306.224WO01 (P251707-WO-UTL)devices for storing digital samples, such as a cache memory (e.g., a cache memory of the processor 1760), random access memory (RAM), magnetoresistive RAM (MRAM), readonly memory (ROM), programmable read-only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, solid state memory device, hard disk drives, other forms of volatile and non-volatile memory, or a combination of different types of memory.

[0066] However, during inactive or sleep periods, denoted as “Sleep” in timing diagram 420, all or both receiver paths 401, 402 can be at least partially put in a power saving mode (or sleep mode) to conserve power. In some embodiments, only some of the radio components are at least partially powered down during sleep periods. For example, in some embodiments, the IF components, ADCs, and signal conditioning circuits are completely shut off. In some embodiments, some of the RF blocks remain at least partially active during sleep periods, for example, if their switching activity would not otherwise disturb nearby systems. Control signals are provided to the receiver paths 401 and 402 as shown to control the power to circuitry on those receiver paths to set the sleep and non-sleep periods. At least a portion of the first analog circuitry 291 and a portion of the second analog circuitry 292 may be toggled on and off in alternating time slots (or time periods) of a plurality of time slots as shown in system timing diagram 420.

[0067] To perform the method illustrated using receiver timing diagram 420, a processor, such as processor 280, is configured to selectively receive digital data corresponding with RF signals received by one of multiple antennas during active antenna slots. The processor 280 is configured to process the received digital signals for each antenna to detect communication packets and, in some embodiments, to select a receiver path.

[0068] In some embodiments, the processor 280 is configured to receive digital data corresponding with RF signals received at both of the antennas 211, 212 for an integer number of periods of a preamble pattern, where the preamble has for example, multiple periods. In some embodiments, each of the multiple periods has a repeated preamble data pattern. For example, the 802.15.4 PHY standard used by Zigbee and Matter has a preamble consisting of 8 repeated chip patterns each lasting 16 ps. In this example, the processor may be configured to receive digital data corresponding with RF signals received at both of the antennas for N* 16 ps where N is an integer. The processor may be configured to use a cyclicDocket No. 62306.224WO01 (P251707-WO-UTL)correlation to identify 802.15.4 packets. The method illustrated using receiver timing diagram 420 illustrates an example method which is relevant to the 802.15.4 standard where N = 1.

[0069] The processor is switched back and forth between receiver paths 401, 402 until one or more full preamble symbols S0-S7 are received, and the cyclic correlation shows a peak indicating the preamble symbol.

[0070] In the illustrated example, the first occurrence of antenna data slot A0+A1 is not time aligned with any preamble symbol data. Accordingly, the processor 280 determines that no preamble symbol data has been received.

[0071] During the first occurrence of the sleep antenna data slot, some or all of the first and second antenna paths are at least partially powered down, for example, to reduce power consumption. For example, in some embodiments, the analog portions of the first and second antenna paths are at least partially powered down.

[0072] In the illustrated example, the second occurrence of antenna data slot A0+A1 is partially time aligned with preamble symbol SO. Accordingly, data corresponding with a beginning portion of preamble symbol SO is received at first and second antennas during the second occurrence of antenna data slot A0+A1 and are respectively partially processed by the first and second antenna paths. The digital data corresponding with the beginning portion of preamble symbol SO may be stored or buffered.

[0073] Similarly, a third occurrence of antenna data slot A0+A1 is partially time aligned with preamble symbols SI and S2. Accordingly, data corresponding with an ending portion of preamble symbol SI and the beginning portion of preamble symbol S2 is received at first and second antennas during the third occurrence of antenna data slot A0+A1 and are respectively partially processed by the first and second antenna paths. The partially processed digital data corresponding with the ending portion of preamble symbol SO and the beginning portion of preamble symbol S2 may be stored or buffered.

[0074] The processor processes the beginning portion of either of preamble symbols SO and S2 from each of the first and second antennas and processes the ending portion of preamble symbol SI from each of the first and second antennas. The cyclic correlation indicates that a preamble symbol has been received. In some embodiments, the processor processes the beginning portion of either of preamble symbols SO and S2 from each of theDocket No. 62306.224WO01 (P251707-WO-UTL)first and second antennas, and processes the ending portion of preamble symbol SI from each of the first and second antennas during a 2 x 16us period which at least partially overlaps the sleep antenna data slot. In some embodiments, the processor processes the beginning portion of either of preamble symbols SO and S2 from each of the first and second antennas, and processes the ending portion of preamble symbol SI from each of the first and second antennas during a 1 x 16us period which at least partially overlaps the sleep antenna data slot or doesn’t overlap the sleep antenna data slot. In some embodiments, the processor determines which of the two antenna paths provided a signal having the better SNR and selects the antenna path having the better SNR to use for receiving the remainder of the packet. In this embodiment, the processor selects the first antenna path.

[0075] During the second occurrence of the sleep antenna data slot, some or all of the first and second antenna paths are at least partially powered down, for example, to reduce power consumption.

[0076] An advantage of this approach is that antenna diversity can be achieved with minimal power consumption, and without antenna impedance changes or switching transient effects. This is helpful, for example, for battery-powered end-node loT devices. Accordingly, receiver 200 and similar receivers may be used well with other wireless systems, such as WiFi, co-existing on the same board.Multi-channel antenna diversity with digital switching

[0077] Figure 5A is an example block diagram another receiver 550, and Figure 5B is an example of another antenna switching method, according to some aspects of the present disclosure. Method 500 may be used, for example, in loT systems. The method may be performed, for example, by receiver 550. As compared to the receiver 200, the receiver 550 explicitly illustrates a phase lock loop (PLL) connected to each receiver path 501 and 502, respectively. That is, PLL 511 is used to control a frequency of mixer 241, and PLL 512 is used to control a frequency of mixer 242. An exemplary signal format is illustrated according to signal timing diagram 510, and an exemplary receiver timing diagram illustrating the method is shown in diagram 520. The mixers 241 and 242 may controlled to be tuned to various channels.

[0078] Receivers having features of receivers 200, 450, or 550 can be applied to implement multi-channel antenna diversity. For example, receiver 550 can switch betweenDocket No. 62306.224WO01 (P251707-WO-UTL)different combinations of channels (e.g., denoted in Figure 5B as channels CO and Cl) and antennas / receive circuitry (denoted as AO and Al) for each antenna / channel data slot to detect preamble symbols. When a preamble symbol is found, the receiver can switch to the other receiver path on the same frequency channel, evaluate its SNR, and select the best antenna path for the rest of the packet.

[0079] In some embodiments, changing the PLL frequency to switch between (or tune to) different channels does not cause co-existence problems. Accordingly, multi-channel antenna diversity can be achieved using, for example, method illustrated using receiver timing diagram 520.

[0080] To perform the method illustrated using receiver timing diagram 520, a processor, such as processor 280 of receiver 550 is configured to selectively receive digital data corresponding with RF signals received by one of multiple antennas at one of multiple channel frequencies. The processor may be configured to process the received digital signals for each antenna to detect, for example, preamble symbols.

[0081] In some embodiments, the processor is configured to receive digital data corresponding with RF signals received at one of the antennas on one of the frequency channels for an integer number of periods of a preamble pattern, where the preamble pattern has, for example, multiple periods. In some embodiments, each of the multiple periods has a repeated preamble data pattern. For example, the 802.15.4 PHY standard used by Zigbee and Matter has a preamble consisting of 8 repeated chip patterns each lasting 16us. In this example, the processor may be configured to receive digital data corresponding with RF signals received at one of the antennas for N* 16 ps where N is an integer. The processor may be configured to use a cyclic correlation to identify 802.15.4 packets.

[0082] The method illustrated using receiver timing diagram 520 illustrates an example method which is relevant to the 802.15.4 standard where N = 1. The processor is switched back and forth between antennas and between multiple channels until, for example, one or more full preamble symbols S0-S7 are received, and the cyclic correlation shows a peak indicating the start of a packet.

[0083] In the illustrated example, a first occurrence of antenna / channel data slot C0A0 (denoting that receiver path with antenna A0, such as receiver path 501 including antenna 211, receives a channel designated as CO), for which data from a first antenna at a firstDocket No. 62306.224WO01 (P251707-WO-UTL)frequency channel is received, is partially time aligned with preamble symbol SO. In addition, a first occurrence of antenna / channel data slot C0A1, for which data from a second antenna at the first frequency channel is received, is partially time aligned with each of preamble symbols SO and SI. Furthermore, a first occurrence of antenna / channel data slot CIAO, for which data from the first antenna at a second frequency channel is received, is partially time aligned with each of preamble symbols SI and S2. Similarly, a first occurrence of antenna / channel data slot Cl Al, for which data from the second antenna at the second frequency channel is received, is partially time aligned with each of preamble symbols S2 and S3. Furthermore, a second occurrence of antenna / channel data slot COAO, for which data from a first antenna at the first frequency channel is received, is partially time aligned with preamble symbols S3 and S4. In addition, a second occurrence of antenna / channel data slot C0A1, for which data from the second antenna at the first frequency channel is received, is partially time aligned with each of preamble symbols S4 and S5.

[0084] In some embodiments, the antenna / channel data slots C0A0, C0A1, CIAO, and Cl Al are cyclically repeated until or at least until a preamble symbol is detected. In the illustration of Figure 5B, a preamble symbol is detected after the second occurrence of antenna / channel data slot C0A0, which is an illustrative example, as a preamble symbol may be detected at any point in a repeating cycle of antenna / channel combinations. Each time a receiver path is tuned to a channel, a digital signal is generated, and digital signals are generated and analyzed until the presence of a packet is identified and a receiver path is selected.

[0085] To detect the preamble symbol, the processor processes a beginning portion of either or both of preamble symbols SO and S4 from data of the first or second occurrence of antenna / channel data slot C0A0, and processes an ending portion of preamble symbol S3 from data of the second occurrence of antenna / channel data slot C0A0. The cyclic correlation indicates that a preamble symbol has been received by the first antenna at the first frequency channel.

[0086] In some embodiments, the first, second, third, and fourth antenna / channel data slots C0A0, C0A1, CIAO, and Cl Al are cyclically repeated until or at least until a second preamble is detected, for example, based on data from the other antenna. In the illustration of figure 5, a second preamble symbol is detected after the second occurrence of antenna / channel data slot C0A1.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0087] To detect the second preamble symbol, the processor processes an ending portion of either or both of preamble symbols SO and S4 and processes a beginning portion of either or both of preamble symbols SI and S5. The cyclic correlation indicates that a preamble symbol has been received at the second antenna and at the first channel.

[0088] In the illustrated embodiment, the processor determines which of the two antenna paths provided a signal having the better SNR and selects the antenna path having the better SNR to use for receiving the remainder of the packet. In this embodiment, the processor selects the first antenna path of antenna / channel data slot C0A0.

[0089] An advantage of this approach using receiver 200 is that antenna diversity and multiple channel performance can be achieved without antenna impedance changes or switching transient effects because the switching between antenna signals is done digitally. Accordingly, receiver 200 and similar receivers may be used well with other wireless systems co-existing on the same board, such as Wi-Fi.Multi-channel digital antenna switching

[0090] Figure 6 is illustrates an example of another antenna switching method, according to some aspects of the present disclosure. A exemplary signal format is illustrated according to signal timing diagrams 605 (for exemplary channel Cl) and 610 (for exemplary channel 0), and an exemplary receiver timing diagram illustrating the method is shown in diagram 620. The method may be used, for example, in loT systems. The method illustrated in receiver timing diagram 620 may be performed, for example, by a receiver, such as a receiver that combines features of receivers 450 and 550 (e.g., a receiver having PLLs and memory devices as well as the other components). In some embodiments, such as receiver can be applied to implement multi-channel antenna diversity.

[0091] In this embodiment, during active antenna slots, all or both receiver paths of the receiver are active simultaneously such that an RF signal is received and partially processed by all or both antenna paths, where the partially processed data from each antenna is generated and stored in buffers. A receiver may be configured to select one of the different combinations of channels (CO and Cl) and antennas (A0 and Al) for each active antenna / channel data slot. The data is also processed by the processor to detect preamble packets and, in some embodiments, to select an antenna. However, during sleep or inactiveDocket No. 62306.224WO01 (P251707-WO-UTL)periods, between active antenna / channel data slots, all or both antenna paths are at least partially put in a power saving mode to conserve power.

[0092] In some embodiments, only some of the radio components are at least partially powered down during sleep periods. For example, in some embodiments, the IF components, ADCs, and signal conditioning circuits are completely shut off. In some embodiments, some of the RF blocks remain at least partially active during sleep periods, for example, if their switching activity would otherwise disturb nearby systems. In some embodiments, that the duration of the sleep periods is corresponds with the duration of the preamble symbols and the number of antennas and / or channels supported. In the illustrated embodiment, the sleep period has a duration equal to 2 x 16 us.

[0093] In some embodiments, when a preamble symbol is found, the receiver switches to the other receiver path on the same frequency channel, evaluates its SNR, and selects, based on a comparison of the SNRs of the antenna paths, the best antenna path for the rest of the packet.

[0094] In the illustrated embodiment, preamble symbol data is received on frequency channel CO and no preamble symbol data is received on frequency channel Cl.

[0095] In this embodiment, during active antenna slots, all or both receiver paths of the receiver are simultaneously active for a number of antenna / channel data slots such that an RF signal is received at all or both antennas, and data for each antenna is generated and stored in buffers. The data is processed by the processor to detect preamble packets and, in some embodiments, to select an antenna.

[0096] However, during inactive or sleep periods, all or both radio paths can be at least partially put in a power saving mode to conserve power. In some embodiments, only some of the radio components are at least partially powered down during sleep periods. For example, in some embodiments, the IF components, ADCs, and signal conditioning circuits are completely shut off. In some embodiments, some of the RF blocks remain at least partially active during sleep periods, for example, if their switching activity would not otherwise disturb nearby systems.

[0097] To perform the method illustrated in receiver timing diagram 620, a processor, such as processor 280 of receiver 200 is configured to selectively receive digital dataDocket No. 62306.224WO01 (P251707-WO-UTL)corresponding with RF signals received by one of multiple antennas at one of multiple frequency channels. The processor is configured to process the received digital signals for each antenna and frequency channel to detect, for example, preamble symbols.

[0098] In some embodiments, the processor is configured to receive digital data corresponding with RF signals received by both of the antennas at a first frequency channel for an integer number of periods of a preamble pattern, where the preamble has for example, multiple periods. In addition, the processor may be configured to receive digital data corresponding with RF signals received by both of the antennas at each of one or more next frequency channels for a same integer number of periods of the preamble pattern.

[0099] In some embodiments, each of the periods of the preamble pattern has a repeated preamble data pattern. For example, the 802.15.4 PHY standard used by Zigbee and Matter has a preamble consisting of 8 repeated chip patterns each lasting 16us. In this example, the processor may be configured to receive digital data corresponding with RF signals received at both of the antennas for N* 16us where N is an integer. The processor may be configured to use a cyclic correlation to identify 802.15.4 packets. The method in Figure 6 illustrates an example embodiment which is relevant to the 802.15.4 standard where N = 1.

[0100] The processor is switched back and forth between antenna paths and between multiple frequency channels until one or more full preamble symbols S0-S7 are received, and the cyclic correlation shows a peak indicating a preamble symbol.

[0101] In the illustrated example, a first occurrence of antenna / channel data slot C0(A0+Al) is partially time aligned with preamble symbol SO. Accordingly, data corresponding with a beginning portion of preamble symbol SO is received by first and second antennas at a first frequency channel and is partially processed by each of first and second antenna paths. The partially processed digital data corresponding with the beginning portion of preamble symbol SO may be stored or buffered.

[0102] The first occurrence of antenna / channel data slot Cl(A0+Al) is not aligned with any preamble symbol data because such preamble data is not received on frequency channel Cl.

[0103] During the sleep period, some or all of the first and second antenna paths are at least partially powered down to reduce power consumption.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0104] The second occurrence of antenna / channel data slot C0(A0+Al) is partially time aligned with preamble symbols S3 and S4. Accordingly, data corresponding with an ending portion of preamble symbol S3 and a beginning portion of preamble symbol S4 is received at first and second antennas on the second frequency channel and are partially processed by first and second antenna paths. The partially processed digital data corresponding with the ending portion of preamble symbol S3 and the beginning portion of preamble symbol S4 may be stored or buffered.

[0105] The processor processes the beginning portion of either or both of preamble symbols SO and S4 from each of the first and second antennas at frequency channel CO and processes the ending portion of preamble symbol S3 from each of the first and second antennas at frequency channel CO. The cyclic correlation indicates that a preamble symbol has been received. In some embodiments, the processor processes the beginning portion of either or both of preamble symbols SO and S4 from each of the first and second antenna paths during a 2 x 16us period which at least partially overlaps the sleep antenna / channel data slot or doesn’t overlap the sleep antenna / channel data slot.

[0106] In some embodiments, the processor determines which of the two antenna paths provided a signal having the better SNR and selects the antenna path having the better SNR to use for receiving the remainder of the packet. In this embodiment, the processor selects the first antenna path.

[0107] An advantage of this approach is that multi-channel antenna diversity can be achieved with minimal power consumption, and without antenna impedance changes or switching transient effects. This is helpful, for example, for battery-powered end-node loT devices. Accordingly, receivers 200, 450, and 550 and similar receivers may be used well with other wireless systems, such as Wi-Fi, co-existing on the same board.

[0108] The processors discussed herein, such as processor 280, may include a central processing unit (CPU), a digital signal processor (DSP), an ASIC, a controller, or any combination of general -purpose computing devices, reduced instruction set computing (RISC) devices, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other related logic devices, including mechanical and quantum computers. A processor may also comprise another hardware device, a firmware device, or any combination thereof configured to perform the operations described herein. A processor mayDocket No. 62306.224WO01 (P251707-WO-UTL)also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0109] Figure 7 illustrates a communication device 700 having features similar or identical to the circuits discussed herein, and being configured to perform the methods discussed herein, according to aspects of the present disclosure. The communication device 700 can be a communication device such as a mobile terminal, an access point, an loT gateway device, or any other type of wireless communication device that supports wireless communications discussed herein, such as wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communications.

[0110] The communication device 700 generally includes a control system 50, a baseband processor 52, transmit circuitry 54, receive circuitry 56, antenna switching circuitry 58, multiple antennas 60, and user interface circuitry 62. In a non-limiting example, the control system 50 can be a field-programmable gate array (FPGA). In this regard, the control system 50 can include one or more of at least a microprocessor, an embedded memory circuit, and a communication bus interface. In some embodiments, the receive circuitry 56 has features and capabilities similar or identical to receivers discussed herein, such as receivers 200, 450, or 550. The receive circuitry 56 receives radio frequency signals via the multiple antennas 60 and through the antenna switching circuitry 58 from one or more base stations. A low-noise amplifier and a filter may cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using one or more analog-to-digital converters (ADCs).[oni] The baseband processor 52 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 52 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs). The baseband processor 52 may implement functionality of the processors discussed previously, such as processor 280.Docket No. 62306.224WO01 (P251707-WO-UTL)

[0112] For transmission, the baseband processor 52 receives digitized data, which may represent voice, data, or control information, from the control system 50, which it encodes for transmission. The encoded data is output to the transmit circuitry 54, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level appropriate for transmission and delivers the modulated carrier signal to the multiple antennas 60 through the antenna switching circuitry 58. The multiple antennas 60 and the replicated transmit circuitry 54 and receive circuitry 56 may provide spatial diversity.Modulation and processing details will be understood by those skilled in the art. In an embodiment, the RF receiver front-end 10 may be provided in any one or more of the circuitries in the communication device 700, such as the receive circuitry 56. The antenna switching circuitry 58 may connect the antennas 60 to either the receive circuitry 56 for reception or the transmit circuitry 54 for transmission.

[0113] Some embodiments include a system performing a method of estimating the crystal frequency offset between two devices, the system and method including: a compensating hardware / software unit which compensates a current packet’s received signal for the crystal frequency offset between two devices; a hardware / software control loop which iteratively refines the crystal frequency offset between the two devices based on measurements of the phase or frequency error obtained on each data symbol in the packet; a hardware / software control unit which initializes the compensating unit’s compensating frequency with a crystal frequency offset estimate obtained by from a previously received packet; and a hardware / software control unit which initializes the parameters of the control loop to reflect the expected accuracy of this frequency estimate.

[0114] Persons skilled in the art will recognize that the apparatus, systems, and methods described above can be modified in various ways. Accordingly, persons of ordinary skill in the art will appreciate that the embodiments encompassed by the present disclosure are not limited to the particular exemplary embodiments described above. In that regard, although illustrative embodiments have been shown and described, a wide range of modification, change, and substitution is contemplated in the foregoing disclosure. It is understood that such variations may be made to the foregoing without departing from the scope of the presentDocket No. 62306.224WO01 (P251707-WO-UTL)disclosure. Accordingly, it is appropriate that the appended claims be construed broadly and, in a manner, consistent with the present disclosure.

Claims

Docket No. 62306.224WO01 (P251707-WO-UTL)CLAIMSWhat is claimed is:

1. A receiver comprising:a first receiver path comprising a first antenna and a first analog-to-digital converter (ADC), wherein the first receiver path is configured to receive a first radio frequency (RF) signal and to generate a first digital signal from the first RF signal as an output of the first ADC during a first time period;a second receiver path comprising a second antenna and a second ADC, wherein the second receiver path is configured to receive a second RF signal and to generate a second digital signal from the second RF signal as an output of the second ADC during the first time period;a processor; anda digital switch configured to select one of the first receiver path and the second receiver path for connection to the processor,wherein the processor is configured to control the digital switch to select between the first receiver path and the second receiver path for receiving data during a second time period based on the first digital signal and the second digital signal.

2. The receiver of claim 1, wherein the first time period is a multiple of a preamble period, and wherein the processor is further configured to:perform a cyclic correlation of the first digital signal to generate a first output; and perform a cyclic correlation of the second digital signal to generate a second output, wherein the selecting between the first receiver path and the second receiver path is based on the first output and the second output.

3. The receiver of claim 1, wherein:the first receiver path further comprises first analog front-end circuitry, wherein the first antenna, the first analog front-end circuitry, and the first ADC are connected in series; andDocket No. 62306.224WO01 (P251707-WO-UTL)the second receiver path further comprises second analog front-end circuitry, wherein the second antenna, the second analog front-end circuitry and the second ADC are connected in series.

4. The receiver of claim 3,wherein a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry is configured to be toggled on and off in alternating time slots of a plurality of time slots,wherein the first time period is a first time slot in the plurality of time slots, and wherein the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal,wherein the receiver further comprises at least one memory,wherein the at least one memory is configured to store the second digital signal, and wherein the processor is configured to retrieve the second digital signal and process the second digital signal after processing the first digital signal.

5. The receiver of claim 3,wherein the first time period includes a plurality of time slots including a first time slot and a second time slot,wherein the first digital signal is obtained by tuning the first receiver path to a first channel during the first time slot,wherein the second digital signal is obtained by tuning the second receiver path to the first channel during the second time slot, andwherein the first receiver path and the second receiver path are further configured to tune to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals, andwherein the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

6. The receiver of claim 5, wherein the first analog front-end circuitry comprises a first mixer and a first phase lock loop configured to control a first frequency of the first mixer, wherein the second analog front-end circuitry comprises a second mixer and a second phase lock loop configured to control a second frequency of the first mixer, wherein first receiverDocket No. 62306.224WO01 (P251707-WO-UTL)path is tuned to a channel by tuning the first frequency, and wherein the second receiver path is tuned to a channel by tuning the second frequency.

7. The receiver of claim 3,wherein the first analog front-end circuitry comprises first radio frequency (RF) circuitry, a first mixer, and first intermediate frequency (IF) circuitry connected in series with the first antenna, andwherein the second analog front-end circuitry comprises second RF circuitry, a second mixer, and second IF circuitry connected in series with the second antenna.

8. A wireless communication device comprising:a transmitter; anda receiver comprising:a first receiver path comprising a first antenna and configured to receive a first radio frequency (RF) signal and to generate a first digital signal from the first RF signal during a first time period;a second receiver path comprising a second antenna and configured to receive a second RF signal and to generate a second digital signal from the second RF signal during the first time period;a processor; anda switch configured to select one of the first receiver path and the second receiver path for connection to the processor,wherein the processor is configured to control the switch to select between the first receiver path and the second receiver path for receiving data during a second time period based on the first digital signal and the second digital signal, andwherein the transmitter is configured to use the first antenna and the second antenna for transmission.

9. The wireless communication device of claim 8, wherein the first time period is a preamble period, and wherein the processor is further configured to:perform a cyclic correlation of the first digital signal to generate a first output; and perform a cyclic correlation of the second digital signal to generate a second output, wherein the selecting between the first receiver path and the second receiver path is based on the first output and the second output.Docket No. 62306.224WO01 (P251707-WO-UTL)10. The wireless communication device of claim 8, wherein:the first receiver path further comprises first analog front-end circuitry and a first analog-to-digital converter (ADC), wherein the first antenna, the first analog front-end circuitry, and the first ADC are connected in series; andthe second receiver path further comprises second analog front-end circuitry and a second ADC, wherein the second antenna, the second analog front-end circuitry and the second ADC are connected in series,wherein the first digital signal is based on an output of the first ADC, and wherein the second digital signal is based on an output of the second ADC.

11. The wireless communication device of claim 10,wherein a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry is configured to be toggled on and off in alternating time slots of a plurality of time slots,wherein the first time period is a first time slot in the plurality of time slots, and wherein the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal,wherein the receiver further comprises at least one memory,wherein the at least one memory is configured to store the second digital signal, and wherein the processor is configured to retrieve the second digital signal and process the second digital signal after processing the first digital signal.

12. The wireless communication device of claim 10,wherein the first time period includes a plurality of time slots including a first time slot and a second time slot,wherein the first digital signal is obtained by tuning the first receiver path to a first channel during the first time slot,wherein the second digital signal is obtained by turning the second receiver path to the first channel during the second time slot, andwherein the first receiver path and the second receiver path are further configured to tune to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals, andDocket No. 62306.224WO01 (P251707-WO-UTL)wherein the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

13. The wireless communication device of claim 12, wherein the first analog front-end circuitry comprises a first mixer and a first phase lock loop controlling a first frequency of the first mixer, wherein the second analog front-end circuitry comprises a second mixer and a second phase lock loop controlling a second frequency of the first mixer, wherein first receiver path is tuned to a channel by tuning the first frequency, and wherein the second receiver path is tuned to a channel by tuning the second frequency.

14. The wireless communication device of claim 10,wherein the first analog front-end circuitry comprises first radio frequency (RF) circuitry, a first mixer, and first intermediate frequency (IF) circuitry connected in series with the first antenna, andwherein the second analog front-end circuitry comprises second RF circuitry, a second mixer, and second IF circuitry connected in series with the second antenna.

15. A method of operating a receiver comprising a first receiver path and a second receiver path, the method comprising:receiving a first radio frequency (RF) signal during a first time period by a first antenna, wherein the first receiver path comprises the first antenna;processing the first RF signal by the first receiver path to generate a first digital signal;receiving a second RF signal during the first time period by a second antenna, wherein the second receiver path comprises the second antenna;processing the second RF signal by the second receiver path to generate a second digital signal;selecting between the first receiver path and the second receiver path as a selected receiver path for receiving data during a second time period based on the first digital signal and the second digital signal; andreceiving the data during the second time period, by the selected receiver path.

16. The method of claim 15, further comprising:performing a cyclic correlation of the first digital signal to generate a first output; andDocket No. 62306.224WO01 (P251707-WO-UTL)performing a cyclic correlation of the second digital signal to generate a second output,wherein the selecting between the first receiver path and the second receiver path is based on the first output and the second output.

17. The method of claim 15, wherein:the first receiver path further comprises first analog front-end circuitry and a first analog-to-digital converter (ADC), wherein the first antenna, the first analog front-end circuitry, and the first ADC are connected in series; andthe second receiver path further comprises second analog front-end circuitry and a second ADC, wherein the second antenna, the second analog front-end circuitry and the second ADC are connected in series,the first digital signal is based on an output of the first ADC, andthe second digital signal is based on an output of the second ADC.

18. The method of claim 17, further comprising:toggling on and off a portion of the first analog front-end circuitry and a portion of the second analog front-end circuitry in alternating time slots of a plurality of time slots, wherein the first time period is a first time slot in the plurality of time slots, and wherein the portion of the first analog front-end circuitry and the portion of the second analog front-end circuitry are toggled on during the first time slot to generate the first digital signal and the second digital signal;storing the second digital signal; andretrieving the second digital signal and processing the second digital signal after processing the first digital signal.

19. The method of claim 17, wherein the first time period includes a plurality of time slots including a first time slot and a second time slot, wherein the method further comprises: tuning the first receiver path to a first channel during the first time slot;tuning the second receiver path to a first channel during the second time slot; and tuning the first receiver path and the second receiver path to a second channel after the first time slot and the second time slot in the plurality of time slots to generate additional digital signals,Docket No. 62306.224WO01 (P251707-WO-UTL)wherein the selecting between the first receiver path and the second receiver path is further based on the additional digital signals.

20. The method of claim 19,wherein the first analog front-end circuitry comprises a first mixer and a first phase lock loop configured to control a first frequency of the first mixer,wherein the second analog front-end circuitry comprises a second mixer and a second phase lock loop configured to control a second frequency of the first mixer,wherein the tuning the first receiver path to the first channel comprises tuning the first frequency to the first channel, andwherein the tuning the second receiver path to the first channel comprises tuning the second frequency to the first channel.

Images