Power amplifier having active voltage balancing systems and methods

Abstract

A power amplifier is disclosed. The power amplifier includes a first power amplifier transistor, a second power amplifier transistor, and a first bias generator coupled to the first and second power amplifier transistors, where the first bias generator includes a power sense input configured to sense an indication of power of the power amplifier, and a bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.

Description

Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCTPOWER AMPLIFIER HAVING ACTIVE VOLTAGE BALANCING SYSTEMS AND METHODSDaoud SalamehCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 755,188 filed February 6, 2025 and entitled “POWER AMPLIFIER HAVING ACTIVE VOLTAGE BALANCING,” which is incorporated herein by reference in its entirety.TECHNICAL FIELD

[0002] The present invention relates generally to power amplifiers, and, more particularly, to bias voltage generators for power amplifiers.BACKGROUND

[0003] Communications transmitter circuits generally have processing circuitry which generates a communication signal to be transmitted, an up-conversion circuit, which the communication signal modulates, and a power amplifier which drives an antenna with the modulated high frequency carrier signal. Some power amplifiers use multiple transistors in series between the output and power and / or ground nodes. The multiple transistors have beneficial effects of increased gain and reduced drain to source voltages (Vds). The Vds voltages are distributed among the transistors in series according to bias voltages provided to the gates of the transistors. Bias voltage generation circuits providing improved performance is needed in the art.SUMMARY

[0004] One inventive aspect is a power amplifier including a first power amplifier transistor, a second power amplifier transistor, and a first bias generator coupled to the first and second power amplifier transistors, where the first bias generator includes a power sense input configured to sense an indication of power of the power amplifier, and a bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.

[0005] In some implementations, the power amplifier also includes a first current path including the first power amp transistor, and a second current path including the second power amp transistor, where the first bias generator is coupled to the first and second current paths,Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCTand where the bias output of the first bias generator is configured to source the bias current from the first and second current paths to the first and second power amp transistors.

[0006] In some implementations, the power sense input is coupled to first and second gates of the first and second power amplifier transistors, respectively.

[0007] In some implementations, the power sense input is coupled to first and second sources of the first and second power amplifier transistors, respectively.

[0008] In some implementations, the bias output is coupled to first and second gates of the first and second power amplifier transistors, respectively.

[0009] In some implementations, the power amplifier also includes an input transformer coupled to a common mode voltage source by a resistor.

[0010] In some implementations, the first bias generator further includes first and second bias generation transistors configured to source the bias current, where first and second gates of the first and second bias generation transistors are respectively coupled to the first and second power amplifier transistors by first and second resistors, respectively.

[0011] In some implementations, the first bias generator further includes first and second coupling capacitors configured to respectively couple charge from first and second sources of the first and second power amplifier transistors to first and second gates of the first and second power amplifier transistors, respectively.

[0012] Another inventive aspect is a method of amplifying power, the method including sensing an indication of power output of the power amplifier, and sourcing a bias current to first and second gates of first and second power amplifier transistors based on the sensed indication, where the bias current causes first and second gate bias voltages to change.

[0013] In some implementations, the method also includes sourcing the bias current from first and second current paths respectively including the first and second power amp transistors.

[0014] In some implementations, the method also includes sensing the indication of power at the first and second gates of the first and second power amplifier transistors.

[0015] In some implementations, the method also includes sensing the indication of power at first and second sources of the first and second power amplifier transistors.

[0016] Another inventive aspect is a transmitter including a mixer configured to generate an RF signal, and a power amplifier configured to amplify the RF signal, the power amplifierDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTincluding a first power amplifier transistor, a second power amplifier transistor, and a first bias generator coupled to the first and second power amplifier transistors, where the first bias generator includes a power sense input configured to sense an indication of power of the power amplifier, and a bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.

[0017] In some implementations, the power amplifier further includes a first current path including the first power amp transistor, and a second current path including the second power amp transistor, where the first bias generator is coupled to the first and second current paths, and where the bias output of the first bias generator is configured to source the bias current from the first and second current paths to the first and second power amp transistors.

[0018] In some implementations, the power sense input is coupled to first and second gates of the first and second power amplifier transistors, respectively.

[0019] In some implementations, the power sense input is coupled to first and second sources of the first and second power amplifier transistors, respectively.

[0020] In some implementations, the bias output is coupled to first and second gates of the first and second power amplifier transistors, respectively.

[0021] In some implementations, the power amplifier further includes an input transformer coupled to a common mode voltage source through a resistor.

[0022] In some implementations, the first bias generator further includes first and second bias generation transistors configured to source the bias current, where first and second gates of the first and second bias generation transistors are respectively coupled to the first and second power amplifier transistors by first and second resistors, respectively.

[0023] In some implementations, the first bias generator further includes first and second coupling capacitors configured to respectively couple charge from first and second sources of the first and second power amplifier transistors to first and second gates of the first and second power amplifier transistors, respectively.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Fig. 1 illustrates a block diagram of a transceiver circuit according to some embodiments.

[0025] Fig. 2 illustrates a power amplifier according to some embodiments.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0026] Fig. 3 illustrates a portion of a power amplifier having a bias voltage generator circuit according to some embodiments.

[0027] Fig. 4 illustrates a portion of a power amplifier having a bias voltage generator circuit according to some embodiments.

[0028] Fig. 5 illustrates a portion of a power amplifier having a bias voltage generator circuit according to some embodiments.

[0029] Fig. 6 illustrates a power amplifier according to some embodiments.

[0030] Fig. 7 illustrates a power amplifier according to some embodiments.

[0031] Figs. 8-10 illustrate performance parameters of power amplifiers according to some embodiments.

[0032] Fig. 11 illustrates a power amplifier according to some embodiments.

[0033] Figs. 12-15 illustrate performance parameters of power amplifiers according to some embodiments.

[0034] Fig. 16 illustrates flowchart diagram of a method of amplifying power.

[0035] Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.DETAILED DESCRIPTION

[0036] The operation and circuitry of a power amplifier (PA) having a Common Source Class C bias generator (CSCCB) and a Common Gate Class B bias generator (CGCBB) have been introduced. Improved performance, reliability, and stability over temperature has been observed. A PA having advantageous bias generation techniques is used to improve RF performance. In some embodiments, a PA uses an internal loop around PA transistors. The loop senses input or output power and generates a current based on the sensed power. For example, the generated current may be proportional or substantially proportional to the sensed power. The current may be applied to a gate resistor which increases or decreases the gate bias voltage of the PA transistors in response to the sensed power increasing or decreasing. Changing the gate bias voltages according to power results in improved performance and better reliability. The common gate bias generator (CGCBB) architecture provides improvement, for example, as it operates in a class B mode. Running the equalizer in the class B mode controlsDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTthe quiescent current, which has the effect of increasing quiescent current for increased temperature. In some embodiments, the sensitivity of the gate voltage versus power using the CGCBB architecture is less than the sensitivity of the gate voltage versus power using the CSCCB architecture.

[0037] In some embodiments, the CSCCB architecture provides further RF improvement with no voltage control on quiescent current. Also, no extra control for the loop is needed and the CSCCB architecture can be used for the driver as well. In some embodiments, the sensitivity of the gate voltage versus power using the CSCCB architecture can be controlled by controlling resistance of one or more resistors in the bias voltage generator circuit, either through design, or through electrical control.

[0038] In some manufacturing processes, transistor drain voltage (Vds) is limited, for example, to 1 to 1.2V. Power amplifiers which use a series of transistors, each having its Vds limited, can reliably generate higher output voltages, to generate higher output power.

[0039] Some power amplifiers use constant bias voltages for gates of at least some transistors in the series. This results in a drop in Vds versus power of some transistors, and an increase in Vds versus power of at least one transistor. This behavior limits the performance and degrades reliability. The increase in Vds versus power of the at least one transistor becomes more significant as the number of transistors in the series increases.

[0040] In some embodiments, bias voltage generators sense input or output power and generate a current based on the sensed power. For example, the generated current may be proportional or substantially proportional to the sensed power. The current may be used to generate gate bias voltages which increases or decreases the gate bias voltage of the PA transistors in response to the sensed power increasing or decreasing. Changing the gate bias voltages according to power results in improved performance and better reliability.

[0041] The techniques discussed herein allow for the Vds voltages of the series of transistors to be balanced, such that they are equal or substantially equal. The balance may be maintained over wide power ranges. As a result, RF signal performance and reliability are improved.

[0042] Fig. 1 illustrates a block diagram of a transceiver 100 that might be used in a wireless device, such as a cellular telephone, and which may beneficially incorporate an embodiment of the present invention, for example, for improved performance and power efficiency. As illustrated, the transceiver 100 includes a mix of RF analog circuitry for directly conveying and / or transforming signals on an RF signal path, non-RF analog circuity for operational needsDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCToutside of the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes RF Front End, IF Block, Back-End, and Baseband sections (noting that in some implementations, the differentiation between sections may be different).

[0043] The receiver path Rx receives over-the-air RF signals through an antenna 102 and a switching unit 104, which may be implemented with active switching devices (e.g., field effect transistors or FETs), or with passive devices that implement frequency-domain multiplexing, such as a diplexer or duplexer. An RF filter 106 passes desired received RF signals to an LNA 108, the output of which is combined in a mixer 110 with the output of a first local oscillator 112 to produce an intermediate frequency (IF) signal. The IF signal may be amplified by an IF amplifier 114 and subjected to an IF filter 116 before being applied to a demodulator 118, which may be coupled to a second local oscillator 120. The demodulated output of the demodulator 118 is transformed to a digital signal by an anal og-to-digi tai converter 122 and provided to one or more system components 124 (e.g., a video graphics circuit, a sound circuit, memory devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, symbols, such as text or other characters, or other data.

[0044] In the illustrated example, a transmitter path Tx includes Baseband, Back-End, IF Block, and RF Front End sections (again, in some implementations, the differentiation between sections may be different). Digital data from one or more system components 124 is transformed to an analog signal by a digital-to-analog converter 126, the output of which is applied to a modulator 128, which also may be coupled to the second local oscillator 120. The modulated output of the modulator 128 may be subjected to an IF filter 130 before being amplified by an IF amplifier 132. The output of the IF amplifier 132 is then combined in a mixer 134 with the output of the first local oscillator 112 to produce an RF signal. The RF signal may be amplified by a driver 136, the output of which is applied to a power amplifier (PA) 138. Performance characteristics, such as linearity and / or power consumption of the PA 138 may benefit from improvements brought about by use of the aspects discussed herein. The amplified RF signal may be coupled to an RF filter 140, the output of which is coupled to the antenna 102 through the switching unit 104.

[0045] The operation of the transceiver 100 is controlled by a microprocessor 142, which interacts with system control components (e.g., user interfaces, memory / storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver 100 will generally include other circuitry, such as bias circuitry 146 (which may beDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTdistributed throughout the transceiver 100 in proximity to transistor devices), electro-static discharge (ESD) protection circuits, testing circuits (not shown), factory programming interfaces (not shown), etc. For example, the microprocessor 142 may cause the transceiver to perform actions discussed elsewhere herein.

[0046] In some embodiments, there are more than one receiver path Rx and transmitter path Tx, for example, to accommodate multiple frequencies and / or signaling modalities. Further, as should be apparent to one of ordinary skill in the art, some components of the transceiver 100 may be positioned in a different order (e.g., filters) or omitted. Other components can be (and frequently are) added (e.g., additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.).

[0047] As a person of ordinary skill in the art will understand, a system like the general type shown in FIG. 5 is beneficially impacted by the aspects discussed herein in various ways, including better range, better transmission fidelity, lower power, and longer battery life. These system-level improvements are specifically enabled by the aspects discussed herein at least because a number of RF standards require high linearity and low power consumption while increasing power output efficiently. Accordingly, some embodiments include or are systems having features similar or identical to the general type shown in FIG. 5 in which various aspects discussed herein are incorporated.

[0048] Fig. 2 illustrates features of a power amplifier 200 according to some embodiments. Power amplifier 200 includes power amplifier transistors 205, 215, and 225, bias voltage generators 208, 218, and 228, input transformer Xi, input transformer tap resistor Rci, and output transformer Xo. The power amplifier 200 may be used, for example, as power amplifier 138 illustrated in Figure 1.

[0049] Bias voltage generator 208 is configured to generate a first gate bias voltage at the gates of power amplifier transistors 205. For example, bias voltage generator 208 may be configured to receive an indication of input power or of output power, and to generate the first gate bias voltage based on the received indication. In some embodiments, bias voltage generator 208 generates the first gate bias voltage by providing a current to input transformer Xi to adjust the common mode output voltage of input transformer Xi according to input transformer tap resistor Rci coupled to an input common mode voltage source Vci. Bias voltage generator 208 may have features similar or identical to the bias voltage generator circuits discussed elsewhereDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTherein, for example, with reference to figures 3, 4, and / or 5. Other bias voltage generator circuits may be used.

[0050] Bias voltage generator 218 is configured to generate a second gate bias voltage at the gates of power amplifier transistors 215. For example, bias voltage generator 218 may be configured to receive an indication of input power or of output power, and to generate the second gate bias voltage based on the received indication. In some embodiments, bias voltage generator 218 generates the second gate bias voltage by providing a current to a bias voltage source through a resistor. Bias voltage generator 218 may have features similar or identical to the bias voltage generator circuits discussed elsewhere herein, for example, with reference to figures 3, 4, and / or 5. Other bias voltage generator circuits may be used.

[0051] Bias voltage generator 228 is configured to generate a third gate bias voltage at the gates of power amplifier transistors 225. For example, bias voltage generator 228 may be configured to receive an indication of input power or of output power, and to generate the third gate bias voltage based on the received indication. In some embodiments, bias voltage generator 228 generates the third gate bias voltage by providing a current to a bias voltage source through a resistor. Bias voltage generator 228 may have features similar or identical to the bias voltage generator circuits discussed elsewhere herein, for example, with reference to figures 3, 4, and / or 5. Other bias voltage generator circuits may be used.

[0052] Power amplifier 200 is configured to receive an RF input signal input node IN, and to generate a differential RF input signal at the gates of power amplifier transistors 205. The differential RF input signal causes a differential current output signal to be produced across the input inductor of the output transformer Xo, which generates an RF output signal at output node OUT according to the differential current output signal.

[0053] In the illustrated embodiment, power amplifier 200 includes three pairs of power amplifier transistors. In alternative embodiments, power amplifier 200 may include fewer or additional pairs of power amplifier transistors. Each of the fewer or additional pairs of power amplifier transistors may receive gate bias voltages from circuits having features similar or identical to the bias voltage generator circuits discussed herein.

[0054] Fig. 3 illustrates a portion of a power amplifier 300 having a bias voltage generator circuit 310 and power amplifier transistors 305 according to some embodiments. Bias voltage generator circuit 310 provides generates a bias voltage for the gates of power amplifier transistors 305. In some embodiments, power amplifier transistors 305 may correspond withDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTor be used as power amplifier transistors 205 of power amplifier 200. In some embodiments, bias voltage generator circuit 310 may correspond with or be used as bias voltage generator 208 of power amplifier 200. Alternatively, power amplifier transistors 305 and bias voltage generator circuit 310 may be used or correspond with other portions of power amplifier 200 or with portions of other power amplifiers.

[0055] Bias voltage generator circuit 310 includes input resistors Rl, bias generation transistors 312 and 314, and coupling capacitor C. Input resistors Rl are coupled to a voltage reference input node and the gates of bias generation transistors 312 and 314. In the illustrated embodiment, the source of each bias generation transistors 312 and 314 is coupled to the gate of a different one of power amplifier transistors 305, and the drain of each bias generation transistors 312 and 314 is coupled to the drain of a different one of power amplifier transistors 305. As illustrated, each bias generation transistor 312 and 314 has its source coupled to one of the power amplifier transistors 305 and its drain coupled to the other of the power amplifier transistors 305. Furthermore, coupling capacitor C is coupled to the gates of power amplifier transistors 305.

[0056] Bias voltage generator circuit 310 receives a reference voltage Vref at the voltage reference input node coupled to input resistors Rl. Input resistors Rl provide the reference voltage Vref as a DC bias to the gates of bias generation transistors 312 and 314. In some embodiments, the reference voltage Vref is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltage drop above the expected gate voltages of power amplifier transistors 305 at a nominal input or output power condition.

[0057] In operation, increased input power results in a greater RF signal amplitude in the differential RF signal across the gates of power amplifier transistors 305. The greater RF signal amplitude causes each of bias generation transistors 312 and 314 to experience greater Vgs voltage swings. During each swing, one of bias generation transistors 312 and 314 experiences a greater gate to source voltage (Vgs), and the other experiences a lesser Vgs. While the changes in Vgs are substantially equal and opposite, the effect on current is not equal and opposite. Because the current conduction response of bias generation transistors 312 and 314 is not linear, the collective current conduction of bias generation transistors 312 and 314 is positively correlated with RF signal input amplitude across the gates of power amplifier transistors 305 increases. Accordingly, increased RF signal input amplitude results in increased current from bias generation transistors 312 and 314 to the gates of power amplifier transistors 305, and decreased RF signal input amplitude results in decreased current from bias generationDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTtransistors 312 and 314 to the gates of power amplifier transistors 305. Therefore, increased RF signal input amplitude causes an increase in the gate voltages of power amplifier transistors 305, and correspondingly causes increased conduction in power amplifier transistors 305. Accordingly, bias voltage generator circuit 310 provides a negative feedback loop which increases the stability of the voltages at the drains of power amplifier transistors 305.

[0058] Furthermore, in some embodiments, increased power sourced by power amplifier the 300 causes the voltages at the drains of power amplifier transistors 305 to increase. The resulting increased Vds of bias generation transistors 312 and 314 causes bias generation transistors 312 and 314 to provide increased current to the gates of power amplifier transistors 305. As a result, the gate voltages of power amplifier transistors 305 increase, causing power amplifier transistors 305 to conduct more current from the drains of power amplifier transistors 305. Similarly, decreased power sourced by power amplifier 300 causes the voltages at the drains of power amplifier transistors 305 to decrease. The resulting decreased Vds of bias generation transistors 312 and 314 causes bias generation transistors 312 and 314 to provide decreased current to the gates of power amplifier transistors 305. As a result, the gate voltages of power amplifier transistors 305 decrease, causing power amplifier transistors 305 to conduct less current from the drains of power amplifier transistors 305. Accordingly, bias voltage generator circuit 310 provides a negative feedback loop which increases the stability of the voltages at the drains of power amplifier transistors 305.

[0059] Coupling capacitor C is coupled to the gates of bias generation transistors 312 and 314. In operation, coupling capacitor C attenuates coupling of the RF signal from the drains and sources of bias generation transistors 312 and 314 to the gates of bias generation transistors 312 and 314. Consequently, the currents provided to the gates of bias generation transistors 312 and 314 are less influenced by the RF signal of power amplifier 300.

[0060] Fig. 4 illustrates a portion of a power amplifier 400 having a bias voltage generator circuit 410 and power amplifier transistors 405 according to some embodiments. Bias voltage generator circuit 410 provides generates a bias voltage for the gates of power amplifier transistors 405. In some embodiments, power amplifier transistors 405 may correspond with or be used as power amplifier transistors 205 of power amplifier 200. In some embodiments, bias voltage generator circuit 410 may correspond with or be used as bias voltage generator 208 of power amplifier 200. Alternatively, power amplifier transistors 405 and bias voltage generator circuit 410 may be used or correspond with other portions of power amplifier 200 or with portions of other power amplifiers.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0061] Bias voltage generator circuit 410 includes input resistors Rl, bias generation transistors 412 and 414, and coupling capacitor C. Input resistors Rl are each coupled to the gate of one of the power amplifier transistors 405 and to the gate of one of the bias generation transistors 412 and 414. In addition, each input resistor Rl is coupled to the gate of one of the power amplifier transistors 405 and to the source of the other of the power amplifier transistors 405. Furthermore, the source of each bias generation transistors 412 and 414 is coupled to the gate of a different one of power amplifier transistors 405, and the drain of each bias generation transistors 412 and 414 is coupled to the drain of a different one of power amplifier transistors 405. As illustrated, each bias generation transistor 412 and 414 has its source coupled to one of the power amplifier transistors 405and its drain coupled to the other of the power amplifier transistors 405. Furthermore, coupling capacitor C is coupled to the gates of power amplifier transistors 405.

[0062] Bias voltage generator circuit 410 effectively receives the gate voltages of power amplifier transistors 405 at input resistors Rl as a gate bias voltage for bias generation transistors 412 and 414.

[0063] In operation, increased input power has a greater RF signal amplitude in the differential RF signal across the gates of power amplifier transistors 405. The greater RF signal amplitude causes each of bias generation transistors 412 and 414 to experience greater Vgs voltage swings. During each swing, one of bias generation transistors 412 and 414 experiences a greater gate to source voltage (Vgs), and the other experiences a lesser Vgs. While the changes in Vgs are substantially equal and opposite, the effect on current is not equal and opposite. Because the current conduction response of bias generation transistors 412 and 414 is not linear, the collective current conduction of bias generation transistors 412 and 414 is positively correlated with RF signal input amplitude across the gates of power amplifier transistors 405 increases. Accordingly, increased RF signal input amplitude results in increased current from bias generation transistors 412 and 414 to the gates of power amplifier transistors 405, and decreased RF signal input amplitude results in decreased current from bias generation transistors 412 and 414 to the gates of power amplifier transistors 405. Therefore, increased RF signal input amplitude causes an increase in the gate voltages of power amplifier transistors 405, and correspondingly causes increased conduction in power amplifier transistors 405. Accordingly, bias voltage generator circuit 410 provides a negative feedback loop which increases the stability of the voltages at the drains of power amplifier transistors 405. Because the nominal Vgs voltages of bias generation transistors 412 and 414 are less than the VgsDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTvoltages of bias generation transistors 412 and 414 of power amplifier 400, the sensitivity of bias voltage generator circuit 410 to differences in power is greater than the sensitivity of bias voltage generator circuit 410. Accordingly, as discussed in further detail below, the effect of bias voltage generator circuit 410 on the power amplifier performance is more advantageous than the effect of bias voltage generator circuit 410 on power amplifier performance.

[0064] Furthermore, increased power sourced by power amplifier the 400 causes the voltages at the drains of power amplifier transistors 405 to increase. The resulting increased Vds of bias generation transistors 412 and 414 causes bias generation transistors 412 and 414 to provide increased current to the gates of power amplifier transistors 405. As a result, the gate voltages of power amplifier transistors 405 increase, causing power amplifier transistors 405 to conduct more current from the drains of power amplifier transistors 405. Similarly, decreased power sourced by power amplifier 400 causes the voltages at the drains of power amplifier transistors 405 to decrease. The resulting decreased Vds of bias generation transistors 412 and 414 causes bias generation transistors 412 and 414 to provide decreased current to the gates of power amplifier transistors 405. As a result, the gate voltages of power amplifier transistors 405 decrease, causing power amplifier transistors 405 to conduct less current from the drains of power amplifier transistors 405. Accordingly, bias voltage generator circuit 410 provides a negative feedback loop which increases the stability of the voltages at the drains of power amplifier transistors 405.

[0065] Coupling capacitor C is coupled to the gates of bias generation transistors 412 and 414. In operation, coupling capacitor C attenuates coupling of the RF signal from the drains and sources of bias generation transistors 412 and 414 to the gates of bias generation transistors 412 and 414. Consequently, the currents provided to the gates of bias generation transistors 412 and 414 are less influenced by the RF signal of power amplifier 400.

[0066] Fig. 5 illustrates a portion of a power amplifier 500 having a bias voltage generator circuit 510 and power amplifier transistors 515 according to some embodiments. Bias voltage generator circuit 510 provides generates a bias voltage for the gates of power amplifier transistors 515. In some embodiments, power amplifier transistors 515 may correspond with or be used as power amplifier transistors 215 or 225 of power amplifier 200. In some embodiments, bias voltage generator circuit 510 may correspond with or be used as bias voltage generator 218 or 228 of power amplifier 200. Alternatively, power amplifier transistors 515 and bias voltage generator circuit 510 may be used or correspond with other portions of power amplifier 200 or with portions of other power amplifiers.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0067] Bias voltage generator circuit 510 includes input resistors R1 and coupling capacitor Cl. Input resistors R1 are coupled to a voltage reference input node and the gates of Power amplifier transistors 515. Furthermore, coupling capacitor Cl is coupled to the gates of power amplifier transistors 515. Bias voltage generator circuit 510 also includes coupling network 520 comprising Coupling capacitors C2, resistors R2, diodes D, resistors R3, and coupling capacitor C3.

[0068] Bias voltage generator circuit 510 receives a reference voltage Vref at the voltage reference input node coupled to input resistors Rl. Input resistors R1 provide the reference voltage Vref as a DC bias to the gates of power amplifier transistors 515 and to coupling network 520. In some embodiments, the reference voltage Vref is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltage drop above the expected source voltages of power amplifier transistors 515 at a nominal input or output power condition.

[0069] Coupling network 520 is configured to transiently change the gate voltages of power amplifier transistors 515 according to power of power amplifier 500.

[0070] In operation, increased input power has a greater RF signal amplitude in the differential RF signal across the sources of power amplifier transistors 515. The greater RF signal amplitude causes the sources of each of power amplifier transistors 515 to experience greater voltage swings. During each swing, one of power amplifier transistors 515 experiences a greater source voltage, and the other experiences a reduced source voltage. The power amplifier transistor 515 experiencing a greater source voltage also experiences a greater gate voltage because of coupling network 520. For example, because of the increased source voltage, coupling capacitor C2 injects charge through resistor R2 as a bias current to the gate, and the gate voltage correspondingly increases. As a result, the power amplifier transistor 515 experiencing the greater source voltage conducts more current from its drain to its source than it would without the increased gate voltage. The increased current relatively reduces the increase in drain voltage. The power amplifier transistor 515 experiencing a decreased source voltage does not experience a similarly corresponding decrease in gate voltage. Instead, any potential decrease in the gate voltage is mitigated, reduced, or eliminated because charge is provided to coupling capacitor C2 from voltage reference Vref through resistor R3 and diode D instead of from the gate of the power amplifier transistor 515. As a result, the power amplifier transistor 515 experiencing the decreased source voltage has a greater Vgs voltage and becomes more conductive, and, accordingly, resists further reduction in the decreased source voltage byDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTsourcing additional current. Coupling capacitor C3 attenuates RF signal at the anodes of diodes D. Accordingly, bias voltage generator circuit 510 provides a negative feedback loop which increases the stability of the Vds voltages of power amplifier transistors 515, and any other power amplifier transistors (not shown) also in the power amplifier.

[0071] Coupling capacitor Cl is coupled to the gates of bias generation transistors 512 and 514. In operation, coupling capacitor Cl attenuates unwanted coupling of the RF signal from the drains and sources of bias generation transistors 512 and 514 to the gates of bias generation transistors 512 and 514.

[0072] Fig. 6 illustrates features of a power amplifier 600 according to some embodiments. Power amplifier 600 includes power amplifier transistors 605, 615, and 625, bias voltage generators 608, 618, and 628, input transformer Xi, input transformer tap resistor Rci, and output transformer Xo. The power amplifier 600 may be used, for example, as power amplifier 138 illustrated in Figure 1.

[0073] Bias voltage generator 608 may be considered a common gate class B bias generator (CGCBB), and is configured to generate a first gate bias voltage at the gates of power amplifier transistors 605. In the illustrated embodiment, bias voltage generator 608 is configured to receive an indication of input power or of output power, for example, at either or both the gates and drains of power amplifier transistors 605, and to generate the first gate bias voltage based on the received indication. In the illustrated embodiment, bias voltage generator 608 generates the first gate bias voltage by providing a current to input transformer Xi to adjust the common mode output voltage of input transformer Xi according to input transformer tap resistor Rci coupled to input common mode voltage Vci. Bias voltage generator 608 is an embodiment of bias voltage generator circuit 310, discussed with reference to figure 3, and operates according to principles similar or identical to those discussed above with reference to bias voltage generator circuit 310. Other bias voltage generator circuits may be used.

[0074] Bias voltage generator 618 may be considered a fixed voltage bias generator, and is configured to generate a second gate bias voltage at the gates of power amplifier transistors 615. In the illustrated embodiment, bias voltage generator 618 is configured to receive a reference voltage Vref2 at a voltage reference input node coupled to the input resistors of bias voltage generator 618. The input resistors provide the reference voltage Vref2 as a DC bias to the gates of power amplifier transistors 615. In some embodiments, the reference voltage Vref2 is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltageDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTdrop above the expected source voltages of power amplifier transistors 615 at a nominal input or output power condition. The coupling capacitor of bias voltage generator 618 is coupled to the gates of power amplifier transistors 615. In operation, the coupling attenuates coupling of the RF signal from the drains and sources of power amplifier transistors 615 to the gates of power amplifier transistors 615. Consequently, the bias voltage provided to the gates of power amplifier transistors 615 are less influenced by the RF signal of power amplifier 600. Other bias voltage generator circuits may be used.

[0075] Bias voltage generator 628 is configured to generate a second gate bias voltage at the gates of power amplifier transistors 625. In the illustrated embodiment, bias voltage generator 628 is configured to receive a reference voltage Vref3 at a voltage reference input node coupled to the input resistors of bias voltage generator 628. The input resistors provide the reference voltage Vref3 as a DC bias to the gates of power amplifier transistors 625. In some embodiments, the reference voltage Vref3 is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltage drop above the expected source voltages of power amplifier transistors 625 at a nominal input or output power condition. The coupling capacitor of bias voltage generator 628 is coupled to the gates of power amplifier transistors 625. In operation, the coupling attenuates coupling of the RF signal from the drains and sources of power amplifier transistors 625 to the gates of power amplifier transistors 625. Consequently, the bias voltage provided to the gates of power amplifier transistors 625 are less influenced by the RF signal of power amplifier 600. Other bias voltage generator circuits may be used.

[0076] Power amplifier 600 is configured to receive an RF input signal input node IN, and to generate a differential RF input signal at the gates of power amplifier transistors 605. The differential RF input signal causes a differential current output signal to be produced across the input inductor of the output transformer Xo, which generates an RF output signal at output node OUT according to the differential current output signal. Certain performance parameters of power amplifier 600 are discussed below, for example, with reference to figures 8-10.

[0077] In the illustrated embodiment, power amplifier 600 includes three pairs of power amplifier transistors. In alternative embodiments, power amplifier 600 may include fewer or additional pairs of power amplifier transistors. Each of the fewer or additional pairs of power amplifier transistors may receive gate bias voltages from circuits having features similar or identical to the bias voltage generator circuits discussed herein.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0078] Fig. 7 illustrates features of a power amplifier 700 according to some embodiments. Power amplifier 700 includes power amplifier transistors 705, 715, and 725, bias voltage generators 708, 718, and 728, input transformer Xi, input transformer tap resistor Rci, and output transformer Xo. The power amplifier 700 may be used, for example, as power amplifier 138 illustrated in Figure 1.

[0079] Bias voltage generator 708 may be considered a common source class C bias generator (CSCCB), and is configured to generate a first gate bias voltage at the gates of power amplifier transistors 705. In the illustrated embodiment, bias voltage generator 708 is configured to receive an indication of input power or of output power, for example, at either or both the gates and drains of power amplifier transistors 705, and to generate the first gate bias voltage based on the received indication. In the illustrated embodiment, bias voltage generator 708 generates the first gate bias voltage by providing a current to input transformer Xi to adjust the common mode output voltage of input transformer Xi according to input transformer tap resistor Rci coupled to input common mode voltage Vci. Bias voltage generator 708 is an embodiment of bias voltage generator circuit 410, discussed with reference to figure 4, and operates according to principles similar or identical to those discussed above with reference to bias voltage generator circuit 410. Other bias voltage generator circuits may be used.

[0080] Bias voltage generator 718 may be considered a fixed voltage bias generator, and is configured to generate a second gate bias voltage at the gates of power amplifier transistors 715. In the illustrated embodiment, bias voltage generator 718 is configured to receive a reference voltage Vref2 at a voltage reference input node coupled to the input resistors of bias voltage generator 718. The input resistors provide the reference voltage Vref2 as a DC bias to the gates of power amplifier transistors 715. In some embodiments, the reference voltage Vref2 is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltage drop above the expected source voltages of power amplifier transistors 715 at a nominal input or output power condition. The coupling capacitor of bias voltage generator 718 is coupled to the gates of power amplifier transistors 715. In operation, the coupling attenuates coupling of the RF signal from the drains and sources of power amplifier transistors 715 to the gates of power amplifier transistors 715. Consequently, the bias voltage provided to the gates of power amplifier transistors 715 are less influenced by the RF signal of power amplifier 700. Other bias voltage generator circuits may be used.

[0081] Bias voltage generator 728 is configured to generate a second gate bias voltage at the gates of power amplifier transistors 725. In the illustrated embodiment, bias voltage generatorDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCT728 is configured to receive a reference voltage Vref3 at a voltage reference input node coupled to the input resistors of bias voltage generator 728. The input resistors provide the reference voltage Vref3 as a DC bias to the gates of power amplifier transistors 725. In some embodiments, the reference voltage Vref3 is set to be equal or substantially equal to one gate source voltage (Vgs) or one diode voltage drop above the expected source voltages of power amplifier transistors 725 at a nominal input or output power condition. The coupling capacitor of bias voltage generator 728 is coupled to the gates of power amplifier transistors 725. In operation, the coupling attenuates coupling of the RF signal from the drains and sources of power amplifier transistors 725 to the gates of power amplifier transistors 725. Consequently, the bias voltage provided to the gates of power amplifier transistors 725 are less influenced by the RF signal of power amplifier 700. Other bias voltage generator circuits may be used.

[0082] Power amplifier 700 is configured to receive an RF input signal input node IN, and to generate a differential RF input signal at the gates of power amplifier transistors 705. The differential RF input signal causes a differential current output signal to be produced across the input inductor of the output transformer Xo, which generates an RF output signal at output node OUT according to the differential current output signal. Certain performance parameters of power amplifier 700 are discussed below, for example, with reference to figures 8-10.

[0083] In the illustrated embodiment, power amplifier 700 includes three pairs of power amplifier transistors. In alternative embodiments, power amplifier 700 may include fewer or additional pairs of power amplifier transistors. Each of the fewer or additional pairs of power amplifier transistors may receive gate bias voltages from circuits having features similar or identical to the bias voltage generator circuits discussed herein.

[0084] Figs. 8-10 illustrate performance parameters of power amplifiers according to some embodiments.

[0085] Fig. 8 illustrates a graph 800 showing power amplifier transistor gate voltages Vg as a function of RF output signal power for the embodiments illustrated in Figs. 6 and 7.

[0086] Curve 810 illustrates the gate voltages of power amplifier transistors 605 of power amplifier 600. As shown, as RF output signal power increases, the gate voltages of power amplifier transistors 605 correspondingly increase.

[0087] Curve 820 illustrates the gate voltages of power amplifier transistors 705 of power amplifier 700. As shown, as RF output signal power increases, the gate voltages of power amplifier transistors 705 also correspondingly increase. Furthermore, the increase in the gateDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTvoltages of power amplifier transistors 705 is greater than the increase in the gate voltages of power amplifier transistors 605.

[0088] Fig. 9 illustrates a graph 900 showing power amplifier amplitude-to-phase modulation (AM / PM) performance as a function of RF output signal power for the embodiments illustrated in Figs. 6 and 7.

[0089] Curve 910 illustrates amplitude-to-phase modulation (AM / PM) performance of power amplifier 600. Curve 920 illustrates the amplitude-to-phase modulation (AM / PM) performance of power amplifier 700. As shown, the amplitude-to-phase modulation (AM / PM) performance of power amplifier 700 is better than the amplitude-to-phase modulation (AM / PM) performance of power amplifier 600.

[0090] Fig. 10 illustrates a graph 1000 showing power amplifier amplitude-to-amplitude modulation (AM / AM) performance as a function of RF output signal power for the embodiments illustrated in Figs. 6 and 7.

[0091] Curve 1010 illustrates amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 600. Curve 1020 illustrates the amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 700. As shown, the amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 700 is better than the amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 600.

[0092] Fig. 11 illustrates features of a power amplifier 1100 according to some embodiments. Power amplifier 1100 includes power amplifier transistors 1105, 1115, and 1125, bias voltage generators 1108, 1118, and 1128, input transformer Xi, input transformer tap resistor Rci, and output transformer Xo. The power amplifier 1100 may be used, for example, as power amplifier 138 illustrated in Figure 1.

[0093] Bias voltage generator 1108 is an embodiment of a bias voltage generator circuit which is similar to bias voltage generator circuit 310, discussed with reference to figure 3, and operates according to principles similar or identical to those discussed above with reference to bias voltage generator circuit 310. In some embodiments, bias voltage generator circuit 310 or bias voltage generator circuit 410 is used. Other bias voltage generator circuits may be used.

[0094] Bias voltage generator 1118, having coupling network 1119, is an embodiment of bias voltage generator circuit 510 , discussed with reference to figure 5, and operates according to principles similar or identical to those discussed above with reference to bias voltage generator circuit 510. Other bias voltage generator circuits may be used.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0095] Bias voltage generator 1128, having coupling network 1129, is an embodiment of bias voltage generator circuit 510, discussed with reference to figure 5, and operates according to principles similar or identical to those discussed above with reference to bias voltage generator circuit 510. Other bias voltage generator circuits may be used.

[0096] Power amplifier 1100 is configured to receive an RF input signal input node IN, and to generate a differential RF input signal at the gates of power amplifier transistors 1105. The differential RF input signal causes a differential current output signal to be produced across the input inductor of the output transformer Xo, which generates an RF output signal at output node OUT according to the differential current output signal. Certain performance parameters of power amplifier 1100 are discussed below, for example, with reference to figures 12-15.

[0097] In the illustrated embodiment, power amplifier 1100 includes three pairs of power amplifier transistors. In alternative embodiments, power amplifier 1100 may include fewer or additional pairs of power amplifier transistors. Each of the fewer or additional pairs of power amplifier transistors may receive gate bias voltages from circuits having features similar or identical to the bias voltage generator circuits discussed herein.

[0098] Figs. 12-15 illustrate performance parameters of power amplifier 1100 according to some embodiments.

[0099] Fig. 12 illustrates a graph 1200 showing power amplifier transistor gate voltages Vg as a function of RF output signal power for power amplifier 1100 illustrated in Fig. 11.

[0100] Curve 1205 illustrates the gate voltages of power amplifier transistors 1105 of power amplifier 1100. As shown, as RF output signal power increases, the gate voltages of power amplifier transistors 1105 correspondingly increase.

[0101] Curve 1215 illustrates the gate voltages of power amplifier transistors 1115 of power amplifier 1100. As shown, as RF output signal power increases, the gate voltages of power amplifier transistors 1115 correspondingly increase. Curves 1205 and 1215 also illustrate that the gate voltages of power amplifier transistors 1115 are greater than the gate voltages of power amplifier transistors 1105, as expected.

[0102] Curve 1225 illustrates the gate voltages of power amplifier transistors 1125 of power amplifier 1100. As shown, as RF output signal power increases, the gate voltages of power amplifier transistors 1125 correspondingly increase. Curves 1205, 1215, and 1225 also illustrate that the gate voltages of power amplifier transistors 1125 are greater than the gate voltages of power amplifier transistors 1115 and 1105, as expected.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0103] Fig. 13 illustrates a graph 1300 showing power amplifier transistor drain to source voltages Vds as a function of RF output signal power for power amplifier 1100 illustrated in Fig. H.

[0104] Curve 1305 illustrates the Vds voltages of power amplifier transistors 1105 of power amplifier 1100. Curve 1315 illustrates the Vds voltages of power amplifier transistors 1115 of power amplifier 1100. Curve 1325 illustrates the Vds voltages of power amplifier transistors 1125 of power amplifier 1100. As shown, as RF output signal power increases, the Vds voltages of power amplifier transistors 1105, 1115, and 1125 change by less than about 0.1 V for output power less than about 10 dBm.

[0105] Fig. 14 illustrates a graph 1400 showing amplitude-to-phase modulation (AM / PM) performance of power amplifier 1100 illustrated in Fig. 11 as a function of RF output signal power.

[0106] Curve 1410 shows amplitude-to-phase modulation (AM / PM) of a power amplifier having three fixed bias voltage generators, such as bias voltage generators 718 and 728 of power amplifier 700. In addition, curve 1420 shows amplitude-to-phase modulation (AM / PM) of power amplifier 1100. As shown, the amplitude-to-phase modulation (AM / PM) performance of power amplifier 1100 is better than the amplitude-to-phase modulation (AM / PM) performance of the power amplifier having three fixed bias volage generators.

[0107] Fig. 15 illustrates a graph 1500 showing amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 1100 illustrated in Fig. 11 as a function of RF output signal power.

[0108] Curve 1510 shows amplitude-to-amplitude modulation (AM / AM) of a power amplifier having three fixed bias voltage generators, such as bias voltage generators 718 and 728 of power amplifier 700. In addition, curve 1520 shows amplitude-to-amplitude modulation (AM / AM) of power amplifier 1100. As shown, the amplitude-to-amplitude modulation (AM / AM) performance of power amplifier 1100 is better or at least no worse than the amplitude-to-amplitude modulation (AM / AM) performance of the power amplifier having three fixed bias volage generators.

[0109] Fig. 16 illustrates flowchart diagram of a method 1600 of amplifying power. The method may be performed, for example, by any of the power amplifiers discussed herein.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0110] At block 1610, an indication of power output of the power amplifier is sensed. For example, as discussed herein, one or more bias voltage generator circuits may sense the indication of power output of the power amplifier.[oni] At block 1620, a bias current is sourced to gates of first and second power amplifier transistors based on the sensed indication. As a result, the bias current maintains or changes gate bias voltages of the first and second power amplifier transistors. For example, as discussed herein, one or more bias voltage generator circuits may source the bias current based on the sensed indication.

[0112] In some embodiments, the bias current is sourced from first and second current paths respectively including the first and second power amp transistors. In some embodiments, the indication of power output is sensed at the first and second gates of the first and second power amplifier transistors. In some embodiments, the indication of power output is sensed at first and second sources of the first and second power amplifier transistors. In some embodiments, on or more other functions described with reference to the power amplifiers and / or bias voltage generator circuits discussed herein are additionally or alternatively performed as part of method 1600.

[0113] Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also, where applicable, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and / or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the spirit of the present disclosure. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice-versa.

[0114] Software in accordance with the present disclosure, such as program code and / or data, can be stored on one or more computer readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and / or separated into sub-steps to provide features described herein.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT

[0115] Embodiments described above illustrate but do not limit the invention. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.

Claims

Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCTCLAIMSWhat is claimed is:

1. A power amplifier, comprising:a first power amplifier transistor;a second power amplifier transistor; anda first bias generator coupled to the first and second power amplifier transistors, wherein the first bias generator comprises:a power sense input configured to sense an indication of power of the power amplifier, anda bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.

2. The power amplifier of claim 1, further comprising:a first current path comprising the first power amp transistor; anda second current path comprising the second power amp transistor,wherein the first bias generator is coupled to the first and second current paths, and wherein the bias output of the first bias generator is configured to source the bias current from the first and second current paths to the first and second power amp transistors.

3. The power amplifier of claim 1, wherein the power sense input is coupled to first and second gates of the first and second power amplifier transistors, respectively.

4. The power amplifier of claim 1, wherein the power sense input is coupled to first and second sources of the first and second power amplifier transistors, respectively.

5. The power amplifier of claim 1, wherein the bias output is coupled to first and second gates of the first and second power amplifier transistors, respectively.

6. The power amplifier of claim 1, further comprising an input transformer coupled to a common mode voltage source by a resistor.

7. The power amplifier of claim 1, wherein the first bias generator further comprises first and second bias generation transistors configured to source the bias current, wherein first and second gates of the first and second bias generation transistors are respectively coupled to the first and second power amplifier transistors by first and second resistors, respectively.

8. The power amplifier of claim 1, wherein the first bias generator further comprises first and second coupling capacitors configured to respectively couple charge from first andDocket No. 61658.235WO01 Client Ref. No.: PER-593-PCTsecond sources of the first and second power amplifier transistors to first and second gates of the first and second power amplifier transistors, respectively.

9. A method of amplifying power, the method comprising:sensing an indication of power output of the power amplifier; andsourcing a bias current to first and second gates of first and second power amplifier transistors based on the sensed indication, wherein the bias current causes first and second gate bias voltages to change.

10. The method of claim 9, further comprising sourcing the bias current from first and second current paths respectively including the first and second power amp transistors.

11. The method of claim 9, further comprising sensing the indication of power at the first and second gates of the first and second power amplifier transistors.

12. The method of claim 9, further comprising sensing the indication of power at first and second sources of the first and second power amplifier transistors.

13. A transmitter, comprising:a mixer configured to generate an RF signal; anda power amplifier configured to amplify the RF signal, the power amplifier comprising:a first power amplifier transistor;a second power amplifier transistor; anda first bias generator coupled to the first and second power amplifier transistors, wherein the first bias generator comprises:a power sense input configured to sense an indication of power of the power amplifier, anda bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.

14. The transmitter of claim 13, wherein the power amplifier further comprises:a first current path comprising the first power amp transistor; anda second current path comprising the second power amp transistor,wherein the first bias generator is coupled to the first and second current paths, and wherein the bias output of the first bias generator is configured to source the bias current from the first and second current paths to the first and second power amp transistors.Docket No. 61658.235WO01 Client Ref. No.: PER-593-PCT15. The transmitter of claim 13, wherein the power sense input is coupled to first and second gates of the first and second power amplifier transistors, respectively.

16. The transmitter of claim 13, wherein the power sense input is coupled to first and second sources of the first and second power amplifier transistors, respectively.

17. The transmitter of claim 13, wherein the bias output is coupled to first and second gates of the first and second power amplifier transistors, respectively.

18. The transmitter of claim 13, wherein the power amplifier further comprises an input transformer coupled to a common mode voltage source through a resistor.

19. The transmitter of claim 13, wherein the first bias generator further comprises first and second bias generation transistors configured to source the bias current, wherein first and second gates of the first and second bias generation transistors are respectively coupled to the first and second power amplifier transistors by first and second resistors, respectively.

20. The transmitter of claim 13, wherein the first bias generator further comprises first and second coupling capacitors configured to respectively couple charge from first and second sources of the first and second power amplifier transistors to first and second gates of the first and second power amplifier transistors, respectively.

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