Ferroelectric devices enabled by superlattice structure and methods of making and using thereof

Abstract

Ferroelectric devices enabled by superlattice structure and methods of making and using thereof. The superlattice structures can be MnXm / ApBq / NInXm superlattice structures, such as HfO2 / Al2O3 / HfO2 superlattice structures or HfO2 / ZrO2 superlattice structures. The process to make these superlattice structures can include flash Joule heating (FJH), for rapid thermal annealing (RTA), and achieving precise crystallization at a heating rate of 900 °C / s and a cooling rate of 200 °C / s. The ferroelectric devices can exhibit low operation voltage (<3 V), fast switching speed (nanosecond domain), high retention (>10 years), and high endurance (>108 cycles). The ferroelectric superlattice structures can replace or complement conventional NAND flash memory, including SLC, MLC, TLC, and QLC architectures, as well as dynamic random access memory (DRAM), by enabling fast, nonvolatile, and energy-efficient memory operation. Such devices are applicable in embedded systems, Al accelerators, cold and warm data storage, and neuromorphic and compute-in-memory platforms.

Description

Attorney Docket No.: 072174-07704FERROELECTRIC DEVICES ENABLED BY SUPERLATTICE STRUCTURE AND METHODS OF MAKING AND USING THEREOF CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] The application claims priority to U.S. Patent Appl. Serial No. 63 / 754,436, to James M. Tour, etal., entitled “Ferroelectric Devices Enabled By Superlattice Structure AndMethods Of Making And Using Thereof,” filed February 5, 2025.

[0002] The application further claims priority to U.S. Patent Appl. Serial No. 63 / 790,442, to James M. Tour, et al., entitled “Ferroelectric Devices Enabled By Superlattice Structure And Methods Of Making And Using Thereof,” filed April 17, 2025.

[0003] The application further claims priority to U.S. Patent Appl. Serial No. 63 / 880,629, to James M. Tour, et al., entitled “Ferroelectric Devices Enabled By Superlattice Structure And Methods Of Making And Using Thereof,” filed September 12, 2025.

[0004] The application further claims priority to U.S. Patent Appl. Serial No. 63 / 946,511, to James M. Tour, et al., entitled “Ferroelectric Devices Enabled By Superlattice Structure And Methods Of Making And Using Thereof,” filed December 22, 2025.

[0005] Each of these patent applications is commonly owned by the owner of the present invention_and is incorporated herein in its entirety.TECHNICAL FIELD

[0006] The present invention relates to ferroelectric devices enabled by superlattice structure and methods of making and using thereof, and, more particularly, ferroelectric devices enabled by superlattice structure for neuromorphic computing and artificial intelligence (Al) chips and methods of making and using thereof and specifically including potential replacement or complementary usage for traditional NAND flash memory, DRAM and other related memory applications.GOVERNMENT INTEREST

[0007] This invention was made with government support under Grant No. FA9550-22-1-Attorney Docket No.: 072174-07704 0526, awarded by the Air Force Office of Scientific Research, Grant No. W912HZ-21-2-0050, awarded by the United States Engineer Research and Development Center for the United States Army Corp of Engineers, and Grant No. HR0011-22-9-0122 by the Defense Advanced Research Projects Agency (DARPA) of the United States Department of Defense. The United States government has certain rights in the invention.BACKGROUND

[0008] The advancement of ferroelectric materials has been crucial for developing high-performance, low-power, and scalable electronic devices. [Scott 2007], Traditional ferroelectric materials, such as barium titanate (BTO), strontium titanate (STO), and hafnium zirconium oxide (HZO), have played significant roles in memory, energy storage, and transistor applications. [Daw be r 2005], However, these materials face various limitations. BTO and STO require high processing temperatures and exhibit poor compatibility with silicon-based technology, limiting their scalability. [Uchino 1996], HZO, although CMOS-compatible, suffers from phase instability, requires precise dopant control, and is constrained by wafer selectivity, requiring specific substrates such as titanium nitride (TiN) or platinum (Pt).[Mikolajick 2019}. These challenges restrict their integration into diverse architectures and advanced applications.

[0009] Accordingly, traditional ferroelectric materials, such as barium titanate (BTO), strontium titanate (STO), and hafnium zirconium oxide (HZO), face critical limitations, including high processing temperatures, incompatibility with silicon-based technology, scalability issues, and phase instability. While HZO is CMOS-compatible, it requires precise dopant control and specific substrates like TiN or Pt, making it less versatile for integration into diverse architectures.

[0010] Moreover, conventional NAND flash memory, despite enabling advances in mobile computing, SSD, and data center storage, faces severe limitations including high operationalAttorney Docket No.: 072174-07704 voltages (~20 V), slow operation speeds (microsecond to millisecond domain), limited endurance (~104- 105cycles), increasing complexity in 3D stacking technology, and challenges in further scaling. Thus, a next-generation nonvolatile memory technology that is faster, lower voltage, lower power consumption, more durable, and CMOS-compatible is urgently required.

[0011] Accordingly, the need remains for improved ferroelectric devices.SUMMARY OF THE INVENTION

[0012] The present invention relates to ferroelectric devices enabled by superlattice structure and methods of making and using thereof, and, more particularly, ferroelectric devices enabled by superlattice structure for neuromorphic computing and Al chips and methods of making and using thereof.

[0013] In some embodiments, ferroelectric superlattice structures enable integration of various related device types into nonvolatile memory applications, providing low operation voltage, fast switching, and long-term retention, to replace or complement NAND flash and / or DRAM and / or other related memory device implementations.

[0014] This present invention introduces novel superlattice structures, such as, for example, HfCh / AhOs / HfCh or HfCh / ZrCh superlattice structures, which stabilize the orthorhombic ferroelectric phase of hafnium oxide (HfCh, also known as hafnium dioxide) providing enhanced ferroelectric properties without substrate selectivity. The superlattice design leverages aluminum oxide (AI2O3) layers and / or zirconium oxide (ZrCh, also known as zirconium dioxide) to overcome phase instability while enabling integration with various substrates, including Si, Mo, W, TiN, and Pt. Additionally, embodiments can innovatively employ flash Joule heating (FJH) for rapid thermal annealing, achieving precise crystallization at a heating rate of 900 °C / s and a cooling rate of 200 °C / s. This process not only reduces energy consumption and processing time but also minimizes destructive effects on deviceAttorney Docket No.: 072174-07704 structures, a significant improvement over traditional annealing methods. Moreover, embodiments extend beyond traditional ferroelectric applications to enable hardware-based neuromorphic computing systems in both two-terminal ferroelectric tunneling junction (FTJ) and three-terminal ferroelectric field-effect transistor (Fe-FET) configurations.

[0015] The superlattice structure also provides a scalable, energy-efficient alternative to conventional gate dielectrics in the CMOS industry, addressing the critical need for high-k materials compatible with advanced device architectures. It is believed that the present invention is the first to combine the scalability of HZO, the stabilization offered by AI2O3, and the processing efficiency of FJH to enable next-generation ferroelectric devices and neuromorphic computing systems.

[0016] The ferroelectric devices can exhibit low operation voltage (<3 V), fast switching speed (nanosecond domain), high retention (>10 years), and high endurance (>108cycles), making them suitable for use in next-generation nonvolatile memory and Al applications. The ferroelectric superlattice structures can replace or complement conventional NAND flash memory, including SLC, MLC, TLC, and QLC architectures, as well as dynamic random access memory (DRAM), by enabling fast, nonvolatile, and energy-efficient memory operation. Such devices are applicable in embedded systems, Al accelerators, cold and warm data storage, and neuromorphic and compute-in-memory platforms.

[0017] Various embodiments of the invention, such as FeFET and FTJ configurations described in further detail herein, may offer substantial improvements over existing NAND flash, DRAM and other memory component solutions. These improvements may include one or more of significantly reduced operational voltage (approximately 3 V or lower), ultra-fast operation speeds in the nanosecond domain, enhanced endurance and reliability, simplified device structures, and improved scalability at or below the 10 nm node. In some specific embodiments, both FeFET and FTJ devices are particularly suitable for replacing Single-LevelAttorney Docket No.: 072174-07704 Cell (SLC) flash memory as well as DRAM used in high-performance embedded applications, edge Al devices, and Al accelerators as non-limiting examples. In similar embodiments, both FeFET and FTJ devices, due to their multi-state operation and high-density capabilities, may potentially replace Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC) flash memory in data center and cold / warm storage applications where memory usage may be characterized by low or moderate usage.

[0018] In general, in one embodiment, the invention features a process for fabricating a ferroelectric device. The process includes depositing a superlattice structure comprising layering (I) two or more MnXmlayers and (II) one or more APBqlayers. Each of the MnXmlayers is a layer of MnXm. M is a transition or main group metal. X is selected from the group consisting of N, O, S, and Se. The MnXmof each MnXmlayer is the same or different than the MnXm of the two or more MnXmlayers. In each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m. In each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. Each of the APBqlayers is a layer of APBq. A is a transition or main group metal. B is selected from the group consisting of N, O, S, and Se. The APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers. In each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q. In each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p. One of the MnXmlayers is positioned at a top face of the superlattice structure. Another of the MnXmlayers is positioned at a bottom face of the superlattice structure. The two or more MnXmlayers and the one or more APBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers. The two or more MnXmlayers and the one or more APBqlayers areAttorney Docket No.: 072174-07704 layered in a predetermined thickness ratio. The process further includes using a rapid annealing process to induce ferroelectricity.

[0019] In general, in one embodiment, the invention features a process for fabricating a ferroelectric device. The process includes depositing a superlattice structure comprising layering (I) two or more MnXmlayers and (II) one or more APBqlayers. Each of the MnXmlayers is a layer of MnXm. M is a transition or main group metal. X is selected from the group consisting of N, O, S, and Se. The MnXmof each MnXmlayer is the same or different than the MnXm of the two or more MnXmlayers. In each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m. In each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. Each of the APBqlayers is a layer of APBq. A is a transition or main group metal. B is selected from the group consisting of N, O, S, and Se. The APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers. In each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q. In each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p. One of the MnXmlayers is positioned at a top face of the superlattice structure. Another of the MnXmlayers is positioned at a bottom face of the superlattice structure. The two or more MnXm layers and the one or more APBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers. The two or more MnXmlayers and the one or more APBqlayers are layered in a predetermined thickness ratio. The process further includes using a rapid annealing process to induce ferroelectricity. The process further includes forming a device stack in which the superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-Attorney Docket No.: 072174-07704 ferroelectric-insulator-semiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS).

[0020] Implementations of the invention can include one or more of the following features:

[0021] The thermal processing in steps subsequent to the deposition of a superlattice structure may be controlled such that the superlattice structure is maintained in the resulting product.

[0022] This control of temperature may include one or more of utilizing short duration rapid thermal anneal, and exposure limits to temperatures under 400 °C - 900 °C.

[0023] In general, in another embodiment, the invention features a process for fabricating a ferroelectric device. The process includes depositing a superlattice structure comprising layering (I) two or more MnXm layers and (II) one or more ApBq layers. Each of the MnXm layers is a layer of MnXm. M is a transition or main group metal. X is selected from the group consisting of N, O, S, and Se. The MnXm of each MnXm layer is the same or different than the MnXm of the two or more MnXm layers. In each of the of the MnXm layers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m. In each of the of the MnXm layers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. Each of the ApBq layers is a layer of ApBq. A is a transition or main group metal. B is selected from the group consisting of N, O, S, and Se. The ApBq of each ApBq layer is the same or different than the ApBq of the two or more ApBq layers. In each of the of the ApBq layers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q. In each of the of the ApBq layers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p. At least one of the MnXm layers is positioned at a top face or a bottom face of the superlattice structure. The two or more MnXm layers and the one or more ApBq layers are layered alternatively such that each of the one or more ApBq layers is positioned between two of the two or more MnXm layers. The two or more MnXm layers andAttorney Docket No.: 072174-07704 the one or more ApBq layers are layered in a predetermined thickness ratio. The process further includes using a rapid annealing process to induce ferroelectricity. The process further includes forming a device stack in which the superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-ferroelectric-insulator-semiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal -insulator-ferroelectric-insulator-semiconductor (MIFIS).

[0024] Implementations of the invention can include one or more of the following features:

[0025] MnXm can be HfO2.

[0026] ApBqcan be AI2O3 and / or ZrCh.

[0027] The step of depositing the superlattice structure can include layering a first MnXmlayer, a first ApBq layer, and a second MnXmlayer. The first MnXmlayer can be positioned at the top face of the superlattice structure. The second MnXmlayer can be positioned at the bottom face of the superlattice structure. The first APBqlayer can be positioned between the first MnXmlayer and the second MnXmlayer. The predetermined thickness ratio can be the ratio of thickness of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXm layer.

[0028] The first APBqlayer can be a layer of AI2O3.

[0029] The first APBqlayer can be a layer of ZrCh.

[0030] The predetermined thickness ratio can be 5: 1 :5.

[0031] The predetermine ratio can include ratio of the thickness of the first MnXmlayer to the thickness of the first APBqlayer is at least 4:1. The predetermine ratio can include ratio of the thickness of the first MnXmlayer to the thickness of the second MnXmlayer is between 1:1.1 and 1.1:1.

[0032] The predetermined thickness ratio can be x:y:z. x can be between 0.1 and 10. y can beAttorney Docket No.: 072174-07704 between 0.1 and 10. z can be between 0.1 and 10.

[0033] The step of depositing the superlattice structure can include layering a first MnXmlayer, a first ApBqlayer, a second MnXmlayer, a second APBqlayer, and a third MnXmlayer. The first MnXm layer can be positioned at the top face of the superlattice structure. The third MnXmlayer can be positioned at the bottom face of the superlattice structure. The first APBqlayer can be positioned between the first MnXmlayer and the second MnXmlayer. The second APBqlayer can be positioned between the second MnXmlayer and the third MnXmlayer. The predetermined thickness ratio can be ratio of thickness of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXmlayer: thickness of the second APBqlayer: thickness of the third MnXmlayer.

[0034] The first APBqlayer can be a layer of AI2O3.

[0035] The first APBqlayer can be a layer of ZrCh.

[0036] The second APBqlayer can be a layer of AI2O3.

[0037] The second APBqlayer can be a layer of ZrCh.

[0038] The predetermined thickness ratio can be x:y:z:v:w. x can be between 0.1 and 10. y can be between 0.1 and 10. z can be between 0.1 and 10. v can be between 0.1 and 10. w can be between 0.1 and 10.

[0039] The step of depositing can include depositing (I) j+1 MnXmlayers and (II) j APBqlayers, j is an integer greater or equal to 3; The first MnXm layer can be positioned at the top face of the superlattice structure. The jthMnXmlayer can be positioned at the bottom face of the superlattice structure. The kthAPBqlayer can be positioned between the kthMnXmlayer and the k+lthMnXm layer, k can be the set of integers between 1 andj, inclusive. The predetermined thickness ratio can be ratio of thicknesses of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXmlayer: thickness of the second APBqlayer: ... thickness of the kthMnXm layer: thickness of the kthAPBqlayer (0ABk): thickness of the second MnXmlayerAttorney Docket No.: 072174-07704 (0MXk+l).

[0040] The formation of the superlattice structure can further include forming a capping or encapsulation layer at the top surface and / or bottom surface of the superlattice, the capping or encapsulation layer including one or more of HfCh, ZrCh, AI2O3, SiCh, SiON, or combinations thereof.

[0041] The dielectric interlayer can be disposed at both a topmost interface and a bottommost interface of the ferroelectric superlattice structure.

[0042] The dielectric interlayer can have a thickness in a range of about 0.3 nm to about 3 nm.

[0043] The dielectric interlayer can be configured to suppress charge injection and defect migration at interfaces of the ferroelectric superlattice.

[0044] The dielectric interlayer can improve endurance of a ferroelectric device formed by the process during repeated polarization switching.

[0045] The dielectric interlayer can enhance retention characteristics by reducing charge trapping and interfacial degradation.

[0046] The process can further include performing retention measurements at an elevated temperature and projecting long-term retention under operating conditions using a power-law degradation model and an Arrhenius-type temperature acceleration model.

[0047] The predetermined thickness ratio can be 0MXI: 0ABI: 0MX2: 0AB2 ... : 0MX ; 0ABk: 0MXk+i. Each of 0MXk+i through 0MXk+i can be independently between 0.1 and 10. Each of 0ABI through 0ABk can be between 0.1 and 10.

[0048] The process can further include adding bottom electrodes with a size of less than 5 pm. The bottom electrodes can be added to minimize leakage currents.

[0049] The step of adding the bottom electrodes can be performed after the step of depositing a superlattice structure. The step of adding the bottom electrodes can include patterning and depositing the bottom electrodes.Attorney Docket No.: 072174-07704

[0050] The rapid annealing process can be selected from the group consisting of flash Joule heating (FJH), rapid thermal annealing (RTA), spike annealing, laser annealing, or any other thermal process capable of inducing ferroelectric crystallization in the superlattice structure.

[0051] The rapid annealing process can be a flash Joule heating (FJH) process.

[0052] The FJH process can be performed using a direct current power supply (DCPS).

[0053] The process temperature of the rapid thermal annealing process can be between 400 °C and 1200 °C.

[0054] The process temperature of the rapid thermal annealing process can be between 700 and 900 °C.

[0055] The rapid annealing process can reduce effects on the structure (such as interdiffusion or chemical reactive changes) while achieving crystallization.

[0056] The rapid annealing process (which can include the flash Joule heating (FJH)m RTA, or laser annealing process) can minimize destructive effects on the structure while achieving crystallization.

[0057] Atomic layer deposition (ALD) can be used to layer the first metal oxide, the second metal oxide, and the third metal oxide.

[0058] The process can further be adding top electrodes patterned with no overlap with source and drain electrodes to avoid unexpected leakage currents.

[0059] The superlattice thickness can be adjustable while maintaining the predetermined ratio to accommodate a specific device application.

[0060] The specific device application can be an application for a device selected from the group consisting of random access memory (RAM), ferroelectric random access memory (FeRAM or FRAM), ferroelectric field-effect transistor (FeFET or FFET), ferroelectric tunnel junction (FeTJ or FTJ), and neuromorphic computing devices.

[0061] The superlattice thickness can be adjustable while maintaining the predetermined ratioAttorney Docket No.: 072174-07704 to accommodate a specific device functionality.

[0062] The specific device functionality can be a functionality for a device selected from the group consisting of random access memory (RAM), ferroelectric random access memory (FeRAM or FRAM), ferroelectric field-effect transistor (FeFET or FFET), ferroelectric tunnel junction (FeTJ or FTJ), and neuromorphic computing devices.

[0063] The superlattice structure can enable integration into a system / application selected from the group consisting of neuromorphic computing systems, non-volatile memory applications, and memory systems configured to replace or complement NAND flash and / or DRAM.

[0064] The superlattice structure can demonstrate a characteristic selected from the group consisting of (a) low latency, enabling high-speed operation in logic and memory devices; (b) high capacity for data storage applications; (c) superior energy efficiency, making it suitable for low-power electronic systems; (d) non-volatility, allowing long-term data retention; (e) scalability and flexibility, supporting integration into various architectures; and (f) combinations thereof.

[0065] The various architectures can include flexible or wearable electronics.

[0066] The superlattice structure can demonstrates a combination of the characteristics of (a) low latency, enabling high-speed operation in logic and memory devices; (b) high capacity for data storage applications; (c) superior energy efficiency, making it suitable for low-power electronic systems; (d) non-volatility, allowing long-term data retention; and (e) scalability and flexibility, supporting integration into various architectures.

[0067] The superlattice structure can exhibit a feature selected from the group consisting of (a) high endurance and retention characteristics for ferroelectric random-access memory (FeRAM); (b) dynamic switching speeds suitable for high-frequency operations; (c) superior fatigue resistance under cyclic electric fields; and (d) combinations thereof.

[0068] The superlattice structure demonstrates a combination of the features of (a) highAttorney Docket No.: 072174-07704 endurance and retention characteristics for ferroelectric random-access memory (FeRAM); (b) dynamic switching speeds suitable for high-frequency operations; and (c) superior fatigue resistance under cyclic electric fields.

[0069] The superlattice structure can be operable to support neuromorphic computing by enabling synaptic behavior through polarization switching.

[0070] The ferroelectric device can be configured in a compute-in-memory (CIM) architecture to support data storage and processing in the same physical structure.

[0071] The superlattice structure can be operable to support multi-state memory configurations for advanced data encoding and storage density.

[0072] The superlattice structure can be operable to enable efficient operation in a system / network / application selected from the group consisting of hardware-based neuromorphic computing systems, mimicking neural networks for artificial intelligence applications.

[0073] The superlattice structure can have one or more tunable coercive field properties that are operable, enabling adaptability for logic and memory architectures.

[0074] The superlattice structure can support synaptic weight modulation, enabling hardwarebased neuromorphic computing systems to perform real-time pattern recognition and learning in both two-terminal (ferroelectric tunnel junction) and three-terminal (ferroelectric field-effect transistor) configurations.

[0075] The superlattice structure can be integrated into a hardware-based artificial intelligence (Al) architecture, providing energy-efficient synaptic behavior for neuromorphic computing without reliance on software-based Al, and is adaptable for use in two-terminal FTJs and three-terminal Fe-FETs.

[0076] The superlattice structure can be configured to enable spike-timing-dependent plasticity (STDP), supporting real-time learning and adaptability in hardware-based neural networks,Attorney Docket No.: 072174-07704 with its functionality extending to both two-terminal FTJ and three-terminal Fe-FET architectures.

[0077] The superlattice structure can be integrated into a compute-in-memory (CIM) neuromorphic architecture. The integration of the superlattice structure into the CIM neuromorphic architecture can allow simultaneous data storage and processing, reducing latency and power consumption in Al applications, while maintaining scalability for CMOSbased architectures.

[0078] The process can have a scalability for wafer-scale fabrication, supporting industrial scaling with minimal process variation.

[0079] In general, in another embodiment, the invention features a ferroelectric device made by any of the above-described the processes.

[0080] In general, in another embodiment, the invention features a ferroelectric material including a superlattice structure including (I) two or more MnXmlayers and (II) one or more ApBqlayers. Each of the MnXmlayers is a layer of MnXm. M is a transition or main group metal. X is selected from the group consisting of N, O, S, and Se. The MnXmof each MnXmlayer is the same or different than the MnXmof the two or more MnXmlayers. In each of the of the MnXm layers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m. In each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. Each of the APBqlayers is a layer of APBq. A is a transition or main group metal. B is selected from the group consisting of N, O, S, and Se. The ApBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers. In each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q. In each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p. One of the MnXmlayers isAttorney Docket No.: 072174-07704 positioned at a top face of the superlattice structure. Another of the MnXmlayers is positioned at a bottom face of the superlattice structure. The two or more MnXmlayers and the one or more ApBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers. The two or more MnXmlayers and the one or more APBqlayers are in a predetermined thickness ratio. The superlattice structure stabilizes an orthorhombic ferroelectric phase of the ferroelectric material. The superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-ferroelectric-insulatorsemiconductor (MFIS), metal -insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS).

[0081] Implementations of the invention can include one or more of the following features:

[0082] MnXm can be HfO2.

[0083] APBqcan be AEO and / or ZrCh.

[0084] The ferroelectric material can further include a substrate-independent and compatible with Si, TiN, Mo, and Pt.

[0085] The ferroelectric material can be operable for use in a two-terminal (FTJ) device.

[0086] The FTJ device can be operable as a diode or selector, providing rectifying behavior or access control functionality in memory arrays, neuromorphic architectures, or other integrated systems

[0087] The ferroelectric material can be operable for use in a three-terminal (Fe-FET) device.

[0088] The Fe-FET device can be configured for integration into advanced transistor architectures

[0089] The advanced transistor architectures can be selected from the group consisting of FinFETs and gate-all-around (GAA) FETs.

[0090] The superlattice structure can include a first MnXmlayer, a first APBqlayer, and a secondAttorney Docket No.: 072174-07704 MnXm layer. The first MnXmlayer can be positioned at the top face of the superlattice structure. The second MnXmlayer can be positioned at the bottom face of the superlattice structure. The first ApBqlayer can be positioned between the first MnXmlayer and the second MnXmlayer. The predetermined thickness ratio can be ratio of thickness of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXmlayer.

[0091] The first APBqlayer can be a layer of AI2O3.

[0092] The first APBqlayer can be a layer of ZrCh.

[0093] The predetermined thickness ratio can be 5: 1 :5.

[0094] The predetermine ratio can include: (a) ratio of the thickness of the first MnXmlayer to the thickness of the first APBqlayer is at least 4:1; and (b) ratio of the thickness of the first MnXm layer to the thickness of the second MnXmlayer is between 1:1.1 and 1.1:1.

[0095] The predetermined thickness ratio can be x:y:z. x can be between 0.1 and 10. y can be between 0.1 and 10. z can be between 0.1 and 10.

[0096] The superlattice structure can include a first MnXmlayer, a first APBqlayer, a second MnXm layer, a second APBqlayer, and a third MnXmlayer. The first MnXmlayer can be positioned at the top face of the superlattice structure. The third MnXmlayer can be positioned at the bottom face of the superlattice structure. The first APBqlayer can be positioned between the first MnXm layer and the second MnXmlayer. The second APBqlayer can be positioned between the second MnXm layer and the third MnXm layer. The predetermined thickness ratio can be ratio of thickness of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXmlayer: thickness of the second APBqlayer: thickness of the third MnXmlayer.

[0097] The first APBqlayer can be a layer of AI2O3.

[0098] The first APBqlayer can be a layer of ZrCh.

[0099] The second APBqlayer can be a layer of AI2O3.

[0100] The second APBqlayer can be a layer of ZrCh.Attorney Docket No.: 072174-07704

[0101] The predetermined thickness ratio can be x:y:z:v:w. x can be between 0.1 and 10. y can be between 0.1 and 10. z can be between 0.1 and 10. v can be between 0.1 and 10. w can be between 0.1 and 10.

[0102] The superlattice structure can include (I) j+1 MnXmlayers and (II) j APBqlayers, wherein j is an integer greater or equal to 3. The first MnXmlayer can be positioned at the top face of the superlattice structure. The jthMnXmlayer can be positioned at the bottom face of the superlattice structure. The kthAPBqlayer can be positioned between the kthMnXmlayer and the k+lthMnXm layer, k is the set of integers between 1 and j, inclusive. The predetermined thickness ratio can be ratio of thicknesses of the first MnXmlayer: thickness of the first APBqlayer: thickness of the second MnXmlayer: thickness of the second APBqlayer: ... thickness of the kthMnXm layer: thickness of the kthAPBqlayer (0ABk): thickness of the second MnXmlayer (0MXk+l).

[0103] The predetermined thickness ratio can be 0MXI: 0ABI: 0MX2: 0AB2 ... : 0MX ; 0ABk: 0MXk+i. Each of 0MXk+i through 0MXk+i can be independently between 0.1 and 10. Each of 0ABI through 0ABk can be between 0.1 and 10.

[0104] The superlattice structure can demonstrate stable multi-state ferroelectric polarization, enabling analog or digital synaptic operations for hardware-based Al systems and offering compatibility with CMOS processes as a gate dielectric replacement.

[0105] The superlattice structure can serve as a high-k gate dielectric material, offering an energy-efficient and scalable replacement for traditional SiO2-based and HfO2-based gate dielectrics in CMOS technology.

[0106] The superlattice based ferroelectric structure can be formed upon one or more underlayers. A layer of the one or more underlayers can be planarized

[0107] In general, in another embodiment, the invention features a method that includes selecting a ferroelectric device made by any of the above-described methods. The methodAttorney Docket No.: 072174-07704 further includes integrating the ferroelectric device in a system / application selected from the group consisting of neuromorphic computing systems and non-volatile memory applications.

[0108] Implementations of the invention can include one or more of the following features:

[0109] The above-described superlattice-based ferroelectric material or device, wherein the structure is operable for use selected from the group consisting of memory, logic, compute-inmemory, and neuromorphic application. The structure can be operable for use such as replacement or complementation of NAND flash memory or DRAM.

[0110] The configuration can be selected from the group consisting of symmetric or asymmetric, vertically or laterally integrated, and compatible with front-end-of-line (FEOL) or back-end-of-line (BEOL) semiconductor processes.[OHl] The ferroelectric tunnel junction (FTJ) can include the superlattice structure is operable as a diode and / or a selector in a memory array or crossbar architecture, enabling rectification and / or access control functionality.

[0112] The ferroelectric field-effect transistor (Fe-FET) can include the superlattice structure is configured for integration into advanced logic transistor architectures.

[0113] The advanced logic transistor architectures can be selected from the group consisting of FinFETs and gate-all-around (GAA) FETs.

[0114] The superlattice structure can be configured for integration into two-dimensional (2D) or three-dimensional (3D) architectures.

[0115] The two-dimensional (2D) or three-dimensional (3D) architectures can be selected from the group consisting of monolithic 3D stacks, vertical channel structures, and back-end-of-line (BEOL) memory or logic layers.

[0116] The superlattice structure can be compatible with both front-end-of-line (FEOL) and back-end-of-line (BEOL) semiconductor processing steps, allowing integration into standard CMOS process flows.Attorney Docket No.: 072174-07704

[0117] The processing steps are performed under processing conditions that maintain the form of the superlattice structure.

[0118] The structure can maintain its ferroelectric switching behavior regardless of electrode geometry, device symmetry or asymmetry, stacking sequence, or annealing method.

[0119] The superlattice structure can be operable across multiple application domains, thereby enabling a unified platform for hardware-based artificial intelligence and next-generation electronic architectures.

[0120] The multiple application domains can be selected from the group consisting of including memory, logic, selector, diode, synaptic element, compute-in-memory systems, and hardware-based neuromorphic systems.

[0121] The structure can be further compatible with silicon-on-insulator (SOI) substrates and trench-based memory architectures formed in front-end-of-line (FEOL) or back-end-of-line (BEOL) processes. The ferroelectric device can be operable with spike-based input and output signaling in neuromorphic computing systems. The device can be programmable using voltage pulse sequences for data storage, learning, and computation across hybrid or neuromorphic architectures.

[0122] The structure can be further compatible with a substrate selected from the group consisting of strained silicon, silicon-germanium (SiGe), and germanium (Ge) based substrates.

[0123] The structure can be further compatible with a substrate or channel selected from the group consisting of III-V compound semiconductors (such as in a non-limiting sense InGaAs or GaN), oxide-based semiconducting materials (such as in a non-limiting sense IGZO, IZO, ITZO, ZTO, HIZO, ZnO, ImCh, SnCh, IAZO, and ZnON), and 2D materials (such as in a nonlimiting sense M0S2 and graphene).

[0124] The ferroelectric device can be integrated with circuit components to form hybrid electronic systems for memory, logic, neuromorphic computing, compute-in-memory, orAttorney Docket No.: 072174-07704 signal processing applications.

[0125] The circuit component can be selected from the group consisting of input / output (I / O) circuitry, comparators, spike generators, multivibrators, and analog or digital control circuits.

[0126] The device can be operable for integration into multi-chip module systems using dielevel or package-level assembly, enabling hybrid integration with conventional CMOS cores or memory controllers.

[0127] The gate electrode material can be a CMOS-compatible metal selected from the group consisting of TiN, TaN, WN, MoN, or metal stacks, enabling threshold voltage tuning through work function engineering, and is deposited using PVD, ALD, or CVD techniques in a gate-first or replacement metal gate (RMG) flow.

[0128] In some embodiments, the gate electrode material is defined as a CMOS-compatible metal material that provides a stable work function and thermal compatibility with conventional CMOS processing. Such metal materials may be selected to enable threshold voltage adjustment through work function engineering, rather than channel doping, thereby improving device variability and scalability.

[0129] In some embodiments, metal nitrides such as TiN, TaN, WN, and MoN, and metals such as Mo, W, and poly-Si exhibit different intrinsic work functions depending on composition, thickness, and deposition conditions. By selecting an appropriate metal or metal stack, the effective work function of the gate electrode may be tuned to achieve the desired threshold voltage for n-type or p-type transistors.

[0130] In some implementations, the gate electrode material may be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and may be integrated in either a gate-first process flow or a replacement metal gate (RMG) process flow. The ability to use the same class of materials across different gate integration schemes provides flexibility in process integration and device design.Attorney Docket No.: 072174-07704

[0131] The device can be integrated into a three-dimensional (3D) monolithic or stacked architecture, including vertical channels, tiered memory / logic stacks, or back-end-of-line (BEOL) embedded layers, enabling vertical scaling and heterogeneous integration within advanced CMOS systems.

[0132] The structure can be operable or integration into hybrid chiplet-based systems, multidie packaging platforms, or interposer-based assemblies, enabling heterogeneous integration with conventional CMOS cores, memory controllers, or neuromorphic accelerators using wafer-level or package-level interconnects.

[0133] In general, in another embodiment, the invention features a process of fabricating a ferroelectric field-effect transistor (Fe-FET) using a CMOS-compatible method, as described herein with reference to defined substrate structures, gate dielectric configurations, and thermal processing techniques. The process further includes providing a substrate selected from a silicon-on-insulator (SOI) wafer or a bulk silicon substrate. The SOI wafer includes a top silicon layer having a thickness from 1 nm to 3 pm, a buried oxide (BOX) layer having a thickness ranging from 10 nm to several micrometers, and an underlaying handle silicon substrate of arbitrary thickness. The process further includes forming isolation regions in the substrate to define active areas, using shallow trench isolation (STI) or local oxidation of silicon (LOCOS). The process further includes forming a channel region in the top silicon layer by performing ion implantation to introduce a lightly doped region. The process further includes forming heavily doped source and drain regions by performing high-dose ion implantation. The process further includes depositing a gate dielectric over the channel region. The gate dielectric comprising a ferroelectric superlattice structure composed of alternating layers of HfCh / ZrCh or ElfLh / AhCh / HfCh. The process further includes forming a gate electrode over the ferroelectric gate dielectric. The material being selected from the group consisting of metals, metal nitrides, and polysilicon. The process further includes annealing the structure toAttorney Docket No.: 072174-07704 crystallize the superlattice using a thermal process selected from rapid thermal annealing (RTA) or flash Joule heating (FJH). The process further includes forming sidewall spacers on the gate electrode using conformal deposition and anisotropic etch-back processes. The process further includes forming contact holes to the source, drain, and gate regions, and depositing metal contacts by either etch-back or lift-off processing techniques. The process further includes completing interconnect metallization and passivation layers using standard front-end-of-line (FEOL) and back-end-of-line (BEOL) CMOS process.

[0134] Implementations of the invention can include one or more of the following features:

[0135] The channel region can include p-type boron (B) doping at a concentration between lxl014and IxlO17atoms / cm3.

[0136] The lightly doped channel region can include n-type doping selected from phosphorus (P) or arsenic (As) at a concentration between 1 x 1014and 1 x 1018atoms / cm3.

[0137] The source and drain regions can include n-type dopants or p-type dopants with concentrations ranging from Ix O19to Ix O21atoms / cm3after activation annealing.

[0138] The n-type dopants can be As or P.

[0139] The p-type dopants can be B.

[0140] The process can further include performing well formation and threshold voltage tuning using ion implantation. The process can further include depositing the ferroelectric superlattice structure post-activation to avoid degradation from thermal budget. The process can further include completing integration using standard FEOL-compatible gate-last or gate-first CMOS process flows.

[0141] The process can further include forming a dummy poly gate and replacing the dummy poly gate with a metal gate in a replacement metal gate (RMG) process after source / drain activation.

[0142] In the RMG process, the dummy polysilicon gate is initially formed to define the gateAttorney Docket No.: 072174-07704 structure and to enable high-temperature source / drain activation processes without degrading the gate dielectric.

[0143] The dummy gate is subsequently removed and replaced with a metal gate material to achieve a desired work function and improved electrical performance.

[0144] The superlattice-based ferroelectric structure can be integrated into a CMOS fabrication flow. Post-formation thermal processing can be controlled to substantially maintain the superlattice structure.

[0145] The post-formation thermal processing can be selected from the group consisting of (a) using a rapid annealing process to induce ferroelectricity, (b) annealing the structure to crystallize the superlattice using a thermal process selected from rapid thermal annealing (RTA) or flash Joule heating (FJH), (c) other annealing processes that occur after formation of the superlattice-based ferroelectric structure, and (d) combinations thereof.

[0146] The post-formation thermal process can be controlled to substantially maintain the superlattice structure in a resulting product.

[0147] The control of the post-formation thermal processing can be selected from the group consisting of (a) limiting one or more of a peak processing temperature, (b) limiting duration of thermal exposure, (c) limiting a thermal ramp profile, and (d) combinations thereof.

[0148] The control of the post-formation thermal process can include utilizing a short-duration thermal process.

[0149] The short-duration thermal process can be selected from the group consisting of flash Joule heating (FJH), rapid thermal annealing (RTA), laser annealing, and combinations thereof.

[0150] The control of the post-formation thermal process can include that the post-formation thermal process is limited to exposure to temperatures having an upper temperature limit in a range of between approximately 400 °C and 900 °C.

[0151] The control of the post-formation thermal process can include that the post-formationAttorney Docket No.: 072174-07704 thermal processing is performed at temperatures less than approximately 900 °C for exposure durations of less than about 60 seconds.

[0152] The control of the post-formation thermal process can include that the duration of the thermal exposure is for at most 90 seconds.

[0153] The control of the post-formation thermal process can include that the duration of the thermal exposure is for at most 60 seconds.

[0154] The control of the post-formation thermal process can include that the duration of the thermal exposure is for at most 45 seconds.

[0155] The control of the post-formation thermal process can include that the duration of the thermal exposure is for at most 30 seconds.

[0156] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 900°C.

[0157] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 800°C.

[0158] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 700°C.

[0159] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 600°C.

[0160] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 500°C.

[0161] The control of the post-formation thermal process can include that the thermal process is limited to exposures to a maximum temperature that is at most 400°C.

[0162] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the post-formation thermal process is limited to exposures to a maximum temperature that is at most 900°C.Attorney Docket No.: 072174-07704

[0163] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 800°C.

[0164] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 700°C.

[0165] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 600°C.

[0166] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 500°C.

[0167] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 60 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 400°C.

[0168] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 30 seconds, the post-formation thermal process is limited to exposures to a maximum temperature that is at most 900°C.

[0169] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 30 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 800°C.

[0170] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 30 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 700°C.

[0171] The control of the post-formation thermal process can include that, for durations of theAttorney Docket No.: 072174-07704 thermal exposure is at least 30 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 600°C.

[0172] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 30 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 500°C.

[0173] The control of the post-formation thermal process can include that, for durations of the thermal exposure is at least 30 seconds, the thermal process is limited to exposures to a maximum temperature that is at most 400°C.

[0174] The control of the post-formation thermal process substantially reduces diffusion of atomic species into and / or out of the superlattice structure.

[0175] The control of the post-formation thermal process substantially eliminates diffusion of atomic species into and / or out of the superlattice structure.

[0176] The superlattice-based ferroelectric structure can be integrated into a CMOS fabrication flow.

[0177] The superlattice structure can be substantially maintained based upon controlling a characteristic selected from the group consisting of material composition, layer thickness, interfacial structure, periodicity of the superlattice structure, and combinations thereof. Such control of the characteristic can be operable for expanding allowable processing conditions to maintain the superlattice structure after formation.

[0178] The CMOS fabrication flow can include one or more of shallow trench isolation (STI), well implantation, threshold voltage adjustment, gate stack patterning, sidewall spacer formation, source / drain doping and activation, contact formation, and dual-damascene metallization, using FEOL and BEOL-compatible thermal budgets and materials.

[0179] The superlattice-based ferroelectric structure can include alternating layers of HfO? and ZrO2. For exposure durations greater than about 60 seconds, a maximum post-formationAttorney Docket No.: 072174-07704 processing temperature can be limited to less than approximately 600 °C.

[0180] The superlattice-based ferroelectric structure can include alternating layers of HfCh and AI2O3. Post-formation thermal processing is performed at temperatures up to approximately 900 °C.

[0181] The method can further include a planarization process performed on one or more layers upon which the superlattice-based ferroelectric structure is formed. The planarization process can include one or more of chemical mechanical polishing, spin-on flowable dielectric deposition with etch-back, glass reflow, electrochemical mechanical polishing, localized laser-induced reflow, and sacrificial layer etching.

[0182] In general, in another embodiment, the invention features an above-described ferroelectric device in which the ferroelectric device includes a three-dimensional (3D) stacked ferroelectric memory architecture including a plurality of vertically stacked memory tiers. Each memory tier includes a ferroelectric active layer including an above-described superlattice structure (such as a superlattice structure including (I) two or more MnXmlayers and (II) one or more APBqlayers. Each of the MnXmlayers is a layer of MnXm. M is a transition or main group metal. X is selected from the group consisting of N, O, S, and Se. The MnXmof each MnXm layer is the same or different than the MnXmof the two or more MnXmlayers. In each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m. In each of the of the MnXm layers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. Each of the APBqlayers is a layer of APBq. A is a transition or main group metal. B is selected from the group consisting of N, O, S, and Se. The APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers. In each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q. In each of the of the APBqlayers, q is selected from the group consisting of 1,Attorney Docket No.: 072174-07704 2, 3, 4, and depends on the oxidation state of A and the value of p. One of the MnXmlayers is positioned at a top face of the superlattice structure. Another of the MnXmlayers is positioned at a bottom face of the superlattice structure. The two or more MnXmlayers and the one or more ApBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers. The two or more MnXmlayers and the one or more APBqlayers are in a predetermined thickness ratio. The superlattice structure stabilizes an orthorhombic ferroelectric phase of the ferroelectric material. The superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-ferroelectric-insulatorsemiconductor (MFIS), metal -insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS)).

[0183] Implementations of the invention can include one or more of the following features:

[0184] The plurality of stacked memory tiers can form a vertical-channel architecture analogous to 3D NAND flash, in which a charge-trap layer of a conventional 3D NAND structure is replaced with the superlattice structure.

[0185] The vertical-channel structure can include deep channel etching and staircase routing similar to 3D NAND flash. Ferroelectric polarization switching can provide nonvolatile memory operation.

[0186] Each memory tier can be fabricated as an independent device layer including a metal-ferroelectric-metal (MFM) stack, a ferroelectric gate stack, or an above-described superlattice structure. The plurality of tiers can be monolithically interconnected without requiring deep vertical channel etching or staircase routing.

[0187] The monolithically stacked tiers can include FTJ-based layers. Each layer can include a ferroelectric superlattice disposed between top and bottom electrodes.

[0188] The monolithically stacked tiers can include FeFET-based layers including aAttorney Docket No.: 072174-07704 ferroelectric gate stack formed around a shared or non-shared semiconductor channel.

[0189] Each memory tier can include independently addressable ferroelectric field-effect transistors (FeFETs) with dedicated gate, source, and drain routing for per-cell access.

[0190] The plurality of stacked FeFET tiers can form a high-bandwidth memory (HBM)-class architecture operable without capacitors, refresh cycles, through-silicon vias (TSVs), or die-to-die bonding.

[0191] The 3D stacked architecture can be integrated above CMOS logic circuitry using a BEOL-compatible thermal budget to form a monolithic memory-on-logic structure.

[0192] The ferroelectric device can be configured as a stand-alone 3D memory block operable as a replacement or complement for NAND flash, DRAM, and / or HBM memory systems.

[0193] The stacked memory tiers can include a combination of two-terminal FTJ devices and three-terminal FeFET devices within a single integrated structure.

[0194] Each ferroelectric layer can exhibit polarization switching that provides nonvolatile retention and low-voltage operation across the stacked tiers.

[0195] In general, in another embodiment, the invention features a method of forming an above-described ferroelectric device. The method includes repeating the process of method of any of the above-described fabrication processes and methods to form a plurality of vertically stacked ferroelectric memory tiers.

[0196] In general, in another embodiment, the invention features a method of forming a ferroelectric device. The method includes forming a superlattice ferroelectric layer on a substrate. The superlattice ferroelectric layer includes a plurality of alternating first oxide layers and second oxide layers. Each of the first oxide layers and the second oxide layers have a thickness of less than about 5 nm. The method further includes annealing the superlattice ferroelectric layer under conditions that induce a ferroelectric crystalline phase. The method further includes forming a first electrode and a second electrode on opposing sides of theAttorney Docket No.: 072174-07704 superlattice ferroelectric layer. The first electrode, the second electrode, and the superlattice ferroelectric layer are configured in a ferroelectric capacitor structure. The ferroelectric device has an endurance of at least 106polarization switching cycles. (Endurance is determined by repeated application of an electric field sufficient to switch polarization of the superlattice ferroelectric layer).

[0197] Implementations of the invention can include one or more of the following features:

[0198] The ferroelectric device has an endurance of at least 107polarization switching cycles.

[0199] The ferroelectric device has an endurance of at least 108polarization switching cycles.

[0200] The ferroelectric device has an endurance of at least 109polarization switching cycles.

[0201] The ferroelectric device has an endurance of at least 1011polarization switching cycles.

[0202] The ferroelectric device has an endurance of at least 1012polarization switching cycles.

[0203] In general, in another embodiment, the invention features a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a plurality of memory tiers monolithically stacked along a vertical direction. Each memory tier includes a plurality of ferroelectric memory cells. The 3D ferroelectric memory device further includes a plurality of word lines extending in a first direction and coupled to the ferroelectric memory cells. The 3D ferroelectric memory device further includes a plurality of bit lines extending in a second direction different from the first direction and coupled to the ferroelectric memory cells. The 3D ferroelectric memory device further includes a page-selectable memory organization in which groups of the ferroelectric memory cells are logically grouped into pages independently of physical stacking of the memory tiers. Each ferroelectric memory cell includes a ferroelectric tunnel junction (FTJ) or a ferroelectric field-effect transistor (FeFET). The ferroelectric memory cell includes a ferroelectric stack selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-ferroelectric-insulator-semiconductor (MFIS), metal-insulator-ferroelectric-semiconductorAttorney Docket No.: 072174-07704 (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS). The 3D ferroelectric memory device is operable for providing random access at a page or word granularity without requiring capacitor-based storage elements or periodic refresh operations.

[0204] Implementations of the invention can include one or more of the following features:

[0205] Each intersection of one of the word lines and one of the bit lines can define a corresponding ferroelectric memory cell.

[0206] Each memory tier can include independently routed word lines and bit lines.

[0207] The page-selectable memory organization can include page select lines extending in a direction different from the word lines and the bit lines, such that activation of a selected page enables access to memory cells within the selected page while preventing access to memory cells in non-selected pages.

[0208] Read or write operations can be performed in parallel across multiple memory cells within the selected page.

[0209] The ferroelectric memory cells can be not connected in a NAND string configuration.

[0210] The word lines can be arranged along the vertical direction across multiple memory tiers.

[0211] The memory device can provide high-bandwidth memory access through parallel activation of multiple pages without using through-silicon vias (TSVs).

[0212] Stored data can be retained in the ferroelectric memory cells without requiring refresh cycles.

[0213] The plurality of memory tiers can be formed using a monolithic three-dimensional (M3D) fabrication process.BRIEF DESCRIPTION OF THE DRAWINGS

[0214] FIGS. 1A-1D show a schematic of a ferroelectric tunnel junction (FTJ) device fabrication procedure with a cross-sectional view of the devices in FIG. ID.Attorney Docket No.: 072174-07704

[0215] FIG. 2 shows a schematic of a ferroelectric field-effect transistor (Fe-FET) device fabrication procedure and front view of the devices.

[0216] FIG. 3 shows an AFM scan image for the bottom electrode and the line profile on the dotted line in AFM scan image.

[0217] FIGS. 4A-4B show, respectively, temperature profile depends on the direct current power supply (DCPS) power and the representative temperature profile for a setting of 300 W.

[0218] FIGS. 5A-5B show, respectively, temperature profiles while heating up and cooling down for the setting of 300 W.

[0219] FIG. 6A-6B show, respectively, the photograph of wafer-scale FTJ devices and the current (I)-voltage (V) characteristics with and ON-OFF ratio of ~104.

[0220] FIGS. 7A-7B shows, respectively, the retention and endurance characteristics of the FTJ device.

[0221] FIGS. 8A-8B show, respectively, I-V and P-E curves derived from the IV curve.

[0222] FIGS. 9A-9B show, respectively, (FIG. 9A) P-E curves for HfO2 / ZrO2 superlattice structure with AI2O3 protecting layer on topmost and bottommost layer, and (FIG.9B) normalized remanent polarization (Pr / Po) values under different cycles.

[0223] FIGS. 10A-10B show, respectively, XRD and Raman spectra of superlattice structure.

[0224] FIGS. 11A-11B show, respectively, AFM scan image and line profile on the line in AFM scan image showing the residue-free interface.

[0225] FIGS. 12A-12B show optical images after Si etching with RIE and addressing the source and drain with maskless photolithography and e-beam evaporation.

[0226] FIGS. 13A-13B show optical microscope images for Fe-FET single cell with different magnification.

[0227] FIGS. 14A-14C show endurance characteristics as a function of the interlayer thickness (AI2O3) at topmost and bottommost layers.Attorney Docket No.: 072174-07704

[0228] FIGS. 15A-15C show retention characteristics as a function of the interlayer thickness (AI2O3) at topmost and bottommost layers.

[0229] FIGS. 16A-16B show retention characteristics of superlattice-based ferroelectric fieldeffect transistor (FeFET) with 1 nm of AI2O3 interlayer under high temperature (85 and 125 °C, respectively).

[0230] FIGS. 17A-17B illustrate cross sectional views of exemplary ferroelectric field-effect transistors (Fe-FET) and ferroelectric tunnel junction (FTJ) devices which may be used in discrete embodiments, in array implementations and in various combinations of multiple elements.

[0231] FIG. 18A illustrates a schematic cross-sectional view of a monolithic three-dimensional (M3D) stacked two-terminal ferroelectric memory array.

[0232] FIG. 18B illustrates an exemplary close up cross section of the bit lines surrounded by superlattice ferroelectric layers.

[0233] FIG. 19 illustrates a three-dimensional view of an example of monolithic three-dimensional (3D) stacked two-terminal ferroelectric tunnel junction (FTJ) memory architecture.

[0234] FIG. 20 illustrates an example of monolithic three-dimensional (3D) stacked three-terminal ferroelectric field-effect transistor (FeFET) architecture.

[0235] FIGS.21A-21B illustrate a side view and top view (top view of each tier), respectively, of an example of monolithic three-dimensional (3D) stacked three-terminal ferroelectric fieldeffect transistor (FeFET) architecture for tier-by-tier stacking architecture.

[0236] FIG. 22A illustrates a monolithic three-dimensional (3D) stacked three-terminal ferroelectric field-effect transistor (FeFET) architecture based on a source design for tier-by-tier stacking architecture.

[0237] FIGS. 22B-22C show, respectively side and top views, of a memory cell of the 3DAttorney Docket No.: 072174-07704 stacked three-terminal ferroelectric field-effect transistor (FeFET) architecture shown in FIG.22A.

[0238] FIG. 23 illustrates a monolithic three-dimensional (3D) stacked three-terminal ferroelectric field-effect transistor (FeFET) architecture based on diagonal gate line design for tier-by-tier stacking architecture.

[0239] FIG. 24 illustrates a monolithic three-dimensional (3D) stacked three-terminal ferroelectric field-effect transistor (FeFET) architecture based on common gate line and vertically connected source design for tier-by-tier stacking architecture.DETAILED DESCRIPTION

[0240] The present invention relates to ferroelectric devices enabled by superlattice structure and methods of making and using thereof, and, more particularly, ferroelectric devices enabled by superlattice structure for neuromorphic computing and Al chips and methods of making and using thereof.

[0241] The described superlattice-based ferroelectric devices and materials are fully compatible with CMOS process integration, allowing their adoption in both front-end-of-line (FEOL) and back-end-of-line (BEOL) semiconductor fabrication flows.

[0242] In some examples, one or more thermal processing steps performed after formation of a superlattice structure may be controlled such that the superlattice structure is substantially maintained in a resulting product. In some examples, such control of thermal processing may include limiting one or more of a peak processing temperature, a duration of thermal exposure, or a thermal ramp profile.

[0243] In some examples, thermal control may include the use of short-duration thermal processes, including, but not limited to, rapid thermal annealing, and limiting exposure to temperatures within a range of approximately 400 °C to 900 °C. In some non-limiting examples, thermal processing may be performed at temperatures less than approximately 900 °C forAttorney Docket No.: 072174-07704 exposure durations of less than about 60 seconds.

[0244] In some examples, an allowable thermal processing window may depend on a material composition of the superlattice structure. Different superlattice material systems may exhibit different thermal stability characteristics during post-formation thermal exposure.

[0245] In some examples, superlattice structures comprising alternating layers of HfCh and ZrCh may be processed such that, for exposure durations greater than about 60 seconds, a maximum processing temperature is limited to less than approximately 600 °C in order to substantially maintain ferroelectric properties.

[0246] In some alternative examples, superlattice structures comprising alternating layers of HfCh and AI2O3 may exhibit increased thermal stability, such that post-formation thermal processing at temperatures up to approximately 900 °C may be tolerated while maintaining a desired structural or functional state.

[0247] It has also been found that, for a variety of superlattice structure described herein, corresponding processing conditions (including post-formation thermal exposure) may be independently selected and applied for different superlattice structures. Accordingly, in some examples, formation of a superlattice structure alone may not be sufficient if subsequent processing steps are not intentionally constrained to preserve a desired structural or functional state of the superlattice structure.

[0248] In some alternative examples, variations in one or more of material composition, layer thickness, interfacial structure, or periodicity of the superlattice structure may be selected to expand allowable processing windows for one or more processing steps subsequent to formation of the superlattice structure.

[0249] In general, allowable post-formation thermal processing conditions may be selected based on one or more of material composition, layer thickness, interfacial structure, periodicity, or desired ferroelectric performance of the superlattice structure.Attorney Docket No.: 072174-07704

[0250] Accordingly, in some examples, for exposure durations greater than about 60 seconds, a maximum processing temperature may be selected to be less than approximately 900 °C, 800 °C, 700 °C, 600 °C, 500 °C, or 400 °C, depending on the selected superlattice material system and processing objectives.

[0251] In general, formation of a superlattice structure alone may not be sufficient if subsequent processing steps are not intentionally constrained to preserve a desired structural or functional state of the superlattice structure.

[0252] The present invention introduces novel superlattice structures, that have alternating layers of MnXmlayers and APBqlayers, with the top face and the bottom face both being MnXmlayers. For each MnXmlayer, for MnXm, (a) M is a transition or main group metal, (b) X is selected from the group consisting of N, O, S, and Se, (c) the MnXmof each MnXmlayer can be the same or different than the MnXmof the two or more MnXmlayers, (d) in each of the of the MnXm layers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m, and in each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n. For each ApBqlayer, for APBq(a) A is a transition or main group metal, (b) B is selected from the group consisting of N, O, S, and Se, (c) the APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers, (d) in each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q, and (e) in each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p,

[0253] For example, superlattice structures can be a HfCh / AFCh / HfCh superlattice structure. Such HfO2 / A12Os / HfO2 superlattice structure is representatively discussed and described herein.

[0254] The inclusion of aluminum oxide (AI2O3) layers stabilizes the orthorhombic ferroelectric phase of HfCh, offering enhanced ferroelectric performance, reduced leakageAttorney Docket No.: 072174-07704 currents, and improved thermal stability. [Lee 2022}. The structure’s independence from specific substrates, such as TiN or Pt, enables seamless integration with various materials, including silicon and molybdenum, enhancing its scalability and flexibility. These advantages allow the superlattice structure to support advanced architectures across a wide range of device configurations.

[0255] The superlattice structure of the present invention can formed by the use of flash Joule heating (FJH) for rapid thermal annealing. [Luong 2020}. FJH can achieve precise crystallization with heating and cooling rates of 900 °C / s and 200 °C / s, respectively. [Li 2021}. Such process minimizes energy consumption, shortens processing times, and reduces destructive effects on device structures compared to traditional annealing methods. These characteristics ensure high efficiency and uniform crystallization, even in industrial-scale fabrication.

[0256] The HfO2 / A12Os / HfO2 superlattice demonstrates significant advantages over traditional ferroelectric materials. Its low latency allows for rapid polarization switching, enabling faster device operation. [Muller 2012}. The structure provides high capacity, supporting increased data storage density for memory applications. [Park 2015}. It offers energy efficiency by reducing power consumption during both fabrication and operation. [Hoffman 2015}. The design’s inherent nonvolatility ensures reliable data retention without a constant power supply.[Schroeder 2014}. Its scalability and flexibility support integration with various substrates and architectures, including flexible electronics. [Polakow ki 2015}. Additionally, the superlattice supports compute-in-memory (CIM) architectures, allowing for simultaneous data storage and processing, reducing latency and data movement in advanced computing applications, making them particularly attractive for graphics processing units (GPUs) that are also used in artificial intelligence (Al) chip designs. [Jerry 2017}.

[0257] The versatility of the superlattice is further demonstrated by its applicability in bothAttorney Docket No.: 072174-07704 two-terminal ferroelectric tunnel junctions (FTJs) and three-terminal ferroelectric field-effect transistors (Fe-FETs). These configurations enable diverse applications, from non-volatile memory to hardware-based neuromorphic computing. The superlattice’s compatibility with neuromorphic computing systems allows for real-time learning and low-power operation, making it an excellent candidate for future Al technologies.

[0258] By addressing the limitations of existing ferroelectric materials and incorporating advanced processing techniques such as FJH, these superlattice structures, such as the HfO2 / A12Os / HfO2 superlattice structure, represent a transformative advancement in ferroelectric materials development. This provides a pathway for integrating ferroelectricity into next-generation electronic devices with enhanced performance, scalability, and efficiency.Parameters / Declarations For Superlattice Ferroelectric Materials

[0259] Parameters / declarations for superlattice ferroelectric materials can include:

[0260] (A) The HfO2 / A12Os / HfO2 superlattice structure is composed of HfCE and AI2O3 layers in a ratio of 5:1:5. This ratio ensures excellent stabilization of the orthorhombic ferroelectric phase. The thickness of each layer can be adjusted to meet specific device requirements while maintaining the ratio. While this is a preferential ratio that has been determined in certain designs, other ratios may prove optimal or more desirable for this and other device architectures.

[0261] (B) The superlattice structure is substrate-independent and can be seamlessly integrated with substrates, including Si, Mo, W, TiN, and Pt. This substrate flexibility enables integration into various device architectures, from traditional CMOS-based systems to next-generation electronics.

[0262] (C) The HfO2 / A12O3 / HfO2 superlattice is suitable for both two-terminal devices such as ferroelectric tunnel junctions (FTJs) and three-terminal devices such as ferroelectric fieldeffect transistors (Fe-FETs). This versatility enables its application in diverse architectures, including non-volatile memory, advanced logic devices, and neuromorphic computing systems.Attorney Docket No.: 072174-07704

[0263] (D) The superlattice structure is anticipated to support neuromorphic computing applications by enabling polarization switching behavior that mimics biological synapses. The ability to achieve stable multi-state ferroelectric polarization positions the material as a candidate for implementing synaptic weight modulation, spike-timing-dependent plasticity (STDP), and real-time learning in hardware-based Al systems.

[0264] (E) The superlattice is suitable for use in non-volatile memory and hardware-based neuromorphic systems, where long-term data retention, low-power operation, and dynamic switching are critical requirements. While specific neuromorphic applications require further experimental validation, the material's demonstrated ferroelectric properties and compatibility with two-terminal and three-terminal architectures suggest strong potential for such systems.

[0265] (F) Flash Joule heating (FJH) (such as utilizing the systems disclosed, taught, and described in Tour ’780 PCT Application, Tour ’030 PCT Application, Tour ’967 PCT Application, Tour ’535 Application, and Luong 2020) is used for rapid thermal annealing, enabling efficient crystallization with minimal energy consumption and without destructive effects on device structures. This FJH process provides precise control of the crystallization, which has significance for ensuring the stability and reliability required in neuromorphic computing devices. The annealing strategy, including flash Joule heating (FJH) and rapid thermal annealing (RTA), may be selectively optimized based on device architecture, such as FTJ or FeFET, to stabilize the desired orthorhombic ferroelectric phase while minimizing structural degradation.

[0266] (G) The combination of the superlattice structure and FJH processing offers the potential for ultra-low power operation and high-speed data processing in compute-in-memory (CIM) architectures. This capability can reduce the latency and energy overhead commonly associated with traditional von Neumann architectures, making it well-suited for nextgeneration Al and machine learning applications.Attorney Docket No.: 072174-07704 Fabrication Of Ferroelectric Tunnel Junction (FTJ) Devices

[0267] Processes for fabricating ferroelectric tunnel junction (FTJ) devices can be done with conventional lithography (photolithography and E-beam lithography) and deposition techniques (E-beam evaporator, sputter, and atomic-layer deposition (ALD)). FIGS. 1A-1D show a typical workflow of device fabrication procedure. The methods below provide a specific example, but they can be varied to further refine and optimize for one’ s specific device requirements.

[0268] FIG. 1A shows preparing the SiOz / Si substrates. SiOz / Si substrates are cleaned, such as with acetone, ethanol, and isopropyl alcohol (IP A) solutions, to remove contaminants or residues and then dried by N2 gas flow. The additional cleaning process with a piranha solution can be added to eliminate organic residues and enhance surface hydrophilicity.

[0269] FIG. IB shows patterning the bottom electrode. Photolithography or E-beam lithography can be used for making bottom electrode patterns with the size of < 5 pm to minimize the unwanted leakage current. In the patterning process shown in FIG. IB, the double-layer photoresist or E-beam resist was used to minimize the photoresist or E-beam resist residue after the lift-off process.

[0270] 10 nm of Ti was deposited as an adhesion layer using an E-beam evaporator or a sputter technique. The thickness can be adjusted.

[0271] 50 nm of various metals (Mo, W, TiN, and Pt) was deposited to form the bottom electrode using an E-beam evaporator or a sputter technique. The thickness can be adjusted.

[0272] The chips were immersed in lift-off solution (acetone or specific removal solutions).

[0273] All the above are 2-inch wafer-scale fabrication. The fabrication scale will vary when industrially scaled since they are wafer-sized independent.

[0274] FIG. 1C shows deposition of ElfCh / AhCh / HfCh superlattice with ALD. The superlattice structure was deposited by the ALD technique with the sequence ofAttorney Docket No.: 072174-07704 HfO2 / AhO3 / HfO2 in a ratio of 5:1:5. The thickness of each layer can be adjustable depending on the use of the devices with the exact thickness ratio. The ratio could vary depending on the precise operation needed to be optimized.

[0275] In further embodiments, the superlattice structure comprises a HfCh / ZrCh superlattice deposited by atomic layer deposition. In some examples, thin AI2O3 interfacial layers are additionally deposited at the topmost and bottommost interfaces of the superlattice structure to improve electrical stability, suppress degradation mechanisms, and enhance endurance and retention characteristics.

[0276] FIG. ID shows pattern and deposition of the top electrode (TE). Photolithography or E-beam lithography can be used for making top electrode patterns with a size of < 5 pm to minimize the unwanted leakage current. Various metals (Mo, W, TiN, and Pt) can be deposited to form the top electrode using an E-beam evaporator or a sputter technique. The thickness can be adjusted. Cross-sectional view 131 shows the cross-sectional view of the fabricated FTJ devices.

[0277] To generate the ferroelectricity in superlattice structures, the rapid thermal annealing process with a flash Joule heating system was introduced at a temperature of 900 °C for 30 s.Fabrication Of Ferroelectric Field-Effect Transistor (Fe-FET) Devices

[0278] Processes for fabricating ferroelectric field-effect transistor (Fe-FET) devices can be done with conventional lithography (photolithography and E-beam lithography) and deposition techniques (E-beam evaporator, sputter, and ALD). FIG. 2 shows typical workflow of the device fabrication procedure, but the process can be varied to provide desired or optimized devices for one’s needs.

[0279] In step 201, The SiC>2 / Si substrates are cleaned, such as with acetone, ethanol, and isopropyl alcohol (IP A), solutions to remove contaminants or residues and then dried by N2 gas flow. The additional cleaning process with a piranha solution can be added to eliminateAttorney Docket No.: 072174-07704 organic residues and enhance surface hydrophilicity.

[0280] In steps 202-203, the channel material was deposited and defined with photolithography or an E-beam lithography process. The unprotected areas were etched by reactive ion etching (RIE) to isolate the channel from surrounding regions. In step 204, the resist was cleaned with acetone or typical solutions. All the processes were performed on a 2-inch wafer-scale fabrication, but the process was independent of wafer size. The fabrication scale will vary when industrially scaled.

[0281] In step 205, the source and drain electrodes were patterned by photolithography or E-beam lithography and deposited with a thin adhesion layer ( / .<?., Ti or Cr), followed by contact metals (Mo, W, TiN, and Pt). Electrode materials such as TiN, Mo, W, and Pt are selected based on work function alignment, thermal stability, and process compatibility with ferroelectric superlattice integration. The resist was cleaned with acetone or typical solutions.

[0282] In step 206, the superlattice structure was deposited by an ALD technique with the sequence of HfCh / AhCh / HfCh in a ratio of 5:1:5. The thickness of each layer can be adjustable depending on the use of the devices with the exact thickness ratio. Specialized thickness optimizations can be performed for one’s specific device requirements.

[0283] In some embodiments, the deposited superlattice includes alternating HfCh and ZrCh layers with optional AI2O3 interfacial layers disposed at the topmost and bottommost interfaces of the superlattice. The thickness of the AI2O3 interfacial layers may be selectively adjusted, for example from sub-nanometer thickness to a few nanometers, to optimize endurance, retention, and overall device stability.

[0284] In steps 207-208, the top-gate electrodes were patterned by photolithography or E-beam lithography and deposited with contact metals (Mo, W, TiN, and Pt). In step 209, the resist was cleaned with acetone or typical solutions.

[0285] To generate the ferroelectricity in superlattice structures, the rapid thermal annealingAttorney Docket No.: 072174-07704 process with flash Joule heating system was introduced with the temperature of 900 °C for 30 s.Characterization And Result Of FTJ Devices

[0286] After patterning and depositing the bottom electrodes, the surfaces of the bottom electrodes were scanned with atomic force microscopy (AFM) to check the residue or unwanted structure. See FIG. 3 (showing AFM scan image 301 for the bottom electrode and the line profile 303 on the dotted line 302 in AFM scan image 301). The double-layer strategy was introduced to prevent the rabbit-ear effect after the lift-off process. Future industrial processes might incorporate chemical mechanical polishing (CMP) or other related fabrication techniques to further smooth these features.

[0287] After verifying the clean surface on the bottom electrodes, the superlattice structure of HfO2 / AhO3 / HfO2 was deposited by ALD. The device fabrication procedure can be finished after addressing the top electrode with Mo, W, TiN, or Pt metals. To generate the ferroelectricity in the FTJ devices, the rapid thermal annealing process with flash Joule heating was introduced. Using FJH with a DCPS as the power source, the temperature can be precisely controlled, and the target temperature of 900 °C can be achieved with the current setting of 22 A on the DCPS. The temperature, depending on the DCPS setting and target temperature profile, is shown in FIGS. 4A-4B. The rapid heating and cooling, and stable temperature profile, can be obtained by FJH with the DCPS where the destructive effects can be minimized.FIGS. 5A-5B

[0288] After rapid thermal annealing (RTA) by FJH, the basic electrical characteristics were measured with a semiconductor analyzer (B1500A, Keysight) and 4-point probe station under ambient conditions. The devices were fabricated with 2-inch wafer scale (FIG. 6A), and the electrical characteristics with ON-OFF ratios of ~104can be achieved (FIG.6B). The switching behavior originates from the polarization direction switching according to the voltage polarities, making the tunneling width and tunneling mechanism varied (direct tunneling (negative) vsAttorney Docket No.: 072174-07704 FN tunneling (positive)). In addition, based on the switching behavior originated from the ferroelectricity of superlattice structure, the retention (FIG.7A, with plots 701-702 for ON and OFF, respectively) and endurance (FIG.7B) characteristics for 100 s can be obtained with ON-OFF ratio ~103. It has been discovered that ferroelectric devices can be formed that have an endurance of 106polarization switch cycles, including certain embodiments that have a high endurance (at least 108polarization switch cycles), and further certain embodiments that have an endurance of at least 1012polarization switch cycles. Endurance is determined by repeated application of an electric field sufficient to switch polarization of the superlattice ferroelectric layer.

[0289] In addition, the analyzed polarization-electric field (PE) curve (FIG.8B), derived from I-V measurements (FIG. 8A) using the relationship 1 = A- dt / dP (where the A is the area of the device, t is the period, and P is the polarization), demonstrates clear evidence of ferroelectric properties. By integrating the current over time and normalizing with the sample's electrode area, the polarization as a function of electric field was obtained. The resulting PE curve exhibits a characteristic hysteresis loop, indicative of ferroelectric behavior, with a remanent polarization (Pr) and a coercive field (Ec), confirming the material's ability to retain and switch polarization states (FIG. 8B). The non-linear polarization response and the presence of saturation polarization at higher electric fields further validate the reversible domain switching dynamics, which are fundamental to ferroelectric materials. These findings strongly support the material's potential for applications in non-volatile memory, capacitors, and advanced electronic devices, offering reliable performance through its stable and symmetric polarization behavior.

[0290] In addition, alternative superlattice configurations based on HfCh and ZrCh are also fabricated and characterized in the same manner as described in FIGS. 1A-1D. For example, a HfCh / ZrCh superlattice structure, where the individual layer thickness is 0.5 nm, respectively,Attorney Docket No.: 072174-07704 may be deposited using ALD with precisely controlled layer thicknesses and stacking sequences. The ratio, periodicity, and total thickness of the HfCh and ZrCh layers can be systematically varied to tailor ferroelectric, dielectric, and electrical properties of the device. In this device, the total thickness is 10 nm. Such HfCh / ZrCh superlattice structures enable enhanced ferroelectric phase stabilization and improved device performance compared to single-layer films.

[0291] Moreover, to further enhance the stability of the superlattice structures, AI2O3 layers (~1.0 nm) are introduced at both the topmost and bottommost interfaces of the superlattice stack. Specifically, thin AI2O3 layers are deposited by ALD beneath the first ferroelectric layer and above the last ferroelectric layer, forming ALCh / fHfCh / ZrCh superlattice) / AI2O3 structures.

[0292] The incorporation of AI2O3 interfacial layers contributes to improve device stability through multiple mechanisms. First, the AI2O3 layers act as chemically and thermally stable buffer layers, suppressing interfacial reactions and interdiffusion between the ferroelectric superlattice and the metal electrodes during high-temperature annealing processes. Second, AI2O3 provides a diffusion barrier for oxygen vacancies and metal species, thereby reducing defect generation and migration within the ferroelectric layers. The suppression of oxygen vacancy accumulation mitigates leakage current, wake-up degradation, and imprint effects, which are critical factors affecting long-term electrical stability and endurance. Third, the insertion of AI2O3 layers modifies the interfacial electric field distribution and reduces charge injection from the electrodes. Lastly, the AI2O3 layers can induce mechanical and electrostatic boundary conditions that favor the stabilization of the ferroelectric orthorhombic phase in HfCh- and HfCh / ZrCh-based superlattices.

[0293] As a result, well-defined polarization-electric field (P-E) curves were successfully obtained from the fabricated devices, demonstrating clear and reproducible ferroelectricAttorney Docket No.: 072174-07704 behavior. The resulting P-E curves exhibit a stable and symmetric hysteresis loop with well-defined remanent polarization (Pr) and coercive field (Ec), confirming robust polarization switching and reliable polarization retention. Notably, the consistency of the hysteresis characteristics under 109cycles indicates excellent electrical stability of the ferroelectric superlattice structure. FIG. 9A (plots 901-903 for 1st, 100,000thand 1,000,000,000thcycles, respectively); FIG. 9B (plots 911-912 for P up and P down, respectively). Again, endurance of at least 1012polarization switch cycles have been achieved.Characterization And Results Of Fe-FET Devices

[0294] After depositing and defining the semiconductor layers, the XRD and Raman spectra was conducted to confirm the structural information. FIG. 10A (with plots 1001-1002 for 24: 1 and 16:1, respectively); FIG. 10B (with plots 1011-1012 for raw data and Si peak extracted, respectively). To obtain the XRD peak information in thin film structure, the GI-XRD method was used to prevent the peaks from the substrate. In XRD peaks, the typical monoclinic (DB card: 00-072-0471) and orthorhombic (DB card: 00-040-1173) structure can be observed, meaning polycrystalline structure of HfCh in superlattice structure. The orthorhombic structure can only generate the ferroelectricity in HfCh, therefore, our device can show the switching behavior originated from the polarization switching depending on the bias polarities. In addition, in Raman spectra, to extract the substrate effect, the Si peak was extracted by using the reference Si peaks (-520 cm'1), and it showed typical orthorhombic peaks.

[0295] In addition, the surface of the channel was scanned with an atomic force microscope (AFM) to check the residue or unwanted structures. See FIGS. 11A-11B (showing AFM scan image 1101 for the bottom electrode and the line profile in FIG. 11B on the line 1102 in AFM scan image 1101) The double-layer strategy was introduced to prevent the rabbit-ear effect after the lift-off process. Further CMP or related smoothing methods could be employed. After that, the source and drain electrodes were patterned and deposited onto the isolated channelAttorney Docket No.: 072174-07704 layer. The channel length is 10 gm, and the width is 10 gm. FIG. 12A-12B show optical images after Si etching with RIE and addressing the source and drain with maskless photolithography and e-beam evaporation.

[0296] The superlattice structure of HfCh / AhCh / HfCh was deposited by ALD. To avoid unexpected leakage current, the top-electrodes were patterned and deposited without overlapping regions. FIGS. 13A-13B. After the fabrication procedure, the RTA with FJH was introduced to generate the ferroelectricity in superlattice structure. The temperature and time for RTA with FJH are the same as those of FTJ devices.

[0297] In addition, the superlattice structure of HfCh / ZrCh with an AI2O3 interlayers at topmost and bottommost layer can be also fabricated in the same manner as described above. After the fabrication procedure, the RTA was introduced to generate the ferroelectricity in superlattice structure. Following the fabrication and annealing process, the endurance and retention characteristics of the devices were systematically evaluated as a function of the AI2O3 interlayer (IL) thickness. The device stability was found to be strongly dependent on the presence and thickness of the AI2O3 interlayers introduced at the topmost and bottommost interfaces of the HfCh / ZrCh superlattice. In particular, devices incorporating AI2O3 interlayers exhibited significantly enhanced endurance and retention characteristics compared to devices without interlayers. When the AI2O3 interlayers thickness was optimized to 1 nm and 2 nm, the devices demonstrated markedly improved stability. For endurance measurements, no observable degradation in the electrical characteristics was detected up to 109switching cycles, indicating highly reliable polarization switching behavior. FIGS. 14A-14C (for without interlayer thickness, with 1 nm interlayer thickness, and with 2 nm interlayer thickness, respectively).

[0298] Furthermore, retention measurements confirmed stable polarization states maintained for up to 104s without noticeable decay, demonstrating excellent long-term data retention capability. FIG. 15A (for without interlayer thickness, with plots 1501-1502 for on and off,Attorney Docket No.: 072174-07704 respectively); FIG. 15B (for with 1 nm interlayer thickness, with plots 1511-1512 for on and off, respectively); FIG. 15C (for with 2 nm interlayer thickness, , with plots 1521-1522 for on and off, respectively). These results indicate that the insertion of appropriately thick AI2O3 interlayers effectively enhances device stability by suppressing degradation mechanisms, thereby enabling reliable endurance and retention performance in superlattice-based ferroelectric devices.

[0299] In addition, to estimate the long-term retention characteristics, retention measurements were performed at elevated temperatures. FIG. 16A (retention @ 85 °C, with plots 1601-1602 for on and off, respectively); FIG. 16B (retention @ 125 °C, with plots 1611-1612 for on and off, respectively). Based on the experimentally measured high-temperature retention data, the long-term retention behavior was projected using a power-law model in conjunction with an Arrhenius-type temperature acceleration assumption. The retention degradation of the ON / OFF ratio was modeled using a power-law relationship of the form:R(t) = Ro ■where R(f) is the ON / OFF ratio at time / , Ao is the initial ON / OFF ratio, and n is the degradation exponent extracted from the experimental data.

[0300] The temperature dependence of the retention time was further described using an Arrhenius relationship:t(T) = to • exp (Ea / ksT),where to is a pre-exponential factor, Eais the activation energy, kn is the Boltzmann constant, and T is the absolute temperature.

[0301] Using these models, the long-term retention characteristics were extrapolated to operating conditions. When a critical ON / OFF ratio of 105was defined as the failure criterion, the projected retention time of the device was estimated to be on the order of approximately two years. This result indicates that the device exhibit promising long-term data retentionAttorney Docket No.: 072174-07704 capability, supported by their stable polarization behavior and suppressed degradation mechanisms

[0302] Referring now to FIG. 17A, item 1700, an exemplary cross-section of a transistor device which may be called a three-tap device, a three-terminal device or an example of a FeFET, herein is illustrated. It may be noted that the use of the term three tap device is for reference and various FeFET device implementations with more than three physical connections, such as devices with backgate contacts, multiple gate connections and the like may be formed with the fundamental structure illustrated.

[0303] The device may include a gate electrode 1710 in some examples. In a non-limiting sense, the gate electrode may include polysilicon gate electrodes which may be common in higher dimension technologies. In other examples, metal gate electrodes may be utilized. These metal gates may be composed of materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and molybdenum (Mo) as non-limiting examples. Various selections may be made based on physical characteristics such as the work function of the material and its compatibility with different types of devices and consistency with ferroelectric aspects. In some other examples, materials like ruthenium (Ru) and cobalt (Co) and alloys of all the examples may be utilized.

[0304] In some embodiments, a dummy gate structure is initially formed over the channel region of the transistor. The dummy gate may be composed of a sacrificial material such as polycrystalline silicon (poly-Si), optionally capped with a dielectric layer such as silicon nitride (SiN) or silicon oxynitride (SiON). This temporary gate structure is patterned and etched prior to source / drain formation and serves to define the gate length and position with high precision. Following the formation and activation of heavily doped source and drain regions, the dummy gate is removed in a selective etching process to create a gate trench. This process step is typically performed after high-temperature annealing for dopant activation to avoid thermalAttorney Docket No.: 072174-07704 degradation of the final metal gate materials.

[0305] A metal gate stack is then formed in the gate trench to replace the removed dummy gate (a process known as the replacement metal gate, or RMG process). The metal gate stack may include one or more work function tuning layers, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or molybdenum (Mo), chosen to set the desired threshold voltage for n-channel or p-channel devices. A conductive fill layer, such as tungsten (W) or aluminum (Al), may be deposited to complete the gate electrode, followed by chemicalmechanical polishing (CMP) to planarize the surface.

[0306] The RMG process offers several advantages over a conventional “gate-first” approach, including improved work function control, reduced gate leakage, and compatibility with high-k dielectric layers such as hafnium oxide (HfCh). By delaying the introduction of the final metal gate until after high-temperature steps, the process minimizes thermal damage to sensitive gate materials and enables finer threshold voltage tuning. In certain embodiments, the RMG process may be combined with high-k / metal gate integration schemes in advanced CMOS nodes (e.g., < 14 nm gate length) to enhance device performance and scalability. In some examples, for some superlattice structures which are deposited at the gate deposition step or in a nearby deposition step, the thermal processing after the deposition step may be tightly controlled to ensure that the superlattice structure is maintained.

[0307] The gate electrode 1710 may be an example of one of the contacts made to exemplary FeFET devices. Other contacts may be made to the source 1711 and drain 1712 regions of the exemplary FeFET devices. The source 1711 and drain 1712 regions may be defined in various substrate types 1713. The portion of the substrate type 1713 between the source 1711 and drain 1712 regions at the surface of the substrate may define a channel region 1714 of the various FeFET device types. In some examples, the substrate may include bulk silicon substrates, which may be cost-effective for some applications. Additionally, the substrate types 1713 mayAttorney Docket No.: 072174-07704 include silicon-on-insulator (SOI) substrates which may enhance high-performance applications due to their reduced parasitic capacitance and better isolation. In some other examples, the substrate types 1713 may include examples with strained silicon, silicongermanium (SiGe), and germanium (Ge) based substrates. Still further examples may include III-V compound semiconductors (such as in a non-limiting sense InGaAs or GaN), oxide-based semiconducting materials (such as in a non-limiting sense IGZO, IZO, ITZO, ZTO, HIZO, ZnO, I Ch, SnO2, IAZO, and ZnON), and 2D materials (such as in a non-limiting sense M0S2 and graphene) as potential substrates or channel materials upon exemplary substrates.

[0308] In one embodiment, the BOX layer is formed of silicon oxide (SiO2), providing high electrical resistivity and thermal stability. Alternative dielectric materials, such as silicon oxynitride (SiON) or other insulating oxide, may also be employed depending on integration requirements.

[0309] The thickness of the BOX layer may range from approximately 10 nanometers to several micrometers. For example, in certain embodiments, the thickness may be between 50 nm and 2 pm. A thinner BOX layer (e.g., -10-100 nm) can improve thermal conduction from the active device region to the handle substrate, which may be desirable for high-power devices. Conversely, a thicker BOX layer e.g., > 1 pm) can enhance electrical isolation, which may be advantageous for high-voltage circuits or noise-sensitive analog devices.

[0310] The underlying handle silicon substrate may be of arbitrary thickness, typically ranging from 100 pm to 800 pm for standard wafer formats, and serves as a mechanical support structure. In some embodiments, the handle substrate may be lightly doped with either p-type or n-type dopants to serve additional functions such as backside biasing (back-gate configuration) or thermal conduction enhancement.

[0311] As described herein, the dielectric layer of various types of FET devices may be replaced with a superlattice structure 1720 including one or more ferroelectric layers. In someAttorney Docket No.: 072174-07704 examples, the superlattice_may include a combination of two or more interspersed layer types as illustrated in an exemplary fashion as layer type one 1722 and layer type two 1723. In nonlimiting examples, layer type one 1722 may include zirconium oxide (ZrCh) and aluminum oxide (AI2O3). In some examples, the layer type one 1722 depositions may be formed by atomic layer deposition (ALD). Other examples may include pulsed laser deposition or sputtering in a non-limiting sense. In some examples, other materials may be utilized, including one or more of the following: BaTiOs (BTO), Pb(Zr,Ti)O3 (PZT), SrBi2Ta2O9 (SBT), amongst other ferroelectric type materials. In some examples, layer type two 1723 may include HfO2. Herein, examples for layer type two 1723 may be formed by atomic layer deposition. Other examples may include other layer formation techniques, including pulsed laser deposition or sputtering. Still further examples may include layers of HfO2 with incorporation of dopant materials, such as, in a non-limiting perspective, zirconium, amongst other examples. Still further examples may include the use of one or more layers, including zirconium oxide (ZrO2), aluminum oxide (AI2O3), BaTiOs (BTO), Pb(Zr,Ti)O3 (PZT), SrBi2Ta2O9 (SBT), amongst other ferroelectrictype materials.

[0312] In some examples, other layers may be added to the superlattice structure 1720. In a non-limiting example, barrier layers 1721 and / or 1724 may be added to limit potential diffusion of various atomic species into or out of the superlattice structure 1720. In non-limiting examples, the barrier layer may include one or more of TiN, TaN, AI2O3, SiNx, La2C>3, and metals like Ru, Mo, or W. In some other examples, layers may include 2D materials such as graphene and hexagonal boron nitride, and metal carbides such as titanium carbide TiC and tantalum carbide TaC, which may impart enhanced diffusion blocking and thermal stability.

[0313] As illustrated in FIG. 17A, the superlattice structure 1720 may be formed from a plurality of interlayered levels of the various types as has been described. There may be different numbers of layers that may be added consistent with the present disclosure, with asAttorney Docket No.: 072174-07704 little as two layers to dozens of layers in some examples. Accordingly, the physical size may be scaled by the number of layers included. Furthermore, each of the layer type one 1722 and layer type two 1723 examples may be processed to have controlled thickness which, in some examples, may be between 0.1 nm to 10 nm in thickness. Examples outside this exemplary range may also be utilized.

[0314] Referring again to FIG. 17A, various processing including flash Joule heating (FJH), rapid thermal annealing (RTA) and laser annealing, amongst other examples may thermally treat the formed superlattice structure 1720 and induce the evolution of an internal ferroelectric polarization field 1730 as illustrated in exemplary form as the positive and negative field indicators in the illustration as they are oriented in the superlattice structure 1720. In some examples, the various connections to the device, such as the gate electrode 1710, may have applied potential bias 1740. The source 1711 and drain 1712 contacts may also include aspects of potential bias in their connections. Accordingly, the field experienced at the channel region 1714 may be a composite of the effects of the internal ferroelectric polarization field 1730 and externally applied biasing fields.

[0315] Referring now to FIG. 17B, item 1750, another non-limiting example of a device type that may incorporate a superlattice structure is illustrated. In FIG. 17B, item 1750, an exemplary cross-section of a diode device, which may be called a two-terminal or two tap device, or an example of a ferroelectric tunnel junction (FTJ), herein is illustrated.

[0316] The device may include a top electrode 1760 and a bottom electrode 1761 in some examples. In a non-limiting sense, the top electrode may include metal electrode examples. These metal electrodes may be composed of materials like titanium nitride (TiN), platinum (Pt), tantalum nitride (TaN), tungsten (W), and molybdenum (Mo), as non-limiting examples. Various selections may be made based on physical characteristics such as the work function of the material and its compatibility with different types of devices and consistency withAttorney Docket No.: 072174-07704 ferroelectric aspects. In some examples, the metals may be chosen based on the ability of the electrode to be defined in standard manufacturing processing conditions. In some other examples, materials like ruthenium (Ru) and cobalt (Co), and alloys of all the examples, may be utilized. Such examples may be typically formed in layers characterized as back-end-of-line (BEOL) layers or in additional layers within said BEOL layers.

[0317] In some other examples, the top electrode may include polysilicon gate electrodes which may be common in front-end-of-line (FEOL) processing and resulting FEOL layers.

[0318] Referring again to FIG. 17B, the top electrode 1760 and bottom electrode 1761 may be positioned above the underlying layers 1762. In an example, where the FTJ device is formed in FEOL locations, the underlying layers 1762 may include one or more of a substrate, isolation structures, transistors, passivates, and the like that may be included in FEOL layers. In some embodiments of a FEOL location, the design layout may be performed such that the underlying layers 1762 may be limited to non-active structures, such as isolation structures and a substrate.

[0319] In other examples, the FTJ device may be formed in BEOL locations, such as at the contact level, between metal interconnect layers, or above metal interconnect layers, as nonlimiting examples. When the FTJ device is formed in BEOL locations, the underlying layers may include one or more of a substrate, isolation structure, transistors, passives, contacts, vias, metal lines, and insulating layers as non-limiting examples. In some examples of a BEOL location, the underlying layers may be limited to insulating layers (both FEOL and BEOL), to a substrate, and in some examples to underlying metal layers that may function with guarding or isolating functions, including passive and active isolating functions.

[0320] As described herein, a dielectric layer of exemplary FTJ devices may be defined as a superlattice structure 1770 including one or more ferroelectric layers. In some examples, the superlattice may include a combination of two or more interspersed layer types, as illustrated in an exemplary fashion, as layer type one 1771 and layer type two 1772. In non-limitingAttorney Docket No.: 072174-07704 examples, layer type one 1771 may include zirconium oxide (ZrCh) and aluminum oxide (AI2O3). In some examples, the layer type one 1771 depositions may be formed by atomic layer deposition. Other examples may include pulsed laser deposition or sputtering in a non-limiting sense. In some examples, other materials may be utilized, including one or more of the following: BaTiO3 (BTO), Pb(Zr,Ti)O3 (PZT), SrBi2Ta2O9 (SBT), amongst other ferroelectric-type materials. In some examples, layer type two 1772 may include HflCh. Herein, examples for layer type two 1772 may be formed by atomic layer deposition. Other examples may include other layer formation techniques, including pulsed laser deposition or sputtering. Still further examples may include layers of HfO2 with incorporation of dopant materials, such as in a non-limiting perspective, zirconium, amongst other examples. Still further examples may include the use of one or more layers, including zirconium oxide (ZrO2), aluminum oxide (AI2O3), BaTiOs (BTO), Pb(Zr,Ti)O3 (PZT), SrBi2Ta2O9 (SBT), amongst other ferroelectrictype materials.

[0321] In some examples, other layers may be added to the superlattice structure 1770. In a non-limiting example, barrier layers 1773 and / or 1774 may be added to limit potential diffusion of various atomic species into or out of the superlattice structure 1770. In non-limiting examples, the barrier layer may include one or more of TiN, TaN, AI2O3, SiNx, La2C>3, and metals like Ru, Mo, or W. In some other examples, layers may include 2D materials such as graphene and hexagonal boron nitride, and metal carbides such as titanium carbide TiC and tantalum carbide TaC, which may impart enhanced diffusion blocking and thermal stability.

[0322] As illustrated in FIG. 17B, the superlattice structure 1770 may be formed from a plurality of interlayered levels of the various types as has been described. There may be different numbers of layers that may be added consistent with the present disclosure, with as few as two layers to dozens of layers in some examples. Accordingly, the physical size may be scaled by the number of layers included. Furthermore, each of the layer type one 1771 andAttorney Docket No.: 072174-07704 layer type two 1772 examples may be processed to have controlled thickness, which, in some examples, may be between 0.1 nm and 10 nm in thickness. Examples outside this exemplary range may also be utilized.

[0323] Referring again to FIG. 17B, various processing including flash Joule heating (FJH), rapid thermal annealing (RTA) and laser annealing, amongst other examples may thermally treat the formed superlattice structure 1770 and induce the evolution of an internal ferroelectric polarization field 1780 as illustrated in exemplary form as the positive and negative field indicators in the illustration as they are oriented in the superlattice structure 1770. In some examples, the various connections to the device, such as the top electrode 1710, may have applied potential bias 1790. The bottom electrode 1761 contacts may also include aspects of potential bias 1791 in their connections. Accordingly, the field experienced in the FTJ 1750 may be a composite of the effects of the internal ferroelectric polarization field 1780 and externally applied biasing fields.

[0324] In certain embodiments, the superlattice structure may additionally include one or more encapsulation or capping layers positioned above the topmost superlattice ferroelectric layer and / or below the bottommost superlattice ferroelectric layer. Such capping layers may comprise AI2O3, SiCE, SiON, or other dielectric materials compatible with the overall stack. These encapsulation layers may improve interface quality, enhance thermal stability, suppress unwanted oxygen diffusion, or facilitate integration with adjacent process layers. The presence or absence of such top or bottom capping layers does not alter the underlying superlattice periodicity.

[0325] TABLE I illustrates a tabular presentation of various significant features of memory devices comparing Flash (NAND-based) devices with the devices disclosed herein.Attorney Docket No.: 072174-07704> > >< <<&

[0326] For example, with respect to non-volatility, all three memory technologies — Flash (NAND-based), FeFET (Ferroelectric Field-Effect Transistor), and FTJ (Ferroelectric Tunnel Junction) devices can be configured to be non-volatile, meaning they retain data without power, making them suitable for a wide range of persistent storage applications. Furthermore, from an endurance perspective, flash memory may typically support between 104to 106program / eraseAttorney Docket No.: 072174-07704 (PZE) cycles, which may limit its durability in applications with frequent rewrites. In contrast, FeFET devices as described herein may offer significantly higher endurance, ranging from 106to over 108PZE cycles. FTJ devices as described herein are potentially even more durable, supporting up to 109+ cycles. The characteristics / quality of the barrier material used may be important contributors to endurance performance

[0327] From a retention perspective, all three technologies may provide long data retention, generally exceeding 10 years.

[0328] From a device speed perspective, flash memory may be characterized as relatively slow, with write speeds in the microseconds to milliseconds range and read speeds around 10 microseconds. FeFET devices as disclosed herein improve substantially on this, with both write and read operations occurring in the nanoseconds to microseconds range. Furthermore, FTJ devices as disclosed here offer extremely fast read and write times in the picoseconds to nanoseconds range, which may make the device ideal for high-speed applications.

[0329] From a scalability perspective, flash memory may scale below 20 nm by employing 3D stacking techniques. FeFET devices as disclosed herein offer more aggressive scalability, with potential for gate lengths under 10 nm using advanced transistor structures. Furthermore, FTJ devices as disclosed here may be capable of further scaling due to the device's two-terminal structure and very thin ferroelectric layers, which support a few-nanometer thickness.

[0330] From a power consumption perspective, flash may be relatively power-hungry, requiring 15-20V internally generated voltage supplies, which are drawn upon during write operations. FeFET devices according to the present disclosure reduce power demand significantly by operating at lower voltages (1-3 V) and using energy-efficient write mechanisms. Furthermore, FTJ devices according to the present disclosures may be the most energy-efficient, using low voltages (under 1 V) and consuming minimal energy, making these devices well-suited for energy-constrained environments.Attorney Docket No.: 072174-07704

[0331] From a process compatibility perspective, flash memory may generally be considered a specialized process tailored to NAND fabrication. FeFET device production according to the present disclosure, however, is fully compatible with common CMOS front-end-of-line (FEOL) processing, making integration with logic circuits straightforward. Furthermore, FTJ devices produced as described here are compatible with back-end-of-line (BEOL) processes and may also be produced in FEOL processes and can be stacked on existing circuitry, enhancing its flexibility in 3D integration and chip layout.

[0332] From a multi-bit storage perspective, flash memory supports multi-bit storage configurations like SLC, MLC, TLC, and QLC, which enable higher densities at the cost of endurance and reliability. Both FeFET and FTJ devices, as described here, can also store singlebit and multi-bit data.

[0333] From a 3D stackability perspective, 3D stacking is a mature technology in NAND-based Flash, enabling massive capacity gains. FeFET devices, according to the present disclosure, are still under development with respect to 3D stackability. FTJ devices under the current disclosure are highly consistent with high-density 3D memory solutions.

[0334] From a radiation / temperature robustness perspective, flash memory is sensitive to radiation and temperature extremes, which may limit its use in space or military environments. FeFET devices according to the present disclosure may show greater robustness, especially when fabricated on silicon-on-insulator (SOI) substrates. In some examples, FTJ devices, according to the present disclosure, could be even more robust due to their simple metal-ferroelectric-metal (MFM) structure.

[0335] From a cell structure perspective, flash uses either floating gate or charge trap structures. FeFET devices according to the present disclosures use a MOSFET with a ferroelectric gate to store data, providing a compact and CMOS-compatible solution. FTJ devices according to the present disclosure have a simpler design, comprising just twoAttorney Docket No.: 072174-07704 terminals — a metal-ferroelectric-metal stack — which offers significant advantages in scalability and integration.

[0336] From a write mechanism perspective, the write mechanism in Flash devices involves charge injection and tunneling, which contributes to wear over time. FeFET devices according to the present disclosure use polarization switching to modulate the channel, enabling faster and lower-energy writes. FTJ devices, according to the present disclosure, by contrast, modulate the tunneling barrier using ferroelectric polarization, offering a completely different physical mechanism with potential benefits in endurance and speed.

[0337] Comparing the read / write path, flash and FTJ devices according to the present disclosure, both use a shared read / write path, which can limit performance and complicate the design. FeFET devices according to the present disclosure may use separate paths for reading and writing operations, which can improve performance and reduce interference during operation.

[0338] From a process complexity perspective, flash memory fabrication may be relatively complex, involving intricate 3D structuring and precise oxide control. FeFET device fabrication according to the present disclosure simplifies this by adding a ferroelectric layer to the standard MOS stack, making it relatively easy to integrate with existing CMOS processes. Furthermore, FTJ devices according to the present disclosure are the simplest, requiring only a planar capacitor and no channel.

[0339] The described superlattice-based ferroelectric devices and materials may be fully compatible with CMOS process integration, allowing their adoption in both front-end-of-line (FEOL) and back-end-of-line (BEOL) semiconductor fabrication flows.

[0340] In some examples, annealing after deposition of ferroelectric superlattice structure layers, including flash Joule heating (FJH), laser annealing, and rapid thermal annealing (RTA), may be selectively optimized based on device architecture, such as FTJ or FeFET, toAttorney Docket No.: 072174-07704 stabilize the desired orthorhombic ferroelectric phase while minimizing structural degradation.

[0341] In some examples, electrode materials such as TiN, Mo, W, and Pt may be selected based on work function alignment, thermal stability, and process compatibility with ferroelectric superlattice integration.3D stacked Ferroelectric Architectures

[0342] Referring now to FIG. 18A, an illustration of an exemplary three-dimensional (3D) stacked ferroelectric memory architectures enabled by the superlattice-based ferroelectric devices described herein is provided. Because the ferroelectric superlattice layers may be thermally processed after deposition to be crystallized at BEOL-compatible temperatures without losing the superlattice structure, multiple device tiers may be vertically integrated directly on top of logic devices or other underlying circuitry without exceeding thermal budgets. This allows true monolithic “memory-on-logic” integration, in which a high-density nonvolatile memory stack is constructed above logic transistors, processors, accelerators, or other circuitry.

[0343] In addition to being compatible with BEOL integration above logic, the disclosed ferroelectric device structures may also be implemented as a stand-alone monolithic 3D memory array, independent of the existence of any underlying logic layer. In such implementations, repeated vertical stacking of two-terminal ferroelectric tunnel junction (FTJ) devices or three-terminal ferroelectric field-effect transistor (FeFET) devices forms a high-density 3D memory block that may function similarly to, and in many cases exceed the performance of, conventional 3D NAND flash or stacked DRAM / HBM-type memory. Unlike 3D NAND, the disclosed architectures do not require extremely deep channel etches, staircase word-line routing, or complex oxide / nitride trapping structures. In some embodiments, unlike HBM or stacked DRAM dies, the ferroelectric 3D stacks may not depend on capacitors, TSVs, multi-die bonding, or thick-die stacking, thereby reducing thermal load and interconnectAttorney Docket No.: 072174-07704 overhead.

[0344] In some embodiments, FIG. 18A illustrates a schematic cross-sectional view of a monolithic three-dimensional (M3D) stacked two-terminal ferroelectric memory array. Multiple horizontal device tiers are sequentially formed above a substrate. The stacked layers may include conductive metal layers 1802 upon insulator layers 1801. The stacking process may replicate the structure for many layer repeats.

[0345] In various examples, each tier, such as at conductive metal layer 1802, may include a metal-ferroelectric-metal (MFM), metal-ferroelectric-interlayer-metal (MFIM), metal-interlayer-ferroelectric-metal (MIFM), or metal-interlayer-ferroelectric-interlayer-metal (MIFIM) structure in which the ferroelectric superlattice layer is sandwiched between metallic electrodes (e.g., W, TiN, or other conductive materials). Vertical conductive pillars extend through the entire stack to provide inter-layer connectivity or bit-line routing, while insulating spacers (e.g., SiCh, AI2O3, ZrCh, HfCh or equivalent dielectric materials) isolate adjacent pillars from horizontal electrode lines.

[0346] In FIG. 18B, an enlarged inset highlights an individual two-terminal FTJ cell. The cell includes a superlattice ferroelectric layer 1853 disposed between conductive layers. In particular, conductive layer 1851 serves as a metal electrode, while interlayers 1852 and 1854 are positioned adjacent to the superlattice ferroelectric layer 1853 to provide interface control and electrical isolation as needed.

[0347] In some embodiments, an additional conductive material 1855 is formed within a vertical column structure of the FTJ cell. In certain examples, the vertical column structure may be partially unfilled, while in other examples it may be filled with the conductive material 1855 to provide an electrical conduction path or structural support.

[0348] Referring again to FIG. 18A, reference numeral 1810 denotes a unit cell (unit device) of the memory array. The tops of the vertical bit lines may be filled with metal depositions,Attorney Docket No.: 072174-07704 where the metal deposition may fill just a portion of the top of the pillar. The resulting metal top contact 1850 may allow for facilitated interconnection to bit lines in further processing. Referring to the peripheries of the structure, a staircase type structure (such as at the example of etched layers 1830, 1831, and 1832) may be used to form word line interconnects 1825.Such a structure can bring the bit line interconnects and word line interconnects into a single layer for their interconnection to external devices. In an example such a layer may further connect underlying logic circuits through a layer above the top of the bit line interconnects 1850 and the word line interconnects 1825.

[0349] Two-Terminal FTJ-Based 3D Stacks: As described, a plurality of two-terminal ferroelectric tunnel junction (FTJ) devices may be arranged in a monolithic 3D stack. Each horizontal tier includes metal-ferroelectric-metal (MFM), metal-interlayer-ferroelectric-metal (MIFM), metal-ferroelectric-interlayer-metal (MFIM), or metal-interlayer-ferroelectric-interlayer-metal (MIFIM) stacks in which a ferroelectric superlattice layer is disposed between top and bottom metal electrodes.

[0350] Referring now to FIG. 19, a three dimension view of the two terminal FTJ based 3D stacks is provided. The tiers may be separated by inter-layer dielectrics and can be repeated at any suitable number of times. The unit cell 1901 includes vertical conductive pillars 1902 that extend through the stack and may serve as bit-lines, sense lines, or shared electrodes for multiple tiers, while horizontal electrodes (such as 1910, 1911, 1912 and the like) define individual FTJ cells within each tier. In some examples, the conductive electrodes in each tier may be separated by insulating layers 1915. As illustrated, the peripheral staircase type structure may allow for individualized word line interconnects 1920 to be formed as well.

[0351] In some embodiments, the FTJ tiers form cross-point or vertical-pillar arrays that may achieve storage-class density comparable to or greater than 3D NAND flash without the need for deep channel etching or complex staircase routing. Unlike capacitor-based DRAM or HBM,Attorney Docket No.: 072174-07704 the FTJ cells are nonvolatile and do not require refresh operations, enabling low-power, high-bandwidth memory structures suitable for both storage and working-memory applications.

[0352] Three-Terminal FeFET-Based 3D Stacks: Referring now to FIG. 20, a monolithic 3D stacked three-terminal ferroelectric transistor (FeFET) architecture is shown. A vertical semiconductor channel 2020 (e.g., a silicon pillar) extends through multiple stacked tiers above a silicon wafer base layer 2010. Surrounding the vertical channel is a ferroelectric gate stack 2030 that includes a superlattice ferroelectric layer and one or more interfacial layers. Alternating conductive 2050 and insulating layers 2040 (for example, conductive silicon and silicon dioxide) provide per-tier gate electrodes and isolation around the channel.

[0353] In the illustrated embodiment, conductive materials 2060 and 2080 are provided to form electrical connections and electrodes within the three-terminal FeFET structure. The conductive materials 2060 and 2080 may independently comprise one or more metals, metal nitrides, or doped semiconductor materials, such as tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), doped polysilicon, or combinations thereof.

[0354] Spacers 2070 are disposed between adjacent conductive materials 2060 and 2080 to electrically and physically separate the conductive materials from one another. In some embodiments, the spacers 2070 prevent shorting between the conductive materials 2060 and 2080 during fabrication and operation of the device.

[0355] In some examples, the spacers 2070 may comprise dielectric materials such as silicon nitride, silicon oxynitride, silicon dioxide, aluminum oxide, or other insulating materials compatible with CMOS processing.

[0356] Each tier of the stack therefore may function as a distinct FeFET cell sharing the common vertical channel, with independent gate access provided by the conductive layers. The resulting structure provides NAND-like word-line and bit-line addressing while offeringAttorney Docket No.: 072174-07704 nonvolatile retention and fast operation speed. Because the ferroelectric gate stacks are formed at relatively low temperature, additional FeFET tiers can be added monolithically in the BEOL, avoiding TSV-intensive multi-die HBM packaging.

[0357] In another class of embodiments, the ferroelectric devices may be stacked using a superlattice-based FeFET tier-by-tier stacking architecture in which each FeFET cell in every tier is individually addressable, without relying on a vertical NAND-style channel string as shown in FIGS. 21A-21B. In this configuration, each stacked FeFET layer (such as first tier 2101 and second tier 2102) includes its own dedicated gate 2104 / electrode 2103, source 2106 / drain 2107 access, and ferroelectric gate stack 2105, allowing direct per-cell addressing similar to DRAM architectures. Rather than forming a continuous vertical channel, each FeFET tier has a channel 2108 and operates as an electrically independent memory plane with separate word-line, bit-line, and source-line routing.

[0358] This general FeFET stacking structure enables fine-grained access granularity, high parallelism, and per-tier control, making it suitable for high-bandwidth memory (HBM) applications. Unlike conventional HBM, which relies on multiple DRAM dies bonded through TSVs, the disclosed FeFET stacking allows monolithic HBM-class memory in which multiple nonvolatile FeFET tiers are vertically integrated within the FEOL and BEOL without TSVs or die-to-die assembly. As a result, this architecture provides DRAM-like speed with nonvolatile data retention while achieving substantially lower thermal burden and routing overhead compared to TSV-based HBM. Furthermore, because FeFET cells do not require capacitors or refresh cycles, the stacked array offers significantly reduced power consumption and improved scalability relative to DRAM-based HBM.Manufacturing Considerations

[0359] The 3D stacked architectures of FIGS. 18A-18B, 19, 20, 21A-21B, 22A-22C, 23, and 24 may be fabricated using a variety of deposition, patterning, and planarization sequencesAttorney Docket No.: 072174-07704 compatible with standard semiconductor FEOL and BEOL processes. In a typical implementation, each ferroelectric memory tier is formed by depositing a metal-ferroelectric-metal (MFM) structure or a ferroelectric gate stack, followed by interlayer dielectric (ILD) deposition and planarization. In some examples, where the superlattice structures are temperature sensitive, the temperature exposure of the layers may be controlled to ensure that the superlattice is protected. Vertical interconnects, such as conductive pillars or vias, may then be formed to electrically couple adjacent tiers. These operations may be repeated any suitable number of times to construct the desired 3D stack height. For vertical -channel NAND-type FeFET embodiments, a high-aspect-ratio channel trench may be etched prior to gate-stack deposition, whereas in monolithic layer-by-layer embodiments the tiers are formed independently without deep channel etching. The general per-layer FeFET stacking architecture may be implemented by providing per-tier gate, source, and drain interconnect routing, with access lines defined within each horizontal tier. Any equivalent BEOL- or FEOL-compatible sequence capable of producing the structures shown in FIGS. 18A-18B, 19, 20, 21A-21B, 22A-22C, 23, and 24 may be used.

[0360] In some embodiments, a general M3D stacking approach may be used in which each FTJ or FeFET tier is formed as an independent horizontal plane without a vertical channel string. In such cases, each FTJ tier comprises a repeated MFM stack, and each FeFET tier comprises a gate-stack-over-channel structure or a gate-stack-over-silicon-slab structure. The independent tiers are formed sequentially through repeated cycles of deposition, etch, ILD fill, and planarization, enabling a straightforward layer-by-layer M3D assembly.

[0361] In further embodiments, a general per-layer addressable FeFET stacking architecture may be used, in which each FeFET tier includes dedicated gate, source, and drain routing. This approach allows per-cell addressing across tiers and supports HBM-class high-bandwidth memory functionality without capacitors, refresh cycles, TSVs, or die-to-die bonding.Attorney Docket No.: 072174-07704

[0362] Any equivalent BEOL- or FEOL-compatible sequence capable of producing the structures shown in FIGS. 18A-18B, 19, 20, 21A-21B, 22A-22C, 23, and 24 or there multilevel memory element effect, including general M3D stacking of FTJ or FeFET layers, may be used to implement the disclosed architectures.

[0363] Unified Advantages Over NAND and DRAM / HBM: The 3D stacked FTJ and FeFET architectures of FIGS. 18A-18B, 19, 20, 21A-21B, 22A-22C, 23, and 24 overcome key limitations of both 3D NAND and DRAM / HBM technologies. Compared to 3D NAND, the superlattice-based devices do not require extremely high energy for switching and can operate at lower voltages. Compared to DRAM / HBM, the devices do not rely on capacitors or periodic refresh operations and avoid the TSV congestion and thermal bottlenecks associated with stacked DRAM dies. Monolithic 3D integration of FTJ and FeFET tiers therefore enables high-density, high-bandwidth, and energy-efficient memory systems that can serve as a unified platform for both nonvolatile storage and working memory.

[0364] In addition to the device-level and stacking architectures described above, FIGS. 22A-22C, 23, and 24 illustrate scalable memory organization frameworks for 3D stacked ferroelectric memory, in which physical stacking, logical page grouping, and per-layer addressing are decoupled. This enables high-density monolithic integration while preserving fine-grained random access, high bandwidth, and low energy operation.

[0365] FIG. 22A illustrates a representative 3D stacked ferroelectric memory array in which word lines 2203 (WL0-WL7, or any suitable number of WL) extend in a first direction and bit lines 2204 (BL0-BL7, or any suitable number of BL) extend orthogonally. See FIG. 22A (with substate 2201, well 2202, source line (SL) 2205, and gate 2206). Each intersection defines a memory cell 2207 implemented as a ferroelectric tunnel junction (FTJ) or FeFET device. See FIGS.22B-22C. In this architecture, multiple memory tiers are vertically stacked while maintaining per-layer word-line and bit-line routing, enabling high-density integrationAttorney Docket No.: 072174-07704 without requiring capacitor-based storage elements.

[0366] FIG. 24 illustrates a page-selectable memory organization, in which a plurality of memory cells 2304 are grouped into pages (such as pages 2303a, 2303b, and 2303g for pages 1-2 and 7, respectively) spanning multiple word lines (such as word lines 2301a and 2301f for word lines 1 and 6, respectively) and bit lines (such as bit lines 2302a, 2302b, and 2303c, for bit lines 1, 2, and 3, respectively). The pages have page select lines that extend in a direction distinct from the word lines and bit lines, allowing selective activation of a target page without disturbing adjacent pages. This organization enables page-level parallel read and write operations, improving bandwidth and access efficiency compared to conventional string-based NAND architectures. The page select lines shown in FIG. 23 may be implemented using dedicated conductors, shared routing layers, or equivalent selecta ion mechanisms.

[0367] FIG.24 further illustrates a vertically extensible word organization in which word lines 2401 are arranged along a vertical dimension, while bit lines (such as bit lines 2402a, 2402b, and 2402c for bit lines 1, 2, and 3, respectively) extend horizontally across pages (such as for pages 2403a and 2403b for pages 1 and 2, respectively). Each page includes independently addressable word and bit lines, enabling random access at the page or word granularity.

[0368] Because the ferroelectric memory elements retain data without refresh, the architecture supports DRAM- or HBM-like access characteristics without capacitors, refresh cycles, or through-silicon vias (TSVs). Accordingly, the architecture provides high bandwidth through massive parallelism across pages, analogous to HBM architectures but implemented through monolithic 3D integration.

[0369] While embodiments of the invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described and the examples provided herein are exemplary only, and are not intended to be limiting. Many variations and modifications of the inventionAttorney Docket No.: 072174-07704 disclosed herein are possible and are within the scope of the invention. The scope of protection is not limited by the description set out above, but is only limited by the claims which follow, that scope including all equivalents of the subject matter of the claims.

[0370] The described process flows illustrate examples of integrating a ferroelectric gate dielectric into conventional CMOS fabrication sequence. The specific materials, thickness ranges, and process techniques described herein are provided for illustrative purposes and may be varied depending on device design, performance targets, and integration constraints, without departing from the scope of the invention.

[0371] The disclosures of all patents, patent applications, and publications cited herein are hereby incorporated herein by reference in their entirety, to the extent that they provide exemplary, procedural, or other details supplementary to those set forth herein.

[0372] Amounts and other numerical data may be presented herein in a range format. It is to be understood that such range format is used merely for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. For example, a numerical range of approximately 1 to approximately 4.5 should be interpreted to include not only the explicitly recited limits of 1 to approximately 4.5, but also to include individual numerals such as 2, 3, 4, and sub-ranges such as 1 to 3, 2 to 4, etc. The same principle applies to ranges reciting only one numerical value, such as “less than approximately 4.5,” which should be interpreted to include all of the above-recited values and ranges. Further, such an interpretation should apply regardless of the breadth of the range or the characteristic being described.

[0373] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which the presentlyAttorney Docket No.: 072174-07704 disclosed subject matter belongs. Although any methods, devices, and materials similar or equivalent to those described herein can be used in the practice or testing of the presently disclosed subject matter, representative methods, devices, and materials are now described.

[0374] Following long-standing patent law convention, the terms “a” and “an” mean “one or more” when used in this application, including the claims.

[0375] Unless otherwise indicated, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in this specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the presently disclosed subject matter.

[0376] As used herein, the term “about” and “substantially” when referring to a value or to an amount of mass, weight, time, volume, concentration or percentage is meant to encompass variations of in some embodiments ±20%, in some embodiments ±10%, in some embodiments ±5%, in some embodiments ±1%, in some embodiments ±0.5%, and in some embodiments ±0.1% from the specified amount, as such variations are appropriate to perform the disclosed method.

[0377] As used herein, the term “substantially perpendicular” and “substantially parallel” is meant to encompass variations of in some embodiments within ±10° of the perpendicular and parallel directions, respectively, in some embodiments within ±5° of the perpendicular and parallel directions, respectively, in some embodiments within ±1° of the perpendicular and parallel directions, respectively, and in some embodiments within ±0.5° of the perpendicular and parallel directions, respectively.

[0378] As used herein, the term “and / or” when used in the context of a listing of entities, refers to the entities being present singly or in combination. Thus, for example, the phrase “A, B, C,Attorney Docket No.: 072174-07704 and / or D” includes A, B, C, and D individually, but also includes any and all combinations and subcombinations of A, B, C, and D.REFERENCES

[0379] PCT Application No. PCT / US24 / 42780, filed on August 16, 2024, entitled “Methods of Flash-Within-Flash Joule Heating And Systems Thereof,” to J.M. Tour, et al. (" Tour ’780 PCT Application”').

[0380] PCT Application No. PCT / US21 / 52030, filed September 24, 2021, entitled “Ultrafast Flash Joule Heating Synthesis Methods And Systems For Performing Same,” to James M. Tour, et al. ("Tour ’030 PCT Application”)

[0381] PCT Application No. PCT / US 19 / 47967, filed on August 23, 2019, entitled “Flash Joule Heating Synthesis Method and Compositions Thereof,” to J.M. Tour, et al. (" Tour ’967 PCT Application”).

[0382] U.S. Patent Application Serial No. 63 / 645,535, filed May 10, 2024, entitled “Scaled Flash Joule Heating Systems And Methods of Using Same,” to J.M. Tour, et al. (fTour ’535 Application”).

[0383] Dawber, M., et al., “Physics of thin-film ferroelectric oxides,” Reviews of Modern Physics, 2005, 77, 1083 (fDawber 2005”).

[0384] Hoffman, M., et al., “Ferroelectric phase transitions in nanoscale HfCh films enable giant pyroelectric energy conversion and highly efficient supercapacitors,” Nano Energy, 2015, 18, 154-164 (f Hoffman 2015”).

[0385] Jerry, M., et al., “Ferroelectric FET analog synapse for acceleration of deep neural network training,” IEEE International Electron Devices Meeting (IEDM), 2017 (".Jerry 2017”).

[0386] Lee, D., et al., “Enhancing Ferroelectricity in Hafnium Oxide with AI2O3 Interlayers,” Journal of Materials Chemistry C, 2022, 10, 5567-5574 (" ee 2022”).

[0387] Li, W., et al., “High-Speed Crystallization Using Flash Joule Heating." AdvancedAttorney Docket No.: 072174-07704 Materials, 2021, 33, 2000842 (“Zz 2021”).

[0388] Luong, D. X., et al., “Gram-scale bottom-up flash graphene synthesis,” Nature, 2020, 577, 647-651 (“ Luong 2020").

[0389] Mikolajick, T., etal., “Ferroelectric Hafnium Oxide for Advanced Electronics,” Nature, 2019, 546, 124-128 ^Mikolajick 2019”).

[0390] Muller, L, et al., “Fast Polarization Switching in HfO2-based Ferroelectrics,” IEEE Transactions on Electron Devices, 2012, 59, 4199-4202 (f Muller 2012”).

[0391] Park, M. H., etal., “Ferroelectricity and Antiferroelectricity of Doped Thin HfO2-Based Films,” Advanced Materials, 2015, 27, 1811-1831 (fPark 2015”).

[0392] Polakowski, P., et al., “Ferroelectricity in undoped hafnium oxide,” Applied Physics Letters, 2015, 106, 232905 ^Polakowski 2015”).

[0393] Schroeder, U., et al., “Impact of different dopants on the switching properties of ferroelectric hafnium oxide,” Journal of Applied Physics, 2014, 116, 084102 (f Schroeder 2014”).Scott, J. F., “Applications of Modern Ferroelectrics,” Science, 2007, 315, 954-9592007”).Uchino, K., “Ferroelectric Devices,” Marcel Dekker, Inc., New York, 1996 Jllchino 1996”).

Claims

Attorney Docket No.: 072174-07704 WHAT IS CLAIMED IS:

1. A process for fabricating a ferroelectric device, comprising:(a) depositing a superlattice structure comprising layering (I) two or more MnXmlayers and (II) one or more APBqlayers, wherein(i) each of the MnXmlayers is a layer of MnXm, wherein(A) M is a transition or main group metal,(B) X is selected from the group consisting of N, O, S, and Se, (C) the MnXm of each MnXmlayer is the same or different than the MnXm of the two or more MnXmlayers,(D) in each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m, and(E) in each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n,(ii) each of the APBqlayers is a layer of APBq, wherein(A) A is a transition or main group metal,(B) B is selected from the group consisting of N, O, S, and Se, (C) the APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers,(D) in each of the of the ApBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q, and(E) in each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of AAttorney Docket No.: 072174-07704and the value of p,(iii) at least one of the MnXmlayers is positioned at a top face or a bottom face of the superlattice structure.(iv) the two or more MnXmlayers and the one or more APBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers, and(v) the two or more MnXmlayers and the one or more APBqlayers are layered in a predetermined thickness ratio;(b) using a rapid annealing process to induce ferroelectricity;(c) forming a device stack in which the superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric-semiconductor (MFS), metal-ferroelectric- insulator-semiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS).

2. The process of Claim 1, wherein process temperature of the rapid thermal annealing process is between 400 °C and 1200 °C.

3. The process of any of Claims 1-2, wherein the superlattice structure enables integration into a system / application selected from the group consisting of neuromorphic computing systems, non-volatile memory applications, and memory systems configured to replace or complement NAND flash and / or DRAM.

4. A method comprising:(a) selecting a ferroelectric device made by the process of any of Claims 1-3; andAttorney Docket No.: 072174-07704 (b) integrating the ferroelectric device in a system / application selected from the group consisting of neuromorphic computing systems and non-volatile memory applications.

5. A ferroelectric device made by the process or method of any of Claims 1-4.

6. A ferroelectric material comprising a superlattice structure comprising (I) two or more MnXm layers and (II) one or more APBqlayers, wherein(i) each of the MnXmlayers is a layer of MnXm, wherein(A) M is a transition or main group metal,(B) X is selected from the group consisting of N, O, S, and Se, (C) the MnXm of each MnXmlayer is the same or different than the MnXmof the two or more MnXmlayers,(D) in each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m, and(E) in each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n,(ii) each of the APBqlayers is a layer of APBq, wherein(A) A is a transition or main group metal,(B) B is selected from the group consisting of N, O, S, and Se, (C) the APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers,(D) in each of the of the APBqlayers, p is selected from the group consistingAttorney Docket No.: 072174-07704 of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q, and(E) in each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p, (iii) one of the MnXmlayers is positioned at a top face of the superlattice structure, (iv) another of the MnXmlayers is positioned at a bottom face of the superlattice structure,(v) the two or more MnXmlayers and the one or more APBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers,(vi) the two or more MnXmlayers and the one or more APBqlayers are in a predetermined thickness ratio,(vii) the superlattice structure stabilizes an orthorhombic ferroelectric phase of the ferroelectric material, and(viii) the superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal-ferroelectric- semiconductor (MFS), metal-ferroelectric-insulator-semiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal-insulator- ferroelectric-insulator-semiconductor (MIFIS).

7. The ferroelectric material of Claim 6, wherein the superlattice based ferroelectric structure is formed upon one or more underlayers, wherein a layer of the one or more underlayers is planarized.

8. The ferroelectric material or device of any of Claims 5-7, wherein the structure isAttorney Docket No.: 072174-07704 operable for use selected from the group consisting of memory, logic, compute-in-memory, and neuromorphic application.

9. The ferroelectric device or material of any of Claim 5-7, wherein the gate electrode material is a CMOS-compatible metal selected from the group consisting of TiN, TaN, WN, MoN, or metal stacks, enabling threshold voltage tuning through work function engineering, and is deposited using PVD, ALD, or CVD techniques in a gate-first or replacement metal gate (RMG) flow.

10. The ferroelectric device or material of any of Claims 5-7, wherein the device is integrated into a three-dimensional (3D) monolithic or stacked architecture, including vertical channels, tiered memory / logic stacks, or back-end-of-line (BEOL) embedded layers, enabling vertical scaling and heterogeneous integration within advanced CMOS systems.

11. A process of fabricating a ferroelectric field-effect transistor (Fe-FET) using a CMOS-compatible method, wherein the process comprises:(a) providing a substrate selected from a silicon-on-insulator (SOI) wafer or a bulk silicon substrate, wherein the SOI wafer comprises a top silicon layer having a thickness from 1 nm to 3 pm, a buried oxide (BOX) layer having a thickness ranging from 10 nm to several micrometers, and an underlaying handle silicon substrate of arbitrary thickness;(b) forming isolation regions in the substrate to define active areas, using shallow trench isolation (STI) or local oxidation of silicon (LOCOS);(c) forming a channel region in the top silicon layer by performing ion implantation to introduce a lightly doped region;Attorney Docket No.: 072174-07704 (d) forming heavily doped source and drain regions by performing high-dose ion implantation;(e) depositing a gate dielectric over the channel region, wherein the gate dielectric comprising a ferroelectric superlattice structure composed of alternating layers ofHfCh / ZrCh or HfCh / AhCh / HfCh;(f) forming a gate electrode over the ferroelectric gate dielectric, wherein the material being selected from the group consisting of metals, metal nitrides, and polysilicon;(g) annealing the structure to crystallize the superlattice using a thermal process selected from rapid thermal annealing (RTA) or flash Joule heating (FJH); (h) forming sidewall spacers on the gate electrode using conformal deposition and anisotropic etch-back processes;(i) forming contact holes to the source, drain, and gate regions, and depositing metal contacts by either etch-back or lift-off processing techniques; and (j) completing interconnect metallization and passivation layers using standard front-end-of-line (FEOL) and back-end-of-line (BEOL) CMOS process.

12. The process of Claim 11, wherein the channel region comprises p-type boron (B) doping at a concentration between 1 * 1014and 1 * 1017atoms / cm3.

13. The process of Claim 11, wherein the channel region comprises n-type doping selected from phosphorus (P) or arsenic (As) at a concentration between 1 * 1014and 1 x 1018atoms / cm3.

14. The process of Claim 11, wherein the source and drain regions comprise n-type dopants or p-type dopants with concentrations ranging from 1 * 1019to 1 x 1021atoms / cm3after activationAttorney Docket No.: 072174-07704 annealing.

15. The process of Claim 11 further comprising:(a) performing well formation and threshold voltage tuning using ion implantation; (b) depositing the ferroelectric superlattice structure post-activation to avoid degradation from thermal budget; and(c) completing integration using standard FEOL-compatible gate-last or gate-first CMOS process flows.

16. The process or method of any of Claims 1-4 and 11-15, wherein(a) the superlattice-based ferroelectric structure is integrated into a CMOS fabrication flow, and(b) post-formation thermal processing is controlled to substantially maintain the superlattice structure.

17. The process of any of Claims 1-4 and 11-15 further comprising a planarization process performed on one or more layers upon which the superlattice-based ferroelectric structure is formed, wherein the planarization process comprises one or more of chemical mechanical polishing, spin-on flowable dielectric deposition with etch-back, glass reflow, electrochemical mechanical polishing, localized laser-induced reflow, and sacrificial layer etching.

18. The ferroelectric device of any of Claims 5 and 8-10, wherein(a) the ferroelectric device comprises a three-dimensional (3D) stacked ferroelectric memory architecture comprising a plurality of vertically stacked memory tiers, andAttorney Docket No.: 072174-07704 (b) each memory tier comprising a ferroelectric active layer comprising a superlattice structure that comprises (I) two or more MnXmlayers and (II) one or more APBqlayers, wherein(i) each of the MnXmlayers is a layer of MnXm, wherein(A) M is a transition or main group metal,(B) X is selected from the group consisting of N, O, S, and Se, (C) the MnXm of each MnXmlayer is the same or different than the MnXm of the two or more MnXmlayers,(D) in each of the of the MnXmlayers, n is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of m, and(E) in each of the of the MnXmlayers, m is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of M and the value of n,(ii) each of the APBqlayers is a layer of APBq, wherein(A) A is a transition or main group metal,(B) B is selected from the group consisting of N, O, S, and Se, (C) the APBqof each APBqlayer is the same or different than the APBqof the two or more APBqlayers,(D) in each of the of the APBqlayers, p is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of q, and(E) in each of the of the APBqlayers, q is selected from the group consisting of 1, 2, 3, 4, and depends on the oxidation state of A and the value of p,Attorney Docket No.: 072174-07704 (iii) one of the MnXmlayers is positioned at a top face of the superlattice structure,(iv) another of the MnXmlayers is positioned at a bottom face of the superlattice structure,(v) the two or more MnXmlayers and the one or more APBqlayers are layered alternatively such that each of the one or more APBqlayers is positioned between two of the two or more MnXmlayers,(vi) the two or more MnXmlayers and the one or more APBqlayers are in a predetermined thickness ratio,(vii) the superlattice structure stabilizes an orthorhombic ferroelectric phase of the ferroelectric material, and(viii) the superlattice structure is disposed in a configuration selected from the group consisting of metal-ferroelectric-metal (MFM), metal- ferroelectric-semiconductor (MFS), metal -ferroelectric-insulatorsemiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS).

19. A method of forming a ferroelectric device of Claim 18, wherein the method comprises repeating the process or method of any of Claims 1-4 or 11-15 to form a plurality of vertically stacked ferroelectric memory tiers.

20. A method of forming a ferroelectric device, wherein the comprises:(a) forming a superlattice ferroelectric layer on a substrate, whereinAttorney Docket No.: 072174-07704 (i) the superlattice ferroelectric layer comprising a plurality of alternating first oxide layers and second oxide layers, and(ii) each of the first oxide layers and the second oxide layers have a thickness of less than about 5 nm;(b) annealing the superlattice ferroelectric layer under conditions that induce a ferroelectric crystalline phase; and(c) forming a first electrode and a second electrode on opposing sides of the superlattice ferroelectric layer, wherein(i) the first electrode, the second electrode, and the superlattice ferroelectric layer are configured in a ferroelectric capacitor structure, and(ii) the ferroelectric device has an endurance of at least 106polarization switching cycles.

21. A three-dimensional (3D) ferroelectric memory device, comprising:(a) a plurality of memory tiers monolithically stacked along a vertical direction, wherein each memory tier comprises a plurality of ferroelectric memory cells; (b) a plurality of word lines extending in a first direction and coupled to the ferroelectric memory cells;(c) a plurality of bit lines extending in a second direction different from the first direction and coupled to the ferroelectric memory cells; and(d) a page-selectable memory organization in which groups of the ferroelectric memory cells are logically grouped into pages independently of physical stacking of the memory tiers, wherein(i) each ferroelectric memory cell comprises a ferroelectric tunnel junction (FTJ) or a ferroelectric field-effect transistor (FeFET),Attorney Docket No.: 072174-07704 (ii) the ferroelectric memory cell comprises a ferroelectric stack selected from the group consisting of metal-ferroelectric-metal (MFM), metal- ferroelectric-semiconductor (MFS), metal-ferroelectric-insulatorsemiconductor (MFIS), metal-insulator-ferroelectric-semiconductor (MIFS), and metal-insulator-ferroelectric-insulator-semiconductor (MIFIS), and(g) the 3D ferroelectric memory device is operable for providing random access at a page or word granularity without requiring capacitor-based storage elements or periodic refresh operations.

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