Liners for defect reduction and source / drain formation, and related methods, apparatus, and processing chambers

Abstract

The present disclosure relates to liners for defect reduction and source / drain formation, and related methods, apparatus, and processing chambers. In one or more embodiments, a method of substrate processing includes forming an amorphous liner on a structure on a substrate. The amorphous liner includes silicon, and the forming includes a formation temperature. The method includes annealing the amorphous liner to crystallize the amorphous liner into a crystalline liner. The annealing includes ramping the formation temperature to an anneal temperature at a ramp rate, the ramp rate less than 5.0 degrees Celsius-per-second. The method includes removing liner material from a plurality of cap layers of the structure, and forming source and drain material on the crystalline liner.

Description

44025930W001LINERS FOR DEFECT REDUCTION AND SOURCE / DRAIN FORMATION, AND RELATED METHODS, APPARATUS, AND PROCESSING CHAMBERSBACKGROUNDField

[0001] The present disclosure relates to liners for defect reduction and source / drain formation, and related methods, apparatus, and processing chambers.Description of the Related Art

[0002] Semiconductor substrates are processed for a wide variety of applications, including the fabrication of integrated devices and micro-devices. One method of processing substrates includes depositing a material, such as a dielectric material or a semiconductive material, on an upper surface of the substrate. The material may be deposited in a lateral flow chamber by flowing a process gas parallel to the surface of a substrate positioned on a support, and thermally decomposing the process gas to deposit a material from the gas onto the substrate surface.

[0003] However, defects can form throughout formation of the film. As an example, the deposition and etching of film can cause merging of film, stacking faults, and / or forming of voids in the film. As another example, the strain of film can be low, which can hinder performance of the film. Moreover, the inner surfaces of the recesses also can have different materials that provide variable surfaces for growth initiation. The defects can affect electrical properties (such as contact resistance) for source / drain material. Additionally, as transistor dimensions are scaled down to smaller technology nodes, there is a need for further improvements in GAA design and manufacturing.

[0004] Therefore, a need exists for improved methods of forming film.44025930W001SUMMARY

[0005] The present disclosure relates to liners for defect reduction and source / drain formation, and related methods, apparatus, and processing chambers.

[0006] In one or more embodiments, a method of substrate processing includes forming an amorphous liner on a structure on a substrate. The amorphous liner includes silicon, and the forming includes a formation temperature. The method includes annealing the amorphous liner to crystallize the amorphous liner into a crystalline liner. The annealing includes ramping the formation temperature to an anneal temperature at a ramp rate, the ramp rate less than 5.0 degrees Celsius-per-second. The method includes removing liner material from a plurality of cap layers of the structure, and forming source and drain material on the crystalline liner.

[0007] In one or more embodiments, a non-transitory computer readable medium includes instructions that, when executed, cause a plurality of operations to be conducted. The plurality of operations include setting a formation temperature, and flowing a deposition precursor, the deposition precursor including silicon. The plurality of operations include ramping the formation temperature to an anneal temperature at a ramp rate. The ramp rate is less than 5.0 degrees Celsius-per-second. The plurality of operations include flowing a source and drain precursor.

[0008] In one or more embodiments, a device includes a substrate, and a plurality of stacks formed on the substrate to define a plurality of recesses between the plurality of stacks. The device includes a crystalline liner lining side surfaces of at least one of the plurality of stacks, and a source and drain material formed on the crystalline liner. The source and drain material has a strain of 0.4 or higher.

[0009] In one or more embodiments, a method of forming a semiconductor device is provided. The method includes providing a structure having a source / drain cavity defined by a pair of opposing sidewall surfaces, the sidewall surfaces each defined by alternating pairs of a first semiconductor layer and a44025930W001second semiconductor layer. The method further includes exposing the second semiconductor layer to an etching process to remove a portion of the second semiconductor layer and form an inner cavity recess. The method further includes filling the inner cavity recess with a dielectric material to form an inner spacer. The method further includes forming a conformal liner layer over the sidewall surfaces, the conformal liner layer formed on the inner spacer. The method further includes forming a source / drain material on the conformal liner layer in the source / drain cavity.

[0010] In one or more embodiments, a method of forming a semiconductor device is provide. The method includes providing a structure having a source / drain cavity defined by a pair of opposing sidewall surfaces, the sidewall surfaces each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer. The method further includes forming a raised inner spacer on the first semiconductor layer, the raised inner spacer extending past the sidewall surfaces. The method further includes forming a conformal liner layer over the sidewall surfaces and the raised inner spacer. The method further includes forming a source / drain material on the conformal liner layer in the source / drain cavity.

[0011] In one or more embodiments, a non-transitory computer readable medium has stored thereon instructions, which, when executed by a processor, causes the process to perform operations of the above apparatus and / or method.

[0012] In one or more embodiments, a method of forming a semiconductor device is provided. The method includes epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material defining a recess having a U-shaped profile. The method further includes epitaxially growing a second layer of semiconductor material on the first layer of semiconductor material in the recess by a bottom-up growth process.44025930W001

[0013] Implementations may include one or more of the following. The bottom surface has a first crystal plane orientation and the sidewall surfaces have a second crystal plane orientation. A growth rate of the first layer along the first crystal plane orientation is greater than a growth rate of the first layer along the second crystal plane orientation. The first crystal plane orientation is (100) and the second crystal plane orientation is (101). Epitaxially growing the first layer is performed at a first temperature in a range from about 700 degrees Celsius to about 750 degrees Celsius. Epitaxially growing the second layer is performed at a second temperature in a range from about 500 degrees Celsius to about 700 degrees Celsius and the second temperature is less than the first temperature. Epitaxially growing the first layer is performed at a first pressure in a range from about 10 Torr to about 200 Torr. Epitaxially growing the second layer is performed at a second pressure in a range from about 5 Torr to about 20 Torr and the second pressure is less than the first pressure. The first layer includes silicon germanium doped with a p-type dopant, the first layer having a first germanium concentration and a first dopant concentration. The second layer includes silicon germanium doped with the p-type dopant, the second layer having a second germanium concentration, which is greater than the first germanium concentration and a second dopant concentration, which is greater than the first dopant concentration. A bottom surface of the recess is curved.

[0014] In one or more embodiments, a method of forming a semiconductor device is provided. The method includes epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material is a conformal layer and defines a first recess. The method further includes etching the first layer of semiconductor material to form a modified first layer of semiconductor material, the modified first layer of semiconductor material defining a second recess having a U-shape profile. The method further includes epitaxially growing a second layer of semiconductor material on the modified first layer of semiconductor material in the second recess by a bottom-up growth process.44025930W001

[0015] Implementations may include one or more of the following. Etching the first layer of semiconductor material includes removing an upper portion of the first layer of semiconductor material coating an upper portion of the sidewall surfaces at greater rate than a lower portion of the first layer of semiconductor material coating a lower portion of the sidewall surfaces and the bottom surface. The first layer includes silicon germanium doped with a p-type dopant, the first layer having a first germanium concentration and a first dopant concentration. The second layer includes silicon germanium doped with the p-type dopant, the second layer having a second germanium concentration, which is greater than the first germanium concentration and a second dopant concentration, which is greater than the first dopant concentration. A bottom surface of the second recess is curved.

[0016] In one or more embodiments, a processing system is provided. The processing system includes a first processing chamber and a system controller. The system controller includes a memory for storing computer readable instructions and a processor coupled to the memory. The processor is configured by the computer readable instructions that when executed by the processor perform a plurality of operations. The plurality of operations include epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material defining a recess having a U-shaped profile. The plurality of operations further include epitaxially growing a second layer of semiconductor material on the first layer of semiconductor material in the recess by a bottom-up growth process.

[0017] Implementations may include one or more of the following. The bottom surface has a first crystal plane orientation and the sidewall surfaces have a second crystal plane orientation. A growth rate of the first layer along the first crystal plane orientation is greater than a growth rate of the first layer along the second crystal plane orientation. The first crystal plane orientation is (100) and the second crystal plane orientation is (101).44025930W001

[0018] In one or more embodiments, a non-transitory computer readable medium has stored thereon instructions, which, when executed by a processor, causes the process to perform operations of the above apparatus and / or method.BRIEF DESCRIPTION OF THE DRAWINGS

[0019] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0020] FIG. 1 is a partial schematic side cross-sectional view of a processing chamber, according to one or more embodiments.

[0021] FIG. 2 is a schematic block diagram view of a method of substrate processing, according to one or more embodiments.

[0022] FIGS. 3A-3D are schematic partial cross-sectional views of the method conducted in relation to a semiconductor device structure, according to one or more embodiments.

[0023] FIG. 4 illustrates a nanostructure field-effect transistor (nano-FET) in a three dimensional view, according to one or more embodiments.

[0024] FIG. 5 illustrates one example of a flow chart of a method of forming a nano-FET structure, according to one or more embodiments.

[0025] FIGS. 6A-6F illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments.

[0026] FIG. 7 illustrates one example of a flow chart of a method of forming a nano-FET structure, according to one or more embodiments.44025930W001

[0027] FIGS. 8A-8E illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments.

[0028] FIG. 9 illustrates a plan view of a cluster tool, according to one or more embodiments.

[0029] FIG. 10 illustrates a cross-sectional view of a processing chamber, according to one or more embodiments.

[0030] FIG. 11 illustrates a flow chart of a method of forming a nano-FET structure, according to one or more embodiments.

[0031] FIGS. 12A-12C illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments.

[0032] FIG. 13 illustrates one example of a flow chart of a method of forming a nano-FET structure, according to one or more embodiments.

[0033] FIGS. 14A-14D illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments.

[0034] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0035] The present disclosure relates to liners for defect reduction and source / drain formation, and related methods, apparatus, and processing chambers. The liners can be formed using solid phase regrowth. The subject matter can be used to form gate-all-around (GAA) transistor devices. In one or more embodiments, the methods and structures herein can introduce strain on P-type horizontal GAA devices.

[0036] As an example, the liner can be formed as part of n-EPI deposition (such as to form silicon phosphide (SiP)). As an example, the liner can be formed as part of p-EPI deposition (such as to form silicon-germanium-boron44025930W001(SiGeB), SiGe, or SiB). For example, the formation of the liner can include deposition of SiGe or SiB, followed by deposition of high-B SiB or high-Ge SiGe. The liner can provide a continuous crystalline starting surface for the subsequent fill (e.g., epitaxial growth). A solid phase epitaxial regrowth of the epitaxial liner can provide single crystalline growth on a recess with variable surfaces, such as a variety of surfaces that include one or more dielectrics. A subsequent recess fill on the liner can start on a defect free (e.g., with reduced or eliminated defects) and single material surface to provide a strained high quality recess fill on the liner. A doped liner can also help in providing a contamination free starting surface for fill in the recess.

[0001] Scaling down of silicon metal oxide semiconductor (MOS) devices has become a major challenge in the semiconductor industry. One problem with the scaling of conventional planar devices are the short channel effects, which start to dominate over device performance. One solution for this problem came with the introduction of multi-gate devices with three dimensional architecture, such as fin based semiconductor devices or FinFETs and GAA devices. Due to their three-dimensional architecture with either the gate being wrapped around a thin semiconductor fin for FINFET or the gate electrode surrounding all side surfaces of the channel region for GAA, improved gate control (and thus less short channel effects) over the channel could be achieved by using multiple gates.

[0002] Recess cavities with inner spacers, which typically include dielectric materials, have challenges with epitaxial growth on the spacer. Epitaxial films deposited in recesses with inner spacers formed along the sidewalls of the recess often grow with sidewall defects. These epitaxial films are highly defective and often do not impart strain into the channel region of the p-type source / drain epitaxy. L1 liners, which are formed along the sidewalls of the recess, prior to epitaxial deposition of the source / drain features, typically grow selectively around the inner spacers and grow as “knuckles” with multiple crystal orientations. Subsequent epitaxial growth on the L1 liners with multiple crystal orientations is highly defective and does not impart strain to the channel region.44025930W001

[0003] In one or more embodiments, a conformal liner growth process is provided. The conformal liner is grown at low growth rates with lower gas flow rates. The conformal liner process covers the inner spacer and can also cover “knuckles” generated by the L1 liners to provide a smooth recess surface for subsequent epitaxial filling of the recess. The conformal liner process provides a high-quality surface for subsequent epitaxial deposition fill of the recess leading to fewer defect in the formed source / drain feature. The conformal liner can be used with or without an L1 liner.

[0004] In one or more embodiments, a raised inner spacer is provided. The raised inner spacer extends out from the sidewall surfaces defined by the source / drain recess. An L1 liner may then be deposited followed by deposition of the conformal liner to provide a smooth, conformal surface for subsequent recess fill with reduced defects in the formed source / drain feature.

[0001] Multi-gate devices, such as horizontal GAA (hGAA) devices, can lack PMOS strain. An initial tensile strain in the PMOS channel, which is beneficial for device performance, is can be present. However, the introduction of PMOS source drain (S / D) epitaxial material will fill up the trench and reduce channel strain, resulting in loss of device performance. Thus, there is a need for improvements in GAA design and manufacturing which demonstrate improved channel strain.

[0002] In one or more embodiments, deposition of a multi-layer epitaxial source / drain material is performed. A first layer of epitaxial source / drain material is formed over the surface of a source / drain cavity by a partial bottom-up process. The first layer of epitaxial source / drain material defines a recess having a U-shaped, a V-shaped surface, or a combination of a U-shaped surface and a V-shaped surface, for example a V-shaped surface with a rounded or curved bottom. The first layer of epitaxial source / drain material facilitates bottom-up growth of a second layer of epitaxial source / drain material, which generates a source / drain stress that will transfer into the channel.

[0003] In one or more embodiments, deposition of a multi-layer epitaxial source / drain material is performed. A first layer of epitaxial source / drain44025930W001material is formed over the surface of a source / drain cavity by a conformal deposition process. The first layer of epitaxial source / drain material defines a first recess. The first layer of epitaxial source / drain material is etched to form a modified first layer of semiconductor material. The modified first layer of semiconductor material defines a second recess having a U-shaped surface, a V-shaped surface, or a combination of a U-shaped surface and a V-shaped surface, for example a V-shaped surface with a rounded or curved bottom. The modified first layer of epitaxial source / drain material facilitates bottom-up growth of a second layer of epitaxial source / drain material, which generates a source / drain stress that will transfer into the channel.

[0004] The implementations described herein are applicable to nanostructure field-effect transistors (nano-FET) including vertically stacked lateral nanowires (NW) / nanosheets (NS) Gate-AII-Around (GAA) FET devices. In addition, the techniques described herein can be implemented with a gate-first process in which the source and drain are formed after the gate is formed or a gate-last process in which the source and drain are formed prior to the gate, sometimes referred to as a replacement metal gate or RMG process.

[0037] The disclosure contemplates that terms such as “couples,” “coupling,” “couple,” and “coupled” may include but are not limited to embedding, bonding, welding, fusing, melting together, interference fitting, and / or fastening such as by using bolts, threaded connections, pins, and / or screws. The disclosure contemplates that terms such as “couples,” “coupling,” “couple,” and “coupled” may include but are not limited to integrally forming. The disclosure contemplates that terms such as “couples,” “coupling,” “couple,” and “coupled” may include but are not limited to direct coupling and / or indirect coupling, such as indirect coupling through components such as links, blocks, and / or frames.

[0038] Figure 1 is a partial schematic side cross-sectional view of a processing chamber 1000, according to one or more embodiments. The processing chamber 1000 is a deposition chamber. In one or more embodiments, the processing chamber 1000 is an epitaxial deposition chamber. In one or more embodiments, the processing chamber 1000 is44025930W001utilized to grow an epitaxial film on a substrate 102. The processing chamber 1000 creates a cross-flow of precursors across a top surface of the substrate 102. The processing chamber 1000 is shown in a processing condition in Figure 1.

[0039] The processing chamber 1000 includes an upper body 156, a lower body 148 disposed below the upper body 156, a flow module 112 disposed between the upper body 156 and the lower body 148. The upper body 156, the flow module 112, and the lower body 148 form a chamber body. Disposed within the chamber body is a substrate support 106, an upper plate 108 (such as an upper window and / or an upper dome), a lower plate 110 (such as a lower window and / or a lower dome), a plurality of upper heat sources 141, and a plurality of lower heat sources 143. As shown, a controller 190 is in communication with the processing chamber 100 and is used to control processes and methods, such as the operations of the methods described herein. The present disclosure contemplates that each of the heat sources described herein can include one or more of: lamp(s), resistive heater(s), light emitting diode(s) (LEDs), and / or laser(s). The present disclosure contemplates that other heat sources can be used.

[0040] The substrate support 106 is disposed between the upper plate 108 and the lower plate 110. The substrate support 106 includes a support face that supports the substrate 102. The plurality of upper heat sources 141 are disposed between the upper window and a lid 154. The plurality of upper heat sources 141 form a portion of the upper heat source module 155. The lid 154 may include a plurality of sensors disposed therein or thereon for measuring the temperature within the processing chamber 100. The plurality of lower heat sources 143 are disposed between the lower plate 110 and a floor 152. The plurality of lower heat sources 143 form a portion of a lower heat source module 145. In one or more embodiments, the upper plate 108 is an upper dome and is formed of an energy transmissive material, such as quartz. In one or more embodiments, the lower plate 110 is a lower dome and is formed of an energy transmissive material, such as quartz. A pre-heat ring 302 is disposed outwardly of the substrate support 106. A stop 304 includes a plurality of arms44025930W001305a, 305b that each include a lift pin stop on which at least one of the lift pins 132 can rest when the substrate support 106 is lowered (e.g., lowered from a process position to a transfer position).

[0041] The internal volume has the substrate support 106 disposed therein. The substrate support 106 includes a top surface on which the substrate 102 is disposed. The substrate support 106 is attached to a shaft 118. The shaft 118 is connected to a motion assembly 121. The motion assembly 121 includes one or more actuators and / or adjustment devices that provide movement and / or adjustment for the shaft 118 and / or the substrate support 106.

[0042] The substrate support 106 may include lift pin perforations 107 disposed therein. The lift pin perforations 107 are sized to accommodate a lift pin 132 for lifting of the substrate 102 from the substrate support 106 either before or after a deposition process is performed.

[0043] A chamber kit 1010 includes a plate apparatus 210. The plate apparatus 210 includes an isolation plate 111 having a first outer face 1012 and a second outer face 1013 opposing the first outer face 1012. The second outer face 1013 faces the substrate support 106. The chamber body includes a first liner 1020 and a second liner 323. The second liner 323 is disposed below the first liner 1020. The pre-heat ring 302 is supported on a ledge of the second liner 323. The first liner 1020 includes a curved section 1021 (e.g., an annular section). One or more inlet openings 1023 extending to an inner surface 1024 of the curved section 1021 are on a first side of the first liner 1020, and one or more second outlet openings 1025 are on a second side of the first liner 1020. The one or more inlet openings 1023 can be between the first liner 1020 and the upper plate 108. The first liner 1020 includes one or more ledges 1022 sized and shaped to support an outer region of the plate apparatus 210.

[0044] In the embodiment shown in Figure 1, a lowermost end of the plate apparatus 210 is aligned above a lowermost end of the first liner 1020. In one or more embodiments, as shown in Figure 1 , the lowermost end of the plate apparatus 210 is part of the second outer face 1013, and the lowermost end of the first liner 1020 is part of an extension.44025930W001

[0045] At least part of the plate apparatus 210 is in the shape of a disc, and at least part of the curved section 1021 is in the shape of a ring. It is contemplated, however, that the plate apparatus 210 and / or the curved section 1021 can be in the shape of a rectangle, or other geometric shapes. The plate apparatus 210 at least partially fluidly isolates an upper portion 136b of an internal volume from a lower portion 136a of the internal volume. The lower portion 136a is a processing volume. The plate apparatus 210 at least partially defines the processing volume between the plate apparatus 210 and the substrate support 106.

[0046] In one or more embodiments, the isolation plate 111 is omitted, and the processing volume spans the open space between the substrate 102 and the upper plate 108.

[0047] The flow module 112 (which can define at least part of one or more sidewalls of the processing chamber 1000) includes one or more first gas inlets 1014 in fluid communication with the lower portion 136a (e.g., the processing volume) of the internal volume. The flow module 112 includes one or more second inlet openings 1015 in fluid communication with the upper portion 136b of the internal volume. The one or more first gas inlets 1014 are in fluid communication with one or more flow gaps between the first liner 1020 and the second liner 323. One or more inject blocks 1026 having one or more flow openings formed therein can be disposed in one or more flow gaps between the first liner 1020 and the second liner 323. The one or more second inlet openings 1015 are in fluid communication with the one or more inlet openings 1023 above the first liner 1020. The first gas inlets 1014 are fluidly connected to one or more process gas sources 151 and one or more cleaning gas sources 153. The purge gas inlet(s) 164 are fluidly connected to one or more purge gas sources 162. The one or more gas exhaust outlets 116 are fluidly connected to an exhaust pump 157. One or more process gases supplied using the one or more process gas sources 151 can include one or more reactive gases (such as one or more of silicon-containing, phosphorus-containing, and / or germanium-containing gases, and / or one or more carrier gases (such as one or more of nitrogen (N2) and / or hydrogen (H2)). One or more purge gases44025930W001supplied using the one or more purge gas sources 162 can include one or more inert gases (such as one or more of argon (Ar), helium (He), and / or nitrogen (N2)). One or more cleaning gases and / or etching gases supplied using the one or more cleaning gas sources 153 can include one or more of hydrogen and / or chlorine (such as hydrochloric acid (HCI)). In one or more embodiments, the one or more process gases include silicon hydrides (such as one or more silanes and / or one or more halogenated silanes, for example one or more chlorinated silanes), germanium, germanium hydrides (such as germane (GeH4) or digermane (Ge2He)), halogenated germanes (such as chlorinated germanes), Group III dopant(s) (such as boron-containing gases for example diborane (B2H6)), and / or Group V dopant(s) such as phosphine (PH3) or arsine (ASH3).

[0048] The one or more gas exhaust outlets 116 are further connected to or include an exhaust system 178. The exhaust system 178 fluidly connects the one or more gas exhaust outlets 116 and the exhaust pump 157. The exhaust system 178 can assist in the controlled deposition of a layer on the substrate 102. The exhaust system 178 is disposed on an opposite side of the processing chamber 100 relative to the flow module 112.

[0049] During a deposition operation (e.g., an epitaxial growth operation), the one or more process gases P1 flow through the one or more first gas inlets 1014, through the one or more gaps, and into the lower portion 136a to flow horizontally over the substrate support 106 and the substrate 102 and to the one or more gas exhaust outlets 116. During the deposition operation, one or more purge gases P2 flow through the one or more second inlet openings 1015, through the one or more inlet openings 1023 of the first liner 1020, and into the upper portion 136b. The one or more purge gases P2 flow simultaneously with the flowing of the one or more process gases P1. The flowing of the one or more purge gases P2 through the upper portion 136b facilitates reducing or preventing flow of the one or more process gases P1 into the upper portion 136b that would contaminate the upper portion 136b. The one or more process gases P1 are exhausted through exhaust gaps between the first liner 1020 and the second liner 323, and through the one or more gas exhaust outlets 116.44025930W001The one or more purge gases P2 are exhausted through the one or more second outlet openings 1025, through the same exhaust gaps between the first liner 1020 and the second liner 323, and through the same one or more gas exhaust outlets 116 as the one or more process gases P1. The present disclosure contemplates that that one or more purge gases P2 can be separately exhausted through one or more second gas exhaust outlets that are separate from the one or more gas exhaust outlets 116.

[0050] The present disclosure also contemplates that one or more purge gases can be supplied to the purge volume 138 (through the plurality of purge gas inlets 164) during the deposition operation, and exhausted from the purge volume 138.

[0051] The controller 190 generally includes a central processing unit (CPU) 191, memory 192, and support circuits 193. The CPU 191 may be one of any form of a general purpose processor that can be used in an industrial setting. The memory 192, or non-transitory computer-readable medium, is accessible by the CPU 191 and may be one or more of memory such as read only memory (ROM) (e.g., electrically erasable programmable read-only memory (EEPROM)), flash memory (e.g., flash drive), floppy disk, hard disk, random access memory (RAM) (e.g., non-volatile random access memory (NVRAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)), or any other form of digital storage, local or remote. The support circuits 193 are coupled to the CPU 191 and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein (such as the method 200, the method 500, the method 700, the method 1100, and / or the method 1300) may generally be implemented under the control of the CPU 191 by the CPU 191 executing computer instruction code stored in the memory 192 (or in memory of a particular processing chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 191, the CPU 191 controls the chambers to perform processes in accordance with the various methods.44025930W001

[0052] The instructions stored in the memory 192 of the controller 190 can include one or more machine learning / artificial intelligence algorithms that can be executed in addition to the operations described herein. As an example, a machine learning / artificial intelligence algorithm executed by the controller 190 can generate, prioritize, accept, and / or reject signal profiles and / or data (such as metrology data and / or substrate map data) used in relation to the method 200. The machine learning / artificial intelligence algorithm can account for previous operational runs to monitor and update the signal profiles and / or data. The machine learning / artificial intelligence algorithm can optimize process parameter(s) of process recipes. The one or more machine learning / artificial intelligence algorithms can use, for example, a regression model (such as a linear regression model) or a clustering technique to estimate optimized parameters and / or optimized values for signal profiles and / or data. As an example, the one or more machine learning / artificial intelligence algorithms can optimize the exemplary parameter values described herein (such as the method 200). The algorithm(s) can be unsupervised or supervised. In one or more embodiments, the controller 190 automatically conducts the operations described herein without the use of one or more machine learning / artificial intelligence algorithms. In one or more embodiments, the controller 190 compares measurements to data in a look-up table and / or a library to optimize process parameters. The controller 190 can store measurements as data in the look-up table and / or the library.

[0053] Figure 2 is a schematic block diagram view of a method 200 of substrate processing, according to one or more embodiments.

[0054] Optional operation 202 includes positioning a substrate on a substrate support in a processing volume of a processing chamber. The positioning can include moving the substrate into the processing volume, such as through a slit valve or another opening. In one or more embodiments, the positioning includes moving a substrate support and / or a plurality of lift pins relative to each other to land the substrate on the substrate support.

[0055] Optional operation 204 of the method 200 includes heating the substrate support and / or the substrate in the processing volume to a target44025930W001temperature. One or more heat sources (such as heat sources 141, 143 in Figure 1) can emit energy (such as radiation) that is absorbed for example by the substrate support 106. The absorbed energy of the substrate support 106 can heat the substrate supported thereon.

[0056] Operation 206 includes forming an amorphous liner on a structure on a substrate. The amorphous liner includes silicon, and the forming including a formation temperature. For example, the formation temperature can be set for the forming (e.g., deposition) of the amorphous liner. The forming includes flowing a deposition precursor. The deposition precursor includes silicon. For example, the deposition precursor can include one or more silanes. Other materials are contemplated for the deposition precursor. In one or more embodiments, the amorphous liner is formed at a pressure less than 100 Torr, such as within a range of 35 Torr to 45 Torr, for example about 40 Torr. Other pressure values are contemplated. In one or more embodiments, the deposition precursor includes silicon and / or phosphorus, such as to form silicon film or silicon phosphorus (SiP) film. In one or more embodiments, the deposition precursor includes silicon, germanium, and / or boron, such as to form silicon-germanium-boron (SiGeB) film.

[0057] The formed amorphous liner can include a promotion material that promotes the crystallization in operation 208. The present disclosure contemplates that operation 208 can occur subsequently to operation 206 such that the promotion material can be included during the forming of the liner in operation 206, and the promotion material can promote subsequent crystallization in operation 208. In one or more embodiments, the promotion material includes one or more of: germanium, gallium, tin, or arsenic. An atomic percentage of the promotion material in the amorphous liner is 10% or less. In one or more embodiments, the atomic percentage is 5% or less, such as 2% or less. In one or more embodiments, n-EPI deposition is conducted, and the atomic percentage of the germanium in the amorphous liner is 10% or less. In one or more embodiments, p-EPI deposition is conducted, and the atomic percentage of the germanium in the amorphous liner is within a range of 5% to 30%.44025930W001

[0058] Operation 208 includes annealing the amorphous liner to crystallize the amorphous liner into a crystalline liner. In one or more embodiments, the annealing includes (at optional operation 209) ramping the formation temperature to an anneal temperature at a ramp rate. The ramp rate is less than 5.0 degrees Celsius-per-second, such as 3.0 degrees Celsius-per-second or less. In one or more embodiments, the ramp rate is less than 1.0 degrees Celsius-per-second. In one or more embodiments, the ramp rate is within a range of 0.1 degrees Celsius-per-second to 0.5 degrees Celsius-per-second. In one or more embodiments, the annealing includes (at optional operation 211 ) soaking the amorphous liner at the anneal temperature after the formation temperature is ramped to the anneal temperature. As an example, the soaking can include maintaining the anneal temperature for a time period to bake the liner. For example, operation 209 can include ramping the temperature until the anneal temperature is reached, and then the anneal temperature is maintained for the time period at operation 211.

[0059] The anneal temperature is higher than the formation temperature. The formation temperature is less than 500 degrees Celsius, and the anneal temperature is greater than 650 degrees Celsius. In one or more embodiments, the formation temperature 400 degrees Celsius or less, such as 100 degrees Celsius to 400 degrees Celsius. In one or more embodiments, the anneal temperature is within a range of 650 degrees Celsius to 850 degrees Celsius, such as about 700 degrees Celsius.

[0060] Optional operation 212 incudes doping the crystallized liner with a dopant material. In one or more embodiments, the doping is conducted after the annealing of operation 208. In one or more embodiments, the doping is conducted before and / or after the annealing of operation 208. For example, the doping of operation 212 can be conducted during the formation of the liner in operation 206. The dopant material includes one or more Group III and / or Group V elements. In one or more embodiments, the dopant material includes phosphorus and / or boron. Other elements are contemplated for the dopant material.44025930W001

[0061] Optional operation 214 includes removing liner material. In one or more embodiments, the liner material is removed from a plurality of cap layers of the structure. In one or more embodiments, the removing can include etching, such as a halide etch. An etch material can include, for example, hydrochloric acid (HCI), boron trichloride (BCh), and / or chlorine gas (CI2). Other etch materials are contemplated. The liner material that is removed can be amorphous liner material that is not crystallized in operation 208. For example, the liner material that is removed can be liner material that remains amorphous after the annealing of operation 208 The liner material can be removed from materials of the substrate that are dielectric.

[0062] Operation 216 includes forming source and drain material on the crystalline liner. The forming can include flowing a source and drain precursor, such as a precursor that includes one or more silanes. The source and drain material is a crystalline semiconductor, such as a crystalline silicon.

[0063] Figures 3A-3D are schematic partial cross-sectional views of the method 200 conducted in relation to a semiconductor device structure 300, according to one or more embodiments. The semiconductor device structure 300 can be made, for example, using the processing chamber 1000 described herein.

[0064] The structure 300 includes stacks 310 formed on a silicon substrate 301. The stacks 310 include first composition layers 312 and second composition layers 311 disposed in an alternating arrangement, and a cap layer 315. A plurality of spacers 313 are disposed on both sides of the respective second composition layers 311. Using subject matter described herein, it is believed that the flatness, uniformity, and / or selectivity of the structure 300 can be enhanced. As an example, the flatness of recessed surfaces 303 between the stacks 310 and / or the flatness of outer surfaces of the spacers 313 and / or the first composition layers 312 can be enhanced. As another example, the merging of the stacks 310 can be controlled and / or prevented. As a further example, a source and drain material is formed with increased strain to facilitate enhanced device performance properties (such as contact resistance and / or mobility). In one or more embodiments, the second composition layers 311 are44025930W001silicon germanium (SiGe) layers, the first composition layers 312 are silicon (Si) layers, and the spacers 313 are silicon nitride (SiN) spacers. In one or more embodiments, the second composition layers 311 are dielectric (e.g., SiN) layers, and the first composition layers 312 are Si layers. The second composition layers 311 and the spacers 313 can be formed of the same or different composition.

[0065] At Figure 3A, an amorphous liner 321 is formed in the trenches between stacks 310. The amorphous liner 321 can be formed on a dielectric bottom layer 307 (such as a silicon channel).

[0066] At Figure 3B, sections of the amorphous liner 321 are crystallized into a crystalline liner 421, with sections remaining as amorphous liner material 423 on cap layers 315.

[0067] At Figure 3C, the amorphous liner material 423 is etched to be removed from the cap layers 315.

[0068] At Figure 3D, a source and drain material 425 is formed within the crystalline liner 421 to fill in the trench.

[0069] The crystalline liner 421 is formed on inner surfaces of a plurality of recesses of the structure 300, and the crystalline liner 421 lines a plurality of stacks (e.g., the stacks 310) of the structure 300. The recesses are defined between the stacks 310. In one or more embodiments, the crystalline liner 421 lines the first composition layers 312 and the spacers 313. In one or more embodiments, the crystalline liner 421 has a tensile strain of 0.4% or higher prior to fill of the source and drain material 425, such as 0.4% to 0.6% or higher. In one or more embodiments, the source and drain material 425 has a compressive strain. The compressive strain is within a range of 0 to 1.5%, or higher. Other values and ranges are contemplated for the strain of the liner 421 and the strain of the source and drain material 425. The formed crystalline liner 421 has a thickness T1 that is less than 10 nm. In one or more embodiments, the thickness T1 is 5 nm or less. After annealing, the liner 421 enhances coverage on the spacers 313 to facilitate an enhanced starting surface for recess fill using the source and drain material 425.44025930W001

[0005] FIG. 4 illustrates one example of a nanostructure field-effect transistor (nano-FET) 400 in a three-dimensional view in according to one or more embodiments. The nano-FET 400 includes nanostructures 420, for example, nanosheets, nanowire, or the like, formed over fin structures 430 on a substrate 410, for example, a semiconductor substrate, wherein the nanostructures 420 act as channel regions for the nano-FET. The nanostructure 420 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 440 are disposed between adjacent fin structures 430, which may protrude above and from between neighboring isolation regions 440. Although the isolation regions 440 are described / illustrated as being separate from the substrate 410, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although a bottom portion of the fin structures 430 are illustrated as being single, continuous materials with the substrate 410, the bottom portion of the fin structures 430 and / or the substrate 410 may include a single material or a plurality of materials. In this context, the fin structures 430 refer to the portion extending between the neighboring isolation regions 440.

[0006] Gate dielectric layers 460 are over top surfaces of the fin structures 430 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 420. Gate electrodes 470 are over the gate dielectric layers 460. Epitaxial source / drain regions 450 are disposed on the fin structures 430 on opposing sides of the gate dielectric layers 460 and the gate electrodes 470. Source / drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

[0007] Embodiments discussed herein can be applicable to nano-FETs formed using a gate-last process and nano-FETs formed using a gate-first process. Also, embodiments contemplate aspects used in planar devices, such as planar FETs or in fin field-effect transistors (FinFETs).

[0008] FIG. 5 illustrates an exemplary flow chart of a method 500 of forming a nano-FET structure, according to one or more embodiments.44025930W001

[0009] FIGS. 6A-6F illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments. With reference to FIGS. 6A-6F, schematic views of embodiments of a nano-FET structure at various stages of manufacture are provided to illustrate the method of FIG. 5. Although FIGS. 6A-6F are described in relation to the method 500, it will be appreciated that the structures disclosed in FIGS. 6A-6F are not limited to the method 500, but instead may stand alone as structures independent of the method 500. Similarly, although the method 500 is described in relation to FIGS. 6A-6F, it will be appreciated that the method 500 is not limited to the structures disclosed in FIGS. 6A-6F, but instead may stand alone independent of the structures disclosed in FIGS. 6A-6F. The method 500 may be used to form portions of the nano-FET 400 depicted in FIG. 4.

[0010] Referring to FIG. 6A, at operation 510 a semiconductor device structure 600 having a source / drain cavity 608 is provided. The semiconductor device structure 600 may be or be part of a multi-gate device with three-dimensional architecture, such as fin based semiconductor devices including nano-FETs and gate-all-around (GAA) transistor devices. The semiconductor device structure 600 includes a first semiconductor region 602 also referred to as a first fin structure and a second semiconductor region 604 also referred to as a second fin structure formed on a substrate 606. The first semiconductor region 602 and the second semiconductor region 604 are separated by a feature, such as the source / drain cavity 608, which exposes the substrate 606. In one or more embodiments, as is shown in FIG. 6A, a portion of the source / drain cavity 608 extends into the substrate 606.

[0011] As shown in FIG. 6A, the first semiconductor region 602 and the second semiconductor region 604 each include a plurality of alternating semiconductor layers 609. The plurality of alternating semiconductor layers 609 include first semiconductor layers 610A-C and second semiconductor layers 612A-C that are alternately and repeatedly stacked on the substrate 606. Although the example shown in FIG. 6A shows three pairs, each pair including the first semiconductor layer 610A-C and the second semiconductor layer 612A-C, the number of pairs may be varied based on different process needs44025930W001with or without the first semiconductor layers 610A-C and the second semiconductor layers 612A-C being needed. The first semiconductor layers 61 OA-C are formed of a first material having etch selectivity to a second material of which the second semiconductor layers 612A-C are formed, for example, an etch rate of the first material is higher than an etch rate of the second material. The etch selectivity, a ratio of the etch rate of the first material to the etch rate of the second material, is between about 10:1 to 200:1. Example combinations of the first material and the second material include silicon-germanium (SiGe)Zsilicon (Si), silicon-germanium (SiGe) / germanium (Ge), and germanium tin (GeSn)Zsilicon (Si). In one or more embodiments, the first semiconductor layers 61 OA-C are or include SiGe and the second semiconductor layers 612A-C are or include silicon, for example, crystalline silicon. The second semiconductor layers 612A-C may serve as channels having a width of between several nanometers and several tens of nanometers. The first semiconductor layers 61 OA-C and the second semiconductor layers 612A-C can be nanostructures, for example, nanowires or nanosheets.

[0012] The first semiconductor layers 61 OA-C and the second semiconductor layers 612A-C may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the sourceZdrain cavity 308 is formed by a patterning technique, such as lithography followed by an etch or ashing process. The first semiconductor layers 61 OA-C and the second semiconductor layers 612A-C may each have thickness of between about 1 nm and about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layers 61 OA-C may be performed by any appropriate etch process, such as a dry plasma etch process.

[0013] The semiconductor device structure 600 further includes a dummy gate structure 620 formed over at least a portion of each of the first semiconductor region 602 and the second semiconductor region 604. The dummy gate structure 620 includes a dummy gate 622. The dummy gate 622 may be a conductive or nonconductive material and may be selected from amorphous silicon, doped or undoped polycrystalline silicon (polysilicon),44025930W001polycrystalline silicon-germanium (poly-SiGe), silicon oxide, metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate 622 may be formed using any suitable techniques such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), CVD, ALD, or the like. The dummy gate 622 includes a top surface 622t, which defines a top surface of the semiconductor device structure 600.

[0014] The dummy gate structure 620 may further includes a dummy gate dielectric layer 624 formed on or over the alternating semiconductor layers 609, for example, on or over the first semiconductor layer 610C. The dummy gate 622 is formed on or over the dummy gate dielectric layer 624 with the dummy gate dielectric layer 624 formed in between the alternating semiconductor layers 609 and the dummy gate 622 such that the dummy gate dielectric layer 624 separates the dummy gate 622 from the alternating semiconductor layers 609. The dummy gate dielectric layer 624 protects the underlying alternating semiconductor layers 609 during subsequent removal of the dummy gate 622. The dummy gate dielectric layer 624 may be formed of any suitable oxide, for example, silicon oxycarbonitride, silicon oxide, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0015] The dummy gate structure 620 may further include one or more spacers 626. The spacer 626 may function as a spacer for forming self-aligned source / drain regions. The spacer 626 may be formed along the sidewalls of the dummy gate 622 and the dummy gate dielectric layer 624. The spacer 626 may be formed of silicon oxycarbonitride, silicon oxide, silicon nitride, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0016] The dummy gate structure 620 may further include a capping layer 670 (See FIG. 6D). The capping layer 670 may be or include a dielectric material. The capping layer 670 can be formed from the same material as the spacer 626. The capping layer 670 can be formed from a material that is different from the material of the spacer 626.44025930W001

[0017] The substrate 606 has a frontside 606f (also referred to as a front surface) and a backside 606b opposite the frontside 606f. The substrate 606 may be a material such as crystalline silicon (e.g., Si< 100> or Si< 111 >), silicon oxide, strained silicon, silicon-germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. In one or more embodiments, the substrate 606 is or includes crystalline silicon.

[0018] The source / drain cavity 608 is defined by a pair of opposing sidewalls 608s and a bottom surface 608b. The sidewalls 608s may be defined by the dummy gate structure 620 and the alternating pairs of the first semiconductor layers 610A-C and the second semiconductor layers 612A-C. The bottom surface 608b of the source / drain cavity 608 is defined by the substrate 606.

[0019] Referring to FIG. 6B, at operation 520, an inner cavity recess process may be performed. As shown in FIG. 6B, portions of the sidewalls 608s of the plurality of alternating semiconductor layers 609 formed of the first semiconductor layers 610A-C exposed by the source / drain cavity 608 are etched to form sidewall recesses 630A-C along the sidewalls 608s. Although sidewalls of the first semiconductor layers 610A-C in the sidewall recesses 630A-C are illustrated as being straight in FIG. 6B, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In one or more embodiments in which the first semiconductor layers 610A-C include, for example, SiGe, and the second semiconductor layers 612A-C include, for example, Si or SiC, a wet etch process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NF OH), or the like may be used to etch the sidewalls of the first semiconductor layers 610A-C.

[0020] Referring to FIG. 6C, at operation 530, inner spacer layers are formed. As shown in FIG. 6C, first inner spacers 632A-C are formed in the sidewall recess 630A-C. The first inner spacers 632A-C may be formed by depositing an inner spacer layer (not separately illustrated) over the structure illustrated in FIG. 6B. The first inner spacers 632A-C act as isolation features44025930W001between subsequently formed source / drain regions and a gate structure. As will be discussed in greater detail below, source / drain regions will be formed in the source / drain cavity 608, while the first semiconductor layers 610A-C in the n-type region and in the p-type region (not shown) will be replaced with corresponding gate structures.

[0021] The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may be or include a material such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The inner spacer layer may then be anisotropically etched to form the first inner spacers 632A-C. Although outer sidewalls of the first inner spacers 632A-C are illustrated as being flush with sidewalls of the second semiconductor layers 612A-C in the n-type region shown in FIG. 6C and in the p-type region (not shown), the outer sidewalls of the first inner spacers 632A-C may extend beyond or be recessed from sidewalls of the second semiconductor layers 612A-C and / or the first inner spacers 632A-C, respectively.

[0022] Moreover, although the outer sidewalls of the first inner spacers 632A-C are illustrated as being straight in FIG. 6C, the outer sidewalls of the first inner spacers 632A-C may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process, such as reactive ion etching (RIE) or the like. The first inner spacers 632A-C may be used to prevent damage to the subsequently formed source / drain region, for example, the source / drain region 680 discussed below with respect to FIG. 6J, by subsequent etching processes, such as etching processes used to form gate structures.

[0023] The first inner spacers 632A-C may be formed of dielectric material, such as silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN). In one or more embodiments, the first inner spacers 632A-C are formed from the same material as the spacer 626. For example, both the first inner spacers 632A-C and the spacer 626 are formed from silicon oxycarbonitride. In one or more embodiments, the first44025930W001inner spacers 632A-C are formed from a material that is different from the material of the spacer 626.

[0024] Referring to FIG. 6D, at operation 540, a non-conformal L1 liner 640 may be formed. The non-conformal L1 liner 640 is selectively grown on the exposed silicon-containing surfaces, for example, the sidewalls of the second semiconductor layers 612A-C and the bottom surface 608b of the recess defined by the substrate 606 relative to the dielectric surfaces of the inner spacers 632A-C. The composition of the non-conformal L1 liner 640 can depend on the conductivity type of the semiconductor device structure 600. If the semiconductor device structure 600 is an n-type structure, non-conformal L1 liner 640 can include silicon (Si) doped with an n-type dopant such as phosphorous or arsenic. If the semiconductor device structure 600 is a p-type structure, non-conformal L1 liner 640 can include silicon germanium (SiGe) doped with a p-type dopant, such as boron or gallium. The non-conformal L1 liner 640 may be epitaxially and selectively formed from the exposed sidewall surfaces 608s of the second semiconductor layers 612A-C and the bottom surface 608b, which is defined by the substrate 606. Suitable epitaxial processes include vapor-phase epitaxial (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), low pressure CVD (LPCVD), plasma epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous precursors, which interact with the material of the substrate 606 and the second semiconductor layers 612A-C.

[0025] Referring to FIG. 6E, at operation 550, a conformal L2 liner 650 is formed. The conformal L2 liner 650 covers the sidewalls 608s conformally despite the presence of the inner spacers 632A-C. The conformal L2 liner 650 covers the inner spacers 632A-C can also cover the knuckles 642 generated by the nonconformal L1 liner 640 to provide a smooth surface for subsequent filling of the source drain cavity 608. The composition of the conformal L2 liner 650 can depend on the conductivity type of the semiconductor device structure 600. If the semiconductor device structure 600 is an n-type structure, the conformal L2 liner 650 can include silicon (Si) doped with an n-type dopant such as phosphorous or arsenic. If the semiconductor device structure 600 is a p-44025930W001type structure, the conformal L2 liner 650 can include silicon germanium (SiGe) doped with a p-type dopant, such as boron or gallium. The conformal L2 liner 650 may be epitaxially grown on the exposed surfaces of the inner spacers 632A-C and optionally the exposed sidewall surfaces 608s of the second semiconductor layers 612A-C and the bottom surface 608b (if the nonconformal L1 liner 640 is not present), which is defined by the substrate 606. Suitable epitaxial processes include vapor-phase epitaxial (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), low pressure CVD (LPCVD), plasma epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous precursors, which interact with the material of the substrate 606 and the second semiconductor layers 612A-C. The flow rates of the gaseous precursor used to form the conformal L2 liner 650 may be lower than the flow rates used for typical epitaxially grown S / D materials. Not to be bound by theory but it is believed that the lower flow rates lead to lower growth rates of the epitaxial material, which enables epitaxial growth on the dielectric surfaces of the inner spacers.

[0026] Referring to FIG. 6F, at operation 560, a source / drain region 660 is formed in the source / drain cavity 608. The source / drain region 660 fills the source / drain cavity 608 in between the first semiconductor region 602 and the second semiconductor region 604. In one or more embodiments, as shown in FIG. 6F, the source / drain region 660 is formed on the conformal L2 liner 650.

[0027] The source / drain region 660 may be formed via an epitaxial deposition process. The use of an epitaxially grown material in the source / drain region 660 allows the source / drain region 660 to exert stress in the channel regions. The materials used for the source / drain region 660 may be varied for the n-type and p-type nano-FETs, such that one type of material is used for the n-type nano-FETs to exert a tensile stress in the channel region and another type of material for the p-type nano-FETs to exert a compressive stress. For example, SiP or SiC may be used to form n-type nano-FETs and SiGe or Ge may be used to form p-type nano-FETs. However, any suitable material may be used. The source / drain region 660 may be doped either through an implanting process to implant appropriate dopants, or by in-situ doping as the44025930W001material is grown. In one or more embodiments, the source / drain region 660 is formed of SiC or SiP doped with phosphorus (P) to form an n-type nano-FET device. In one or more embodiments, the source / drain region 660 is formed of SiGe or Ge doped with boron (B) to form a p-type nano-FET device.

[0028] After deposition of the source / drain features 660, an anneal process may be performed to activate the source / drain features 660. In one or more embodiments, the anneal process may include a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. The anneal process may include a peak anneal temperature in a range from about 900 degrees Celsius and about 1000 degrees Celsius. In one or more embodiments, the peak anneal temperature may be maintained for a duration measured by seconds or microseconds. Through the anneal process, a desired electronic contribution of the p-type dopant in the semiconductor host, such as silicon germanium (SiGe) or germanium (Ge), may be obtained. The anneal process may generate vacancies that facilitate movement of the p-type dopant from interstitial sites to substitutional lattice sites and reduce damage or defects in the lattice of the semiconductor host.

[0029] FIG. 7 illustrates an exemplary flow chart of a method 700 of forming a nano-FET structure, according to one or more embodiments. FIGS. 8A-8E illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments. With reference to FIGS. 8A-8E, schematic views of embodiments of a nano-FET structure at various stages of manufacture are provided to illustrate the method of FIG. 7. Although FIGS.8A-8E are described in relation to the method 700, it will be appreciated that the structures disclosed in FIGS. 8A-8E are not limited to the method 700, but instead may stand alone as structures independent of the method 700. Similarly, although the method 700 is described in relation to FIGS. 8A-8E, it will be appreciated that the method 700 is not limited to the structures disclosed in FIGS. 8A-8E, but instead may stand alone independent of the structures disclosed in FIGS. 8A-8E. The method 700 may be used to form portions of the nano-FET 400 depicted in FIG. 4.44025930W001

[0030] Referring to FIG. 8A, at operation 710 a semiconductor device structure 800 having a source / drain cavity 608 is provided. The semiconductor device structure 800 is similar to the semiconductor device structure 600.

[0031] Optionally, at operation 720, an inner cavity recess may be performed. The inner cavity recess is performed similarly to the inner cavity recess described at operation 520.

[0032] Referring to FIG. 8B, at operation 730, a raised inner spacer 832A-C is formed. The raised inner spacer 832A-C extends past the sidewall surfaces 608s. In one or more embodiments where the inner cavity recess is performed, the raised inner spacer 832A-C fills the inner cavity recess and extends past the sidewall surfaces. In one or more embodiments where the inner cavity recess is not present, the raised inner spacers are selectively formed on the exposed surfaces of the first semiconductor layers 610A-C. The raised inner spacer 632A-C can be formed similarly to the inner spacers 632A-C described at operation 530.

[0033] Referring to FIG. 8C, optionally, at operation 740, a nonconformal L1 liner 840 can be formed. The non-conformal L1 liner 840 is selectively grown on the exposed silicon-containing surfaces, for example, the sidewalls of the second semiconductor layers 612A-C and the bottom surface 608b of the recess defined by the substrate 606 relative to the dielectric surfaces of the raised inner spacers 832A-C. The composition of the non-conformal L1 liner 840 can depend on the conductivity type of the semiconductor device structure 600. If the semiconductor device structure 600 is an n-type structure, non-conformal L1 liner 840 can include silicon (Si) doped with an n-type dopant such as phosphorous or arsenic. If the semiconductor device structure 600 is a p-type structure, non-conformal L1 liner 840 can include silicon germanium (SiGe) doped with a p-type dopant, such as boron or gallium. The non-conformal L1 liner 840 may be epitaxially and selectively formed from the exposed sidewall surfaces 608s of the second semiconductor layers 612A-C and the bottom surface 608b, which is defined by the substrate 606. Suitable epitaxial processes include vapor-phase epitaxial (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), low pressure CVD (LPCVD),44025930W001plasma epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous precursors, which interact with the material of the substrate 606 and the second semiconductor layers 612A-C.

[0034] Referring to FIG. 8D, at operation 750, a conformal L2 liner 850 is formed. The conformal L2 liner 850 covers the sidewalls 608s conformally despite the presence of the raised inner spacers 832A-C. The conformal L2 liner 850 covers the raised inner spacers 832A-C can also cover the knuckles 842 generated by the nonconformal L1 liner 640 to provide a smooth surface for subsequent filling of the source drain cavity 608. The composition of the conformal L2 liner 850 can depend on the conductivity type of the semiconductor device structure 600. If the semiconductor device structure 600 is an n-type structure, the conformal L2 liner 850 can include silicon (Si) doped with an n-type dopant such as phosphorous or arsenic. If the semiconductor device structure 600 is a p-type structure, the conformal L2 liner 850 can include silicon germanium (SiGe) doped with a p-type dopant, such as boron or gallium. The conformal L2 liner 850 may be epitaxially grown on the exposed surfaces of the raised inner spacers 832A-C and optionally the exposed sidewall surfaces 608s of the second semiconductor layers 612A-C and the bottom surface 608b (if the nonconformal L1 liner 640 is not present), which is defined by the substrate 606. Suitable epitaxial processes include vapor-phase epitaxial (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), low pressure CVD (LPCVD), plasma epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous precursors, which interact with the material of the substrate 606 and the second semiconductor layers 612A-C. The flow rates of the gaseous precursor used to form the conformal L2 liner 850 may be lower than the flow rates used for typical epitaxially grown S / D materials. Not to be bound by theory but it is believed that the lower flow rates lead to lower growth rates of the epitaxial material, which enables epitaxial growth on the dielectric surfaces of the inner spacers.

[0035] Referring to FIG. 8E, at operation 760, a source / drain region 860 is formed in the source / drain cavity 608. The source / drain region 860 fills the source / drain cavity 608 in between the first semiconductor region 602 and the44025930W001second semiconductor region 604. In one or more embodiments, as shown in FIG. 8E, the source / drain region 860 is formed on the conformal L2 liner 850.

[0036] The source / drain region 860 may be formed via an epitaxial deposition process. The use of an epitaxially grown material in the source / drain region 860 allows the source / drain region 860 to exert stress in the channel regions. The materials used for the source / drain region 860 may be varied for the n-type and p-type nano-FETs, such that one type of material is used for the n-type nano-FETs to exert a tensile stress in the channel region and another type of material for the p-type nano-FETs to exert a compressive stress. For example, SiP or SiC may be used to form n-type nano-FETs and SiGe or Ge may be used to form p-type nano-FETs. However, any suitable material may be used. The source / drain region 860 may be doped either through an implanting process to implant appropriate dopants, or by in-situ doping as the material is grown. In one or more embodiments, the source / drain region 860 is formed of SiC or SiP doped with phosphorus (P) to form an n-type nano-FET device. In one or more embodiments, the source / drain region 660 is formed of SiGe or Ge doped with boron (B) to form a p-type nano-FET device.

[0037] After deposition of the source / drain features 860, an anneal process may be performed to activate the source / drain features 860. In one or more embodiments, the anneal process may include a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. The anneal process may include a peak anneal temperature in a range from about 900 degrees Celsius and about 1000 degrees Celsius. In such an embodiment, the peak anneal temperature may be maintained for a duration measured by seconds or microseconds. Through the anneal process, a desired electronic contribution of the p-type dopant in the semiconductor host, such as silicon germanium (SiGe) or germanium (Ge), may be obtained. The anneal process may generate vacancies that facilitate movement of the p-type dopant from interstitial sites to substitutional lattice sites and reduce damage or defects in the lattice of the semiconductor host.

[0038] FIG. 9 illustrates a plan view of a cluster tool 900, according to one or more embodiments. The cluster tool 900 may be used to perform various44025930W001operations of the method 500 or the method 700. The cluster tool 900 features at least one material deposition chamber, for example, a plasma-enhanced chemical vapor deposition (PECVD) chamber and optionally an epitaxial deposition chamber. The epitaxial deposition chamber may be a plasma-enhanced epitaxial deposition chamber. One example of the cluster tool 900 is the CENTURA® EPI system available from Applied Materials, Inc., of Santa Clara, California. Cluster tools manufactured by others may be used as well. A transfer robot 904 of any convenient type is disposed in a transfer chamber 902 of the cluster tool 900. A load-lock 906, with two load-lock chambers 906A, 906B is coupled to the transfer chamber 902. A plurality of processing chambers 908, 910, 912, 914, and 916 are also coupled to the transfer chamber 702. In at least one aspect, the plurality of processing chambers 908, 910, 912, 914, and 916 includes at least one of a pre-clean chamber, a material deposition chamber such as an epitaxial deposition chamber, a plasma-enhanced chemical vapor deposition chamber, and a thermal processing chamber, such as an anneal, degas, or oxidation chamber.

[0039] Processing chamber 908 may be a pre-clean chamber configured to clean the substrate prior to material deposition of materials, for example, a sacrificial capping layer, a source / drain material, or a superlattice structure. The pre-clean chamber may be configured to perform the Applied Materials SICONI™ Pre-clean process. Processing chamber 910 and / or 914 may be a material deposition chamber such as an epitaxial deposition chamber capable of performing an epitaxial growth process or a plasma-enhanced chemical vapor deposition process. Processing chamber 912 and / or 916 may be an additional material deposition chamber or a thermal treatment chamber capable of performing a thermal treatment process.

[0040] A system controller 957 is in communication with the transfer robot 904, and the plurality of processing chambers 908, 910, 912, 914, and 916. The system controller 957 can be any suitable component that can control the processing chambers and robots. For example, the system controller 957 can be a computer including a central processing unit (CPU) 992, memory 994, inputs / outputs 996, suitable circuits 998, and storage.44025930W001

[0041] Processes, for example, one or more of operations 510-560 or one or more of operations 710-760, may generally be stored in the memory of the system controller 957 as a software routine that, when executed by the processor, causes the process chamber to perform processes of the present disclosure. The software routine may also be stored and / or executed by a second processor that is remotely located from the hardware being controlled by the processor. Some or all of the method of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, for example, an application specific integrated circuit or other type of hardware embodiment, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general-purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed.

[0042] In one or more embodiments, the system controller 957 has a configuration to control the epitaxial growth chamber to grow epitaxial materials, for example, one or more of the source / drain feature 660 and the source / drain feature 880.

[0043] The cluster tool 900 may be used to perform at least portions of the method 500 or the method 700 described above. During processing, a substrate that is to be processed may arrive to the cluster tool 900 in a pod. The substrate is transferred from the pod to the vacuum compatible load-lock chambers 906A, 906B by the factory interface robot (not shown). The substrate is then picked by the transfer robot 904 in the transfer chamber 902, which is generally kept in a vacuum state. The transfer robot 904 then loads the substrate into the processing chamber 908 for cleaning. The transfer robot 904 then picks up the substrate from the processing chamber 908 and loads the substrate into the processing chamber 910 or 914, whichever is available, for epitaxial deposition. Epitaxial materials as described may be grown on the cleaned substrate in the processing chamber 910 or 914. The transfer robot 904 then picks up the substrate from the processing chamber 910 or 914 and transfers the substrate into the processing chamber 912 or 916, which are44025930W001thermal processing chambers, whichever is available. The epitaxial materials may then be exposed to a rapid heating / cooling process. The transfer robot 904 then picks the substrate from the processing chamber 912 or 916 and transfers the substrate to processing chamber 914 for deposition of additional materials over the epitaxial materials.

[0044] FIG. 10 illustrates a cross-sectional view of a processing chamber 1000, according to one or more embodiments. The processing chamber 1000 is adapted to perform an epitaxial (Epi) deposition process as detailed below. The processing chamber 1000 may be the processing chamber 908, 910, 912, 914, or 916 shown in FIG. 9.

[0045] The processing chamber 1000 includes a housing structure 1002 made of a process resistant material, such as aluminum or stainless steel, for example 716L stainless steel. The housing structure 1002 encloses various functioning elements of the processing chamber 1000, such as a quartz chamber 1004, which includes an upper quartz chamber 1006, and a lower quartz chamber 1008, in which a processing volume 1010 is contained. Reactive species are provided to the quartz chamber 1004 by a gas distribution assembly 1012, and processing byproducts are removed from the processing volume 1010 by an outlet port 1014, which can be in communication with a vacuum source.

[0046] A substrate support 1016 is adapted to receive a substrate 1018 that is transferred to the processing volume 1010. The substrate support 1016 is disposed along a longitudinal axis 1020 of the processing chamber 1000. The substrate support 1016 may be made of a ceramic material or a graphite material coated with a silicon material, such as silicon carbide, or other process resistant material. Reactive species from precursor reactant materials are applied to a surface 1022 of the substrate 1018, and byproducts may be subsequently removed from the surface 1022 of the substrate 1018. Heating of the substrate 1018 and / or the processing volume 1010 may be provided by radiation sources, such as upper lamp modules 1024Aand lower lamp modules 1024B.44025930W001

[0047] In one or more embodiments, the upper lamp modules 1024A and the lower lamp modules 1024B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 1024A and 1024B travels through an upper quartz window 1026 of the upper quartz chamber 1006, and through a lower quartz window 1028 of the lower quartz chamber 1008. Cooling gases for the upper quartz chamber 1006, if needed, enter through an inlet 1070 and exit through an outlet 1072. Precursor reactant materials, as well as diluent, purge and vent gases for the processing chamber 1000, enter through the gas distribution assembly 1012 and exit through the outlet port 1014. While the upper quartz window 1026 is shown as being curved or convex, the upper quartz window 1026 may be planar or concave as the pressure on both sides of the upper quartz window 1026 is substantially the same (e.g., atmospheric pressure).

[0048] The low wavelength radiation in the processing volume 1010, which is used to energize reactive species and assist in adsorption of reactants and desorption of process byproducts from the surface 1022 of the substrate 1018, typically ranges from about 0.8 pm to about 1.2 pm, for example, between about 0.95 pm to about 1.05 pm, with combinations of various wavelengths being provided, depending, for example, on the composition of the film which is being epitaxially grown.

[0049] The component gases enter the processing volume 1010 via the gas distribution assembly 1012. Gas flows from the gas distribution assembly 1012 and exits through the outlet port 1014 as shown generally by a flow path 1074. Combinations of component gases, which are used to clean / passivate a substrate surface, or to form the silicon and / or germanium-containing film that is being epitaxially grown, are typically mixed prior to entry into the processing volume 1010. The overall pressure in the processing volume 1010 may be adjusted by a valve on the outlet port 1014. At least a portion of the interior surface of the processing volume 1010 is covered by a liner 1036. In one or more embodiments, the liner 1036 comprises a quartz material that is opaque. In this manner, the chamber wall is insulated from the heat in the processing volume 1010.44025930W001

[0050] The temperature of surfaces in the processing volume 1010 may be controlled within a temperature range of about 200°C to about 600°C, or greater, by the flow of a cooling gas, which enters through the inlet 1070 and exits through the outlet 1072, in combination with radiation from the upper lamp modules 1024A positioned above the upper quartz window 1026. The temperature in the lower quartz chamber 1008 may be controlled within a temperature range of about 200°C to about 600°C or greater, by adjusting the speed of a blower unit which is not shown, and by radiation from the lower lamp modules 1024B disposed below the lower quartz chamber 1008. The pressure in the processing volume 1010 may be between about 0.1 Torr to about 600 Torr, such as between about 5 Torr to about 70 Torr.

[0051] The temperature on the surface 1022 of the substrate 1018 may be controlled by power adjustment to the lower lamp modules 1024B in the lower quartz chamber 1008, or by power adjustment to both the upper lamp modules 1024A overlying the upper quartz window 1026, and the lower lamp modules 1024B in the lower quartz chamber 1008. The power density in the processing volume 1010 may be between about 40 W / cm2to about 400 W / cm2, such as about 80 W / cm2to about 120 W / cm2.

[0052] In one aspect, the gas distribution assembly 1012 is disposed normal to, or in a radial direction 1038 relative to, the longitudinal axis 1020 of the processing chamber 1000 or the substrate 1018. In this orientation, the gas distribution assembly 1012 is adapted to flow process gases in the radial direction 1038 across, or parallel to, the surface 1022 of the substrate 1018. In one processing application, the process gases are preheated at the point of introduction to the processing chamber 1000 to initiate preheating of the gases prior to introduction to the processing volume 1010, and / or to break specific bonds in the gases. In this manner, surface reaction kinetics may be modified independently from the thermal temperature of the substrate 1018.

[0053] In operation, precursors used to form silicon (Si) and silicon germanium (SiGe) blanket or selective epitaxial films are provided to the gas distribution assembly 1012 from one or more gas sources 1040A and 1040B. IR lamps 1042 (one is shown in Fig. 10) may be utilized to heat the precursors44025930W001within the gas distribution assembly 1012 as well as along the flow path 1074. The gas sources 1040A, 1040B may be coupled the gas distribution assembly 1012 in a manner adapted to facilitate introduction zones within the gas distribution assembly 1012, such as a radial outer zone and a radial inner zone between the outer zones when viewed in from a top plan view. The gas sources 1040A, 1040B may include valves to control the rate of introduction into the zones.

[0054] The gas sources 1040A, 1040B may include silicon precursors such as silanes, including silane (SiF ), disilane (Si2He,), dichlorosilane (SibhCF), hexachlorodisilane (Si2Cle), dibromosilane (SiH2Br2), higher order silanes, derivatives thereof, and combinations thereof. The gas sources 1040A, 1040B may also include germanium containing precursors, such as germane (GeH4), digermane (Ge2He), germanium tetrachloride (GeCk), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof. The silicon and / or germanium containing precursors may be used in combination with hydrogen chloride (HCI), chlorine gas (CI2), hydrogen bromide (HBr), and combinations thereof. The gas sources 1040A, 1040B may include one or more of the silicon and germanium containing precursors in one or both of the gas sources 1040A, 1040B.

[0055] The precursor materials enter the processing volume 1010 through openings or holes 1044 (one is shown in FIG. 10) in the perforated plate 1046 in this excited state, which in one embodiment is a quartz material, having the holes 1044 formed therethrough. The perforated plate 1046 is transparent to IR energy, and may be made of a clear quartz material. In other embodiments, the perforated plate 1046 may be any material that is transparent to IR energy and is resistant to process chemistry and other processing chemistries. The energized precursor materials flow toward the processing volume 1010 through the holes 1044 in the perforated plate 1046, and through channels 1048 (one is shown in FIG. 10). A portion of the photons and non-thermal energy from the IR lamps 1042 also passes through the holes 1044, the perforated plate 1046, and channels 1048 facilitated by a reflective material and / or surface disposed on the interior surfaces of the gas distribution assembly 1012, thereby44025930W001illuminating the flow path 1074 of the precursor materials. In this manner, the vibrational energy of the precursor materials may be maintained from the point of introduction to the processing volume 1010 along the flow path.

[0005] FIG. 11 illustrates an exemplary flow chart of a method 1100 of forming a nano-FET structure, according to one or more embodiments.

[0006] FIGS. 12A-12C illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments. With reference to FIGS. 12A-12C, schematic views of embodiments of a nano-FET structure at various stages of manufacture are provided to illustrate the method of FIG. 11. Although FIGS. 12A-12C are described in relation to the method 200, it will be appreciated that the structures disclosed in FIGS. 12A-12C are not limited to the method 1100, but instead may stand alone as structures independent of the method 1100. Similarly, although the method 1100 is described in relation to FIGS. 12A-12C, it will be appreciated that the method 1100 is not limited to the structures disclosed in FIGS. 12A-12C, but instead may stand alone independent of the structures disclosed in FIGS. 12A-12C. The method 1100 may be used to form portions of the nano-FET 400 depicted in FIG. 4.

[0007] Referring to FIG. 12A, at operation 1110 a semiconductor device structure 1200 having a source / drain cavity 1208 is provided. The semiconductor device structure 1200 may be or be part of a multi-gate device with three-dimensional architecture, such as fin based semiconductor devices including nano-FETs and gate-all-around (GAA) transistor devices. The semiconductor device structure 1200 includes a first semiconductor region 1202 also referred to as a first fin structure and a second semiconductor region 1204 also referred to as a second fin structure formed on a substrate 1206. The first semiconductor region 1202 and the second semiconductor region 1204 are separated by a feature, such as the source / drain cavity 1208, which exposes the substrate 1206. In one or more embodiments, a portion of the source / drain cavity 1208 extends into the substrate 1206.44025930W001

[0008] As shown in FIG. 12A, the first semiconductor region 1202 and the second semiconductor region 1204 each include a plurality of alternating semiconductor layers 1209. The plurality of alternating semiconductor layers 1209 include first semiconductor layers 1210A-C and second semiconductor layers 1212A-C that are alternately and repeatedly stacked on the substrate 1206. Although the example shown in FIG. 12A shows three pairs, each pair including the first semiconductor layer 1210A-C and the second semiconductor layer 1212A-C, the number of pairs may be varied based on different process needs with or without the first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C being needed. The first semiconductor layers 1210A-C are formed of a first material having etch selectivity to a second material of which the second semiconductor layers 1212A-C are formed, for example, an etch rate of the first material is higher than an etch rate of the second material. The etch selectivity, a ratio of the etch rate of the first material to the etch rate of the second material, is between about 10:1 to 200:1. Example combinations of the first material and the second material include silicon-germanium (SiGe)Zsilicon (Si), silicon-germanium (SiGe) / germanium (Ge), and germanium tin (GeSn)Zsilicon (Si). In one or more embodiments, the first semiconductor layers 1210A-C are or include SiGe and the second semiconductor layers 1212A-C are or include silicon, for example, crystalline silicon. In one or more embodiments, the first semiconductor layers 1210A-C include inners spacers formed from dielectric material. The second semiconductor layers 1212A-C may serve as channels having a width of between several nanometers and several tens of nanometers. The first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C can be nanostructures, for example, nanowires or nanosheets.

[0009] The first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C may be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the sourceZdrain cavity 1208 is formed by a patterning technique, such as lithography followed by an etch or ashing process. The first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C may each have thickness of between about 144025930W001nm and about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layers 1210A-C may be performed by any appropriate etch process, such as a dry plasma etch process.

[0010] In one or more embodiments, the semiconductor device structure 1200 further includes a dummy gate structure 1220 formed over at least a portion of each of the first semiconductor region 1202 and the second semiconductor region 1204. The dummy gate structure 1220 includes a dummy gate 1222. The dummy gate 1222 may be or include a conductive or nonconductive material and may be selected from amorphous silicon, doped or undoped polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), silicon oxide, metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate 1222 may be formed using any suitable techniques such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), CVD, ALD, or the like.

[0011] The dummy gate structure 1220 may further includes a dummy gate dielectric layer 1224 formed on or over the alternating semiconductor layers 1209, for example, on or over the first semiconductor layer 1210C. The dummy gate 1222 is formed on or over the dummy gate dielectric layer 1224 with the dummy gate dielectric layer 1224 formed in between the alternating semiconductor layers 1209 and the dummy gate 1222 such that the dummy gate dielectric layer 1224 separates the dummy gate 1222 from the alternating semiconductor layers 1209. The dummy gate dielectric layer 1224 protects the underlying alternating semiconductor layers 1209 during subsequent removal of the dummy gate 1222. The dummy gate dielectric layer 1224 may be formed of any suitable oxide, for example, silicon oxycarbonitride, silicon oxide, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0012] The dummy gate structure 1220 may further include one or more spacers 1226. The spacer 1226 may function as a spacer for forming selfaligned source / drain regions. The spacer 1226 may be formed along the sidewalls of the dummy gate 1222 and the dummy gate dielectric layer 1224. The spacer 1226 may be formed of silicon oxycarbonitride, silicon oxide, silicon44025930W001nitride, silicon oxynitride, or the like, using any suitable techniques such as thermal oxidation, or deposited by PECVD, CVD, ALD, or the like.

[0013] In one or more embodiments, first inner spacers 1234A-C are formed at the ends of first semiconductor layers 1210A-C. The first inner spacers 1234A-C act as isolation features between subsequently formed source / drain regions and a gate structure. As will be discussed in greater detail below, source / drain regions will be formed in the source / drain cavity 1208, while the first semiconductor layers 1210A-C in the n-type region and in the p-type region (not shown) will be replaced with corresponding gate structures.

[0014] The first inner spacers 1234A-C may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The first inner spacers 1234A-C may be or include a material such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. Although outer sidewalls of the first inner spacers 1234A-C are illustrated as being flush with sidewalls of the second semiconductor layers 1212A-C in the n-type region shown in FIG. 12C and in the p-type region (not shown), the outer sidewalls of the first inner spacers 1234A-C may extend beyond or be recessed from sidewalls of the second semiconductor layers 1212A-C and / or the first inner spacers 1234A-C, respectively.

[0015] Moreover, although the outer sidewalls of the first inner spacers 1234A-C are illustrated as being straight in FIG. 12C, the outer sidewalls of the first inner spacers 1234A-C may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process, such as reactive ion etching (RIE) or the like. The first inner spacers 1234A-C may be used to prevent damage to the subsequently formed source / drain region, for example, the source / drain region 1280 discussed below with respect to FIG. 12J, by subsequent etching processes, such as etching processes used to form gate structures.

[0016] The first inner spacers 1234A-C may be formed of dielectric material, such as silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide44025930W001(SiOC), or silicon oxycarbonitride (SiOCN). In one or more embodiments, the first inner spacers 1234A-C are formed from the same material as the spacer 1226. For example, both the first inner spacers 1234A-C and the spacer 1226 are formed from silicon oxycarbonitride. In one or more other embodiments, the first inner spacers 1234A-C are formed from a material that is different from the material of the spacer 1226.

[0017] The substrate 1206 has a frontside 1206f (also referred to as a front surface) and a backside 1206b opposite the frontside 1206f. The substrate 1206 may be a material such as crystalline silicon (e.g., Si<100> or Si<111 >), silicon oxide, strained silicon, silicon-germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or nonpatterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. In one or more embodiments, the substrate 1206 is or includes crystalline silicon.

[0018] The source / drain cavity 1208 is defined by a pair of opposing sidewall surfaces 1208s and a bottom surface 1208b. The sidewall surfaces 1208s may be defined by the dummy gate structure 1220 and the alternating pairs of the first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C. The bottom surface 1208b of the source / drain cavity 1208 is defined by the substrate 1206. In one or more embodiments, the bottom surface 1208b has a first crystal plane orientation, for example, (100) and the sidewall surfaces 1208s have a second crystal plane orientation, for example, (110).

[0019] A cleaning process may be performed to remove contaminants, such as native oxide layers, patterning residue, and debris present on exposed surfaces of the source / drain cavity 1208. The cleaning process can include a dry clean, a wet clean, or a combination thereof.

[0020] The cleaning process may include use of standard clean 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), standard clean 2 (RCA SC-2, a mixture of DI water, hydrochloric acid and hydrogen peroxide), SPM (a sulfuric peroxide mixture), and / or DHF wet cleaning using dilute hydrofluoric acid solution for oxide removal. The dry44025930W001cleaning process may include an anisotropic remote plasma assisted dry etch process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The dry cleaning process may include an isotropic plasma etching process, such as a SiCoNi™ dry chemical etching process, using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas, such as nitrogen (N2), hydrogen (H2), or a combination thereof. The dry chemical etching process is selective for oxide layers, and thus does not readily etch silicon, germanium, or nitride layers regardless of whether the layers are amorphous, crystalline, or polycrystalline. The dry cleaning process may include an inductively coupled plasma (ICP) etching process, using a plasma formed from a gas including chlorine (CI2) and hydrogen (H2), and a carrier gas including argon (Ar) and helium (He). The dry clean process may include helium (He) and hydrogen (H2) treatment. In one or more embodiments, the cleaning process includes exposing the semiconductor device structure 300 to atomic hydrogen radicals. In one or more embodiments, the cleaning process includes exposing the semiconductor device structure 300 to a thermal annealing process at a temperature of 600 degrees Celsius or higher, for example, in a range from about 650 degrees Celsius to about 900 degrees Celsius. The cleaning process can remove surface oxide, carbon, and debris in order to ensure a clean semiconductor surface, which facilitates growth of high quality epitaxial layers.

[0021] Referring to FIGS. 12B and 12C, the source / drain features 1250 are formed. The composition of the source / drain features depends on the conductivity type of the semiconductor device structure 1200. If the semiconductor device structure 1200 is an n-type structure, the source / drain features 1250 can include silicon (Si) doped with an n-type dopant such as phosphorous or arsenic. If the semiconductor device structure 1200 is a p-type structure, the source / drain features 1250 can include silicon germanium (SiGe) doped with a p-type dopant, such as boron or gallium. In one or more embodiments, as is shown in FIG. 12B and FIG. 12C, the source / drain features 1250 include multiple epitaxial layers each formed by an epitaxial process. The source / drain features 1250 may be epitaxially and selectively formed from the44025930W001exposed sidewall surfaces 1208s of the first semiconductor layers 1210A-C, the second semiconductor layers 1212A-C and the bottom surface 1208b, which is defined by the substrate 1206. Suitable epitaxial processes include vapor-phase epitaxial (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), low pressure CVD (LPCVD), plasma epitaxy, and / or other suitable processes. The epitaxial growth process may use gaseous precursors, which interact with the material of the substrate 1206 and the materials of the first semiconductor layers 1210A-C and the second semiconductor layers 1212A-C.

[0022] Referring to FIG. 12B, at operation 1120, a first layer of semiconductor material 1230 is epitaxially grown. The first layer of semiconductor material 1230 has an upper surface 1230u that has a U-shape or a V-shape that defines a recess 1232. The recess 1232 has a U-shaped surface, a V-shaped surface, or a combination of a U-shaped surface and a V-shaped surface, for example a V-shaped surface with a rounded or curved bottom. The bottom of the upper surface 1230u is curved such that a bottom surface 1232b of the recess 1232 is curved or rounded rather than substantially straight. In one or more embodiments, as is shown in FIG. 12B, the recess 1232 is defined by tapered sidewall surfaces(s) 1232s, which increase in thickness as the tapered sidewall(s) approach the bottom surface 1208b and the bottom surface 1232b defining the recess is curved or rounded.

[0023] In one or more embodiments, the process conditions for the epitaxial growth process of operation 1120 are selected so the first layer of semiconductor material 1230 has an increased growth rate on the (100) surfaces relative to the (110) surfaces such that the epitaxial growth process of operation 1120 is a partial bottom-up growth process. The first layer of semiconductor material 1230 can function as a template layer enabling bottom-up growth of the second layer of semiconductor material 1240. The first layer of semiconductor material 1230 is formed along surfaces of the source / drain cavity 1208, for example the sidewall surfaces 1208s and the bottom surface 1208b of the source / drain cavity 1208.44025930W001

[0024] A thickness of the first layer of semiconductor material 1230 can be equal to or greater than 50 angstroms (A). In one or more embodiments, as is shown in FIG. 12B, the thickness of the first layer of semiconductor material 1230 increases along the sidewall surfaces 1208s toward the bottom surface 1208b.

[0025] In one or more embodiments, a material of the first layer of semiconductor material 1230 is silicon germanium (Sii-xGex, where x is in a range from about 10 to about 30 or in a range from about 10 to about 20). The first layer of semiconductor material 1230 can be epitaxially grown using a germanium source precursor and a silicon source precursor. The germanium source precursor can be or include germane (GeF ), a higher order germane, a halogenated germane, an organogermane, or combinations thereof. Higher order germanes include compounds with an empirical formula GexH(2x+2), such as digermane (Ge2He), trigermane (GesHs), and tetragermane (Ge4H ). Organogermanes include compounds with an empirical formula RyGexH(2x+2-y), where R = methyl, ethyl, propyl or butyl, such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2Hs), dimethyldigermane ((CH3)2Ge2H4) and hexamethyldigermane ((CH3)eGe2). Halogenated germanes include chlorinated germanes. The chlorinated germane gases include germanium tetrachloride (GeCk), dichlorogermane (GeH2Cl2), trichlorogermane (GeHCh), hexachloro-digermane (Ge2Cle), or a combination thereof. The silicon source precursor can be or include silane (SiH4), a higher order silane, halogenated silane, organosilane, or a combination thereof. Higher order silanes include compounds with an empirical formula SixH(2x+2), such as disilane (Si2He), trisilane (SisHs), and tetrasilane (Si4H ). Halogenated silanes include compounds with the empirical formula X'ySixH(2x+2-y), where X' = F, Cl, Br or I, such as dichlorosilane (SiH2Cl2), tetrachlorosilane (SiCk), and hexachlorodisilane (S i2C le), and trichlorosilane (SiHCh). Organosilanes include compounds with an empirical formula RySixH(2x+2-y), where R = methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2Hs), dimethyldisilane ((CH3)2Si2H4) and hexamethyldisilane ((CH3)eSi2).44025930W001

[0026] In one or more embodiments, the silicon source precursor is silane and the germanium source precursor is GeCI4. In one or more embodiments, the silicon source precursor is dichlorosilane and the germanium source precursor is germane.

[0027] A flow rate of the germanium source precursor can be in a range from about 10 standard cubic centimeters per minute (seem) to about 200 seem, and a flow rate of the silicon source precursor can be in a range from about 10 seem to about 1000 seem. A ratio of the flow rate of the germanium source precursor to the flow rate of the silicon source precursor can be in a range from about 1 :5 to about 1.5:1. A first pressure of an environment in a processing chamber in which the epitaxial growth is performed can be maintained in a range from about 3 Torr to about to about 200 Torr, or from about 5 Torr to about 60 Torr, or from about 5 Torr to about 20 Torr. A first temperature of the substrate 1206 during the epitaxial growth can be maintained at about 350 °C or above, or at about 380 °C or above, or at about 400 °C or above, or at about 500 °C or above, or at about 590 °C or above, such as about 600 °C or above, and more particularly in a range from about 350 °C to about 900 °C, or from about 350 °C to about 400 °C, or from about 700 °C to about 750 °C.

[0028] An etchant can be flowed in the epitaxial growth process of operation 1120 to selectively etch epitaxially grown material, such as grown on an amorphous surface, for example, a dielectric surface such as an inner spacer. An etchant can be or include HCI, HF, HBr, Br2, Si2Cle, SiCk, SiHCh, SiH2Cl2, CCk, CI2, GeCk, GeHCh, or a combination thereof. A flow rate of an etchant gas can be in a range from about 0 seem to about 100 seem. A carrier gas, for example, an inert gas, such as nitrogen (N2), argon (Ar), the like, or a combination thereof, can be used in combination with the germanium source precursor, silicon source precursor, etchant, and / or a combination thereof.

[0029] In one or more embodiments, the first layer of semiconductor material 1230 can be doped, such as boron-doped silicon germanium (Sii-xGex(B) or more generally, SiGe(B)). A first concentration of a dopant in the first layer of semiconductor material 330 can be in a range from about 1x1019cm-3to about 5x1021cm-3. A dopant source can be flowed during the epitaxial growth of the44025930W001first layer of semiconductor material 1230 to in-situ dope the first layer of semiconductor material 1230. The dopant source can be or include a borane, organoborane (e.g., alkylboranes), and boron halide. Boranes include borane (BH3), diborane (B2H6), triborane (B3H5), tetraborane (B4H10), pentaborane(9) (B5H9), pentaborane(H), hexaborane( ) (BeH ), hexaborane(12) (B6H12), and decaborane(14) (B10H14), while alkylboranes include compounds with an empirical formula RxBH(3-x), where R = methyl, ethyl, propyl or butyl and x = 0, 1, 2 or 3. Alkylboranes include trimethylborane ((CH3)3B), dimethylborane ((CH3)2BH), triethylborane ((CH3CH2)3B), and diethylborane ((CH3CH2)2BH). Boron halides include electron deficient boron halides such as boron trifluoride (BF3), boron trichloride (BCI3), and boron tribromide (BBrs). A flow rate of the dopant source can be in a range from about 5 seem to about 30 seem. Other dopants, such as arsenide and phosphorus, may be implemented in other examples, and hence, different dopant sources can be used.

[0030] The epitaxial growth of the first layer of semiconductor material 1230 can cause surfaces of the first layer of semiconductor material 1230 to replicate surfaces of the source / drain cavity 1208 on which the first layer of semiconductor material 1230 is grown. Accordingly, the first layer of semiconductor material 1230 can have an upper surface, for example, the upper surface 1230u, that replicates the sidewall surfaces 1208s of the source / drain cavity. In one or more embodiments, where the bottom surface 1208b is a (100) Si surface, the bottom surface 1232b of the first layer of semiconductor material 1230 can be a (100) SiGe surface.

[0031] Referring to FIG. 12C, at operation 1130, a second layer of semiconductor material 1230 is epitaxially grown. The second layer of semiconductor material 1240 is grown in the recess 1232 defined by the first layer of semiconductor material 1230. In one or more embodiments, the second layer of semiconductor material 1240 fills the recess 1232 to complete the source / drain feature 1250. In one or more embodiments, the second layer of semiconductor material 1240 partially fills the recess 1232 and is followed by deposition of one or more additional layers of semiconductor material to fill the recess 1232 and complete the source / drain feature 1250. The second layer of44025930W001semiconductor material 1240 is formed on the upper surface 1230u of the first layer of semiconductor material 1230. In one or more embodiments, the process conditions for the epitaxial growth process of operation 220 are selected so that the second layer of semiconductor material 1240 has an increased growth rate on the (100) surfaces relative to the (110) surfaces such that the epitaxial growth process of operation 220 is a substantially bottom-up or anisotropic growth process. The tapering provides both (110), (111) and (100) growth surfaces but the second layer of semiconductor material 1240 has limited growth on the (110) and (111) surfaces the first layer of semiconductor material 1230, so the second layer of semiconductor material 1240 predominantly grows in the 100 plane, which provides a defect free layer and helps transfer strain to the channel.

[0032] In one or more embodiments, a material of the second layer of semiconductor material 1240 is silicon germanium (Sii-yGey, where y is in a range from about 30 to about 50 or in a range from about 40 to about 50), which may be doped, such as by boron (e.g., boron-doped silicon germanium (SiGe(B))). A second concentration of a dopant in the second layer of semiconductor material 1240 can be in a range from about 1x1018cm-3to about 5x1021cm-3. In one or more embodiments, the second concentration of dopant in the second layer of semiconductor material 1240 is greater than the first concentration of dopant in the first layer of semiconductor material 1230. The second layer of semiconductor material 1240 can be epitaxially grown using a germanium source precursor and a silicon source precursor. The germanium source precursor can be or include germane (GeH4), a higher order germane, a halogenated germane, an organogermane, or combinations thereof as previously described herein. The silicon source precursor can be or include silane (SiH4), a higher order silane, halogenated silane, for example, dichlorosilane, organosilane, or a combination thereof as previously described herein.

[0033] In one or more embodiments for forming the second layer of semiconductor material 1240, the silicon source precursor is silane and the germanium source precursor is GeCI4. In one or more embodiments for44025930W001forming the second layer of semiconductor material 1240, the silicon source precursor is dichlorosilane and the germanium source precursor is germane.

[0034] A dopant source gas can be flowed during the epitaxial growth of the second layer of semiconductor material 1240 to in-situ dope the second layer of semiconductor material 1240. The dopant source gas can be or include a borane, organoborane (e.g., alkylboranes), and boron halide as previously described.

[0035] An etchant can be flowed in the epitaxial growth process of operation 1130 to selectively etch epitaxially grown material, such as grown on an amorphous surface, for example, a dielectric surface such as an inner spacer. An etchant gas can be or include HCI, HF, HBr, Br2, Si2Cle, SiCk, SiHCh, SiH2Cl2, CCk, CI2, GeCk, GeHCh, or a combination thereof. A flow rate of an etchant gas can be in a range from about 0 seem to about 100 seem. A carrier gas, for example, an inert gas, such as nitrogen (N2), argon (Ar), the like, or a combination thereof, can be used in combination with the germanium source precursor, silicon source precursor, etchant, and / or a combination thereof.

[0036] A flow rate of the germanium source precursor can be in a range from about 10 seem to about 1,000 seem or in a range from about 50 seem to about 500 seem, and a flow rate of the silicon source precursor can be in a range from about 10 seem to about 1,000 seem or in a range from about 50 seem to about 500 seem. A ratio of the flow rate of the silicon source precursor to the flow rate of the germanium source precursor can be in a range from about 2:1 to about 1.2:1. A flow rate of the dopant source gas can be in a range from in a range from about 1 seem to about 150 seem or in a range from about 5 seem to about 30 seem. A carrier gas (e.g., an inert gas), such as nitrogen (N2), argon (Ar), the like, or a combination thereof, can be used in combination with the germanium source precursor, the silicon source precursor, dopant source gas, or a combination thereof. A second pressure of an environment in a processing chamber in which the epitaxial growth is performed can be maintained in a range from about 5 Torr to about 100 Torr, or in a range from about 5 Torr to about 40 Torr, or in a range from about 5 Torr to about 20 Torr. A second temperature of the substrate 306 during the epitaxial growth can be maintained44025930W001at about 350 °C or above, at about 500 °C or above, such as in a range from about 500 °C to about 700 °C, or in a range from about 540 °C to about 600 °C.

[0037] Under these conditions, epitaxial growth of the silicon germanium can be anisotropically deposited. In one or more embodiments, where the upper surface 1230u of the first layer of semiconductor material 1230 is a (100) SiGe surface, the second layer of semiconductor material 1240 can be anisotropically grown from the respective (100) SiGe surfaces in a <100> direction without substantial lateral growth in a <010> direction, such that a (110) surface is not formed. Thus, a lateral growth component of the second layer of semiconductor material 1240 can be suppressed. Suppression of a lateral growth component can reduce or eliminate a facet (e.g., a (110) surface) formed in the source / drain features 1250. During the epitaxial growth process of the source / drain features 1250, chlorine dissociated from the chlorinated germane gas can etch lateral growth that can form a (110) surface. The combination of vertical deposition and etch rates and lateral deposition and etch rates result in a vertical growth rate that is significantly greater than a lateral growth rate, which helps generate a S / D stress that will transfer into the channel region.

[0038] In one or more embodiments, the second layer of semiconductor material 1240 is epitaxially grown via a cyclic deposition / purge process including an epitaxial deposition portion followed by a purge portion. The number of cycles can be as low as one, for example, deposition / purge / deposition only. The epitaxial deposition portion includes coflowing the silicon precursor, the germanium precursor, optionally the etchant gas, and optionally a carrier gas for a first period of time to epitaxially grow a first portion of the second layer of semiconductor material 1240 via bottom-up growth followed by the purge portion for a second period of time. The pump / purge process can be performed for any number of cycles until the source / drain feature 1250 achieves a targeted thickness. In addition, the first period of time and the second period of time may be adjusted for each subsequent deposition cycle as the size of the recess 1232 decreases. In one or more embodiments, the first time period is in a range from about 5 seconds44025930W001to about 45 second and the second time period is in a range from about 5 second to about 45 seconds. For example, during deposition of the first portion the first time period is about 30 seconds and the second time period is about 10 seconds and during deposition of a second portion, the first time period is about 10 seconds and the second time period is about 30 seconds. During the purge portion, the flow of the silicon precursor and the germanium are stopped while the flow of the etchant gas and / or carrier gas continues. Not to be bound by theory but it is believed that the purge portion removes the deposition gases from the recess 1232, which reduces or prevents deposition of the second layer of semiconductor material 1240 along the tapered sidewall surface(s) 1232s and contributes to bottom-up growth on the bottom surface 1232b.

[0039] In one or more embodiments of the cyclic deposition / purge process, the epitaxial deposition portion includes co-flowing DCS, GeH4, and HCI and the purge portion includes stopping the flow of DCS and GeH4 while continuing to flow HCI. In one or more embodiments, the epitaxial deposition portion includes co-flowing DCS, GeH4 and GeCI4 and the purge portion includes stopping the flow of DCS and GeH4 while continuing to flow GeCI4.

[0040] During operation 1130, a second pressure of an environment in a processing chamber in which the epitaxial growth is performed can be maintained in a range from about 5 Torr to about to about 200 Torr, or from about 5 Torr to about 60 Torr, or from about 5 Torr to about 20 Torr. A second temperature of the substrate 1206 during the epitaxial growth can be maintained at about 350 °C or above, or at about 380 °C or above, or at about 590 °C or above, such as about 600 °C or above, and more particularly in a range from about 350 °C to about 900 °C, or from about 350 °C to about 400 °C, or from about 700 °C to about 750 °C. The second pressure and second temperature of operation 1130 may be the same as or similar to the first pressure and the first temperature of operation 1120. The second pressure and second temperature of operation 1130 may be different from the first pressure and the first temperature of operation 1120.

[0041] As depicted in FIG. 12C, the feature 1250 can further include additional layers, for example a third layer of semiconductor material 1242 and44025930W001a fourth layer of semiconductor material 1244. The various layers of semiconductor material can have varying concentrations of germanium. In one or more embodiments, where the feature 1250 is formed using a deposition / purge process, during the purge process, gases remaining in the recess deposit a layer of semiconductor material that is compositionally different from a layer of semiconductor material deposited during the deposition process. For example, the second layer of semiconductor material 1240 is deposited during a deposition process and has a higher concentration of germanium whereas the third layer of semiconductor material 1242 deposited during the purge process has a lower concentration of germanium and the fourth layer of semiconductor material 1244 deposited during the deposition process has a higher concentration of germanium.

[0042] After deposition of the source / drain features 1250, an anneal process may be performed to activate the source / drain features 1250. In one or more embodiments, the anneal process may include a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. The anneal process may include a peak anneal temperature in a range from about 900 degrees Celsius and about 1000 degrees Celsius. The peak anneal temperature may be maintained for a duration measured by seconds or microseconds. Through the anneal process, a desired electronic contribution of the p-type dopant in the semiconductor host, such as silicon germanium (SiGe) or germanium (Ge), may be obtained. The anneal process may generate vacancies that facilitate movement of the p-type dopant from interstitial sites to substitutional lattice sites and reduce damage or defects in the lattice of the semiconductor host.

[0043] FIG. 13 illustrates an exemplary flow chart of a method 1300 of forming a nano-FET structure, according to one or more embodiments.

[0044] FIGS. 14A-14D illustrate schematic views of various stages of forming a nano-FET structure, according to one or more embodiments. With reference to FIGS. 14A-14D, schematic views of embodiments of a nano-FET structure at various stages of manufacture are provided to illustrate the method of FIG. 13. Although FIGS. 14A-14D are described in relation to the method44025930W0011300, it will be appreciated that the structures disclosed in FIGS. 14A-14D are not limited to the method 1300, but instead may stand alone as structures independent of the method 1300. Similarly, although the method 1100 is described in relation to FIGS. 14A-14D, it will be appreciated that the method 1300 is not limited to the structures disclosed in FIGS. 14A-14D, but instead may stand alone independent of the structures disclosed in FIGS. 14A-14D. The method 1300 may be used to form portions of the nano-FET 400 depicted in FIG. 4.

[0045] Referring to FIG. 14A, at operation 410, a semiconductor device structure 1400 having a source / drain cavity 1208 is provided. The semiconductor device structure 1400 may be or be part of a multi-gate device with three-dimensional architecture, such as fin based semiconductor devices including nano-FETs and gate-all-around (GAA) transistor devices. The semiconductor device structure 1400 is similar to the semiconductor device structure 1200. A cleaning process may be performed to remove contamination, oxide, and debris present in the source / drain cavity 1208 prior to operation 1320.

[0046] Referring to FIG. 14B, at operation 1320, a first layer of semiconductor material 1430 is epitaxially grown. The first layer of semiconductor material 1430 is a conformal or substantially conformal layer. In one or more embodiments, the first layer of semiconductor material 1430 is a liner. In one or more embodiments, the process conditions for the epitaxial growth process of operation 1320 are selected so that the first layer of semiconductor material 1430 has a similar growth rate on the (100) surfaces, for example, the bottom surface 1208b, relative to the (110) surfaces, for example, the sidewall surfaces 1208s such that the first layer of semiconductor material 1430 is a conformal or substantially conformal layer. The first layer of semiconductor material 330 is formed on surfaces of the source / drain cavity 1208, for example the sidewall surfaces 1208s and the bottom surface 1208b of the source / drain cavity 1208. The first layer of semiconductor material 1430 defines a first recess 1432. The first layer of semiconductor material 1430 includes sidewall surfaces 1430s and a bottom surface 1430b. In one or more44025930W001embodiments, the sidewall surfaces 1430s and the bottom surface 1430b are straight or substantially straight.

[0047] Referring to FIG. 14C, at operation 1330, the first layer of semiconductor material 1430 is exposed to an etching process to form a modified first layer of semiconductor material 1450. The modified first layer of semiconductor material 1450 has a partial U-shape or a partial V-shape that defines a second recess 1460. The first layer of semiconductor material 1430 is etched such that an upper portion 1452 of the first conformal layer coating an upper portion of the sidewall surfaces 1208s is removed at greater rate than a lower portion 1454 of the modified first layer of semiconductor material 1450 coating a lower portion of the sidewall surfaces 1208s and the bottom surface 1208b to form the modified first layer of semiconductor material 1450. The etching process of operation 1330 can be performed with a limited partial pressure of the etchant so that the upper portion 1452 of the first layer of semiconductor material 1430 etches at a greater rate relative to the lower portion 1454 of the first layer of semiconductor material 1430. The modified first layer of semiconductor material 1450 can function as a template layer enabling bottom-up growth of a second layer of semiconductor material 1470 during operation 1340.

[0048] The modified first layer of semiconductor material 1450 has an upper surface 1450u that has a U-shape or a V-shape that defines the second recess 1460. The second recess 1460 has a U-shaped surface, a V-shaped surface, or a combination of a U-shaped surface and a V-shaped surface, for example a V-shaped surface with a rounded or curved bottom. In one or more embodiments, the bottom of the upper surface 1450u is curved such that a bottom surface 1460b of the second recess 1460 is curved or rounded rather than substantially straight. In one or more embodiments, the bottom of the upper surface 1450u is substantially flat such that a bottom surface 1460b of the second recess 1460 is substantially straight rather than curved. In one or more embodiments, as is shown in FIG. 14C, the second recess 1460 is defined by tapered sidewall(s) 1460s, which increase in thickness as the tapered sidewall(s) approach the bottom surface 1460b and the bottom surface 1460b44025930W001defining the second recess is flat or substantially straight. In one or more embodiments, as is shown in FIG. 14C, the second recess 1460 is defined by the tapered sidewall(s) 1460s, which increase in thickness as the tapered sidewall(s) approach the bottom surface 1460b and the bottom surface 1460b defining the second recess is rounder or curved similar to FIG. 12B.

[0049] Any suitable etching process that achieved the targeted profile of the modified first layer of semiconductor material 1450 may be used. An etchant gas can be flowed during operation 1330 to selectively remove portions of the first layer of semiconductor material 1430. The etchant gas can be or include HCI, HF, HBr, Br2, S Cb, SiCk, SiHCb, SiH2CI2, CCk, Cl2, GeCI4, GeHCb, or a combination thereof. A flow rate of an etchant gas can be in a range from about 10 seem to about 100 seem. A carrier gas, for example, an inert gas, such as nitrogen (N2), argon (Ar), the like, or a combination thereof, can be used in combination with the etchant gas. In one or more embodiments, the etching process of operation 1330 is performed in the same processing chamber as the epitaxial deposition process of operation 1320, the epitaxial deposition process of operation 1330, or both the epitaxial deposition process of operation 1320 and operation 1330.

[0050] Referring to FIG. 14D, at operation 1340, a second layer of semiconductor material 1470 is epitaxially grown. The second layer of semiconductor material 1470 is grown in the second recess 1460 defined by the modified first layer of semiconductor material 1450. In one or more embodiments, the second layer of semiconductor material 1470 fills the second recess 1460 to complete the source / drain feature 1480. In one or more embodiments, the second layer of semiconductor material 1470 partially fills the second recess 1460 and is followed by deposition of one or more additional layers of semiconductor material to fill the second recess 1460 and complete the source / drain feature 1480. The second layer of semiconductor material 1470 is formed on the surface 1450s of the modified first layer of semiconductor material 1450. In one or more embodiments, the process conditions for the epitaxial growth process of operation 1340 are selected so that the second layer of semiconductor material 1470 has an increased growth rate on the (100)44025930W001surfaces relative to the (110) surfaces such that the epitaxial growth process of operation 1340 is a substantially bottom-up or anisotropic growth process. The epitaxial deposition process of operation 1340 may be performed similarly to the deposition process of operation 1130.

[0051] As depicted in FIG. 14D, the feature 1480 can further include additional layers, for example a third layer of semiconductor material 1472 and a fourth layer of semiconductor material 1474. The various layers of semiconductor material can have varying concentrations of germanium. In one or more embodiments, where the feature 1480 is formed using a deposition / purge process, during the purge process, gases remaining in the recess deposit a layer of semiconductor material that is compositionally different from a layer of semiconductor material deposited during the deposition process. For example, the second layer of semiconductor material 1470 is deposited during a deposition process and has a higher concentration of germanium whereas the third layer of semiconductor material 1472 deposited during the purge process has a lower concentration of germanium and the fourth layer of semiconductor material 1474 deposited during the deposition process has a higher concentration of germanium.

[0052] After deposition of the source / drain features 1480, an anneal process may be performed to activate the source / drain features 1480. In one or more embodiments, the anneal process may include a rapid thermal anneal (RTA) process, a laser spike anneal process, a flash anneal process, or a furnace anneal process. The anneal process may include a peak anneal temperature in a range from about 900 degrees Celsius and about 1000 degrees Celsius. In such an embodiment, the peak anneal temperature may be maintained for a duration measured by seconds or microseconds. Through the anneal process, a desired electronic contribution of the p-type dopant in the semiconductor host, such as silicon germanium (SiGe) or germanium (Ge), may be obtained. The anneal process may generate vacancies that facilitate movement of the p-type dopant from interstitial sites to substitutional lattice sites and reduce damage or defects in the lattice of the semiconductor host.44025930W001

[0056] The subject matter herein can be described in the following Examples.

[0057] Example 1 includes a method of forming a semiconductor device, comprising:providing a structure having a source / drain cavity defined by a pair of opposing sidewall surfaces, the sidewall surfaces each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer;exposing the second semiconductor layer to an etching process to remove a portion of the second semiconductor layer and form an inner cavity recess;filling the inner cavity recess with a dielectric material to form an inner spacer;forming a conformal liner layer over the sidewall surfaces, the conformal liner layer formed on the inner spacer; andforming a source / drain material on the conformal liner layer in the source / drain cavity.

[0058] Example 2 includes a method of forming a semiconductor device, comprising:providing a structure having a source / drain cavity defined by a pair of opposing sidewall surfaces, the sidewall surfaces each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer;forming a raised inner spacer on the first semiconductor layer, the raised inner spacer extending past the sidewall surfaces;forming a conformal liner layer over the sidewall surfaces and the raised inner spacer; andforming a source / drain material on the conformal liner layer in the source / drain cavity.44025930W001

[0059] Example 3 includes a non-transitory computer readable medium comprising instructions that, when executed, cause a plurality of operations to be conducted, the plurality of operations comprising:setting a formation temperature;flowing a deposition precursor, the deposition precursor including silicon; ramping the formation temperature to an anneal temperature at a ramp rate, the ramp rate less than 5.0 degrees Celsius-per-second; andflowing a source and drain precursor.

[0060] Example 4 includes the non-transitory computer readable medium of Example 3, wherein the ramp rate is less than 1.0 degrees Celsius-per-second.

[0061] Example 5 includes the non-transitory computer readable medium of claim Example 4, wherein the ramp rate is within a range of 0.1 degrees Celsius-per-second to 0.5 degrees Celsius-per-second.

[0062] Example 6 includes the non-transitory computer readable medium of Example 3, wherein the formation temperature is less than 500 degrees Celsius, and the anneal temperature is greater than 650 degrees Celsius.

[0063] Example 7 includes a method of forming a semiconductor device, comprising:epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material defining a recess having a U-shaped profile; and epitaxially growing a second layer of semiconductor material on the first layer of semiconductor material in the recess by a bottom-up growth process.

[0064] Example 8 includes the method of Example 7, wherein the bottom surface has a first crystal plane orientation and the sidewall surfaces have a second crystal plane orientation.44025930W001

[0065] Example 9 includes the method of Example 8, wherein a growth rate of the first layer along the first crystal plane orientation is greater than a growth rate of the first layer along the second crystal plane orientation.

[0066] Example 10 includes the method of Example 9, wherein the first crystal plane orientation is (100) and the second crystal plane orientation is (101).

[0067] Example 11 includes the method of Example 7, wherein epitaxially growing the first layer is performed at a first temperature in a range from about 700 degrees Celsius to about 750 degrees Celsius.

[0068] Example 12 includes the method of Example 11 , wherein epitaxially growing the second layer is performed at a second temperature in a range from about 500 degrees Celsius to about 700 degrees Celsius and the second temperature is less than the first temperature.

[0069] Example 13 includes the method of Example 7, wherein epitaxially growing the first layer is performed at a first pressure in a range from about 10 Torr to about 200 Torr.

[0070] Example 14 includes the method of Example 13, wherein epitaxially growing the second layer is performed at a second pressure in a range from about 5 Torr to about 20 Torr and the second pressure is less than the first pressure.

[0071] Example 15 includes the method of Example 7, wherein the first layer comprises silicon germanium doped with a p-type dopant, the first layer having a first germanium concentration and a first dopant concentration.

[0072] Example 16 includes the method of Example 16, wherein the second layer comprises silicon germanium doped with the p-type dopant, the second layer having a second germanium concentration, which is greater than the first germanium concentration and a second dopant concentration, which is greater than the first dopant concentration.44025930W001

[0073] Example 17 includes the method of Example 7, wherein a bottom surface of the recess is curved.

[0074] Example 18 includes a method of forming a semiconductor device, comprising:epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material is a conformal layer and defines a first recess;etching the first layer of semiconductor material to form a modified first layer of semiconductor material, the modified first layer of semiconductor material defining a second recess having a U-shape profile; and epitaxially growing a second layer of semiconductor material on the modified first layer of semiconductor material in the second recess by a bottom-up growth process.

[0075] Example 19 includes the method of Example 18, wherein etching the first layer of semiconductor material comprises removing an upper portion of the first layer of semiconductor material coating an upper portion of the sidewall surfaces at greater rate than a lower portion of the first layer of semiconductor material coating a lower portion of the sidewall surfaces and the bottom surface.

[0076] Example 20 includes the method of Example 18, wherein the first layer comprises silicon germanium doped with a p-type dopant, the first layer having a first germanium concentration and a first dopant concentration.

[0077] Example 21 includes the method of Example 20, wherein the second layer comprises silicon germanium doped with the p-type dopant, the second layer having a second germanium concentration, which is greater than the first germanium concentration and a second dopant concentration, which is greater than the first dopant concentration.

[0078] Example 22 includes the method of Example 18, wherein a bottom surface of the second recess is curved.44025930W001

[0079] Example 23 includes a processing system, comprising:a first processing chamber; anda system controller, comprising:a memory for storing computer readable instructions; and a processor coupled to the memory, the processor configured by the computer readable instructions that when executed by the processor perform a plurality of operations, comprising:epitaxially growing a first layer of semiconductor material on a pair of opposing sidewall surfaces and a bottom surface, the pair of opposing sidewall surfaces and the bottom surface defining a source drain cavity, the first layer of semiconductor material defining a recess having a U-shaped profile; andepitaxially growing a second layer of semiconductor material on the first layer of semiconductor material in the recess by a bottom-up growth process.

[0080] Example 24 includes the method of Example 23, wherein the bottom surface has a first crystal plane orientation and the sidewall surfaces have a second crystal plane orientation.

[0081] Example 25 includes the processing system of Example 24, wherein a growth rate of the first layer along the first crystal plane orientation is greater than a growth rate of the first layer along the second crystal plane orientation.

[0082] Example 26 includes the processing system of Example 24, wherein the first crystal plane orientation is (100) and the second crystal plane orientation is (101).

[0070] Benefits of the present disclosure include quick and efficient formation of materials (such as silicon-containing materials), enhanced strain for enhanced device performance, reduced or eliminated (or controlled) merging of the materials, and with reduced or eliminated formation of voids in the deposited materials. Benefits also include reduced or eliminated notches of the deposited materials. Benefits also include reduced downtime.44025930W001

[0071] In one or more embodiments, a conformal liner growth process is provided. The conformal liner is grown at low growth rates with lower gas flow rates. The conformal liner process covers the inner spacer and can also cover “knuckles” generated by the L1 liners to provide a smooth recess surface for subsequent epitaxial filling of the recess. The conformal liner process provides a high-quality surface for subsequent epitaxial deposition fill of the recess leading to fewer defect in the formed source / drain feature. The conformal liner can be used with or without an L1 liner.

[0072] In one or more embodiments, deposition of a multi-layer epitaxial source / drain material is performed. A first layer of epitaxial source / drain material is formed over the surface of a source / drain cavity by a partial bottom-up process. The first layer of epitaxial source / drain material defines a recess having a U-shaped, a V-shaped surface, or a combination of a U-shaped surface and a V-shaped surface, for example a V-shaped surface with a rounded or curved bottom. The first layer of epitaxial source / drain material facilitates bottom-up growth of a second layer of epitaxial source / drain material, which generates a source / drain stress that will transfer into the channel. =

[0073] The present disclosure does not necessitate that all the beneficial features and all the benefits need to be incorporated into every embodiment and implementation of the present disclosure.

[0074] It is contemplated that one or more aspects disclosed herein may be combined. As an example, one or more aspects, features, components, operations and / or properties of the processing chamber 1000, the method 200, the semiconductor device structure 300, the operations shown in Figures 3A-3D, the nano-FET 400, the method 500, the semiconductor device structure 600, the method 700, the semiconductor device structure 800, the cluster tool 900, the processing chamber 1000, the method 1100, the semiconductor device structure 1200, the method 1300, and / or the semiconductor device structure 1400 may be combined. Moreover, it is contemplated that one or more aspects disclosed herein may include some or all of the aforementioned benefits.44025930W001

[0083] In the Summary and in the Detailed Description, and the Claims, and in the accompanying drawings, reference is made to particular features (including method operations) of the present disclosure. It is to be understood that the disclosure in this specification includes all possible combinations of such particular features. For example, where a particular feature is disclosed in the context of a particular aspect, embodiment, implementation, or example of the present disclosure, or a particular claim, that feature can also be used, to the extent possible in combination with and / or in the context of other particular aspects and embodiments of the present disclosure, and in the present disclosure generally.

[0084] Embodiments and all of the functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and structural equivalents thereof, or in combinations of them. Embodiments described herein can be implemented as one or more non-transitory computer program products, e.g., one or more computer programs tangibly embodied in a machine readable storage device, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple processors or computers.

[0085] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0086] The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management44025930W001system, an operating system, or a combination of one or more of them. Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.

[0087] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0088] Where reference is made herein to a method including two or more defined operations, the defined operations can be carried out in any order or simultaneously (except where the context excludes that possibility), and the method can include one or more other operations which are carried out before any of the defined operations, between two of the defined operations, or after all of the defined operations (except where the context excludes that possibility).

[0075] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

44025930W001Claims:

1. A method of substrate processing, comprising:forming an amorphous liner on a structure on a substrate, the amorphous liner comprising silicon, and the forming including a formation temperature;annealing the amorphous liner to crystallize the amorphous liner into a crystalline liner, the annealing comprising:ramping the formation temperature to an anneal temperature at a ramp rate, the ramp rate less than 5.0 degrees Celsius-per-second; removing liner material from a plurality of cap layers of the structure; and forming source and drain material on the crystalline liner.

2. The method of claim 1, wherein the crystalline liner is formed on inner surfaces of a plurality of recesses of the structure, the crystalline liner lines a plurality of stacks of the structure, and the plurality of stacks respectively comprise a plurality of first composition layers and a plurality of second composition layers.

3. The method of claim 2, wherein the crystalline liner lines the plurality of first composition layers and dielectric spacers disposed outwardly of the plurality of second composition layers.

4. The method of claim 1 , wherein the annealing further comprises soaking the amorphous liner at the anneal temperature after the formation temperature is ramped to the anneal temperature.

5. The method of claim 1, wherein the ramp rate is less than 1.0 degrees Celsius-per-second.

6. The method of claim 5, wherein the ramp rate is within a range of 0.1 degrees Celsius-per-second to 0.5 degrees Celsius-per-second.44025930W0017. The method of claim 1 , wherein the formation temperature is less than 500 degrees Celsius, and the anneal temperature is greater than 650 degrees Celsius.

8. The method of claim 1 , wherein the amorphous liner further comprises a promotion material that promotes the crystallize, the promotion material including one or more of germanium, gallium, tin, or arsenic, and an atomic percentage of the promotion material in the amorphous liner is 10% or less.

9. The method of claim 1, further comprising doping the crystalline liner with a dopant material after the annealing, the dopant material including one or more Group III and / or Group V elements.

10. The method of claim 1, wherein the source and drain material has a strain of 0.4 or higher.

11. A method of substrate processing, comprising:forming one or more inner spacers along a pair of opposing sidewall surfaces defining a source / drain cavity, the sidewall surfaces respectively defined by alternating pairs of a first semiconductor layer and a second semiconductor layer;forming a liner over the sidewall surfaces, the liner formed on the one or more inner spacers; andforming a source / drain material on the liner in the source / drain cavity.

12. The method of claim 11 , further comprising:exposing the second semiconductor layer to an etching process to remove a portion of the second semiconductor layer and form one or more inner cavity recesses, wherein the one or more inner cavity recesses are filled with a dielectric material of the one or more inner spaces.

13. The method of claim 11, wherein the one or more inner spacers are raised to extend past the sidewall surfaces.44025930W00114. The method of claim 11, wherein the liner defines a recess having a U-shaped profile.

15. The method of claim 11 , wherein:the forming of the liner is performed at a first temperature in a range from about 700 degrees Celsius to about 750 degrees Celsius, and at a first pressure in a range from about 10 Torr to about 200 Torr; andthe forming of the source / drain material is performed at a second temperature in a range from about 500 degrees Celsius to about 700 degrees Celsius and the second temperature is less than the first temperature, and at a second pressure in a range from about 5 Torr to about 20 Torr, wherein the second pressure is less than the first pressure.

16. The method of claim 11, wherein the source / drain cavity defines a bottom surface, the bottom surface has a first crystal plane orientation and the sidewall surfaces have a second crystal plane orientation, and a growth rate of the liner along the first crystal plane orientation is greater than a growth rate of the liner along the second crystal plane orientation.

17. A device comprising:a substrate;a plurality of stacks formed on the substrate to define a plurality of recesses between the plurality of stacks;a crystalline liner lining side surfaces of at least one of the plurality of stacks; anda source and drain material formed on the crystalline liner, the source and drain material having a strain of 0.4 or higher.

18. The device of claim 17, wherein the crystalline liner comprises silicon and one or more of: germanium, gallium, tin, arsenic, one or more Group III elements, or one or more Group V elements.

19. The device of claim 17, wherein:44025930W001the crystalline liner further comprises a promotion material, the promotion material including one or more of germanium, gallium, tin, or arsenic; andthe promotion material has an atomic percentage in the crystalline liner, and the atomic percentage is 10% or less.

20. The device of claim 17, wherein the crystalline liner has a thickness less than 10 nm.

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