Digital wallets with multi-party computation security measure

Abstract

In one embodiment, an apparatus includes a monolithic integrated circuit chip. The chip includes a microcontroller unit (MCU), a secure element (SE) including a secure storage configured to store one or more cryptographic key shares, and a physical countermeasure mechanism (PCM) shield configured to protect both the MCU and the SE. The PCM shield includes hardware layers integrated directly into top levels of the monolithic integrated circuit chip. The MCU is configured to provide one or more commands to the SE to perform one or more atomic inline operations associated with multi-party computation (MFC) signing using the one or more cryptographic key shares stored in the secure storage. The SE is configured to perform the one or more atomic inline operations with the one or more cryptographic key shares remaining confined within the SE and to return to the MCU one or more results of the atomic inline operations.

Description

ATTORNEY DOCKET PATENT APPLICATION 088603.01111 of 14Digital Wallets with Multi-Party Computation Security Measure TECHNICAL FIELD

[0001] This disclosure generally relates to systems and methods for enabling multiparty computation (MPC) for applications with heightened security needs, such as digital wallets.BACKGROUND

[0002] Multi-party computation (MPC) is an advanced cryptographic technique that enables multiple parties / devices to collaboratively compute a function over their inputs while keeping those inputs private from one another. MPC is emerging as a critical technology to enhance security, privacy, and functionality, such as in the fields of digital wallets, cryptocuiTcncy storage, decentralized finance, and multi-device wallets.

[0003] Traditionally, digital wallets rely on single-key architectures where a private key is stored on a user’s device or in a centralized server. FIG. 1 shows a private / public key pair used to authenticate messages by ensuring their integrity and verifying the sender’s identity. The key pair consists of a private key 110, which is kept secret by the owner (e.g., user 115), and a public key 120, which is openly shared. In other words, any user 125 may use the public key 120. These keys are mathematically linked so that data encrypted or signed with one can only be decrypted or verified using the other. To authenticate a message 130, the sender 115 first computes a cryptographic hash of the message 130. This hash is a unique, fixed-size representation of the message’s 130 content, ensuring that even the slightest change in the message 130 alters the hash. The sender 115 then encrypts the hash using their private key 110, creating a digital signature 140. This signature 140, along with the message 130, is sent to the recipient 125. When the recipient 125 receives the message 130, they recompute the hash from the message content and use the sender’s 115 public key 120 to decrypt the digital signature 140. This decryption reveals the original hash created by the sender 115. The recipient 125 then performs signature validation 150 by comparing the decrypted hash with their recomputed hash. If the hashes match, it confirms that the message 130 was not altered during transit and that the signature 140 was created by the sender 115 using their private key 110. This process ensures both the integrity of the message 130 and the authenticity of the sender 115. The system relies on the secrecy of the private key 110, the transparency of the public key 120, and theATTORNEY DOCKET PATENT APPLICATION 088603.01112 of 14one-way nature of the cryptographic functions, making it a cornerstone of secure communication protocols like HTTPS, secure email, and blockchain technology.

[0004] Digital wallets use private / public key pairs to ensure secure authentication and transaction management. Each wallet generates a private key, known only to the owner, and a public key, which can be shared. The public key is often used to derive the wallet address for sending or receiving assets. When a user initiates a transaction, the wallet software uses the private key to create a unique digital signature, proving the transaction's authenticity and integrity. The recipient or network verifies the signature using the public key, confirming it was authorized by the rightful owner without exposing the private key. Additionally, public keys can encrypt sensitive information, ensuring only the private key holder can decrypt it. This system ensures ownership, tamper-proof transactions, and trust while maintaining confidentiality and control over digital assets.

[0005] This approach, while straightforward, poses significant security risks. For example, if the private key is compromised, lost, or stolen, the user’s assets may be irretrievably lost. To mitigate these vulnerabilities, MPC offers a decentralized approach to key management. In an MPC-based digital wallet, the private key is never created or stored as a whole entity. Instead, it is divided into shares, which are distributed among multiple parties or devices, which are often referred to as “nodes.” Each share, on its own, reveals no information about the private key. These parties or devices can then collaborate through cryptographic protocols to perform operations such as transaction signing, without reconstructing the private key in a single location. Since the private key is never fully assembled, even if one or more shares are compromised, the key remains secure. As illustrated in FIG. 2, the signature of a message 130 is generated using the multiple key shares (e.g., key share 210a, key share 210b, key share 210c, key share 210d, and key share 210e) instead of the private key itself. The signature is then used for authentication (e.g., signature validation 150) using the public key 120.SUMMARY OF PARTICULAR EMBODIMENTS

[0006] In particular embodiments, an apparatus includes a monolithic integrated circuit chip. The monolithic integrated circuit chip may include a microcontroller unit (MCU), a secure element (SE) including a secure storage configured to store one or more cryptographic key shares, and a physical countermeasure mechanism (PCM) shield configured to protect both the MCU and the SE. The PCM shield may include one or more hardware layers integratedATTORNEY DOCKET PATENT APPLICATION 088603.01113 of 14directly into one or more top levels of the monolithic integrated circuit chip. The MCU may be configured to provide one or more commands to the SE to perform one or more atomic inline operations associated with multi-party computation (MPC) signing using the one or more cryptographic key shares stored in the secure storage. The SE may be configured to perform the one or more atomic inline operations with the one or more cryptographic key shares remaining confined within the SE and to return to the MCU one or more results of the atomic inline operations.

[0007] In particular embodiments, the one or more commands include a single command. Correspondingly, the SE may include a state machine configured to autonomously execute an entire MPC protocol in response to the single command from the MCU.

[0008] In particular embodiments, the one or more commands include at least a first command and a second command, the one or more atomic inline operations include at least a first atomic inline operation and a second atomic inline operation. Accordingly, the SE may be configured to perform the first atomic inline operation in response to the first command and to return to the MCU a first result of the first atomic inline operation. The MCU may be configured to, responsive to receiving the first result, provide the second command to coordinate the first and second atomic inline operations to construct a custom MPC protocol.

[0009] In particular embodiments, the secure storage includes a non-volatile memory (NVM).

[0010] In particular embodiments, the NVM is embedded within one or more metal layers of the monolithic integrated circuit chip.

[0011] In particular embodiments, the NVM further includes one or more tamperdetection circuits configured to detect tampering of the one or more metal layers associated with the NVM.

[0012] In particular embodiments, the MCU is further configured to, in response to detecting the tampering, erase data stored in the NVM.

[0013] In particular embodiments, the monolithic integrated circuit chip further includes an internal communication path between the MCU and the SE located within the PCM shield.

[0014] In particular embodiments, the monolithic integrated circuit chip further includes an external memory interface. The external memory interface may be configured to support execute-in-place (XIP) operations with at least one external memory device and to perform real-time encryption and decryption of external memory traffic.ATTORNEY DOCKET PATENT APPLICATION 088603.01114 of 14

[0015] In particular embodiments, the one or more atomic inline operations include generating a signature associated with an MPC protocol.

[0016] In particular embodiments, the signature is configured for blockchain transaction authentication.

[0017] In particular embodiments, the monolithic integrated circuit chip is configured for use in a digital wallet.

[0018] In particular embodiments, the MCU is further configured to operate a user interface for transaction authorization.BRIEF DESCRIPTION OF THE DRAWINGS

[0019] TIG. 1 illustrates an example private / public key pair used to authenticate messages by ensuring their integrity and verifying a sender’s identity.

[0020] FIG. 2 illustrates an example signature of a message generated using multiple key shares instead of a private key itself.

[0021] FIG. 3 illustrates an example non-secure microcontroller unit (MCU) connected to a traditional, discrete secure element (SE).

[0022] FIG. 4 illustrates an example architecture of a secure processing unit (SPU) disclosed herein.

[0023] FIG. 5 illustrates an example block diagram of an SE within the SPU supporting atomic inline operations used for MPC.

[0024] FIG. 6 illustrates an example block diagram of an SE within the SPU performing atomic operations, which the MCU coordinates to construct custom protocols.DESCRIPTION OF EXAMPLE EMBODIMENTS

[0025] MPC offers significant advantages in both security and ease of use. MPC provides enhanced protection against theft and hacking by eliminating a single point of attack. An attacker would need to simultaneously acquire multiple key shares, making the system significantly more secure. Additionally, MPC reduces the reliance on complex PINs, passwords, or passphrases required in traditional single-key systems, as MPC shifts the burden of security from users to devices. MPC is also highly resilient to loss, addressing common issues such as forgotten PINs or misplaced wallets. Key shares distributed across multiple nodes can be recovered without requiring error-prone recovery processes. Moreover, MPC facilitates succession planning by allowing distributed shares to enable asset recovery in casesATTORNEY DOCKET PATENT APPLICATION 088603.01115 of 14of death or incapacitation, ensuring heirs or designated parties can access the assets without relying on input from the deceased. With its natural robustness and self-healing capabilities, MPC effectively manages security, loss, and succession without the need for complicated, error-prone systems, making it a practical and secure solution for modem workflows.

[0026] MPC takes multiple shares and computes a valid signature, but that process is computationally heavy. Performing such computations in software on a general processing unit could take 10 or more seconds, which is unacceptable in many use cases. Thus, for MPC to be practical, hardware silicon support is needed.

[0027] A traditional system that uses off-the-shelf computing units and secure elements has several shortcomings. FIG. 3 illustrates a non-secure microcontroller unit (MCU) connected to a traditional, discrete secure element (SE), which stores a share of a key. An SE may be a dedicated microprocessor chip designed to protect sensitive data, such as private keys and key shares, from unauthorized access and physical attacks. The SE achieves the protection by isolating security functions from a device’s main processor. The MCU 310 may execute code 320 which may include, for example, firmware / software instructions that drive the digital wallet workflow, transaction construction, UI prompts, and coordination with the SE 340. Data / RAM (random access memory) 330 may represent the MCU’s 310 working memory used at runtime. For example, data / RAM 330 may be temporary storage for variables and state, I / O buffers, message / transaction payloads, intermediate results of computations, communication buffers for the link 380 to the SE 340.

[0028] As shown, the MCU 310 has no physical countermeasure mechanisms (PCM) shield 390 and is therefore not secure, while the SE 340 is secured by a PCM shield 390. Since the SE 340 is protected by the PCM shield 390, the share of a key stored thereon (e.g., in secret storage 360) is secure. However, when the SE 340 transmits the share to the non-secure MCU 310 via a non-secure bus (e.g., link 380), the share is vulnerable to attacks. Moreover, traditional SEs have limited cryptographic capabilities (e.g., unused legacy crypto 350) and only support conventional primitives that may not suffice for modern blockchain and cryptographic applications. They rely on flash memory 370, which is inherently insecure and offers limited storage capacity, typically only tens of kilobytes, as well as limited shelf life due to discharge. Additionally, these elements adopt a centralized security approach that operates as a black box, offering no transparency or verifiability and requiring users to trust manufacturers blindly. Furthermore, traditional secure elements are often manufactured using outdated technologies, which limit their performance, security, and efficiency.ATTORNEY DOCKET PATENT APPLICATION 088603.01116 of 14

[0029] To address the issue of the non-secure MCU connected to the SE in MPC, the embodiments disclosed herein develop a secure processing unit (SPU) that integrates all components, including memory, CPU, secure storage, and accelerators, into a single monolithic chip. FIG. 4 illustrates an example architecture of such an SPU 400. The processing environment and flexible SE of such SPU are in a single system-on-chip (SOC). The SPU 400 may include MCU 410, code 420, data / RAM 430, secret storage 440, crypto accelerators 450. With the MCU 410 and secure storage 440 now being on the same chip and protected within the same PCM shield 470, messages between the MCU 410 and secret storage 440 are hidden and secured. Having the MCU 410 protected within the PCM shield 470 also enhances security, since the MCU 410 is responsible for computing signatures and controlling the user interface (UI) used for approving transactions. If the UI is not protected, the assets can be compromised even if the keys are not. Therefore, protecting the MCU 410 is important to reduce attack surfaces.

[0030] In particular embodiments, an SE within the SPU may be configured to support atomic inline operations used for MPC or other cryptography operations. FIG. 5 illustrates an example block diagram 500 of an SE within the SPU supporting atomic inline operations used for MPC. For example, as shown in FIG. 5, the MCU 510 issues a command, and the SE 520 (hardware engine), operating as a state machine, may perform atomic operations 530. The SE 520 may autonomously process the entire protocol inline without further coordination from the MCU 510. Sensitive data remains confined within the SE 520 and is never exposed to the MCU 510. Only the results of the operations 530 are sent back to the MCU 510. This mode provides a robust additional layer of defense, with the SE 520 managing the complete protocol independently for highly secure and streamlined operations 530.

[0031] FIG. 6 illustrates an example block diagram 600 of an SE within the SPU performing atomic operations, which the MCU coordinates to construct custom protocols. In another embodiment shown in FIG. 6, the SE 620 (hardware engine) does not support full protocol acceleration. In this case, the SE 620 performs atomic operations 630, which the MCU 610 coordinates to construct custom protocols. Although the MCU 610 plays a more active role in this mode, sensitive data is still not exposed to the MCU 610, as all critical data handling occurs securely within the SE 620. This approach allows for greater flexibility, enabling the implementation of arbitrary protocols while maintaining security.

[0032] The two modes illustrated in FIGS. 5-6 offer a balance between flexibility and security. The shared PCM shield ensures the integrity of both the MCU and SE, making eitherATTORNEY DOCKET PATENT APPLICATION 088603.01117 of 14mode a secure solution for modem applications requiring customizable and protected cryptographic operations.

[0033] Aside from enhanced security, having the integrated components on a single chip allows the SPU to achieve superior cost, power, and size. In particular embodiments, the secure storage comprises a non-volatile memory (NVM) such as flash memory, resistive RAM (ReRAM), magnetoresistive RAM (MRAM), phase-change RAM (PCRAM), etc. In an embodiment, the solution uses ReRAM-based (resistive RAM) memory 460 which provides greater reliability and performance. Additionally, as previously mentioned, the solution incorporates cryptographic primitives (e.g., crypto accelerators 450) tailored to modem blockchain applications, ensuring its relevance and adaptability.

[0034] In particular embodiments, the SPU may be built using a cutting-edge 22nm manufacturing process, providing superior cost efficiency, lower power consumption, reduced size, and enhanced security compared to SEs typically manufactured at 40-130nm. The SPU may employ ReRAM instead of floating gate flash, making it more robust against temperature, aging, radiation, and magnetic fields. The SPU may integrate a power management integrated circuit (PMIC) with a low-dropout (LDO) regulator, enabling efficient operation from a 2.7-3.6V supply range.

[0035] A notable feature may include the SPU’ s external memory interface, supporting execute -in-place (XIP) operations with external flash such as quad serial peripheral interface (QSPI) and octal serial peripheral interface (OSPI) and static RAM (SRAM) such as highspeed serial peripheral interface (HSPI), while offering real-time encryption and decryption of external memory traffic — capabilities not found in typical SEs, which lack external memory support altogether. The dual-processor architecture may combine RISC-V and other high-performance cores, significantly outperforming SEs, which typically use a single low-performance core. As such, the SPU delivers faster processing speeds, higher clock rates due to advanced pipelining, and enhanced memory capabilities, including larger non-volatile memory (NVM) (e.g., 4MB) and SRAM (e.g., 2MB), along with advanced caching and tightly coupled memory.

[0036] For efficient data transfer, the SPU may feature a dedicated I / O bus with direct memory access (DMA) and buffer memory for high-speed operations, a main DMA controller on an advanced multi-port AXI bus, and an AXI (advanced extensible interface) architecture superior to the simpler advanced high-performance bus (AHB)-like buses used in SEs. TheseATTORNEY DOCKET PATENT APPLICATION 088603.01118 of 14advancements may collectively enhance performance, flexibility, and security, making the SPU a robust solution for modem secure applications.

[0037] As described elsewhere herein, shares of a key may be stored in an SE. An SE could use any suitable type of persistent storage to store shares. For example, traditional flash memory is low-cost and widely available, but as described in further detail below, Resistive RAM (ReRAM) has several advantages that makes it an improved solution for key storage.

[0038] The high-level comparison of the advantages of ReRAM over flash is described as follows. Flash memory is widely used in a variety of applications, such as SD cards and a variety of digital devices, but several of its limitations make it unsuitable for storing key shares. In flash memory, retaining electrons is challenging due to inherent vulnerabilities like defects, ionic contamination, and direct tunneling. As flash memory scales down to smaller nodes, it becomes increasingly prone to data loss because even a single electron can escape due to these factors. This leads to poor retention and renders flash memory impractical for secure applications below 28nm. Consequently, conventional secure elements and chips remain limited to larger process nodes, such as 40nm, due to flash memory constraints. In addition, flash memory cannot be integrated with advanced logic. This means that any application that requires advanced logic would need to read the data from the flash memory and process the data using a separate compute unit (i.e., the flash memory cannot perform complex logic inline). Lastly, the charge stored in a flash memory is readable by microscopy, which means it is not suitable for storing secrets, such as key shares.

[0039] In contrast, ReRAM operates on an atomic scale using only a few metal ions, making it far more robust against scaling limitations. It is capable of functioning below 20nm and is already being developed at 12nm. This scalability enhances its performance and retention capabilities, making it ideal for advanced secure applications.

[0040] Furthermore, ReRAM can be configured to support more complex logic nodes than flash memory, making it particularly advantageous for SEs. As discussed earlier, having an SE capable of performing cryptographic operations directly within the hardware is beneficial from both security and efficiency standpoints, as it eliminates the need to transfer sensitive data between the SE and the MCU. Achieving this requires the SE to possess the capability to handle complex logic inline. ReRAM’s inherent flexibility and advanced configurability make it an ideal choice for this purpose, enabling SEs to execute sophisticated cryptographic functions more efficiently and securely.ATTORNEY DOCKET PATENT APPLICATION 088603.01119 of 14

[0041] ReRAM is also less vulnerable to hacking. Conventional memory types such as flash, SRAM, ROM, or one-time programmable memory (OTP) are vulnerable to optical attacks, which exploit the ability of light to penetrate silicon and reveal the underlying transistor activity. While metal layers in a chip can deflect light, the silicon substrate and transistor layer remain vulnerable, allowing adversaries to use imaging techniques to access sensitive data in conventional memory.

[0042] In contrast, ReRAM is built as a “back-end” memory, embedded within the metal layers rather than at the silicon wafer level. This positioning makes ReRAM inherently more resistant to light penetration from either the top or bottom of the chip. Additionally, ReRAM chips incorporate advanced countermeasures, such as active meshes and sensors, which detect any attempts to remove metal layers for tampering. When tampering is detected, the SPU may erase the data stored in ReRAM, providing robust security against optical attacks.

[0043] For additional security, ReRAM may be secured within a physical countermeasure (PCM) shied. Unlike conventional approaches that focus on specific core areas, this design protects the entire chip to protect the SE and MCU, enhancing overall security. Key features include active shields and secure layouts to defend against cross-section analysis and probing attacks, along with countermeasures against fault injections such as laser attacks and voltage glitches. These protections are supplemented with detectors and glue logic to identify and block malicious glitches. To mitigate side-channel attacks, the PCM design employs constant-time and constant-power computations, as well as advanced noise-injection techniques to obscure data patterns. Additionally, the SPU supports secure boot processes, including multi-signature schemes, and incoiporates secure memory mechanisms for added protection. A high-quality true random number generator (TRNG) further strengthens cryptographic operations, ensuring robust security at both hardware and algorithmic levels.

[0044] Embodiment 1. An apparatus comprising: a monolithic integrated circuit chip comprising: a microcontroller unit (MCU); a secure element (SE) comprising a secure storage configured to store one or more cryptographic key shares; and a physical countermeasure mechanism (PCM) shield configured to protect both the MCU and the SE, wherein the PCM shield comprises one or more hardware layers integrated directly into one or more top levels of the monolithic integrated circuit chip; wherein: the MCU is configured to provide one or more commands to the SE to perform one or more atomic inline operations associated with multi-party computation (MFC) signing using the one or more cryptographic key shares stored in the secure storage; and the SE is configured to perform the one or more atomic inlineATTORNEY DOCKET PATENT APPLICATION 088603.011110 of 14operations with the one or more cryptographic key shares remaining confined within the SE and to return to the MCU one or more results of the atomic inline operations.

[0045] Embodiment 2. The apparatus of embodiment 1, wherein the one or more commands comprise a single command, and wherein the SE comprises a state machine configured to autonomously execute an entire MPC protocol in response to the single command from the MCU.

[0046] Embodiment 3. The apparatus of embodiment 1 or 2, wherein: the one or more commands comprise at least a first command and a second command, the one or more atomic inline operations comprise at least a first atomic inline operation and a second atomic inline operation, the SE is configured to perform the first atomic inline operation in response to the first command and to return to the MCU a first result of the first atomic inline operation, and the MCU is configured to, responsive to receiving the first result, provide the second command to coordinate the first and second atomic inline operations to construct a custom MPC protocol.

[0047] Embodiment 4. The apparatus of any one of embodiments 1-3, wherein the secure storage comprises a non-volatile memory (NVM).

[0048] Embodiment 5. The apparatus of any one of embodiments 1-4, wherein the NVM is embedded within one or more metal layers of the monolithic integrated circuit chip.

[0049] Embodiment 6. The apparatus of any one of embodiments 1-5, wherein the NVM further comprises one or more tamper-detection circuits configured to detect tampering of the one or more metal layers associated with the NVM.

[0050] Embodiment 7. The apparatus of any one of embodiments 1-6, wherein the MCU is further configured to, in response to detecting the tampering, erase data stored in the NVM.

[0051] Embodiment 8. The apparatus of any one of embodiments 1-7, wherein the monolithic integrated circuit chip further comprises an internal communication path between the MCU and the SE located within the PCM shield.

[0052] Embodiment 9. The apparatus of any one of embodiments 1-8, wherein the monolithic integrated circuit chip further comprises an external memory interface, and wherein the external memory interface is configured to support execute-in-place (XIP) operations with at least one external memory device and to perform real-time encryption and decryption of external memory traffic.ATTORNEY DOCKET PATENT APPLICATION 088603.011111 of 14

[0053] Embodiment 10. The apparatus of any one of embodiments 1-9, wherein the one or more atomic inline operations comprise generating a signature associated with an MPC protocol.

[0054] Embodiment 11. The apparatus of any one of embodiments 1-10, wherein the signature is configured for blockchain transaction authentication.

[0055] Embodiment 12. The apparatus of any one of embodiments 1-11, wherein the monolithic integrated circuit chip is configured for use in a digital wallet.

[0056] Embodiment 13. The apparatus of any one of embodiments 1-12, wherein the MCU is further configured to operate a user interface for transaction authorization.

[0057] Herein, “or” is inclusive and not exclusive, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A or B” means “A, B, or both,” unless expressly indicated otherwise or indicated otherwise by context. Moreover, “and” is both joint and several, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A and B” means “A and B, jointly or severally,” unless expressly indicated otherwise or indicated otherwise by context.

[0058] The scope of this disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments described or illustrated herein that a person having ordinary skill in the art would comprehend. The scope of this disclosure is not limited to the example embodiments described or illustrated herein. Moreover, although this disclosure describes and illustrates respective embodiments herein as including particular components, elements, feature, functions, operations, or steps, any of these embodiments may include any combination or permutation of any of the components, elements, features, functions, operations, or steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend. Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Additionally, although this disclosure describes or illustrates particular embodiments as providing particular advantages, particular embodiments may provide none, some, or all of these advantages.

Claims

ATTORNEY DOCKET PATENT APPLICATION 088603.011112 of 14CLAIMSWhat is claimed is:

1. An apparatus comprising:a monolithic integrated circuit chip comprising:a microcontroller unit (MCU);a secure element (SE) comprising a secure storage configured to store one or more cryptographic key shares; anda physical countermeasure mechanism (PCM) shield configured to protect both the MCU and the SE, wherein the PCM shield comprises one or more hardware layers integrated directly into one or more top levels of the monolithic integrated circuit chip; wherein:the MCU is configured to provide one or more commands to the SE to perform one or more atomic inline operations associated with multi-party computation (MPC) signing using the one or more cryptographic key shares stored in the secure storage; andthe SE is configured to perform the one or more atomic inline operations with the one or more cryptographic key shares remaining confined within the SE and to return to the MCU one or more results of the atomic inline operations.

2. The apparatus of claim 1, wherein the one or more commands comprise a single command, and wherein the SE comprises a state machine configured to autonomously execute an entire MPC protocol in response to the single command from the MCU.

3. The apparatus of claim 1, wherein:the one or more commands comprise at least a first command and a second command, the one or more atomic inline operations comprise at least a first atomic inline operation and a second atomic inline operation,the SE is configured to perform the first atomic inline operation in response to the first command and to return to the MCU a first result of the first atomic inline operation, and the MCU is configured to, responsive to receiving the first result, provide the second command to coordinate the first and second atomic inline operations to construct a custom MPC protocol.ATTORNEY DOCKET PATENT APPLICATION 088603.011113 of 144. The apparatus of claim 1, wherein the secure storage comprises a non-volatile memory (NVM).

5. The apparatus of claim 4, wherein the NVM is embedded within one or more metal layers of the monolithic integrated circuit chip.

6. The apparatus of claim 5, wherein the NVM further comprises one or more tamperdetection circuits configured to detect tampering of the one or more metal layers associated with the NVM.

7. The apparatus of claim 6, wherein the MCU is further configured to, in response to detecting the tampering, erase data stored in the NVM.

8. The apparatus of claim 1, wherein the monolithic integrated circuit chip further comprises an internal communication path between the MCU and the SE located within the PCM shield.

9. The apparatus of claim 1, wherein the monolithic integrated circuit chip further comprises an external memory interface, and wherein the external memory interface is configured to support execute-in-place (XIP) operations with at least one external memory device and to perform real-time encryption and decryption of external memory traffic.

10. The apparatus of claim 1, wherein the one or more atomic inline operations comprise generating a signature associated with an MPC protocol.

11. The apparatus of claim 10, wherein the signature is configured for blockchain transaction authentication.

12. The apparatus of claim 1, wherein the monolithic integrated circuit chip is configured for use in a digital wallet.

13. The apparatus of claim 1, wherein the MCU is further configured to operate a user interface for transaction authorization.

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