A computer system comprising a quantum processing unit and a classical computing device

Abstract

This patent document discloses computer systems, methods and techniques that can be implemented using a quantum processing unit and a classical computing device. Some example embodiments of computer systems and methods can be implemented to provide readout signals from a quantum processing unit to a classical computing device in various applications with quantum computing. An example of such a computer system can include a quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits; and a classical computing device.

Description

Attorney Docket No. 133858.8016.WO00A COMPUTER SYSTEM COMPRISING A QUANTUM PROCESSING UNIT AND A CLASSICAL COMPUTING DEVICEPRIORITY CLAIM AND RELATED PRIORITY APPLICATIONS

[0001] This patent document claims the priority and benefits of United Kingdom Patent Application No. 2501616.3 entitled “A COMPUTER SYSTEM COMPRISING A QUANTUM PROCESSING UNIT AND A CLASSICAL COMPUTING DEVICE,” and filed on February 4, 2025, which is incorporated by reference as part of the disclosure of this patent document.TECHNICAL FIELD

[0002] The present disclosure relates to computer systems comprising a quantum processing unit and a classical computing device.BACKGROUND

[0003] Quantum computing provides a new paradigm of computers. Classical computers hold and manipulate information in the form of bits which are represented by two states 0 or 1 (e.g., low signal or high signal). In quantum computing, instead of a classical bit in definitely one of two states, information is stored and manipulated as qubits which can form a quantum superposition of two states.

[0004] A quantum computer can be in communication with a classical computer. As one example, a user may use a classical computer to define a specific application (e.g. a customized quantum algorithm) that is to be executed by the quantum computer and may “upload” corresponding application instructions to the quantum computer. As another exampie, the quantum computer and the ciassicai computer may exchange data in “real-time”, l.e. during the execution of an application on the quantum computer (e.g. to implement a quantum error correction method).

[0005] Various architectures have been proposed for the formation of a quantum computer. Some architectures require that (at least a part of) the quantum computer is operated within a cryogenic refrigeration system which provides significant isolation from the environment. As one example, when the quantum bits are formed by superconducting circuits, these “superconducting quantum bits” need to be cooledAttorney Docket No. 133858.8016.WO00below the critical temperature of the superconducting transition (i.e. typically at low subKelvin temperatures). As another example, when the quantum bits are implemented using single photons, the photons may be generated and manipulated at room temperature but the qubit readout may be implemented within a cryogenic environment (e.g. when a superconducting nanowire single photon detector is used to detect the photons). In such cases, fast data transfer between the (part of the) quantum computer that is be operated within the cryogenic refrigeration system and the classical computer (normally located outside the cryogenic refrigeration system) is needed. However, communication channels for transferring data from a cryogenic (part of the) quantum computer to a classical computer have often a low capacity (e.g. because of the long travel distance of the information, the thermal and electrical properties of the communication channel, and so on) making high-speed, “real-time” data exchange between these systems challenging.SUMMARY

[0006] The present disclosure aims to provide new and useful computer systems and methods for transmitting readout signals from a quantum processing unit to a classical computing device, e.g. to perform quantum error correction.

[0007] in an embodiment, there is provided a computer system comprising a quantum processing unit (QPU) comprising a plurality of quantum bit units (e.g. superconducting qubit circuits) and one or more pluralities of cryogenic readout circuits (e.g. readout circuits comprising classical superconducting digital logic circuits such as Single-Flux Quantum (SFQ) circuits). Each cryogenic readout circuit is configured to output a readout signal from a corresponding quantum bit unit. The readout signal is indicative of a quantum state of said quantum bit unit (e.g. the readout signal may be measurement outcome of a measurement performed on a corresponding quantum bit unit and may be represented by at least one bit). The computer system further comprises, for each plurality of readout circuits, a corresponding cryogenic transmitter module coupled to said plurality of readout circuits and configured to serialize the readout signals into a corresponding stream of digital signals. The computer system further comprises, for each plurality of readout circuits, a corresponding communication channel coupled to said transmitter module and configured to transmit the stream of digital signals. The computer system further comprises, for each plurality of readoutAttorney Docket No. 133858.8016.WO00circuits, a corresponding receiver module coupled to said communication channel and configured to deserialize the stream of digital signals to output deserialized data. The computer system further comprises a classical computing device comprising a memory (partitioned into blocks of words) and configured to store each of the one or more deserialized data in a different block the memory based on a predefined memory map specifying a mapping between the readout circuits and memory locations within said block of the memory. The term “cryogenic” may mean that the corresponding elements, e.g. the readout circuits or transmitter module, need to be held at cryogenic temperatures, when in use, to operate properly (e.g. at a temperature lower than 77 K, lower than 4 K, or lower than 100 mK).

[0008] Embodiments described herein enable, for example, high-speed transfer of a plurality of qubit readout signals (generated by cryogenic readout circuits of the QPU) to the classical computing device over a single communication channel. Embodiments achieve this by serializing the plurality of qubit readout signals within the cryogenic environment (i.e. by using a cryogenic transmitter module) and transmitting the serialized data (i.e. a stream of digital signals) via the communication channel to the non-cryogenic receiver module and classical computer. By using a memory map, software application running on the classical device can correctly interpret data stored in specific memory locations. This eliminates the need to transfer metadata (e.g. information describing which digital signal in the serialized data corresponds to which readout circuit) alongside the QPU readout, significantly reducing communication latency. Further, embodiments allow parallel data transfer of multiple pluralities of qubit readout signals via multiple communications channels and may thereby improve the scalability of the system with respect to the number of readout signals / circuits.

[0009] In an embodiment, each transmitter module may be configured to serialize the readout signals into a corresponding stream of digital signals in response to receiving a corresponding first signal (for example, the first signal may be generated in response to a software trigger by a software application running on the classical device).

[0010] In an embodiment, each receiver module may further be configured to, in response to receiving the stream of digital signals, provide a corresponding block status indicator signal to the classical computing device. This may enable a softwareAttorney Docket No. 133858.8016.WO00application running on the classical device to determine that new data is ready for processing.

[0011] As described below in more detail, many possibilities exist to implement the block status indicator signal. As one example, the block status indicator signal may be encoded in the corresponding deserialized data. As another example, each receiver module may provide the corresponding block status indicator signal to the classical computing device by storing corresponding flag data into a predefined block of the memory of the classical computing device that is different from the block of memory in which corresponding deserialized data is stored. As a further example, providing the respective block status indicator signal may involve triggering the application (to consume the corresponding deserialized data stored in the memory) based on a hardware interrupt, e.g. the classical computing device may run a further software application (e.g. a driver or firmware application) that is triggered by a hardware interrupt generated by the receiver module and that is configured to, in response to the hardware interrupt, trigger or notify the first-mentioned application running on the classical computing device to consume the corresponding deserialized data stored in the memory.

[0012] In an embodiment, the quantum processing unit may comprise two or more pluralities of readout circuits and the system may further comprise a data accumulator unit configured to receive the deserialized data from the two or more receiver modules, to synchronise the received deserialized data and to provide the synchronised deserialized data to the classical computing device for storing in the memory.

[0013] In an embodiment, the data accumulator unit may be further configured to, in response to receiving deserialized data from each receiver module, provide a corresponding transmission status indicator signal to the classical computing device.

[0014] In an embodiment, the transmitter module may comprise a line code encoder unit to generate a line code representation of the readout signals, and a serializer unit to serialize the line code representation of the readout signals into a corresponding stream of digital signals. Alternatively, the transmitter module may comprise a serializer unit configured to serialize the readout signals, and a line code encoder unit configured to generate a line code representation of the serialized signals to generate the stream of digital signals.Attorney Docket No. 133858.8016.WO00

[0015] In an embodiment, the cryogenic readout circuits may comprise a plurality of superconducting circuits (for example, superconducting single-flux quantum circuits; in this case the readout signals may comprise single-flux quantum signals).

[0016] In an embodiment, the system may further comprise a cryogenic refrigeration system that provides a refrigerated environment. The quantum bit units, the one or more pluralities of cryogenic readout circuits and the cryogenic transmitter modules may be positioned within the refrigerated environment and cooled by the cryogenic refrigeration system. The receiver module and the classical computing device may be positioned outside the refrigerated environment.

[0017] In an embodiment, each cryogenic transmitter module may comprise a converter unit to convert the serialized single-flux quantum signals into a corresponding stream of logic-level digital signals and to provide said stream of logic-level digital signals (e.g. CMOS-logic digital signals) to the communication channel.

[0018] In an embodiment, the quantum bit units comprise superconducting qubit circuits.

[0019] In an embodiment, each cryogenic transmitter module may be configured to serialize the readout signals into a corresponding stream of digital signals without adding redundant information.

[0020] In an embodiment, each cryogenic transmitter module does not comprise circuitry configured to, in response to receiving a request from the classical computing system, retransmit the stream of digital signals to implement a classical error correction code.

[0021] In an embodiment, there is provided a method of operating a computer system to transmit readout signals from a quantum processing unit to a classical computing device. The computer system comprises:the quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits;for each plurality of cryogenic readout circuits, a cryogenic transmitter module coupled to the plurality of readout circuits;for each plurality of readout circuits, a receiver module coupled to the cryogenic transmitter module via a corresponding communication channel, andAttorney Docket No. 133858.8016.WO00the classical computing device coupled to the receiver module.

[0022] The method comprises:(i) outputting, by each readout circuit of the one or more pluralities of readout circuits, a respective readout signal from a corresponding quantum bit circuit, the readout signal being indicative of a quantum state of said quantum bit circuit;(ii) serializing, by each transmitter module, the respective readout signals into a corresponding stream of digital signals;(iii) transmitting, via the communication channels, the streams of digital signals from the transmitter modules to the receiver modules;(iv) deserializing, by each receiver module, the respective stream of digital signals to output respective deserialized data;(v) storing, by the classical computing device, the each of one or more deserialized data in a different block of a memory of the classical computing device based on a predefined memory map specifying a mapping between the readout circuits and memory locations within said block of the memory.

[0023] In an embodiment, serializing the readout signals into a corresponding stream of digital signals may comprise:receiving, by each transmitter module, a respective first signal, andin response of receiving the first signal, serializing the readout signals into a corresponding stream of digital signals.

[0024] In an embodiment, the method may further comprise a step of providing, by each receiver module, in response to receiving the respective stream of digital signals a corresponding block status indicator signal to the classical computing device.

[0025] In an embodiment, the method may further comprise a step of consuming, by an application running on the classical computing device, in response to receiving the respective block status indicator signal, data the corresponding deserialized data stored in the memory.

[0026] In an embodiment, the quantum processing unit may comprise two or more pluralities of readout circuits, and the method may further comprise the steps of synchronising the two or more received deserialized data, providing the synchronised deserialized data to the classical computing device for storing in the memory andAttorney Docket No. 133858.8016.WO00 providing a corresponding transmission status indicator signal to the classical computing device.

[0027] In an embodiment, the method may further comprise a step of consuming, by an application running on the classical computing device, in response to receiving the transmission status indicator signal, the two or more deserialized data stored in the memory.

[0028] In an embodiment, each transmitter module may serialize the respective readout signals into a corresponding stream of digital signals without adding redundant information.

[0029] In an embodiment, there is a provided a method of performing quantum error correction. The method comprises:executing, by a quantum processing unit, a step of a quantum application; transmitting readout signals of the quantum processing unit to a classical computing device according to the method of any one of claims 16 to 21;determining, by an application running on the classical computing device, a correction to an intended subsequent step of the quantum application based on the deserialized data;modifying said step of the quantum application based on the determined correction; andexecuting, by the quantum processing unit, the corrected step of the quantum application.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic of a computer system in accordance with an embodiment;

[0031] Figures 2 and 3 are schematics of an example control circuit;

[0032] Figure 4 is a schematic of components of the computer system of Figure 1 in greater detail;

[0033] Figure 5 illustrates a memory mapping in accordance with an embodiment;

[0034] Figure 6 is a schematic of a transmitter module of the computer system of Figure 1;Attorney Docket No. 133858.8016.WO00

[0035] Figure 7 is a schematic of an example serializer module of the transmitter module of Figure 6;

[0036] Figure 8 is a schematic of a variation of the transmitter module of Figure 6;

[0037] Figure 9 illustrates a line encoding by the transmitter module of Figure 8;

[0038] Figure 10 is a schematic of a receiver module of the computer system of Figure 1;

[0039] Figure 11 is a flow diagram of an example process of transmitting readout data;

[0040] Figure 12 is a flow diagram of an example process of performing quantum error correction using the transmission process of Figure 11;

[0041] Figure 13 is a schematic of a variation of the receiver module of Figure 10;

[0042] Figure 14 is a schematic illustrating an example readout data transmission process;

[0043] Figure 15 is flow diagram of an example process of operating the computer system;

[0044] Figure 16 is a schematic illustrating a further example readout data transmission process; and

[0045] Figure 17 is flow diagram of a further example process of operating the computer system;

[0046] To avoid unnecessary repetition, like reference numerals will be used to denote like features in the figures.DETAILED DESCRIPTION

[0047] In cryogenic quantum computer architectures readout signals may be transmitted using analogue radio-frequency (RF) signals such as microwave signals. To address problems of crowding RF lines in multi-qubit quantum computing systems, a microwave “feedline” can be used that allows frequency multiplexing of the analogue signals. This means that using frequency-multiplexing allows several qubit readout resonators to be addressed and readout simultaneously with a single line. The output signal of the feedline (at a room-temperature end of the line) is then demultiplexed inAttorney Docket No. 133858.8016.WO00several stages to retrieve the resonator shifts in terms of in-phase and quadrature components of the signal.

[0048] However, while frequency multiplexing reduces cable crowding, it can lead to problems of frequency crowding. In practice, there is a minimum frequency separation requirement which limits the number of qubits addressable by a single feedline to less than 10. Further, each feedline is coupled to a corresponding readout output line that requires circuitry for extracting the relevant information in the readout signal using demodulation and post-processing techniques. This requires further undesirable overhead microwave infrastructure and computing capabilities as the number of qubits increases.

[0049] In overview, the present disclosure aims to enable reliable, high-speed data-transfer from a quantum processing unit (QPU) to a classical computing device (e.g. to enable real-time processing of quantum bit readout data by the classical computing device) without the need to rely on frequency multiplexing (thereby avoiding at least some of the aforementioned problems associated with frequency multiplexing). In particular, the present disclosure proposes a computing system / method which implements a novel “data communications protocol” for interfacing a QPU (having qubit readout circuits that are operated within a cryogenic environment) with a classical computing device (located outside the cryogenic environment) which is (largely) independent of implementation / architecture details of the QPU and the classical computing device. The proposed protocol improves the scalability of the readout infrastructure of a cryogenic quantum computing system, specifically regarding thermal load on the mixing chamber due to cable numbers required by readout, and in terms of the amount of readout information that can be transmitted per unit time. The proposed protocol is well-suited for implementing quantum error correction techniques, in which the classical computing device performs real-time processing of syndrome readout data (transmitted by the QPU) to generate suitable corrections to a quantum program (i.e. a used-defined quantum algorithm) before a next step of the quantum program is executed by the QPU, as described in detail below. Whilst, in the following, embodiments are described that use superconducting quantum bit circuits, it is to be understood that the proposed systems / methods may be used with QPUs that comprise other types of quantum bits that are read out via cryogenic readout circuits (e.g. single photons that are detected via superconducting photon detector).Attorney Docket No. 133858.8016.WO00

[0050] With reference to Figure 1, a computer system 1 is described. The computer system 1 comprises a quantum processing unit (QPU) 10 communicatively coupled to a classical computer model 12 via a physical layer 14.

[0051] The QPU 10 comprises a quantum chip 16, readout circuits 18, and control circuits 20. The quantum chip 16, the readout circuits 18, and the control circuits 20 are based on superconducting technologies and are provided in a refrigerated environment (cooled by a cryogenic refrigeration system (e.g. a dilution fridge or cryostat) of the system 1, not shown in Figure 1) at temperatures of less than the respective superconducting transition temperatures to function.

[0052] The quantum chip 16 which comprises a plurality of quantum bit units (“qubits” for short). Some of the qubits may be coupled to other qubits via respective couplers (the term “coupler” or “coupler circuit” as used herein refers to a physical device that allows one qubit to influence another qubit). In the embodiment of Figure 1, the qubits are superconducting quantum circuits (e.g. fluxonium qubits: other types of superconducting qubits can also be used).

[0053] Each readout circuit 18 is coupled to a corresponding qubit and configured to output a readout signal indicative of a quantum state of the corresponding qubit. The readout signal may be a digital signal specifying a measurement result of a measurement performed on the corresponding quantum bit unit (the measurement may be performed by the readout circuit). In the embodiment of Figure 1, each readout signal may be represented by one bit. In other embodiments, each readout signal may be represented by more than one bit (e.g. when the readout signal represents amplitude and phase information associated with the quantum state of the corresponding quantum bit unit).

[0054] Each readout circuit 18 comprises classical superconducting digital logic circuits located in proximity of the corresponding qubit. More specifically, the readout circuits 18 comprise known superconducting single-flux quantum (SFQ) circuits, and the readout signals (output by the readout circuits 18) comprise SFQ pulses (e.g. a logical 0 (1 ) state may be represented by the absence (presence) of a SFQ pulse).

[0055] The control circuits 20 are configured to manipulate the qubits (e.g. to implement a corresponding quantum program). The control circuits 20 comprise classical superconducting digital logic circuits, in particular known SFQ circuits.Attorney Docket No. 133858.8016.WO00

[0056] The use of SFQ circuits to implement the readout circuits 18 and the control circuits 20 is advantageous since SFQ circuits can be provided in a dilution fridge or cryostat in close proximity to the superconducting qubits minimizing the number of connections to room temperature electronics and reducing the control signal latency.

[0057] Generally, SFQ digital logic circuits generate, manipulate and store classical bits of information, or logical “0” and “1” values, using voltage pulses, or fluxons, that propagate ballistically along passive superconducting microstrip lines or active Josephson transmission lines. That is, classical bits of information are stored by way of a presence or absence of a phase slip across a Josephson junction in a given clock cycle. The phase slip results in a voltage pulse whose time integral is precisely quantized to the superconducting flux quantum Φ0= h / 2e, where h is Planck’s constant and e is the elementary charge carried by a single electron (1.6 x 10-19C).

[0058] SFQ circuits for implementing the control circuits 20 and the readout circuits 18 are generally known. For example, Yamanashi, Yuki et al. “100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA / cm2 Nb Multi-Layer Process." IEICE Trans. Electron. 93-C (2010): 440-444, discloses a library of standard SFQ cells which may be used in the implementation of the control circuits 20 and the readout circuits 18.

[0059] In some implementations, the readout circuits 18 may be configured to perform qubit readout of a superconducting qubit by performing a measurement that detects a qubit-state-dependent shift of a resonance frequency of a high Q resonator that is (dispersively) coupled to the qubit. For example, the readout circuits 18 may comprise circuity that detects a shift of the resonator frequency by probing the resonator with microwave tones and measuring, using SFQ logic, the response in phase and / or amplitude. As one specific example, the readout circuits 18 may comprise one or more of the Josephson digital phase detectors as described in L. Di Palma et al., “Discriminating the Phase of a Coherent Tone with a Flux-Switchable Superconducting Circuit” Phys. Rev. Applied 19, 064025, 2023.

[0060] In some implementations, the control circuits 20 are configured to control the qubit and coupler degrees of freedom using SFQ logic. In general, superconducting qubits and couplers may have two types of degrees of freedom, flux and charge. Qubit charge and flux degrees of freedom generally need to be controlled. For example,Attorney Docket No. 133858.8016.WO00coherent control of the qubits may be achieved by irradiating qubits with trains of quantized flux pulses produced using Single Flux Quantum (SFQ) digital logic. For typical parameters, SFQ pulse amplitudes are of order 1 mV and pulse durations are around 2 ps, which is roughly two orders of magnitude shorter than the typical qubit oscillation period. As a result, each SFQ pulse imparts a delta function-like kick to the qubit that induces a coherent rotation in the qubit subspace. The couplers’ flux degrees of freedom may be controlled by the control circuits 20 or may be static.

[0061] In some implementations, the control circuits 20 are a combination of circuits comprising charge control circuits (for driving charge degrees of freedom directly with SFQ voltage pulses, which are used for performing rotations in the single qubit Bloch sphere), and flux control circuits (for driving the flux degrees of freedom indirectly using storage inductors mutually coupled to superconducting qubit loops). The flux stored in the storage inductors may be directly controlled using SFQ pulses, which each impart a single flux quantum of flux. Flux can be incremented and decremented in the storage inductor digitally using SFQ pulses.

[0062] Figure 2 illustrates a specific example circuit to implement coherent control of a superconducting qubit. In this example, the qubit is a fluxonium qubit comprising a Josephson Junction (JJ) 28, a capacitor 30 and an inductor 32 each arranged in parallel with one another. Ej is a measure of the strength of the coupling across the Josephson Junction, Ecis the energy needed to increase the charge on the capacitor by “e”, where “e” is a single electron charge, and EL is the inductive energy of the qubit.

[0063] A JJ comprises a tunnel barrier between two superconductors. The fluxonium qubit is a type of so-called flux qubit where the two energy levels that form the qubit are a superposition of the two energy states, for example, corresponding to the current flow in opposing directions through the Josephson junction 28. In this example, the inductance is shown as an inductor. However, the inductance may be provided by JJs. To switch the qubit from an (eigen) energy state to a superposition of states, the qubit is provided with energy to cause a transition between the ground state and excited state. This can be achieved using the control circuit 34 which is inductively coupled to the qubit. The qubit control circuit 34 induces a current across its inductor 32 which induces a magnetic flux through the qubit. In order to correctly excite theAttorney Docket No. 133858.8016.WO00superposed state, the current across the inductor of the control circuit needs to be carefully varied in time, i.e., have precise values at certain times.

[0064] To achieve this control, in an embodiment, the qubit control circuit 34 comprises single flux quantum (SFQ) circuits. Figure 3 is a diagram of a respective example SFQ circuit 36. A simple form of SFQ circuit is a loop of superconducting wire with Josephson Junctions 38 which can hold (store) a single quantum of magnetic flux Φ0. Josephson junctions enable the insertion or release of single flux quantum (SFQ) from this loop. The serially connected pairs of Josephson junctions (J2, J3) allow conditional release of the stored SFQ from the loop upon arrival of clock / reset SFQ. Releasing SFQ from the loop produces and output SFQ pulse. An SFQ pulse produced in this manner has a fixed area under its curve which corresponds to the flux quantum Φ0.

[0065] The use of an SFQ circuit to apply a flux to the qubit has two strong advantages:1 ) The quantised single flux quanta pulses allow the energy provided to the qubit to be very carefully controlled; and2) SFQ circuits can be provided in a dilution fridge or cryostat in close proximity to the qubits minimizing the number of connections to room temperature electronics and reducing the control signal latency.

[0066] The qubit control circuit 34 may be configured to produce a flux pulse profile by using SFQ pulses to depositincrements of magnetic flux in superconducting inductive loop to produce a magnetic flux profile which will allow the state of the qubit to be changed.

[0067] It is to be understood that the circuits of Figures 2 and 3 are mere example circuits and that the qubits, the readout circuits and the control circuits may be implemented using any suitable circuitry.

[0068] Referring back to Figure 1, the classical computer model 12 is a conventional computing device provided outside of the refrigerated environment (e.g. at room temperature). In broad terms, the classical computer 12 is in communication with the QPU 10 to enable transmission of instructions to the QPU 10 and reception of readout data from the QPU 10 (e.g. readout data obtained in response to performingAttorney Docket No. 133858.8016.WO00the instructions). More specifically, the classical computer model 12 comprises a processing module 22, a system memory 24 (partitioned into blocks of words, i.e. each block may be a contiguous part of the memory that comprises one or more words (having a word size matching the bus width of the classical computer 1, e.g. 64 bits)) and an application software 26.

[0069] The application software 26 is an application configured to run on the classical computer 12. The application software 26 may define instructions for QPU 10, i.e. the application software 26 may define a quantum program (i.e. a sequence of qubit control and qubit readout operations to be performed by the QPU 10). Normally, a user of the system 1 interacts with the classical computer 12, rather than directly with the QPU 10. For example, a user may provide input to the application software 26 to define a specific quantum program (once performed, the classical computer 12 may provide results obtained by performing the specified quantum program back to the user). The term “quantum program” may mean a predefined sequence of qubit control operations (performed on (some of) the qubits by the control circuits 20) and qubit readout operations (performed on (some of) the qubits by the readout circuits 18).

[0070] The processing module 22 is configured to read data from the system memory 24 and process the data as required, e.g. by the application software 26. For example, the processing module 22 may process readout data received from the QPU 10 and stored in the memory 24 to determine a result of a quantum program performed by the QPU. To this end, the processing module 22 may comprise one or more of: a CPU, a GPU, and a FPGA.

[0071] The classical computer module 12 may receive readout data from the QPU 10 via the physical layer 14 (it is to be understood that the classical computer module 12 may use a different physical layer to send instructions to the QPU 10, not shown in Figure 1). As further described below with reference to Figure 4, the physical layer 14 is configured to receive, as input, readout signals from the readout circuits 18 and to transmit the readout data to the system memory 24, which stores the readout data at predefined memory address ranges of the system memory 24, e.g. by direct memory access (DMA). In other words, the physical layer 14 implements (independent of the implementation details of the QPU 10) a direct mapping between its input and predefined locations in the system memory 24. To enable the classical computer modelAttorney Docket No. 133858.8016.WO0012 to process the received readout data correctly, a corresponding “memory map” is stored on the classical computer model 22 which specifies a mapping between the readout circuits 10 and corresponding locations in the system memory 24. This memory map depends on the specific implementation of the QPU 10 and may be provided alongside the QPU 10 (e.g. by the manufacturer of the QPU 10) to enable the user / writer of the application software 26 to interpret the readout data stored in the system memory correctly (an example memory map will be described further below with reference to Figure 3). Because the application software 26 “knows” from the memory map how to interpret the incoming data, the readout data can be transferred from the QPU 10 to the classical computer 12 without the overhead of transmitting additional “header” or “meta” data which is conventionally used to “explain” to the classical computer what to do with the received data.

[0072] As noted above, the readout circuits 18 of the QUP 10 are provided within the refrigerated environment while the classical computer model 12 is provided outside the refrigerated environment, in practice, strict thermal management requirements mean that dense wiring from the refrigerated environment to the classical computer 12 Is not possible. In other words, the maximum number of independent communication channels (i.e. physical links) supported by the physical layer 14 is limited by the thermal, electrical and mechanical properties of the transport medium materials (i.e. the materials used to implement the communication channels) and the integration into the refrigerator. Thus, the number of readout circuits is usually much higher than the number of communication channels, which means that it is normally not possible to provide a dedicated communication channel for each individual readout circuit. As described in the following with reference to Figure 4, the computer system 1 (in particular, the arrangement of the readout circuits 18, the physical layer 14 and the system memory 24) provides an elegant and scalable solution that enables high speed / low latency transfer of readout dafa to the classical computer in such a scenario.

[0073] As shown in Figure 4, the readout circuits 10 are grouped into N “readout groups” 40, i.e. each readout group 40 comprises a plurality of readout circuits coupled to a respective plurality of qubits. In the embodiment of Figure 4, the number of readout circuits in each readout group 40 is the same (in other embodiments, the number of readout circuits in each group 40 may be different). Similarly, a contiguous portion of the system memory 24 (i.e. a portion of the system memory 24 that Is allocated to theAttorney Docket No. 133858.8016.WO00application software 26) is partitioned into N “word blocks” 42 (each word block 42 is associated with a corresponding readout group 40). Each word block 42 may be formed by one or more words. The number of words in a specific word block may be selected based on the number of readout circuits that belong to the corresponding readout group (or, more precisely, based on the number of bits output by the readout group). As one example, in an embodiment where each readout group is formed by 60 readout circuits (each outputting a corresponding readout signal that can be presented by one bit) and the word size of the classical computer module 1 is 64 bits, each word block 42 may be formed by a single word. As another example, in an embodiment where each readout group is formed by 100 readout circuits (each outputting a corresponding readout signal that can be presented by one bit) and the word size of the classical computer module 12 is 64 bits, each word block 42 may be formed by a two words.

[0074] The physical layer 14 is configured to implement a one-to-one mapping of the readout groups 40 to the words blocks 42 of the system memory 24 (so as to implement a one-to-one mapping of individual readout circuits to memory addresses in the memory portion allocated to the application software 26), i.e. the physical layer 14 maps readout signals received from different readout groups to different word blocks 42. As noted above, this mapping is specified in the memory map stored on the classical computer 1, so that the application software 26 can correctly interpret the data read from the word blocks 42 of the system memory 24.

[0075] As shown in Figure 4, the physical layer 14 comprises a device endpoint 44 comprising N cryogenic transmitter modules 46, a physical transport medium 48 comprising N channels 50, and a host endpoint 52 comprising N receiver modules 54. Each cryogenic transmitter modules 46 is coupled to a corresponding receiver modules 54 of the host endpoint 52 via a corresponding channel 50 of the physical transport medium 48. In broad terms, the device endpoint 44 is located within the refrigerated environment and is configured to receive N inputs (of equal bit depth) from the N readout groups 40, and provide the input from each readout 40 onto a dedicated channel 50 of the physical transport medium 48. More specifically, each of the N cryogenic transmitter modules 46 is configured to receive in parallel the readout signals (i.e. SFQ logic pulses) from the plurality of readout circuits of the corresponding readout group 40, and to format the received readout signals to be suitable for transmission over the corresponding channel 50, i.e. to serialize the received readout signals into aAttorney Docket No. 133858.8016.WO00corresponding stream of digital signals (e.g. using known line encoding methods), convert the digital signals from SFQ logic to CMOS-compatible level logic, and provide the resulting stream of level-logic digital signals to the corresponding channel 50 (example implementations of the transmitter modules 38 are described further below with reference to Figures 6 and 8).

[0076] The channels 50 of the transport medium 48 extend from the device endpoint 44 located within the refrigerated environment to the host endpoint 52 located outside the refrigerated environment (i.e. each channel 50 comprises a first end coupled a corresponding cryogenic transmitter module 46 and a second end coupled to a corresponding receiver module 54). The output of the channels 50 are fed into the host endpoint 52 which recovers the transmitted data and provides the recovered data to the corresponding word blocks 42 of the system memory 24. More specifically, each receiver module 54 of the host endpoint 52 is configured to receive the stream of serialized data (i.e. N bit-strings of equal length) from the corresponding channel 50, to the recover the transmitted data (i.e. deserialize the serialized data according to the employed line encoding) and provide the recovered data to the corresponding word blocks 42 of the system memory 24 (e.g. using a protocol supported by the classical computer 12, e.g. PCIe).

[0077] With reference to Figure 5, a specific example memory map 43 is described which specifies a mapping of the readout circuits 10 to specific locations within a portion 45 of the system memory 24 that is allocated to the application software 26. In this example, the allocated memory 45 comprises N * M * K bits partitioned into N word blocks each consisting of M words (with a word size of K bits). The memory map 43 specifies a mapping of N * M * K readout circuits (grouped in N readout groups) to the N * M * K bits of the allocated memory 45. For example, the memory map 43 of Figure 3 specifies that the readout signal of the readout circuit 1 is stored in “bit 1" (indicated with reference numeral 47) of “word 1” (reference numeral 49) of the “word block 1” (reference numeral 51) of the allocated memory 45, and so on. The memory map 43 may be stored on the classical computer 12 in a human-readable data format as illustrated in Figure 3 (in other embodiments, the data format of the memory map 43 may be different). As noted above, the application software 26 has access to the memory map 43 (directly or indirectly (e.g. via drivers)) to interpret the data stored in allocated memory 45. In this example, one bit corresponds to one readout circuit; inAttorney Docket No. 133858.8016.WO00other embodiments, multiple bits may be used to represent a single readout circuit. In practice, the memory map 43 may be generated or provided when a new instance of the physical layer 14 Is installed between the QPU 10 and the classical computer 12.

[0078] By using a pre-defined memory map, the application software 26 interprets QPU readout data without the need for embedded metadata or headers. This approach reduces latency and latency variation. This is because the use of metadata or headers requires “parsing” (i.e. processing by the receiving device) which takes variable amounts of time. The proposed architecture eliminates the “computational tax” of real¬ time protocol parsing, transforming the communication link into a deterministic path where latency is governed by physical propagation delay rather than software overhead. By removing the requirement to transmit descriptors for each digital signal, the system can achieve wire-speed performance, effectively saturating the hardware’s line rate (e.g. in some implementations, the transmitter modules transmit the streams of digital signals at data transfer rates exceeding 90% of the wire speed). This ensures that the data transfer speed is limited only by the physical properties of the interface, providing a fixed-latency profile which is advantageous for high-performance quantum-classical feedback loops.

[0079] With reference to Figure 6, a first example implementation of the transmitter module 46 will now be described. The transmitter module 46 comprises a clock 56, a line code encoder 58, a serializer module 60, a SFQ-to-DC converter 62. The clock 56 is configured to provide respective clock signals to the line code encoder 58, and the serializer module 60. The line code encoder 58 is configured to receive the plurality of SFQ-formatted readout signals from the corresponding readout group 40 (the readout signals are fed in parallel into the line code encoder 58). The line code encoder 58 comprises combinatorial logic blocks for implementing a known line code (for example a Manchester code or a 8b / 10b code) and is configured to apply these combinatorial logic blocks to the received readout signals. The line code encoder 58 is coupled to the serializer module 60 which receives the output of the line code encoder 58, i.e. the readout data in line code representation (the individual output signals of the line code encoder 58 are fed in parallel into the serializer module 60 either synchronously or asynchronously). The serializer module 60 may be a “stateful” component that can be in one of two states, “armed” or “writing”. In the “armed” state, the serializer module 60 may be triggered (by receiving a corresponding trigger signal 64) to initialiseAttorney Docket No. 133858.8016.WO00serialization of the input bits. Once triggered, the rate of serialization may be set by the clock signal received from the clock 56 (which determines the data transmission rate of the readout data on the channel 50). In the writing state, the serializer module 60 does not respond to the trigger signal 64 (the serializer module 60 may be in the writing state for the duration of the serialization of the input bits). The serialized SFQ signals output by the serializer module 60 are coupled to the SFQ-to-DC converter 62 which is configured to convert the serialized SFQ signals to level-logic signals (e.g. by generating level-logic signals based on the serialized SFQ signals) suitable for transmission over the channel 50 (an example implementation of the serializer module 60 is described below with reference to Figure 7). In particular, the SFQ-to-DC converter 62 may convert the serialized SFQ signals to CMOS-compatible level-logic signals. The output of the SFQ-to-DC converter 62 (a stream or “burst” of CMOS-compatible levellogic signals) is coupled to and transmitted over the channel 50. Designs of suitable SFQ-to-DC converters are known to those skilled in the art.

[0080] In some embodiments, the trigger signal 64 may be provided simultaneously to all N serializer modules 60 to synchronise the serialization (and thus the start of transmission) of readout groups 40 (however, in other embodiments, the trigger signals 64 provided may be asynchronously provided to the serializer modules 60). Many suitable ways of generating the trigger signal 64 exist. As a first example, the QUP 10 may generate the trigger signal 64, e.g. in response to determining that a quantum program or a certain portion or step of such quantum program has been completed. As a second example, the trigger signal 64 may be generated periodically by a respective trigger generator module (not shown in the Figures). As a third example, the trigger signai 64 may be caused by the application software 26 (e.g. the application software may send instructions (i.e. a “software” trigger) to generate the trigger signal 52, e.g. to the QUP 10).

[0081] The serializer module 60 may be implemented using known SFQ circuits. As a mere example, a specific implementation of the serializer module 60 will now be described with reference to Figure 7. The example circuit of Figure 7 comprises an array of NDRO (non-destructive read out) circuits (a type of SFQ circuit known to those skilled in the art) that receive respective input signals from the line code encoder 58 (in other implementations, the array of NDRO circuits may receive respective input signals from readout circuits 18, e.g. when the serializer module also provides the line encoding asAttorney Docket No. 133858.8016.WO00described below with reference to Figure 8). The NDRO array implements a register. The outputs of the NDRO array are connected to respective TFFs (toggle flip flops circuits, also known to those skilled in the art). The TFFs are daisy chained (connect together in a linear series) from output to input, and each parallel bit is joined to the daisy chain. The TFFs can be loaded synchronously once all the NDROs are loaded, by clocking the NDRO with a trigger signal (e.g. trigger 64). Finally, a high-speed clock, operating at the desired bit rate of the protocol drives the TFF array, which then writes the serial data to a single output. In other words, once all inputs bits 1 to M have arrived at the NDROs, the trigger signal is provided to move the values in the TFFs. Then, a “clear” signal is applied to the NDROs to wipe them ready for the next data set. Once the trigger signal has been asserted, the fast clock signal can be enabled to write the data serially to “serial out”. Thus, the trigger signal allows synchronization with other serializers in parallel.

[0082] With a reference to Figure 8, a variation of the transmitter module will now be described. The transmitter module 46’ of Figure 8 is identical to the transmitter module 46 of Figure 6 except that the transmitter module 46’ of Figure 8 comprises a circuit (serializer module 60’) that is configured to perform both the line encoding and the serialization of the input bits, and that the SFQ-to-DC converter 62' is configured to receive the output from the serializer module 60’ and the clock signal from the clock 56. Thus, in this embodiment, the serializer module 60’ receives, as inputs, the plurality of SFQ-formatted readout signals from the corresponding readout group 40 (the readout signals are fed in parallel into the serializer module 60’), the clock signal and the trigger 64, and generates line encoded, serialized SFQ signals for the SFQ-to-DC converter 62.

[0083] The serializer module 60’ may be configured to generate a line code representation of the readout signals after the readout signals have been serialized. A specific example implementation that can create a Manchester code is illustrated in Figure 9. In this example, pulses that correspond to the qubit readout state are provided at odd or even clock cycles. Driving the SFQ-to-DC converter with this pulse sequence results in a Manchester code output compatible with CMOS logic. In Figure 9, the label " SFQ / DC input” indicates the driving of the SFQ-to-DC converter which results in the encoded signal indicated by the label “Manchester encoding”. Since in a Manchester code, there is a transition at a half-clock period, this corresponds to the SFQ clock shifterAttorney Docket No. 133858.8016.WO00by half a pulse. Additional pulses are placed when there are more than one back-to- back “0” or ‘1 ", which can be verified with additional (known) circuitry. In other words, no additional pulses need to be added when the data is a repeating "10” bit-string. The data can be fed into two D-flip-flop cells which current two values can be compared using a NOT(XOR) gate result to indicate that an additional pulse needs to be added.

[0084] It is to be understood that the above-described transmitter module(s) 46, 46' may comprise further optional features as required by the specific application. For example, the transmitter module may comprise appropriate circuitry (e.g. incorporated in the line encoder or the serializer module) to generate the level-logic output in way that enables the host endpoint 52 to perform “channel bonding”. In these embodiments, the trigger 64 may be used to trigger the generation of an alignment sequence before sending the data payload. This alignment sequence can be stripped out by the host endpoint 52 and is not provided to the system memory 24.

[0085] Further, the above-described transmitter module may, optionally, further include circuity to implement error mitigation and / or classical error correction techniques, e.g. to mitigate / correct classical errors caused by the transmission over the physical layer, in general, error mitigation techniques and classical error correction methods / codes are known from classical digital communication where a sender adds redundant bits to help the receiver / decoder to find out the true message that was encoded by the transmitter. The redundant bits that protect the information are transferred using the same communication resources thai they are trying to protect. This causes a trade-off between reliability and data rate. The code-rate of a given error correction code may be defined as the ratio between the number of information bits and the total number of bits (i.e. information plus redundancy bits) in a given communication burst / package. In error mitigation, the transmitter uses additional bits to encode the data in a way that is more robust against errors occurring during transmission (an example error mitigation technique is described below in more detail). In contrast, error correction methods involve a transmission from the receiver back to the transmitter. More specifically, in classical error correction methods, the receiver determines whether the payload data of a received data packet has an error and if so, sends the data packet back to the sender to request the data again (i.e. to request a corrected data packet). This introduces more latency and increases the complexity of the transmitter compared to error mitigation techniques, because the transmitter that transmitted the erroneousAttorney Docket No. 133858.8016.WO00data must be able to wait for a correction request, interpret the request correctly and send the corresponding data again on demand.

[0086] In some embodiments, the above-described transmitter module is further configured to implement an error mitigation technique (i.e. to add redundant bits to the generated stream of level-logic digital signals that is provided to the corresponding channel 50 to reduce the effect of errors occurring during the transmission through the channel 50) and is not configured to implement a classical error correction code. For example, the transmitter module may be further configured to provide a plurality of temporally spaced copies of the serialized data to the channel 50 (e.g. transmitter module may subsequently transmit three copies of the serialized data). Such an error mitigation technique may enable the computer 12 to determine the “true” values of the serialized data, e.g. by performing respective parity checks between the received copies, without having to request the transmitter module to retransmit the data (as in classical error correction codes). Omitting classical error correction reduces the latency of the transfer of the readout data and reduces the complexity and footprint of the transmitter module. The inventors have realised that, in some implementations, advantages of omitting classical error correction (e.g. reduced latency) may outweigh any disadvantages caused by the absence of classical error correction because the classical error rate (also due the error mitigation technique) is often several orders of magnitude lower than the quantum error rate caused by imperfections of the quantum computer (noise, decoherence, gate errors, readout errors, etc.). Thus, any error in the digital readout data received by the classical computer model is most likely caused by quantum computing errors. This means that omitting classical error correction does not significantly increase the error rate of the data that the classical computer model eventually stores in the system memory. Thus, in some implementations, the proposed techniques use a one-way (simplex) data flow, where the transmitter modules are configured to stream raw digitised readout data to the classical computing device without a return feedback channel, acknowledgment ioop or the like (e.g, the transmitter modules may be configured to not re-transmit the serialised data). By operating in such a “fire-and-forget” mode, latency overhead associated with bi-directional handshaking is eliminated. This absence of a backchannel ensures a strictiy deterministic throughput, as the communication is never interrupted by classical error-correction protocols, flow-Attorney Docket No. 133858.8016.WO00control negotiations or the like. Consequently, a high-speed, forward-only pipeline can be realised.

[0087] Further, in some embodiments, the above-described transmitter module is neither configured to implement an error mitigation technique nor to implement a classical error correction method. That means that the transmitter module may be configured to use the full channel for information transfer purposes (i.e. to implement a code-rate equal to 1). In other words, the transmitter module may be configured to serialize the readout signals into a corresponding stream of digital signals without adding redundant information, e.g. without adding / encoding redundant bits (i.e. bits other than ones from the readout signals).

[0088] With reference to Figure 10, an example implementation of the receiver module 54 will now be described. The receiver module 54 comprises clock recovery module 66, a decoder module 68, and a clock 70. The clock 70 is configured to provide clock signals to the clock recovery module 66 and the decoder module 68 (the clock 70 of the receiver module 54 may be operating at substantially the same clock rate as the clock 56 of the transmitter module 46). In broad terms, the clock recovery module 66 implements a clock and data recovery method (any known and suitable clock and data recovery method may be used, e.g. as described in US 7,197,102 B2) to correct for dispersion and jitter of the incoming data (caused by the transmission over the channel 40) and / or relative phase and frequency drifts of the clocks 56, 70. Thus, the clock recovery module 66 is configured to receive, as input, the stream (or “burst”) of levellogic signals from the output of the channel 50 and to correct the input level-logic signals and / or the clock 70 based on the input signals (e.g. the clock recovery module 66 may generate, as output, clean level-logic signals based on the received level-logic signal, and / or may stabilise the phase and frequency of the clock 70 based on the arrival timings of the input signals). The “clean” output of the clock recovery module 66 is provided to the decoder module 68 which is configured to (on the fly) deserialize the input data (i.e. by performing line decoding of the input data matching the line code used by the line code encoder 58) and to provide, as output, deserialized digital data. The decoder module 68 component maybe a stateless component to be able to process incoming data as it arrives. The decoder module 68 may have an internal buffer memory that allows downstream digital circuits to operate asynchronously.Attorney Docket No. 133858.8016.WO00

[0089] The decoder module 68 interfaces the host endpoint 52 with the system memory 24 via a supported host link protocol 72 (for example PCIe). The host link protocol 72 implements a connection to system memory 24 to enable writing into the word block 30 associated with the readout group 40. The host link protocol 72 may perform packaging and streaming of the data output of the decoder module 68 to the system memory 24 using direct memory access methods via bus mastering supported by the host link protocol 72 (to allow data to be written directly to the host system memory without consuming host processing resources because of the required bus control).

[0090] In broad terms, the system 1, described above with reference to Figures 1 to 10, reduces complexity and overhead at the output side. This is achieved by on-chip digitization (i.e. digitization at the cryogenic side of the system) compressing the information in the readout signal to contain only the relevant information, namely the state of the qubit. As a result, there is no overhead and extra infrastructure required for demodulation and post-processing (since this is effectively done on-chip). Further, the compressed (i.e. digitized) information has significantly lower bandwidth requirements, which makes it more suitable for time-domain multiplexing, or serialization. Moreover, compared to using frequency-mixed microwave readout signals, significantly more readout bits can be transmitted per output cable as a result of the on-chip compression / digitization.

[0091] In some implementations, it can be advantageous to transmit serialised digital signals rather than analogue microwave signals because the number of bits that can be transmitted over a single serial connection depends mostly on the bit duration (which can be much shorter than microwave pulses). For example, some implementations may achieve 10 Gbps or more on a single line. Thus, using the proposed system and protocol, a 1 microsecond-long transmission with a bit rate of 10 Gbps can in principle encode the readout data of 10000 qubits on a single output cable. For comparison, known readout protocols address 6 qubits with a microwave pulse duration of 1 microsecond on a single input and output cable. Therefore, in system with large numbers of qubits (say tens of thousands of qubits) and where the readout inputs pulses are microwave analogue pulses and the readout outputs are digital using our scheme, the proposed system makes it possible to almost halve the total number of data transmission cables required. For example, for 10000 qubits and 5 qubits perAttorney Docket No. 133858.8016.WO00feedline, 2000 feedlines are needed for the input, and only one 10 Gbps output line is needed for the readout (i.e. 2001 lines total), whereas known system require about 4000 feedlines.

[0092] With reference to Figure 11, an example transmission process S1100 will now be described in which readout data is transferred form the QPU 10 to classical computer 12. In an initial step S1101, a portion of the system memory 24 is allocated to the software application 26 for receiving readout data from the QPU 10. The software application 26 may provide instructions to the QPU 10 to perform a quantum program which comprises a series of qubit control instructions and qubit readout instructions. In step S1102, the QUP 10 performs a readout operation according to the instructions by the application software 26, i.e. the readout circuits 18 (grouped in readout groups 40) output (in parallel) readout signals to the corresponding transmitter modules 46 of the device endpoint 44 of the physical layer 14 (thus, the device endpoint 44 acquires the requested readout data). In step S1103, the transmitter modules 46 of the device endpoint 44 receive respective trigger signals 64 (as noted above, the trigger signals 64 may be generated in any suitable manner; in many embodiments, the trigger signal 64 is provided to all the transmitter modules 46 simultaneously) which triggers the serialization of the readout data by transmitter modules 46 and the transmission of the serialized data over the over the transport medium 48. The serial data is then received and deserialized by the host endpoint 52 (S1106). In step S1107, the deserialized readout data is then written to the designated word blocks 42 in the allocated memory. Thus, the system memory 24 is now updated and the stored readout data may now be consumed by the application software 26 (the application software 26 may be made aware of the new / updated readout data in any suitable way, examples possibilities are described further below).

[0093] It is desirable to implement quantum error correction techniques to correct for qubit errors which might occur when the QPU 10 performs a particular quantum program. Many quantum error correction techniques exist. A common principle of these techniques is the performance of a “syndrome” qubit readout operation during the quantum program (i.e. before the quantum program is completed) to obtain a “syndrome” readout signal. The value of the syndrome readout signal is indicative of the presence or absence of a particular error (e.g. a single qubit flip error). The syndrome readout signal is then processed to by a classical computing device toAttorney Docket No. 133858.8016.WO00generate instructions for a qubit controi operation that corrects the detected error. After the correcting control operation is performed, the quantum program may be continued.

[0094] Thus, to implement a quantum error correction technique, the quantum program may be arranged (or programmed) as a plurality of “instruction layers” and an associated plurality of “readout layers”. Each instruction layer may comprise specific qubit control instructions and each readout layer may comprise specific syndrome readout instructions. The instruction layers and the readout layers may be alternatingly performed by the QPU 10 (e.g. a first instruction layer may be followed by a first readout layer which may be followed by a second instruction layer, and so on). After each readout layer, syndrome readout data may be processed to determine whether the next instruction layer needs to be modified (e.g. to include an error correcting operation). Thus, it such an implementation, it is important that the syndrome data is processed by the classical computing device before the next instruction layer needs to performed (e.g. long delays between performing subsequent instruction layers may cause further errors). Since the transmission process S1100 described above enables high-speed / low-latency transmission of readout data, the transmission process S1100 is particularly well-suited for implementing quantum error correction techniques.

[0095] With reference to Figure 12, an example process of implementing quantum error correction using the process S1100 of Figure 11 will now be described. In an initial step S1201, the application software 26 is started, e.g. causing the QUP 10 to be initialised and a portion of the system memory 24 to be allocated. In step S1202, the application software 26 prepares (i.e. generates) a plurality of instruction layers and an associated plurality of readout layers to implement a specific quantum program (e.g. a user of the computer system 1 may define the quantum program by providing input to the classical computer 12 (S1203)). The quantum program is then performed over a number of iterations. In the first iteration, the application software 26 sends the first instruction layer and the first readout layer to the QUP 10 (S1204). The QUP 10 performs the qubit control operations specified in the first instruction layer (S1205), and subsequently the syndrome readout as specified in the first readout layer (S1206). Then, the device endpoint 44 is triggered to initialise the transmission of the acquired syndrome data (S1207). Next, the syndrome data is transmitted using the process S1100 described above with reference to Figure 7 (S1208). In step S1209, the application software 26 reads the syndrome data stored in the respective word blocksAttorney Docket No. 133858.8016.WO0042 to determine whether an error occurred during the performance of the first instruction layer and, if so, to generate correcting instructions and to apply these correcting instructions to the next (i.e. the second) instruction layer (if the application software 26 determines that no error occurred, the next instruction layer is not be modified). Steps S1204 to S1211 are then performed for the second (possibly corrected) instruction and readout layers. Further iterations are performed in the same manner until the last instruction and readout layers are performed and the process is completed (S1212).

[0096] Generally, it is useful for the application software 26 to be able to determine when new readout data has arrived (e.g. to reduce delays in processing the readout data). To this end, a “block status indicator signal” (i.e. a signal that indicates to the application software 26 that new data has been written into a particular word block 42) may be provided to the classical computer 12. This signal can be generated in a number of suitable ways. As a first example, the “block status indicator signal” may be periodically generated (e.g. by the classical computer 12). As a second example, the “block status indicator signal” may be provided in form of “flag data” encoded in the output data provided by the decoder module 68. This may be achieved by selecting the number of readout circuits in the readout groups 40 to be less than the size of the word blocks 42, so that the “unused bit(s)” may be used to implement the flag. For example, the number of readout circuits in the readout groups 40 may be 63, and the word blocks 42 may consist of a single 64-bit word. In this case, the line code encoder 58 of the transmitter module 46 or the decoder module 68 may set the unused bit, say the first bit, to a predefined state, say the logical 1 state. Thus, the application software 26 can then determine that new readout data has arrived by determining that the first bit of a word block 42 has changed from an initialised state (i.e. logical state 0) to a logical 1 state (the application software 26 may then clear / reinitialise this bit to be able to determine the arrival of the next readout data). Thus, by encoding flag data into the output of the host endpoint 52 latencies may be reduced (i.e. the time between writing of the readout data into the system memory 24 and the consumption of the newly stored readout data by the application software 26).

[0097] A third example of providing the “block status indicator signal” will now be described with reference to Figure 13 which illustrates an alternative implementation of the receiver module. The receiver module 74 of Figure 13 is largely identical to the receiver module 54 described above with reference to Figure 10, except that theAttorney Docket No. 133858.8016.WO00receiver module 74 comprises an “enhanced” decoder module 78 and a status indicator circuit 76. The “enhanced” decoder module 78 is configured as the decoder module 68 described above, except that the “enhanced” decoder module 78 is further configured to provide, in response to receiving a burst of serial signals from the clock recovery module 66, a signal to the status indicator circuit 76. The status indicator circuit 76 is configured to, in response to receiving the signal, provide the “block status indicator signal” in form of “flag data” (e.g. consisting of a single bit in the logical 1 state) to the classical computer 12 by storing the flag data into a predefined memory location of the system memory 24 that is different from word blocks in which the deserialized readout data is stored. Thus, the flag data allows the application software 26 (monitoring the memory location associated with the flag data) to determine whether new readout data has arrived from the corresponding readout group 40, For example, the memory location associated with the flag data may be initialised in the logic 0 state, and may be changed to the logical 1 state by the status indicator circuit 76 in response to receiving the signal from the decoder module 78. Thus, the application software may monitor the memory location associated with the flag data and may determine from the change of the bit value that new readout data has been arrived. Thus, the application software 26 may then read and process the data stored in the corresponding word block 30 (the application software may then clear / reinitialise the bit value of the memory location associated with the flag data to be able to determine the arrival of the next readout data). Thus, the receiver module 74 of Figure 13 enables the application software 26 to determine whether new readout from any particular readout group has arrived without reducing the memory space of the word blocks 42 available for readout data.

[0098] As a fourth example, the “block status indicator signal” may be generated by a hardware interrupt. In this case, the classical computing device may run a further software application (e.g. a driver / firmware) that is triggered by a hardware interrupt originating from (i.e. caused by) the host endpoint 52 (e.g. host link protocol 72). The further software application is configured to, in response to being triggered by the hardware interrupt, trigger the application software to start consuming the newly stored readout date. The hardware interrupt acts as the status indicator and is cleared by the CPU. Thus, in such implementations, the application software 26 may not need to “poll” or clear the block status indicator signal. In some implementations, the host endpointAttorney Docket No. 133858.8016.WO00hardware may assert the hardware interrupt after the deserialized data has been sent to the system memory.

[0099] Depending on the specific application / quantum program, the application software 26 may have different synchronisation requirements. For example, the application software 26 may require that the readout signals of all readout groups 40 have been written into the respective word blocks 42 before the newly stored readout data is to be processed (referred to as “synchronous memory updating"). Alternatively, for some embodiments of the application software 26 it may be beneficial to process a newly updated word block 42 as soon as it is written even if other word blocks 42 have not yet been updated (referred to as “asynchronous memory updating").

[0100] An example process of operating the computer system 1 with “asynchronous memory updating” will now be described with reference to Figures 14 and 15. As illustrated in Figure 14, even when all transmitter modules are triggered simultaneously, the serial bursts 90 may arrive at the receiver modules 54 at different times. This is because each channel of the physical layer 14 is independent and may have slight variations in their physical properties. Since the transmitter modules 54 are independent of each other, and each transmitter module 54 processes the serial data as it arrives. In this example, the host link protocol 72 allows writing the outputs from each transmitter modules 54 at different times to system memory 24. This configuration may minimize latency bottlenecks caused by the slowest channel. Thus, the application software using the system memory can begin processing before all word blocks have been updated.

[0101] When the computer system 1 is operated with “asynchronous memory updating”, the transmission process may comprise updating both the memory and the status flag data that describe the state of each word block. The application software may check word-block-specific status flag when attempting to read specific word blocks. When the status flags indicate that specific word blocks were updated, the application software 26 may read these word blocks. When the data has been read, the status flags are cleared.

[0102] Referring to Figure 15, in step S1501, the device endpoint receives a trigger signal (e.g. generated by the application software 26) to start the data transmission over the transport medium 48. In step S1502, the readout data is transmitted as aboveAttorney Docket No. 133858.8016.WO00described with reference to process S1100. As noted above, data from different readout groups may arrive at different time at the respective receiver modules. In step S1503, readout data and flag data are written to the system memory as it arrives (as noted above, the flag data may be encoded in the data output of the decoder module, or may be generated by the “enhanced” receiver module described with reference to Figure 8). While the readout is being transmitted and written into the system memory 24 (i.e. St 502 and S1503), the application software 26 (continuously or periodically) checks the predefined memory locations associated with the flag data to determine whether the associated word blocks have been updated (S1504). In step S1505, the application software 26 determines from the bit value of the memory location associated with a specific word block that this word block has been updated. Next, the application software 26 clears the respective flag data to be able to detect the next data update event (S1506), and proceeds with processing the data stored in this word block even if other word blocks have not yet updated (S1507).

[0103] An example process of operating the computer system 1 with “synchronous memory updating” will now be described with reference to Figures 16 and 17. As noted above, even when all transmitter modules are triggered simultaneously, the serial bursts 90 may arrive at the receiver modules 54 at different times. As shown in Figure 16, embodiments may comprise a data accumulator 92 (as part of the interface to the host link protocol 72; in some embodiments the data accumulator 92 may be integrated into the host link protocol 72). The data accumulator 92 may be configured to receive the outputs of the receiver modules 54 and to resynchronize the received data before sending the resynchronised data to the system memory 24. In some embodiments, the data accumulator 92 may provide a signal (referred to as “transmission status indicator signal”) to the application software 26 each time the memory is updated.

[0104] Referring to Figure 17, in step S1701, the device endpoint receives a trigger signal (e.g. generated by the application software 26) to start the data transmission over the transport medium 48. In step S1702, the readout data is transmitted as above described with reference to process S1100. In step S1703, the system memory 24 is updated with the received readout data. While the readout is being transmitted and written into the system memory 24 (i.e. S1702 and S1703), the application software 26 (continuously or periodically) checks whether the system memory 24 has been updated, e.g. by monitoring the memory location associated with a specific memory blockAttorney Docket No. 133858.8016.WO00(S1704). In step S1705, the application software 26 determines that all word blocks have been updated based on determining that the flag data associated with a specific word block has been updated (or by receiving the transmission status indicator signal from the data accumulator 92). In step S1706, the application software 26 consumes the newly arrived readout data. Thus, in this example, the application software 26 can reliably determine that all word blocks have been updated, either by monitoring the flag of a single word block (this is because the data accumulator 92 ensures that all memory is updated simultaneously, thus if one of the word blocks is updated, the other word blocks must also be updated) or by the transmission status indicator signal generated by the data accumulator 92. After the application software 26 read the new data, the application software 26 may restart the transmission process by sending a new trigger (the application software 26 can do so “safely” because the application software 26 can be sure that all readout data have arrived).

[0105] Whilst certain examples of embodiments have been described, these described examples of embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices, and methods described herein may be implemented in other embodiments, or embodied in a variety of other forms based on what is described and / or illustrated in this patent document.

[0106] Certain aspects of the present disclosure are summarized by the following clauses:1. A computer system comprising:a quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits, each cryogenic readout circuit configured to output a readout signal from a corresponding quantum bit unit, the readout signal being indicative of a quantum state of said quantum bit unit;for each plurality of readout circuits, a corresponding cryogenic transmitter module coupled to said plurality of readout circuits and configured to serialize the readout signals into a corresponding stream of digital signals;Attorney Docket No. 133858.8016.WO00for each plurality of readout circuits, a corresponding communication channel coupled to said transmitter module and configured to transmit the stream of digital signals;for each plurality of readout circuits, a corresponding receiver module coupled to said communication channel and configured to deserialize the stream of digital signals to output deserialized data, anda classical computing device comprising a memory and configured to store the one or more deserialized data in the memory.2. The system of clause 1, wherein each transmitter module is configured to serialize the readout signals into a corresponding stream of digital signals in response to receiving a corresponding first signal.3. The system of clause 1 or 2, wherein the classical computing device stores each of the one or more deserialized data in a different block of the memory based on a predefined memory map specifying a mapping between the readout circuits and memory locations within said block of the memory.4. The system of any preceding clause, wherein each receiver module is further configured to, in response to receiving the stream of digital signals, provide a corresponding block status indicator signal to the classical computing device.5. The system of clause 4, wherein the block status indicator signal is encoded in the corresponding deserialized data.6. The system of clause 4, wherein each receiver module provides the corresponding block status indicator signal to the classical computing device by storing corresponding flag data into a predefined block of the memory of the classical computing device that is different from the block of memory in which corresponding deserialized data is stored.7. The system of any preceding clause, wherein the quantum processing unit comprises two or more pluralities of readout circuits and the system furtherAttorney Docket No. 133858.8016.WO00comprises a data accumulator unit configured to receive the deserialized data from the two or more receiver modules, to synchronise the received deserialized data and to provide the synchronised deserialized data to the classical computing device for storing in the memory.8. The system of clause 7, wherein the data accumulator unit is further configured to, in response to receiving deserialized data from each receiver module, provide a corresponding transmission status indicator signal to the classical computing device.9. The system of any preceding clause, wherein the transmitter module comprises a line code encoder unit configured to generate a line code representation of the readout signals, and a serializer unit configured to serialize the line code representation of the readout signals into a corresponding stream of digital signals.10. The system of any preceding clause, wherein the cryogenic readout circuits comprise a plurality of superconducting circuits.11. The system of clause 10, wherein the superconducting circuits comprise superconducting single-flux quantum circuits, and the readout signals comprise singleflux quantum signals.12. The system of clause 10 or 11 further comprising a cryogenic refrigeration system that provides a refrigerated environment, wherein the quantum bit units, the one or more pluralities of cryogenic readout circuits and the cryogenic transmitter modules are positioned within the refrigerated environment and cooled by the cryogenic refrigeration system, and the receiver module and the classical computing device are positioned outside the refrigerated environment.13. The system of any preceding clause, wherein each cryogenic transmitter module comprises a converter unit to convert the serialized single-flux quantum signals into a corresponding stream of logic-level digital signals and to provide said stream of logic-level digital signals to the communication channel.Attorney Docket No. 133858.8016.WO00 14. The system of clause 13, wherein the logic-level digital signals are CMOS-logic digital signals.15. The system of any preceding clause wherein the quantum bit units comprise superconducting qubit circuits.16. The system of any preceding clause, wherein each cryogenic transmitter module does not comprise circuitry configured to, in response to receiving a request from the classical computing system, retransmit the stream of digital signals to implement a classical error correction code.17. The system of any preceding clause, wherein each cryogenic transmitter module is configured to serialize the readout signals into a corresponding stream of digital signals without adding redundant information.18. A method of operating a computer system to transmit readout signals from a quantum processing unit to a classical computing device, the computer system comprising:the quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits;for each plurality of cryogenic readout circuits, a cryogenic transmitter module coupled to the plurality of readout circuits;for each plurality of readout circuits, a receiver module coupled to the cryogenic transmitter module via a corresponding communication channel; the classical computing device coupled to the receiver module;the method comprising:(i) outputting, by each readout circuit of the one or more pluralities of readout circuits, a respective readout signal from a corresponding quantum bit circuit, the readout signal being indicative of a quantum state of said quantum bit circuit;(ii) serializing, by each transmitter module, the respective readout signals into a corresponding stream of digital signals;Attorney Docket No. 133858.8016.WO00(iii) transmitting, via the communication channels, the streams of digital signals from the transmitter modules to the receiver modules;(iv) deserializing, by each receiver module, the respective stream of digital signals to output respective deserialized data;(v) storing, by the classical computing device, the one or more deserialized data in a memory of the classical computing device.19. The method of clause 18 wherein serializing the readout signals into a corresponding stream of digital signals comprises:receiving, by each transmitter module, a respective first signal, andin response of receiving the first signal, serializing the readout signals into a corresponding stream of digital signals.20. The method of clause 18 or 19 further comprising a step of providing, by each receiver module, in response to receiving the respective stream of digital signals a corresponding block status indicator signal to the classical computing device.21. The method of clause 19 further comprising a step of consuming, by an application running on the classical computing device, in response to receiving the respective block status indicator signal, data the corresponding deserialized data stored in the memory.22. The method of any one of clauses 18 or 19, wherein the quantum processing unit comprises two or more pluralities of readout circuits, and the method further comprises the steps of synchronising the two or more received deserialized data, providing the synchronised deserialized data to the classical computing device for storing in the memory and providing a corresponding transmission status indicator signal to the classical computing device.23. The method of clause 22 further comprising a step of consuming, by an application running on the classical computing device, in response to receiving the transmission status indicator signal, the two or more deserialized data stored in the memory.Attorney Docket No. 133858.8016.WO0024. The method of any one of clauses 19 to 23. wherein each cryogenic transmitter module does not comprise circuitry configured to, in response to receiving a request from the classical computing system, retransmit the stream of digital signals to implement a classical error correction code.25. The method of any one of clauses 18 to 24, wherein each transmitter module serializes the respective readout signals into a corresponding stream of digital signals without adding redundant information.26. A method of performing quantum error correction, the method comprising: executing, by a quantum processing unit, a step of a quantum application; transmitting readout signals of the quantum processing unit to a classical computing device according to the method of any one of clauses 18 to 25; determining, by an application running on the classical computing device, a correction to an intended subsequent step of the quantum application based on the deserialized data;modifying said step of the quantum application based on the determined correction; andexecuting, by the quantum processing unit, the corrected step of the quantum application.

Claims

Attorney Docket No. 133858.8016.WO00CLAIMSl / We claim:

1. A computer system comprising:a quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits, each cryogenic readout circuit configured to output a readout signal from a corresponding quantum bit unit, the readout signal being indicative of a quantum state of said quantum bit unit;for each plurality of readout circuits, a corresponding cryogenic transmitter module coupled to said plurality of readout circuits and configured to serialize the readout signals into a corresponding stream of digital signals; for each plurality of readout circuits, a corresponding communication channel coupled to said transmitter module and configured to transmit the stream of digital signals;for each plurality of readout circuits, a corresponding receiver module coupled to said communication channel and configured to deserialize the stream of digital signals to output deserialized data, anda classical computing device comprising a memory and configured to store each of the one or more deserialized data in a different block of the memory based on a predefined memory map specifying a mapping between the readout circuits and memory locations within said block of the memory.

2. The system of claim 1, wherein each transmitter module is configured to serialize the readout signals into a corresponding stream of digital signals in response to receiving a corresponding first signal.

3. The system of any preceding claim, wherein each receiver module is further configured to, in response to receiving the stream of digital signals, provide a corresponding block status indicator signal to the classical computing device.Attorney Docket No. 133858.8016.WO004. The system of claim 3, wherein the block status indicator signal is encoded in the corresponding deserialized data.

5. The system of claim 3, wherein each receiver module provides the corresponding block status indicator signal to the classical computing device by storing corresponding flag data into a predefined block of the memory of the classical computing device that is different from the block of memory in which corresponding deserialized data is stored.

6. The system of any preceding claim, wherein the quantum processing unit comprises two or more pluralities of readout circuits and the system further comprises a data accumulator unit configured to receive the deserialized data from the two or more receiver modules, to synchronise the received deserialized data and to provide the synchronised deserialized data to the classical computing device for storing in the memory.

7. The system of claim 6, wherein the data accumulator unit is further configured to, in response to receiving deserialized data from each receiver module, provide a corresponding transmission status indicator signal to the classical computing device.

8. The system of any preceding claim, wherein the transmitter module comprises a line code encoder unit configured to generate a line code representation of the readout signals, and a serializer unit configured to serialize the line code representation of the readout signals into a corresponding stream of digital signals.

9. The system of any preceding claim, wherein the cryogenic readout circuits comprise a plurality of superconducting circuits.

10. The system of claim 9, wherein the superconducting circuits comprise superconducting single-flux quantum circuits, and the readout signals comprise single¬ flux quantum signals.Attorney Docket No. 133858.8016.WO0011. The system of claim 9 or 10 further comprising a cryogenic refrigeration system that provides a refrigerated environment, wherein the quantum bit units, the one or more pluralities of cryogenic readout circuits and the cryogenic transmitter modules are positioned within the refrigerated environment and cooled by the cryogenic refrigeration system, and the receiver module and the classical computing device are positioned outside the refrigerated environment.

12. The system of any preceding claim, wherein each cryogenic transmitter module comprises a converter unit to convert the serialized single-flux quantum signals into a corresponding stream of logic-level digital signals and to provide said stream of logic-level digital signals to the communication channel.

13. The system of claim 12, wherein the logic-level digital signals are CMOS- logic digital signals.

14. The system of any preceding claim wherein the quantum bit units comprise superconducting qubit circuits.

15. The system of any preceding claim, wherein each cryogenic transmitter module does not comprise circuitry configured to, in response to receiving a request from the classical computing system, retransmit the stream of digital signals to implement a classical error correction code.

16. The system of any preceding claim, wherein each cryogenic transmitter module is configured to serialize the readout signals into a corresponding stream of digital signals without adding redundant information.

17. A method of operating a computer system to transmit readout signals from a quantum processing unit to a classical computing device, the computer system comprising:the quantum processing unit comprising a plurality of quantum bit units and one or more pluralities of cryogenic readout circuits;Attorney Docket No. 133858.8016.WO00 for each plurality of cryogenic readout circuits, a cryogenic transmitter module coupled to the plurality of readout circuits;for each plurality of readout circuits, a receiver module coupled to the cryogenic transmitter module via a corresponding communication channel;the classical computing device coupled to the receiver module;the method comprising:(i) outputting, by each readout circuit of the one or more pluralities of readout circuits, a respective readout signal from a corresponding quantum bit circuit, the readout signal being indicative of a quantum state of said quantum bit circuit;(ii) serializing, by each transmitter module, the respective readout signals into a corresponding stream of digital signals;(iii) transmitting, via the communication channels, the streams of digital signals from the transmitter modules to the receiver modules;(iv) deserializing, by each receiver module, the respective stream of digital signals to output respective deserialized data;(v) storing, by the classical computing device, each of the one or more deserialized data in a different block of a memory of the classical computing device based on a predefined memory map specifying a mapping between the readout circuits and memory locations within said block of the memory.

18. The method of claim 17 wherein serializing the readout signals into a corresponding stream of digital signals comprises:receiving, by each transmitter module, a respective first signal, andin response of receiving the first signal, serializing the readout signals into a corresponding stream of digital signals.

19. The method of claim 17 or 18 further comprising a step of providing, by each receiver module, in response to receiving the respective stream of digital signals a corresponding block status indicator signal to the classical computing device.Attorney Docket No. 133858.8016.WO0020. The method of claim 18 further comprising a step of consuming, by an application running on the classical computing device, in response to receiving the respective block status indicator signal, data the corresponding deserialized data stored in the memory.

21. The method of any one of claims 17 or 18, wherein the quantum processing unit comprises two or more pluralities of readout circuits, and the method further comprises the steps of synchronising the two or more received deserialized data, providing the synchronised deserialized data to the classical computing device for storing in the memory and providing a corresponding transmission status indicator signal to the classical computing device.

22. The method of claim 21 further comprising a step of consuming, by an application running on the classical computing device, in response to receiving the transmission status indicator signal, the two or more deserialized data stored in the memory.

23. The method of any one of claims 18 to 22, wherein each cryogenic transmitter module does not comprise circuitry configured to, in response to receiving a request from the classical computing system, retransmit the stream of digital signals to implement a classical error correction code.

24. The method of any one of claims 17 to 23, wherein each transmitter module serializes the respective readout signals into a corresponding stream of digital signals without adding redundant information.

25. A method of performing quantum error correction, the method comprising: executing, by a quantum processing unit, a step of a quantum application; transmitting readout signals of the quantum processing unit to a classical computing device according to the method of any one of claims 17 to 24; determining, by an application running on the classical computing device, a correction to an intended subsequent step of the quantum application based on the deserialized data;Attorney Docket No. 133858.8016.WO00 modifying said step of the quantum application based on the determined correction; andexecuting, by the quantum processing unit, the corrected step of the quantum application.

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