Single-input transistor-based driver for multiple-input outphasing power amplifiers

Abstract

An example outphasing modulation driver includes a radio-frequency (RF) input port; a set of transistors operably coupled to the RF input port via transmission lines with appropriate electrical lengths, wherein the set of transistors are configured with distinct gate biasing, a set of splitters operably coupled to the set of transistors; and a set of combiners operably coupled to the set of splitters via transmission lines with appropriate electrical lengths, where each combiner of the set of combiners is configured to output an auxiliary output signal to create a set of auxiliary output signals with variable phase and output power as the input power varies between different power thresholds.

Description

Docket Number: 103362-096WO1T2025-163 SINGLE-INPUT TRANSISTOR-BASED DRIVER FOR MULTIPLE-INPUT OUTPHASING POWER AMPLIFIERS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U. S. provisional patent application No.63 / 754,128, filed on February 5, 2025, and titled “Driver Circuit,” and U. S. provisional patent application No. 63 / 754,207 filed on February 5, 2025, and tilted “HIGH EFFICIENCY STAR AMPLIFIERS WITH LARGE OUTPUT POWER BACKOFF” the disclosures of which are expressly incorporated herein by reference in their entireties.BACKGROUND

[0002] Modern communication systems and devices use amplifiers to implement communication schemes. Orthogonal frequency division multiplexing (OFDM) is a method of signal modulation using multiple closely spaced carriers with minimized interference between them. OFDM can provide high spectral efficiency, but also yields signals with high peak-to-average power ratios. Improvements to amplifier drivers can improve communication systems, including those that use OFDM.SUMMARY

[0003] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, including: a radiofrequency (RF) input port; a set of transistors operably coupled to the RF input port via transmission lines with appropriate electrical lengths, wherein the set of transistors are configured with distinct gate biasing; a set of splitters operably coupled to the set of transistors; and a set of combiners operably coupled to the set of splitters via transmission lines with appropriate electrical lengths, wherein each combiner of the set of combiners is configured to ouKiput an auxiliary ouKiput signal to create a set of auxiliary ouKiput signals.

[0004] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein the radiofrequency input port is operably coupled to the set of transistors by a first set of transmission lines.Docket Number: 103362-096WO1T2025-163

[0005] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein an input matching network is operably coupled to each transistor of the set of transistors.

[0006] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein an ouKiput matching network is operably coupled to each transistor of the set of transistors.

[0007] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein the set of splitters and set of combiners are operably coupled by a second set of transmission lines.

[0008] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein the set of transistors are configured as class B amplifiers.

[0009] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein the set of transistors are configured as class C amplifiers.

[0010] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver, wherein the set of transistors, set of splitters, and set of combiners are configured to define a main branch and at least two auxiliary branches.

[0011] In some aspects, implementations of the present disclosure include an ouKiphasing modulation driver further including an ouKiput port coupled to the set of combiners and configured to ouKiput an RF drive signal for a multi-input power amplifier.

[0012] In some aspects, implementati ons of the present disclosure include an ouKiphasing modulation driver, wherein the auxiliary branches are configured to vary in phase and power with power received by the input port.

[0013] In some aspects, implementations of the present disclosure include a communication system including: a power amplifier; configured to be driven by an ouKiphasing modulation driver; the ouKiphasing modulation driver, including: a radiofrequency (RF) input port; a set of transistors operably coupled to the RF input port via transmission lines with appropriate electrical lengths, wherein the set of transistors are configured with distinct gate biasing; a set of splitters operably coupled to the set of transistors; and a set of combiners operably coupled to the set of splitters via transmission lines with appropriate electrical lengths, wherein each combiner of the set of combiners is configured to ouKiput an auxiliary ouKiput signal to create a set of auxiliary ouKiput signals.Docket Number: 103362-096WO1T2025-163

[0014] In some aspects, implementations of the present disclosure include a communication system, wherein the radiofrequency input port is operably coupled to the set of transistors by a first set of transmission lines.

[0015] In some aspects, implementations of the present disclosure include a communication system, wherein an input matching network is operably coupled to each transistor of the set of transistors.

[0016] In some aspects, implementations of the present disclosure include a communication system, wherein an ouKiput matching network is operably coupled to each transistor of the set of transistors.

[0017] In some aspects, implementations of the present disclosure include a communication system, wherein the set of splitters and set of combiners are operably coupled by a second set of transmission lines.

[0018] In some aspects, implementations of the present disclosure include a communication system, wherein the set of transistors are configured as class B amplifiers.

[0019] In some aspects, implementations of the present disclosure include a communication system, wherein the set of transistors are configured as class C amplifiers.

[0020] In some aspects, implementations of the present disclosure include a communication system, wherein the set of transistors, set of splitters, and set of combiners are configured to define a main branch and at least two auxiliary branches.

[0021] In some aspects, implementations of the present disclosure include a communication system, further including an ouKiput port coupled to the set of combiners and configured to ouKiput an RF drive signal for a multi-input power amplifier.

[0022] In some aspects, implementations of the present disclosure include a communication system, wherein the auxiliary branches are configured to vary in phase and power with power received by the input port.

[0023] It should be understood that the above-described subject matter may also be implemented as a computer-controlled apparatus, a computer process, a computing system, or an article of manufacture, such as a computer-readable storage medium.

[0024] Other systems, methods, features and / or advantages will be or may become apparent to one with skill in the art upon examination of the following drawings and detailedDocket Number: 103362-096WO1T2025-163 description. It is intended that all such additional systems, methods, features and / or advantages be included within this description and be protected by the accompanying claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

[0026] FIG. 1 illustrates an example driver circuit, according to implementations of the present disclosure.

[0027] FIG. 2 illustrates an example communications system including the driver circuit shown in FIG. 1.

[0028] FIG. 3 illustrates an example implementation of the present disclosure with a three-way star topology.

[0029] FIG. 4 illustrates an example of ouKiput signal possible with two transistors, according to a study of an example implementation of the present disclosure.

[0030] FIG. 5 illustrates variation of Ki3versus Ki2for KvLof 2 and 2.1, according to a study of an example implementation of the present disclosure.

[0031] FIG. 6 illustrates CSRP efficiency of the Star OPA versus ouKiput power for frequencies from 1.8 GHz to 2.2 GHz, according to a study of an example implementation of the present disclosure.

[0032] FIG. 7 illustrates an example trajectory of the CSRP load reflection coefficient seen by each of the transistors, according to a study of an example implementation of the present disclosure.

[0033] FIG. 8 illustrates loadline at the CSRP for (1) the main, (2 and 3) the auxiliary PAs at peak, OBI and OB2 together with the transistor intrinsic IV characteristics, according to a study of an example implementation of the present disclosure.

[0034] FIG. 9 illustrates PRP efficiencies versus OBO for the Star OPA with two-way and three-way Doherty PAs and a comparison of the drain voltage of the auxiliary transistor(s) which that are on at OBO1, according to a study of an example implementation of the present disclosure.Docket Number: 103362-096WO1T2025-163 DETAILED DESCRIPTION

[0035] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstance may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. While implementations will be described for OFDM communications, it will become evident to those skilled in the art that the implementations are not limited thereto, but are applicable for driving any amplifier.

[0036] With reference to FIG. 1, implementations of the present disclosure include ouKiphasing modulation drivers that can be used to drive ouKiphasing power amplifiers with multiple inputs, including power amplifiers used for communication circuits. While the example implementation is shown for three-input devices, other configurations of the proposed circuit operating on the same principle can be implemented to drive ouKiphasing amplifiers with two inputs or with N inputs, where N is any number.

[0037] Implementations of the present disclosure include radio-frequency (RF) driver circuits for ouKiphasing power amplifiers (OPAs) that can use multiple RF input ports. As described herein, ouKiphasing PA architectures can provide high efficiency at peak ouKiput power and at one or more ouKiput-backoff (OBO) power levels, but may require multiple input RF signals whose relative phases and / or magnitudes change with ouKiput power. The presentDocket Number: 103362-096WO1T2025-163 disclosure enables a single-input RF driver architecture that generates a plurality of RF drive signals suitable for exciting a multi-input ouKiphasing PA.

[0038] In some implementations, the driver is configured to accept a single RF input signal and to generate (i) a main RF drive signal and (ii) a set of auxiliary RF drive signals (referred to herein as Auxl and Aux2) whose relative phase and ouKiput power vary as a function of the RF input power as the operating point transitions between different power regions, including between a second ouKiput-backoff region (OBO2) and a first ouKiput-backoff region (OBO1), and peak power. In the example arrangement of FIG. 1, this can be achieved using two transistors biased for class C operation with distinct gate biases in combination with passive RF networks that split, phase shift, and recombine signals to generate the auxiliary ouKiputs that follow a desired phasor trajectory over input power.

[0039] With reference to FIG. 1, an example ouKiphasing modulation driver 100 is shown. The ouKiphasing modulation driver 100 is configured to generate a plurality of RF drive signals for a multi-input ouKiphasing power amplifier from a single RF input applied at RF input port 102. In the illustrated embodiment, splitter 110 divides the RF input signal into a plurality of branch signals.

[0040] Any number of branches 104a, 104b, 104n can be connected to the splitter 110. Example numbers of input branches 104a, 104b,,, 104n include two, three, and any other number. But it should be understood that any number of input branches 104a, 104b... 104n can be used in different implementations. Optionally, each input branch of the input branches 104a, 104b... 104n corresponds to a first transmission line, input matching network, transistor, ouKiput matching network, splitter, second transmission line, combiner, and auxiliary signal, as shown in FIG. 1 (also referred to as a “branch” of the driver circuit). The present disclosure contemplates that any number of such branches can be used, and that the number of branches can be configured based on the number of ports of a power amplifier operably coupled to the ouKiphasing modulation driver.

[0041] One of the branch signals (illustrated as 104n) can be the main signal, where the other branch signals (illustrated as 104a, 104b) can be the auxiliary signals. The branches are coupled through the transmission lines 112 with selected electrical lengths to respective input matching networks 120. The input matching networks 120 are coupled to respective transistors 122 with selected gate biases. The transistors can be individually biased (e.g., by gate biasing),Docket Number: 103362-096WO1T2025-163 so that optionally all of the transistors of the set of transistors 122 are biased differently. The gate biases can be selected to operate in class C, or optionally in class B / C, so that the transistor ouKiput contributions depend on the RF input drive level. The ouKiputs of the transistors 122 are coupled through respective ouKiput matching networks 124 to a downstream network of respective splitters 130 and respective combiners 134 joined together by a second set of transmission lines 132. The splitters 130, combiners 134, and transmission lines 132 act as a network to generate the set of auxiliary ouKiput signals 140 shown as Auxl and Aux2. The electrical lengths of the transmission lines are used to determine the phase of the ouKiput signals as the input power varies.

[0042]

[0043] As shown in FIG. 2, implementations of the present disclosure can include communication systems using the drivers shown and described with reference to FIG. 1. The example communication system can include the ouKiphasing modulation driver 100 including any number of branches 104a, 104b... 104n, where the branches 104a, 104b... 104n are configured as inputs to a power amplifier 200 and configured to drive the power amplifier 200. An input port 102 drives the driver 100, and the ouKiput of the power amplifier 200 is ouKiput by an ouKiput port 202 of the power amplifier 200.

[0044] FIG. 3 illustrates an example implementation of an ouKiphasing PA according to the present disclosure with a three-way star topology. The example shown in FIG. 3 can be used as a power amplifier 200, in some implementations of the present disclosure.

[0045] Example Design Parameters

[0046] The present disclosure includes simulations of example implementations of the present disclosure, and examples of parameters that can be used to configure drivers and systems including drivers and amplifiers. For the case in which the two transistors operate with the same voltages at peak ( yv— 1), the combiner circuit can be implemented using two transmission lines. Similarly, the design of a three-transistor ouKiphasing PA will be pursued here using three transmission lines as shown in FIG. 3. This PA topology will be referred to herein as the star OPA topology. Although results are presented here for three transistors, it will become evident that the Star OPA theory can be readily extended to N transistors with N usually odd.

[0047] The theoretical analysis for the Star-PA will be developed at the current source reference plane (CSRP). The characteristic impedances of the three lines should be selected asDocket Number: 103362-096WO1T2025-163 Roptand the ouKiput load RL— Ropt / 3 or Ropt / N for N branches. Roptis the optimal real impedance at the CSRP which yields the optimal tradeoff between peak ouKiput power and efficiency for the transistor operating point selected. Given that a matching network incorporating the device parasitics can usually be designed to approximate the targeted line characteristic impedance Roptand electrical length θp. Broadband operation can then be readily achieved at peak power (or alternatively at OBO1) independently of the electrical length θpof each line.

[0048] The question then arises of the choice of the electrical lengths for the three transmission lines to achieve high efficiency at the two different ouKiput-backoff power levels.

[0049] The example herein assumes that two of the transistors (# 2 and # 3) turn off at the second backoff (OBO2) as in a Doherty PA or HDMAX PA. It results that the first transistor behaves much like the main PA of a Doherty or HDmax PA. This further implies that the example Star OPA achieves an ouKiput backoff of OBO2 = N2= 9 = 9.54 dB.

[0050] One solution is to select the electrical length for the main transistor to be a quarter wavelength ( θ1= π / 4 ). Under such OBO2 conditions, the load impedance seen by transistor 1 at the CSRP will beB02= 3Ropt. Focusing temporarily on the~ n / 4 case, it becomes apparent that at OBO1, the transistors 2 and 3 must collectively provide a negative resistance in shunt with the load RLso that transistor 1 operates with a loadB01between Z?optand 3Z?opt. It is assumed that the loads seen by each transistor RpB01remain resistive (Assumption 4: class B and C operations). This can be achieved at OBO1 if the susceptances provided by transistors 2 and 3 cancel at the load reference plane.

[0051] Returning to the general case, it can be specified that the intrinsic drain voltage at the CSRP be the same for the peak, OBO1 backoff and OBO2 backoff operations for all transistors:VDS,p(peak) = VDS,p(OBO1) = VDS,p(OBO2)

[0052] This is equivalent to setting to one the OBO1 drain voltage ratios:Kvp≜ VDS,p(peak)VP~ VDS,p(OBO1) = 1

[0053] This constant intrinsic operating voltage VDS,por Kvp= 1 is a necessary requirement to ensure that maximum power efficiency is achieved at OBO1 for all transistors pDocket Number: 103362-096WO1T2025-163 just as it is at peak power (and OBO2 for transistor 1 when the appropriate gate drive is applied). The load modulation between the transistors will then lead at OBO1 to various current ratios:ID,p(peak)KipID,p(OBO1)

[0054] with the Kipremaining to be determined. The CSRP loadB01seen by the main transistor is then Ki1Roptwith Ki1usually selected by the designer between 1 and 3.Meanwhile at OBO1, transistors 2 and 3 will be load modulated at the CSRP to Ki2Ropiand j3Ropt, respectively, with Ki2and Ki3to be determined. To determine the mode of operation at OBO1, it is now necessary to take into account the common voltage VL(OBO1) across the ouKiput load RLsupported by the current / L(OBO1). Using the transmission line ABCD parameters of transistor p can be transformed as the CSRP drain voltage VDS,p(OBO1) and drain currentID,p(OBO1) to the load voltage VL(OBO1) and load current IL(OBO1). Enforcing then the common load voltage VL(OBO1) an equation is obtained giving the required electrical 6pfor each line p:Qsin2fU 1 / (0B01)cos(!)'VL t(peak)

[0055] where KvLis defined as the targeted ouKiput voltage modulation at the load RLfor OBOl

[0056] Summing the sub -components of the load current ILpcan be calculated and the total load current ILcan be calculated to enforce the load boundary condition connecting lLto VLat OBOl:4p —RJNp=l

[0057] After some derivation this yields the following requirement for the desired OBO1 operation:N1N / KvL2Ny i sin(20p), (3)Zu \K?P=1 'Docket Number: 103362-096WO1T2025-163

[0058] with N — 3 for the present Star-3 OP A example presented herein and with KvL≜ VL(peak) / VL(OBO1) the user-selected ratio between the ouKiput load voltages at peak and OBO1.

[0059] There is a continuum of possible solutions to these equations. These solutions can be obtained numerically as a function of the user-defined load voltage ratio KvL. FIG. 5 shows the variation of Ki2versus Ki3for a couple of KvLparameters. The large black dots correspond to the solution for θ1= π / 4.

[0060] An analytic solution is obtained for the case of a 3-way hybrid Doherty-Chireix OPA type realized with θ1= π / 4. From (1) it results that Ki1= KvL. Using this result in (2) yields the solution:

[0061] Equ. (3) is enforced for θ1= π / 4 if sin (202) = ~sin (203) (using Ki2= Ki3). Under such conditions the active susceptances provided by transistors 2 and 3 cancel at the load reference plane. The electrical length θ2and θ3should satisfy equation (1). It results that four pairs of solutions (modulo 2n ) for the electrical lengths (02, 03) of line 2 and 3 are possible. They are obtained by selecting a combination of ( 02, 03) providing opposite susceptance at the load among the four phases: θ0, π − θ0, π + θ0, and 2π − θ0, with θ0the solution between 0 and TT / 2 of the equation:sin20(j1cos 0O+ - = -ry.Ai2 / 3Ail

[0062] For wideband operation, the pair with the smallest electrical lengths for line 2 and 3(θ0, π − θ0), is selected for ( 02, 03).

[0063] This OPA is then controlled at the CSRP by two different pairs of ouKiphasing angles at OBO 1 and peak power: θin,2(Pout) − θin,1(Pout) and θin,3(Pout) − θin,1(Pout).

[0064] At peak power one can simply select for transistor p the CSRP gate drive with a phase corresponding to their respective line impedance θin,p≈ θp. At OBO1 the ouKiphasing angles at the CSRP can be selected to be:( sin 0pl0inp— ^- Ros 0.p— ]— - kt JDocket Number: 103362-096WO1T2025-163

[0065] At OBO2 no ouKiphasing angle may be theoretically needed but optimal efficiency and linearity for power levels between OBO2 and OBO1 and below OBO2 is obtained if the ouKiphasing angle of OBO1 is maintained. The optimal ouKiphasing angles between the OBO1 and peak operating points are to first order simply obtained (as shown in FIG. 4) by linear interpolation without any noticeable power-efficiency degradation.

[0066] The design parameters disclosed herein are sufficiently general that it holds if Kiis smaller than one ( Ktl< 1 ) effectively making OBO1 the actual peak power mode.Broadband operation is now achieved at the first backoff. In such a case, using transistors of different sizes can become advantageous.

[0067] Examples

[0068] The following examples are put forth so as to provide those of ordinary skill in the art with a complete disclosure and description of how the compounds, compositions, articles, devices and / or methods claimed herein are made and evaluated, and are intended to be purely exemplary and are not intended to limit the disclosure. Efforts have been made to ensure accuracy with respect to numbers (e.g., amounts, temperature, etc.), but some errors and deviations should be accounted for. Unless indicated otherwise, parts are parts by weight, temperature is in °C or is at ambient temperature, and pressure is at or near atmospheric.

[0069] A study was performed of an example implementation of the present disclosure. The example implementation of the present disclosure illustrated in FIG. 3 was studied.

[0070] The design parameters for a 3 -way Star OP A were validated in simulations. It achieves an ouKiput backoff of 9 = 9.54 dB ( N2for N branches) with a flat efficiency with about 20% fractional bandwidth. A two-transistor circuit was introduced to operate the 3-w'ay Star OPA with a single RF input. A demonstration Star OP A is currently under development.

[0071] To verify the Star OPA design, the study implemented the Star OPA with 01of 90° using a nonlinear embedding model for the CGH40010F MACOM high electron mobility transistor (HEMT) [9], The embedding model facilitates the design of PAs at the current source reference plane while projecting the waveforms to the package reference planes (PRP) for predicting the performance including the device parasitics. The current modulation ratio was set to KVL= K — 2. This yields in turn Ki2— Ki3— 8, 02— 60.8° and 03— 119.2°. The resultingDocket Number: 103362-096WO1T2025-163 PA efficiency is plotted in FIG. 6 for 7 frequencies from 1.8 GHz to 2.2 GHz for a bandwidth of 20%.

[0072] FIG. 4 illustrates a trajectory' (plain line) of the input phasors used to drive the three transistors of the Star OP A. Approximate trajectory (dots) generated by a two-transistor circuit to drive the OP A with a single RF input.

[0073] The trajectories of the CSRP load reflection coefficient rp(Pout) seen by each of the transistors as the ouKiput power varies from peak to OBO1 and OBO2 backoff are shown in FIG. 7. Transistor 1 operates like the main transistor of a Doherty PA from peak to backoff, while transistors 2 and 3 (1) operate like the two transistors of a Chireix PA between peak and OBO1 and (2) jointly turn off between OBO1 and OBO2 like the auxiliary transistor in a two- way Doherty PA. The CSRP loadlines associated with transistors 1 (main) and transistor 2 and 3 (auxiliary) are shown in FIG. 8 for the peak, OBO 1 and OBO 2 backoffs. The auxiliary transistors are on at both the peak and OBO1 backoff, and off at OBO2.

[0074] A comparison of the drain efficiency versus OBO for the Star OPA with a two-way and three-way Doherty PAs is shown in FIG. 9. A flatter efficiency versus OBO is achieved for the Star OPA due to the fact that the auxiliary drain voltage FDSis kept the same at both peak power and OBI compared to the 3-way Doherty PA is also shown in FIG. 9.

[0075] Two transistors operating in class C are used for single-input operation of the OPA as shown in FIG. 1. The resulting phasor trajectories (dots) shown in FIG. 4 sufficiently approximate the linear trajectories (lines) to maintain the drain efficiency.

[0076] FIG. 1 illustrates the driver for single-input Star OPA operation shown in FIG.4.

[0077] Discussion

[0078] Modern cellular communication standards rely on waveforms, such as orthogonal frequency division multiplexing (OFDM), which provide high spectral efficiency but come at the cost of yielding signals with high peak-to-average power ratios (PAPR). To address this challenge new types of power amplifiers (PA) operating with high efficiency at high ouKiput backoff (OBO) are required.

[0079] The present disclosure implements a new three-transistor ouKiphasing power amplifier (OPA) topology, improving on previous four-transistor topologies. The study shows that the example three-transistor ouKiphasing PA exhibits two OBO power levels like the three-Docket Number: 103362-096WO1T2025-163 transistor Doherty PA. However unlike the three -transistor Doherty PA, different ouKiphasing angles can be required at the input of the OPA when the ouKiput power varies between the peak power and the first OBO power level (OBO1). A continuum of modes will be found to be possible including a hybrid Chireix-Doherty operation with a high OBO,

[0080] Despite their high performance, previous ouKiphasing PAs have not been widely adopted due to their requirement for multiple input RF ports and RF input signals dynamically modulated in phase and power (mixed-mode). To address this, implementations of the present disclosure can use a low-power two-transistor RF ouKiphasing driver for generating the three required input RF signals from a single RF input. Using this single RF input driver, the Star OPA exhibits a degradation in power-added efficiency at peak-power but not at backoff, the drain efficiency remaining about the same.

[0081] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0082] As used herein, the terms "about" or "approximately" when referring to a measurable value such as an amount, a percentage, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, or ±1% from the measurable value.

Claims

Docket Number: 103362-096WO1T2025-163 WHAT IS CLAIMED;1. An ouKiphasing modulation driver, comprising:a radiofrequency (RF) input port;a set of transistors operably coupled to the RF input port via transmission lines with appropriate electrical lengths, wherein the set of transistors are configured with distinct gate biasing;a set of splitters operably coupled to the set of transistors; anda set of combiners operably coupled to the set of splitters via transmission lines with appropriate electrical lengths, wherein each combiner of the set of combiners is configured to ouKiput an auxiliary ouKiput signal to create a set of auxiliary ouKiput signals.

2. The ouKiphasing modulation driver of claim 1, wherein the radiofrequency input port is operably coupled to the set of transistors by a first set of transmission lines.

3. The ouKiphasing modulation driver of claim 1 or claim 2, wherein an input matching network is operably coupled to each transistor of the set of transistors.

4. The ouKiphasing modulation driver of any one of claims 1-3, wherein an ouKiput matching network is operably coupled to each transistor of the set of transistors.

5. The ouKiphasing modulation driver of any one of claims 1-4, wherein the set of splitters and set of combiners are operably coupled by a second set of transmission lines.

6. The ouKiphasing modulation driver of any one of claims 1-5, wherein the set of transistors are configured as class B amplifiers.

7. The ouKiphasing modulation driver of any one of claims 1-6, wherein the set of transi stors are configured as class C amplifiers.Docket Number: 103362-096WO1T2025-163 8. The ouKiphasing modulation driver of any one of claims 1-7, wherein the set of transistors, set of splitters, and set of combiners are configured to define a main branch and at least two auxiliary branches.

9. The ouKiphasing modulation driver of claim 8, further comprising an ouKiput port coupled to the set of combiners and configured to ouKiput an RF drive signal for a multi-input power amplifier.

10. The ouKiphasing modulation driver of claim 8, wherein the auxiliary branches are configured to vary in phase and power with power received by the input port.

11. A communication system comprising:a power amplifier; configured to be driven by an ouKiphasing modulation driver; the ouKiphasing modulation driver, comprising:a radiofrequency (RF) input port;a set of transistors operably coupled to the RF input port via transmission lines with appropriate electrical lengths, wherein the set of transistors are configured with distinct gate biasing;a set of splitters operably coupled to the set of transistors; anda set of combiners operably coupled to the set of splitters via transmission lines with appropriate electrical lengths, wherein each combiner of the set of combiners is configured to ouKiput an auxiliary' ouKiput signal to create a set of auxiliary ouKiput signals.

12. The communication system of claim 11, wherein the radiofrequency input port is operably coupled to the set of transistors by a first set of transmission lines.

13. The communication system of claim 11 or claim 12, wherein an input matching network is operably coupled to each transistor of the set of transistors.Docket Number: 103362-096WO1T2025-163 14. The communication system of any one of claims 11-13, wherein an ouKiput matching network is operably coupled to each transistor of the set of transistors.

15. The communication system of any one of claims 11-14, wherein the set of splitters and set of combiners are operably coupled by a second set of transmission lines.

16. The communication system of any one of claims 11-15, wherein the set of transistors are configured as class B amplifiers.

17. The communication system of any one of claims 11-16, wherein the set of transistors are configured as class C amplifiers.

18. The communication system of any one of claims 11-17, wherein the set of transistors, set of splitters, and set of combiners are configured to define a main branch and at least two auxiliary branches.

19. The communication system of claim 18, further comprising an ouKiput port coupled to the set of combiners and configured to ouKiput an RF drive signal for a multi-input power amplifier.

20. The communication system of claim 18, wherein the auxiliary branches are configured to vary in phase and power with power received by the input port.

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