High efficiency star amplifiers with large output power backoff

Abstract

An example outphasing power amplifier realized at the current source reference planes includes a main transistor coupled to a main transmission line; a first auxiliary transistor coupled to a first auxiliary transmission line; a second auxiliary transistor coupled to a second auxiliary transmission line; and a star junction coupling the first auxiliary transistor, second auxiliary transistor, and main transistor to a load.

Description

Docket Number: 103362-097WO1T2025-164 HIGH EFFICIENCY STAR AMPLIFIERS WITH LARGE OUTPUT POWER BACKOFF CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U. S. provisional patent application No. 63 / 754,128, filed on February' 5, 2025, and titled “Driver Circuit,” and U. S. provisional patent application No. 63 / 754,207 filed on February 5, 2025, and titled “HIGH EFFICIENCY STAR AMPLIFIERS WITH LARGE OUTPUT POWER BACKOFF,” the disclosures of which are expressly incorporated herein by reference in their entireties.BACKGROUND

[0002] Modem communications systems and devices use amplifiers to implement communication schemes. Orthogonal frequency division multiplexing (OFDM) is a method of signal modulation using multiple closely spaced carriers with minimized interference between them OFDM can provide high spectral efficiency in communication systems, but also yields signals with high peak-to-average power ratios. Improvements to amplifiers in terms of power efficiency at large backoff can improve communication systems, including those that use OFDM.SUMMARY

[0003] In some aspects, implementations of the present disclosure include an outphasing power amplifier, including: a main intrinsic transistor coupled to a load via an effective main transmission line realized by its output matching network and parasitics of the transistors; a first auxiliary intrinsic transistor coupled to the load and the main intrinsic transistor and a second auxiliary transistor via an effective first auxiliary transmission line realized by its output matching network and the parasitics of the transistors; wherein the second auxiliary intrinsic transistor is effectively coupled to the load and the first auxiliary intrinsic transistor and main intrinsic transistor via an effective second auxiliary' transmission line realized by its output matching network and parasitics of the transistors, wherein the main intrinsic transistor is coupled to the first auxiliary’ intrinsic transistor and second auxiliary intrinsic transistor by the effective main transmission line; and a star junction coupling the first auxiliary transistor, second auxiliary transistor, and main transistor to a load.Docket Number: 103362-097WO1T2025-164

[0004] In some aspects, implementations of the present disclosure include an outphasing power amplifier, further including: a plurality of auxiliary transistors coupled to a respective plurality of auxiliary' transmission lines.

[0005] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the outphasing power amplifier includes an odd number of transistors.

[0006] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the main transistor, first auxiliary transistor, and second auxiliary transistor can be configured to be driven by a single RF input when using an outphasing power amplifier driver.

[0007] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the first auxiliary transistor and / or second auxiliary transistor are configured as peaking amplifiers which are off for output power levels below a second output power backoff (OBO2) and require specific outphasing angles for the first output power backoff (OBO1 ) and at peak power for high efficiency operation.

[0008] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the star junction is coupled to the load by a load transmission line.

[0009] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the load transmission line is a quarter- wav elength line,

[0010] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the outphasing power amplifier is configured for use as an injection PA for a 6G communication system.

[0011] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein the 6G communication system includes a pseudo load-modulated balanced amplifier or a circulator load-modulated amplifier.

[0012] In some aspects, implementations of the present disclosure include an outphasing power amplifier, wherein an overall output backoff of the power amplifier is between 15.5 and 18.5 dB, inclusive.

[0013] In some aspects, implementations of the present disclosure include a communication system including: an outphasing power amplifier, including: a main intrinsic transistor coupled to a load via an effective main transmission line realized by its output matching network and parasitics of the transistors; a first auxiliary intrinsic transistor coupled toDocket Number: 103362-097WO1T2025-164 the load and the main intrinsic transistor and a second auxiliary transistor via an effective first auxiliary transmission line realized by its output matching network and the parasitics of the transistors; wherein the second auxiliary intrinsic transistor is effectively coupled to the load and the first auxiliary' intrinsic transistor and main intrinsic transistor via an effective second auxiliary' transmission line realized by its output matching network and parasitics of the transistors, wherein the main intrinsic transistor is coupled to the first auxiliary intrinsic transistor and second auxiliary' intrinsic transistor by the effective main transmission line; and a star junction coupling the first auxiliary' transistor, second auxiliary' transistor, and main transistor to a load; and an outphasing modulation driver, wherein the outphasing modulation driver is operably coupled to the power amplifier and configured to drive the power amplifier using a single input.

[0014] In some aspects, implementations of the present disclosure include a communication system, further including: a plurality of auxiliary transistors coupled to a respective plurality of auxiliary transmission lines.

[0015] In some aspects, implementations of the present disclosure include a communication system, wherein the outphasing power amplifier includes an odd number of transistors.

[0016] In some aspects, implementations of the present disclosure include a communication system, wherein the main transistor, first auxiliary transistor, and second auxiliary transistor can be configured to be driven by a single RF input when using the outphasing power amplifier driver.

[0017] In some aspects, implementations of the present disclosure include a communication system, wherein the first auxiliary transistor and / or second auxiliary transistor are configured as peaking amplifiers which are off for output power levels below a second output power backoff (OBO2) and require specific outphasing angles for the first output power backoff (OBO1) and at peak power for high efficiency operation.

[0018] In some aspects, implementations of the present disclosure include a communication system, wherein the star junction is coupled to the load by a load transmission line.

[0019] In some aspects, implementations of the present disclosure include a communication system, wherein the load transmission line is a quarter-wavelength line.Docket Number: 103362-097WO1T2025-164

[0020] In some aspects, implementations of the present disclosure include a communication system, wherein the outphasing power amplifier is configured for use as an injection PA for a 6G communication system.

[0021] In some aspects, implementations of the present disclosure include a communication system, wherein the 6G communication system includes a pseudo load- modulated balanced amplifier or a circulator load-modulated amplifier.

[0022] In some aspects, implementations of the present disclosure include a communication system, wherein an overall output backoff is between 15.5 and 18.5 dB, inclusive.

[0023] It should be understood that the above-described subject matter may also be implemented as a computer-controlled apparatus.

[0024] Other systems, methods, features and / or advantages will be or may become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that ail such additional systems, methods, features and / or advantages be included within this description and be protected by the accompanying claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The components in the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding parts throughout the several views.

[0026] FIG. 1 illustrates an example power amplifier circuit at the CSRP describing the targeted operation at the center frequency, according to implementations of the present disclosure.

[0027] FIG. 2 illustrates an example communications system including the power amplifier circuit shown in FIG. 1.

[0028] FIG. 3 illustrates an example implementation at the package reference planes using input and output matching networks.

[0029] FIG. 4 illustrates an outphasing driver that can be optionally used with implementations of the present disclosure.

[0030] FIG. 5 illustrates an example implementation of the present disclosure with a three-way star topology.Docket Number: 103362-097WO1T2025-164

[0031] FIG. 6 illustrates an example of output signal possible with two transistors, according to a study of an example implementation of the present disclosure.

[0032] FIG. 7 illustrates variation of Ki3versus Ki2for KvLof 2 and 2.1, according to a study of an example implementation of the present disclosure.

[0033] FIG. 8 illustrates CSRP efficiency of the Star OPA versus output power for frequencies from 1.8 GHz to 2.2 GHz, according to a study of an example implementation of the present disclosure.

[0034] FIG. 9 illustrates an example trajectory of the CSRP load reflection coefficient seen by each of the transistors, according to a study of an example implementation of the present disclosure.

[0035] FIG. 10 illustrates loadline at the CSRP for (1) the main, (2 and 3) the auxiliary PAs at peak, OBI and OB2 together with the transistor intrinsic IV characteristics, according to a study of an example implementation of the present disclosure.

[0036] FIG. 11 illustrates PRP efficiencies versus OBO for the Star OPA with two-way and three-way Doherty PAs and a comparison of the drain voltage of the auxiliary transistor(s) which that are on at OBO1, according to a study of an example implementation of the present disclosure.

[0037] FIG. 12A illustrates transmission line parameters 02and 03across K^, according to a study of an example implementation of the present disclosure.

[0038] FIG. 12B illustrates current ratio factors Kalacrossaccording to a study of an example implementation of the present disclosure.

[0039] FIG. 13 A illustrates a schematic of a Star OPA prototype with the nonlinear embedding device model and transmission line based combiner, according to a study of an example implementation of the present disclosure.

[0040] FIG. 13B illustrates a single transistor schematic to obtain appropriate RF gate voltage drives as RLvaries between the peak, OBO 1 and OBO 2 values, according to a study of an example implementation of the present disclosure.

[0041] FIG. 14A-14C illustrate intrinsic fundamental reflection coefficients for the main, aux. 1, and aux. 2 transistors. FIG. 14A illustrates K^1= 1.5; FIG. 14B illustrates K^1= 2, and (c) = 2.5, according to a study of an example implementation of the present disclosure.Docket Number: 103362-097WO1T2025-164

[0042] FIGS. 14D-14F illustrate intrinsic RF loadlines for the main, aux. 1, and aux. 2 transistors. FIG. 14D illustrates= 1.5, 14E illustrates= 2, and 14F illustrates= 2.5, according to a study of an example implementation of the present disclosure.

[0043] FIG. 15 illustrates drain efficiency versus output back-off (OBO) for various values of KvLin an example Star OP A, according to a study of an example implementation of the present disclosure.

[0044] FIG. 16A illustrates drain efficiency versus output backoff comparing the Star OPA with the 3-Way Doherty and Asymmetric Doherty, according to a study of an example implementation of the present disclosure.

[0045] FIG. 16B illustrates the magnitude of drain voltage for auxiliary transistor(s) versus output back-off, according to a study of an example implementation of the present disclosure.

[0046] FIG. 17A illustrates embedding the parasistics in an example implementation of the present disclosure.

[0047] FIG. 17B illustrates synthesis of the output matching networks for transistors 1,2,3 for each combiner branch in FIG. 17A using the parasitic network shown in FIG. 17B.

[0048] FIG. 18 illustrates an example fabricated Star OPA, according to a study of an example implementation of the present disclosure.

[0049] FIG. 19 illustrates measured versus simulated drain efficiency and gain across output power at 1.9 GHz, according to a study of an example implementation of the present disclosure.DETAILED DESCRIPTION

[0050] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure. As used in the specification, and in the appended claims, the singular forms “a,” “an,” “the” include plural referents unless the context clearly dictates otherwise. The term “comprising” and variations thereof as used herein is used synonymously with the term “including” and variations thereof and are open, non-limiting terms. The terms “optional” or “optionally” used herein mean that the subsequently described feature, event or circumstanceDocket Number: 103362-097WO1T2025-164 may or may not occur, and that the description includes instances where said feature, event or circumstance occurs and instances where it does not. Ranges may be expressed herein as from "about" one particular value, and / or to "about" another particular value. When such a range is expressed, an aspect includes from the one particular value and / or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about," it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. While implementations will be described for OFDM communications, it will become evident to those skilled in the art that the implementations are not limited thereto, but are applicable for any amplifier.

[0051] With reference to FIG, 1, implementations of the present disclosure include power amplifiers used for communication circuits. An example implementation configured as a star outphasing amplifier according to implementations of the present disclosure is described in Appendix A, hereto.

[0052] With reference to FIG. 1, an example outphasing power amplifier 100 is shown. The outphasing power amplifier 100 includes a main transistor 102 coupled to a main transmission line 104. Any number of auxiliary transistors can be combined with the main transistor 102 in a star configuration to form a star amplifier. As shown in FIG. 1, two auxiliary transistors are shown as the first auxiliary transistor 112 and second auxiliary transistor 122. The first auxiliary transistor 112 is coupled to a first auxiliary transmission line 114 and the second auxiliary transistor 122 is coupled to a second auxiliary transmission line 124. It should be understood that any number of auxiliary transmission lines and auxiliary transistors can be used in different implementations of the present disclosure. In some implementations, the number of auxiliary transistors and corresponding auxiliary transmission lines is selected so that there are an odd number of total transistors (e g., four auxiliary transistors and one main transistor for a total of five transistors, six auxiliary transistors and the main transistor for a total of seven transistors, and so on).

[0053] The first auxiliary transistor and / or second auxiliary transistor can optionally be configured as peaking amplifiers. Optionally, all the inputs to the power amplifier 100 can be performed using a single input coupled to a drive circuit that splits the single input into multipleDocket Number: 103362-097WO1T2025-164 branches (e g., a branch corresponding to each of the main transistor 102 and all the auxiliary transistors).

[0054] The main transmission line 104, first auxiliary transistor 112, and second auxiliary transistor 122 can be joined at a star junction 126. Optionally, the star junction 126 can be coupled to a load 130. In some implementations, the coupling between the load 130 and star junction 126 can be through a load transmission line 128 (e.g., a quarter-wavelength transmission line).

[0055] As shown in FIG. 2, implementations of the present disclosure can include communication systems using the power amplifiers shown and described with reference to FIG.1. The example communication system can include an outphasing modulation driver 200 including any number of branches 204a, 204b..,204n, where the branches 204a, 204b..,204n are configured as inputs to a power amplifier 100 and configured to drive the power amplifier 100. The drive circuit can include a single input 201 and single output 203.

[0056] FIG. 3 illustrates an example implementation at the package reference planes using input and output matching networks. FIG. 4 illustrates an outphasing driver that can be optionally used with implementations of the present disclosure. FIG. 5 illustrates an example implementation of the present disclosure with a three-way star topology.

[0057] Example Design Parameters

[0058] The present disclosure includes simulations of example implementations of the present disclosure, and examples of parameters that can be used to configure drivers and systems including drivers and amplifiers. For the case in which the two transistors operate with the same voltages at peak ( yv= 1), the combiner circuit can be implemented using two transmission lines. Similarly, the design of a three-transistor outphasing PA will be pursued here using three transmission lines as shown in FIG. 3. This PA topology will be referred to herein as the star OPA topology. Although results are presented here for three transistors, it will become evident that the Star OPA theory can be readily extended to N transistors with N usually odd.

[0059] The theoretical analysis for the Star-PA will be developed at the current source reference plane (CSRP). The characteristic impedances of the three lines should be selected as / ?optand the output load RL~ / ?opt / 3 or / ?opt / N for N branches. i?optis the optimal real impedance at the CSRP which yields the optimal tradeoff between peak output power and efficiency for the transistor operating point selected. Given that a matching networkDocket Number: 103362-097WO1T2025-164 incorporating the device parasitics can usually be designed to approximate the targeted line characteristic impedance Roptand electrical length 0p. Broadband operation can then be readily achieved at peak power (or alternatively at OBO1) independently of the electrical length 0pof each line.

[0060] The question then arises of the choice of the electrical lengths for the three transmission lines to achieve high efficiency at the two different output-backoff power levels.

[0061] The example herein assumes that two of the transistors (# 2 and # 3) turn off at the second backoff (OBO2) as in a Doherty PA or HDMAX PA. It results that the first transistor behaves much like the main PA of a Doherty or HDmax PA. This further implies that the example Star OP A achieves an output backoff of OB 02 — N2— 9 — 9.54 dB.

[0062] One solution is to select the electrical lengthfor the main transistor to be a quarter wavelength ( 0 — TT / 4 ). Under such OBO2 conditions, the load impedance seen by transistor 1 at the CSRP will be / ?°B02= 3 / ?opt. Focusing temporarily on the= TT / 4 case, it becomes apparent that at OBO1, the transistors 2 and 3 must collectively provide a negative resistance in shunt with the load RLso that transistor 1 operates with a load RB01between Roptand 3Z?opt. It is assumed that the loads seen by each transistor RpB01remain resistive (Assumption 4: class B and C operations). This can be achieved at OBO1 if the susceptances provided by transistors 2 and 3 cancel at the load reference plane.

[0063] Returning to the general case, the example implementation specified that the intrinsic drain voltage at the CSRP be the same for the peak, OBO1 backoff and OBO2 backoff operations for all transistors:VDSp(peak) = VDSp(0B01) - VD5JP(0B02)

[0064] This is equivalent to seting to one the OBO1 drain voltage ratios:VQNp(Peak) _VP~ IW0B01) ~

[0065] This constant intrinsic operating voltage VDS por Kvp~ 1 is a necessary requirement to ensure that maximum power efficiency is achieved at OBO1 for all transistors p just as it is at peak power (and OBO2 for transistor 1 when the appropriate gate drive is applied). The load modulation between the transistors will then lead at OBO1 to various current ratios:ap.p(peak)“ / o,p(0B01)Docket Number: 103362-097WO1T2025-164

[0066] with the Kipremaining to be determined. The CSRP load seen by the main transistor is then KiRoptwith Ktlusually selected by the designer between 1 and 3. Meanwhile at OBOI, transistors 2 and 3 will be load modulated at the CSRP to Kj2Roptand KL3Ropt, respectively, with Ki2and Ki3to be determined. To determine the mode of operation at OBOI, it is now necessary to take into account the common voltage VL(OBOI) across the output load RLsupported by the current / L(OBO1). Using the transmission line ABCD parameters of transistor p the CSRP drain voltage ’^(OBO!) and drain current / ^(OBOl) can be transformed to the load voltage P (OBO1) and load current / £(OBO1). Enforcing then the common load voltage (OBOI) an equation giving the required electrical 0pfor each line p can be obtained:sin20p1 ^L(OBO1)\COS 0-n H - ” — yip &vL, 1 (peak) /

[0067] where KvLis defined as the targeted output voltage modulation at the load RLfor OBOI.

[0068] Summing the sub-components of the load current ILpthe total load current / £can be calculated and can enforce the load boundary condition connecting ILto VLat OBOI:Z NK-RP=1

[0069] After some derivation this yields the following requirement for the desired OBOI operation:NN1^2KVLN1p=l V‘ip

[0070] with / V = 3 for the present Star-3 OPA example presented herein and with KvLA VLpeak ) / V£( OBOI ) the user-selected ratio between the output load voltages at peak and OBO1.

[0071] There is a continuum of possible solutions to these equations. These solutions can be obtained numerically as a function of the user-defined load voltage ratio KvL. FIG. 7 showsDocket Number: 103362-097WO1T2025-164 the variation of Ki2versus Ki3for a couple of KvLparameters. The large black dots correspond to the solution for 0r— TT / 4.

[0072] An analytic solution is obtained for the case of a 3-way hybrid Doherty-Chireix OP A type realized with 0r~From (I) it results that Ki~ KvL. Using this result in (2) yields the solution:2 / Qi123 - K£1

[0073] Equ. (3 ) is enforced for = TT / 4 if sin (202) — —sin (203) (using Ki2= Ki3). Under such conditions the active susceptances provided by transistors 2 and 3 cancel at the load reference plane. The electrical length and 03should satisfy equation (I). It results that four pairs of solutions (modulo 2n ) for the electrical lengths (02,of line 2 and 3 are possible. They are obtained by selecting a combination of ( 02, 03) providing opposite susceptance at the load among the four phases: 0O, TC — 0Q,n + 0O, and 2TT — 0O, with 0Othe solution between 0 and n / 2 of the equation:sin20Q 1COS 0n H - 5 - — y.At2 / 3Ail

[0074] For wideband operation, the pair with the smallest electrical lengths for line 2 and 3(0O, TT — 0O), is selected for ( 02, 03).

[0075] This OPA is then controlled at the CSRP by two different pairs of outphasing angles at OBO 1 and peak power: 0in 2(Pout) - 0jn 4(Pout) and 0m i3(Poul) - 0in,i(Pout).

[0076] At peak power one can simply select for transistor p the CSRP gate drive with a phase corresponding to their respective line impedance 0in p= 0p. At OBO1 the outphasing angles at the CSRP can be selected to be:( sin@in,p ~z1 0p ~~ J ————ip

[0077] At OBO2 no outphasing angle may be theoretically needed but optimal efficiency and linearity for power levels between OBO2 and OBO1 and below OBO2 is obtained if the outphasing angle of OBO1 is maintained. The optimal outphasing angles between the OBO1 and peak operating points are to first order simply obtained (as shown in FIG. 6) by linear interpolation without any noticeable power-efficiency degradation.Docket Number: 103362-097WO1T2025-164

[0078] The design parameters disclosed herein are sufficiently general that it holds if Ktlis smaller than one ( Ktl< 1 ) effectively making OBO1 the actual peak power mode.Broadband operation is now achieved at the first backoff. In such a case, using transistors of different sizes can become advantageous.

[0079]

[0080] As used herein, the terms "about" or "approximately" when referring to a measurable value such as an amount, a percentage, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, or ±1% from the measurable value.

[0081] Examples

[0082] The following examples are put forth so as to provide those of ordinary skill in the art with a complete disclosure and description of how the compounds, compositions, articles, devices and / or methods claimed herein are made and evaluated, and are intended to be purely exemplary and are not intended to limit the disclosure. Efforts have been made to ensure accuracy with respect to numbers (e.g., amounts, temperature, etc.), but some errors and deviations should be accounted for. Unless indicated otherwise, parts are parts by weight, temperature is in °C or is at ambient temperature, and pressure is at or near atmospheric.

[0083] Example 1:

[0084] A study was performed of an example implementation of the present disclosure. The example implementation of the present disclosure illustrated in FIG. 3 was studied.

[0085] The design parameters for a 3-way Star OPA were validated in simulations. It achieves an output backoff of 9 = 9.54 dB ( N2for N branches) with a flat efficiency with about 20% fractional bandwidth. A two-transistor circuit was introduced to operate the 3-way Star OPA with a single RF input. A demonstration Star OPA is currently under development.

[0086] To verify the Star OPA design herein, the study implemented the Star OPA with 0! of 90° using a nonlinear embedding model for the CGH40010F MACOM high electron mobility transistor (HEMT) [9], The embedding model facilitates the design of PAs at the current source reference plane while projecting the waveforms to the package reference planes (PRP) for predicting the performance including the device parasitics. The current modulation ratio was set to KvL= Kir— 2. This yields in turn Ki2~ Ki3= 8, 02= 60.8° and 03= 119.2°. The resulting PA efficiency is plotted in FIG. 8 for 7 frequencies from 1.8 GHz to 2.2 GHz for a bandwidth of 20%.Docket Number: 103362-097WO1T2025-164

[0087] FIG. 6 illustrates a trajectory (plain line) of the input phasors used to drive the three transistors of the Star OPA. Approximate trajectory (dots) generated by a two-transistor circuit to drive the OPA with a single RF input.

[0088] FIG. 9 illustrates an example trajectory of the CSRP load reflection coefficient seen by each of the transistors, according to a study of an example implementation of the present disclosure. The trajectories of the CSRP load reflection coefficient rp(Pout) seen by each of the transistors as the output power varies from peak to OBO1 and OBO2 backoff are shown in FIG.11. Transistor 1 operates like the main transistor of a Doherty PA from peak to backoff, while transistors 2 and 3 (1) operate like the two transistors of a Chireix PA between peak and OBO1 and (2) jointly turn off between OBO1 and OBO2 like the auxiliary transistor in a two-way Doherty PA. The CSRP loadlines associated with transistors 1 (main) and transistor 2 and 3 (auxiliary) are shown in FIG. 10 for the peak, OBO 1 and OBO 2 backoffs. The auxiliary transistors are on at both the peak and OBO1 backoff, and off at OBO2.

[0089] A comparison of the drain efficiency versus OBO for the Star OPA with a two- way and three-way Doherty PAs is shown in FIG. 11. A flatter efficiency versus OBO is achieved for the Star OPA due to the fact that the auxiliary drain voltage VDSis kept the same at both peak power and OB I compared to the 3-way Doherty PA is also shown in FIG. 11.

[0090] Two transistors operating in class C are used for single-input operation of the OPA as shown in FIG. 6. The resulting phasor trajectories (dots) shown in FIG. 6 sufficiently approximate the linear trajectories (lines) to maintain the drain efficiency.

[0091] Discussion

[0092] Modem cellular communication standards rely on waveforms, such as orthogonal frequency division multiplexing (OFDM), which provide high spectral efficiency but come at the cost of yielding signals with high peak-to-average power ratios (PAPR). To address this challenge new types of power amplifiers (PA) operating with high efficiency at high output backoff (OBO) are required. The driver circuits described herein can be used with the star amplifiers described herein to enable 6G communication protocols.

[0093] The present disclosure implements a new three-transistor outphasing power amplifier (OPA) topology, improving on previous four-transistor topologies. The study shows that the example three-transistor outphasing PA exhibits two OBO power levels like the three-transistor Doherty PA. However unlike the three-transistor Doherty PA, different outphasingDocket Number: 103362-097WO1T2025-164 angles can be required at the input of the OP A when the output power varies between the peak power and the first OBO power level (OBO1). A continuum of modes will be found to be possible including a hybrid Chireix-Doherty operation with a high OBO.

[0094] Despite their high performance, previous outphasing PAs have not been widely adopted due to their requirement for multiple input RF ports and RF input signals dynamically modulated in phase and power (mixed-mode). To address this, implementations of the present disclosure can use a low-power two-transistor RF outphasing driver for generating the three required input RF signals from a single RF input. Using this single RF input driver, the Star OPA exhibits a degradation in power-added efficiency at peak-power but not at backoff, the drain efficiency remaining about the same.

[0095] Example 2:

[0096] A study was performed of an example implementation of the present disclosure including Star OPAs. The star OPAs according to implementations of the present disclosure can be used alone or in combination with the driver circuits described herein to enable 6G communication protocols to be implemented. For example, implementations of the present disclosure include star outphasing power amplifiers that can be used as the injection PA in a 6 or 9 dB Pseudo LMBA or CLMA to achieve an overall output backoff (OBO) of 15.5 or 18.5 dB in support of 6G communication protocols.

[0097] An example implementation of the present disclosure includes

[0098] An example outphasing PA with large output backoff is disclosed and experimentally verified herein. Using nonlinear embedding models, an analysis of the design space for the Star OPA was performed in ter s of the current load modulation factor K^. The Star OPA was compared to other load-modulated PA architectures in terms of the K-factors: / <im, Kva, and Kiato highlight the similarities and differences amongst the architectures.

[0099] Nonlinear embedding models were used to validate, in simulation, the design theory at the CSRP while also projecting the necessary' combiner parameters to the PRP. A prototype circuit was designed and fabricated to operate at a center frequency of 2 GHz. The fabricated PA was characterized using both CW and modulated measurements.

[0100] The Star OPA demonstrated under CW operation a drain efficiency of 61% and 55% at output backoff of 6 dB and 9.5 dB, respectively.Docket Number: 103362-097WO1T2025-164

[0101] The example star OP A herein was implemented with three transistors to realize a 3-Way Star topology providing a OBO 2 value of 9.5 dB. However, the Star topology can be extended to an N-Way architecture for odd values of N. By increasing the number of transistors in the Star OP A, the OBO 2 value can be increased to N2making the Star OP A a promising architecture for future communication systems relying on modulated signals with PAPR values greater than 10 dB(OBO2 = 14 dB for N = 5).

[0102] The Star OPA was demonstrated herein using a three-input testbed to properly drive the PA with the correct input amplitudes and outphasing angles. However a transistor¬ based driver circuit to properly drive the three-input Star OPA with a single RF input should be realizable. A driver circuit described herein (e.g., with reference to example 1) can be used to make the star OPA compatible with RF systems requiring a single RF input.

[0103] A continuum of solution in terms of the peak-to-backoff load-modulation factor of the main PA are disclosed herein. A transmission line based Star OPA is established at the current source reference plane to operate at 2 GHz. The Star OPA is implemented at the package reference plane using a deembeding network so as to sustain the required intrinsic loadmodulation behavior. The Star OPA is fabricated and characterized using both continuous wave (CW) and modulated signals. Under CW excitations, this first experimental Star OPA provides 64% at peak power, 61% at the first backof of 6 dB and 55% and the second backoff of 9.5 dB.

[0104] Example Star Outphasing PA Design

[0105] The analytical generalized Doherty-Chireix continuum theory in describes a two-dimensional continuum of outphasing PAs exhibiting high efficiency at peak and backoff for two transistors. Under the condition that the two transistors have the same peak drain voltage swing ( = 1) the combining circuit can be implemented with two transmission lines. This result can extend the outphasing technique described herein to three transistors as shown in FIG. 1. This PA topology will be referred to as the Star OPA topology herein. The disclosed Star OPA topology features three efficiency peaks at the peak power (label P ) and the two output backoff noted OBO 1 and OBO2 with OBO1 (also noted Bl) the first output backoff below the peak and OBO2 (also noted B2) the second output backoff below OBO1.

[0106] The theoretical analysis of the Star OPA is developed at the CSRP. The present implementation assumes the three transistors to be of the same size and operate with the sameDocket Number: 103362-097WO1T2025-164 maximum drain current magnitude IPand voltage magnitude VPat peak power at the CSRP. All transistors can operate thus with the optimal output load / ?opt— VPIPat peak power. A broadband implementation is obtained at peak power, if (1) the characteri tic impedance Zoof each line is set to / ?optthe optimal real impedance at the CSRP for the transistor operating point selected, and (2) the output load RLis selected to be RL= / ?opt / 3. This implementation corresponds to having a peak power ratio n — 1 in

[0028] with each transistor providing equal output power at peak power for transistors of equal size.

[0107] The electrical lengths 0pfor the three transmission lines must be determined to achieve high efficiency at the two different output backoff power levels. It is assumed that two of the transistors (# 2 and # 3) turn off at the second backoff (OBO2) as in a Doherty P / X or HDmax PA, so that the first transistor behaves much like the main PA of a Doherty resulting in an output backoff OBO 2 of N2= 9 — 9.54 dB with N = 3 for a 3 branch Star OPA.

[0108] For the Star OPA considered herein, the electrical lengthwas selected for the main transistor to be a quarter wave length (= TT / 2 ). It results that the load impedance at OBO 2 seen by the main transistor 1 at the CSRP is R2= 3 / ?opt.

[0109] The auxiliary transistors 2 and 3 can collectively provide a negative resistance in shunt with the load R so that transistor 1 operates with a load1between / ?optand 3 / ?opt. This can be achieved at OBO1 and OBO2 if the susceptances provided by transi stors 2 and 3 cancel at the load reference plane. This implies that their line electrical length must verify 03— n — 02. Further for maximum efficiency operation at class B and C the magnitude of the fundamental RF drain voltage can have the same valueat peak and OBO 1 (and also OBO 2 for the main PA):yB2, Bl, P _ y~ J0B?’B1'PvDS,pl pfc

[0110] with (pp2, B1, P1the phase of the drain voltage at OBO2, OBOl and peak, respectively. Note that the example takes the main transistor as the reference and thus set (1— 0 for all power levels (OBO2, OBOl and peak).

[0111] At peak power all the outphasing angles <p2and (p3are selected to be <p2= 02— TT / 2 and <p — 03— TT / 2 SO the three branch voltages and currents are in phase at the load RL.

[0112] At OBOl the currents will be reduced by a factor and relative to thepeak current magnitude IP= Vp / / ?optfor the main and auxiliary PAs, respectively:Docket Number: 103362-097WO1T2025-164 / „ / Bl >lprBl > TPe^D,1 -KB1’!D,2 ~ - z / 5B^l —, ’ and IQ 3 =^i.a ^ia

[0113] such that the impedances seen by the transistors at OBO1 are R1= K^Roptfor the main PA (p = 1)and / ?f | = K-^Rgpt for the two auxiliary PAs (p = 2,3).

[0114] Using the inverse ABCD parameters of the line 0p, the relation between the voltages and currents at the transistor drain (label D ) and the load (label L ) at OBO 1 are then given by:Vg = cos epV^p -JZosin 0p / f / pIL. P = -J%sin 0pV^p+ cos 0p / f.p(l)with ZQ— Z?opt— 1 / FO. Since the voltages VLpcan all equal at the load:14B1_ J / Bl _:Vp~VL,1 ~ JKB1him sin 0 = cos 6“ia sin 0 = = V^eJ(prcos 0 +J / — / / 5B7l- (2)

[0115] using <p1= 0, 0X= TT / 2 and defining 0 = 02= —03 + n.For the load voltageto hold for all p( 1,2 and 3 ) the following outphasing vectors can be selected:a, -sin0cos 0 +]-7^Te / < H ^ia / oxI:„ sin20^ 0 + ™^I vvtm>,,. sin 0COS 0e / 03 >ia- (4)9a, sin20I vvtm>

[0116] It results from (2) that the electrical length 0 is related to K-^and by:Docket Number: 103362-097WO1T2025-164 1 sin20~ — 57““ = COS20 + ~ — Sy-” (5)(O2(*O2

[0117] The total load current / B1which is equal to the sum of the sub-components of the load current lLpmust also enforce the load boundary condition IL= VL / RLconnecting it to VL:B1-3VLB1T0— 4,1 + 4,2 + 4,32K-B11 +A • (6)nim KiYiBa1

[0118] using (5). From (6) K-^1in terms of can be obtained:,, B1 z(O2m3

[0119] The peak-to-OBOl voltage ratiofor the load voltage VLis equal to K-^: / V Bl ILI _1—;zBlV / - - |TZB1|LMIN IVP / Kim

[0120] At OBO 2 when the two auxiliary transistors are off, the lines 02ar*d 03 present opposite admittances 7 tan (±0) canceling each other. The 2 / 4 line of the main (transistor I) will then sustain the voltage VP(forB„2= I^D. I / ^I | = 1 ) when / 2=with he peak to OBO 2 current ratio X’B2A | / pj / / Bj| = 3. The load seen by the main transistor at OBO 2 is then A’f2= K^Z0= 3Ropt. The peak to OBO 2 voltage ratiofor the auxiliary transistors at OBO 2 can then be calculated using the line h-parameters and setting / B2 / 3= 0 to be / <Ba2A |l4y2 / F^2| — 3cos 0. for the Star OPA is therefore improved (smaller) compared to the conventional Doherty PA for which the Kva— ^ / ~B — 3 for an OBO B of 9

[0028] , Recall that Kvalarger than 1 does not matter at backoff when the auxiliary transistors are off but will introduce the large efficiency dip observed between peak and backoff in the Doherty PA when the auxiliary PAs are turning on. A smaller efficiency dip between OBO 1 and OBO 2 is thus expected in the Star OPA compared to the conventional asymmetric Doherty PA. Note also that like for the Chireix PA, no efficiency dip is expected between OBO1 and peak in the Star OPA given K = A ] V^.p / ^D-p |=1an^ all transistors operate with full voltage swing VPat peak and OBO1.Docket Number: 103362-097WO1T2025-164

[0121] Design and simulation of the example Star Outphasing PA

[0122] To validate the design presented herein, a Star OPA was designed to operate at 2 GHz. The Star OPA design is first verified by performing ideal CSRP simulations using a nonlinear embedding model. The proposed Star OPA combiner circuit and input matching circuits are then synthesized at the package reference plane (PRP). Finally, the simulation results for the fabrication-ready PA circuits are presented and discussed. In this example design, three commercial MACOM GaN HEMTs CGH40010F are used, and a 31 -mil Rogers Duroid 5880 substrate with a dielectric constant of 2.2 was used.

[0123] Verification of the Star Outphasing PA Using A Nonlinear Embedding Model

[0124] Using equations (5) and (7), it can be shown that a continuum of solutions are possible for varying values ofasis highlighted in FIGS. 12A-12B. Thus, the design space can be explored to determine the optimal selection of outphasing combiner parameters for the demonstrator circuit. Replacing the ideal current sources in FIG. 1 with three identical nonlinear embedding device models, as is shown in FIG. 13 A, the Star OPA is initially simulated at the CSRP. The harmonic impedances are all set to short-circuit impedance for each transistor to sustain Class-B and Class-C operation for the main transistor and auxiliary transistors respectively. Using a fixed drain bias of VDD= 28 V, and approximating the knee voltage to be ^knee — 3 V, the fundamental drain voltage for each transistor is equal to be— l^nee I — \VP| = 25 V. The maximum fundamental drain current for the transistors is calculated by using the Class-B approximation of / £>max= / max / 2 with / max= 2 A for the MACOM CGH40010F transistors used in these simulations. This results with the fundamental drain current at peak power for each transistor being equal to / P| = 1 A. Knowing the drain voltage and current values at peak power, the load impedances seen at peak power for each transi stor can be calculated to be I?opt= 2511. The load impedance at OBO1 for the main transistor can be readily calculated by using the current ratiothrough the relationship R1~ K^^opt^ which is to be determined by exploring the design space. Similarly, the load impedance at OBO1 for transistors 2 and 3 can be calculated by1= K^Ropt and R1= KPfRoptwith the current ratioto be determined from (7) once the selection for Kimis made. Therefore to observe the performance for various values, the values 1.5,2, 2.5 for are chosen, and the resulting outphasingDocket Number: 103362-097WO1T2025-164 combiner parameters are calculated using Eqns (5), (7), (3) and (4). The resulting outphasing PA parameters are summarized in Table I herein.

[0125] TABLE I: Outphasing Combiner Parameters.rzBl _ 7= 1-5 '-W, “zC1= 2,5 / CB11.5 2 2.5pBl 37.511 son 62.511pB2 7511 7511 7511KB13 8 25I??1, / if17511 2oon 6251100 00 0002 52,2° 60.8° 66.5°m My c03 M C ' 127.8° 119.2° 113.5°S Oa, Blvm,2 67° 77° 84°aBlain,3 -67° -77° -84°

[0126] To simulate the resulting Star PA performance at the CSRP, nonlinear embedding models are useD. The simulations were performed using a harmonic balance simulator in Keysight Advanced Design System (ADS). Given the outphasing combiner parameters are determined, the remaining item to determine is the appropriate RF input drivers for each transistor at peak, OBO 1 and OBO 2 power levels. Using the schematic shown in FIG. 13B), single transistor simulations were performed to determine the appropriate RF input drive at peak, OBO 1, and OBO 2. By using the calculated peak, OBO 1, and OBO 2 impedance values > P. BI, B2or eac transjstorsubstituted in for RLin FIG. 13B, the appropriate RF input drive level for each transistor is obtained by determining the drive level that corresponds with the expected fundamental drain voltage swing ( Fo^max)- Note that given transistors 2 and 3 areDocket Number: 103362-097WO1T2025-164 assumed to be off at OBO 2, single transistor simulations were not performed for transistors 2 and 3 at the OBO2 level but only peak and OBO1 levels. Following the single transistor simulations, the full Star OP A simulations were performed. Using the schematic shown in FIG 13 A, the Star PA was simulated for a few differentvalues.

[0127] In FIGS. 14A-14F the fundamental reflection coefficients and RF loadlines are plotted at the CSRP for each transistor, for eachvalue simulated. Observing the fundamental reflection coefficients in FIGS. 14A-14F, it can be seen that by increasingthe fundamental reflection coefficient at the OBO1 point moves towards higher impedance values.

[0128] The corresponding drain efficiencies across OBO are plotted in FIG. 15. By moving the impedance seen by the transistors at the OBO1 point towards higher impedance values in FIGS. 14A-14F, the OBO1 efficiency peak moves towards the OBO 2 point and causes a larger dip in efficiency between the OBOI point and peak power as is illustrated in FIG. 15. Comparing the efficiency curves in FIG. 15, one can see that by changing the valueof the first efficiency point (OBO1) moves to lower output power levels with increasing K^.Therefore, to obtain the flattest efficiency profile versus output power, the optimal selection of is 2 which puts the OBO 1 point at 6 dB OBO.

[0129] TABLE II: Comparison of load-modulation factors for different load-modulated PAs with a 9.5 dB obO2 value.C2a PA / < B2 i / Bl i^B2l^va & ^vaaKB1 Aim1 b i b 1 b 1 bAsymmetric- 1 - 3 - 3 00 Doherty1.53 -Way Doherty* 1 1 3 1 | 4 4 | co 00 I 001 00Chireix 1 - 9 1 9HDmax 1 - 4.5 1.28 001.5 |Star OPA 1 1 2 3 1 1 1 8 | 8 00 I co1.5Docket Number: 103362-097WO1T2025-164 Obtained from

[0026] * Obtained from simulation.aAuxiliary' transistor 1.bAuxiliary transistor 2.

[0130] To compare the Star OPA topology with Doherty topologies, specifically the Asymmetric Doherty and 3-Way Doherty, the Star OPA, 3-Way Doherty, and Asymmetric Doherty were all simulated and compared. Similar to the simulations performed for the Star OPA, nonlinear embedding models were used to simulate the Asymmetric Doherty and the 3-Way Doherty. The auxiliary transistor was sized to be twice as large as the main device ( n = 2 ) in the Asymmetric Doherty so that the OBO (given there is only one back-off efficiency peak) point was kept the same at 9.54 dB. The 3 transistors in the 3-Way Doherty were all chosen to be equal sized so that the OBO 2 point in the 3-Way Doherty was also kept consistent to 9.54 dB. This way the three architectures are compared with the same peak power and same OBO 2 point of 9.54 dB. For the Star OPA,was selected to be 2. The simulated drain efficiencies versus output backoff is shown in FIG. 16A. In FIG. 16A, it can be seen that all three architectures exhibit the same efficiency at the 9.54 dB OBO point and also the same efficiency at peak power. However, the Asymmetric Doherty exhibits the deepest valley in between its back-off point and peak power. This due to the fact that the auxiliary transistor does not operate at a high efficiency until it maximizes its drain voltage swing at peak power. The 3 -Way Doherty exhibits a flatter efficiency versus output power than the Asymmetric Doherty. However from the OBO1 point to peak power, the 3 -Way Doherty has a deeper valley compared to the Star OPA. This reduction in drain efficiency in between the OBO1 point and peak power for the 3- Way Doherty can be attributed to the magnitude of the drain voltage for the second auxiliary transistor in the 3-Way Doherty. Due to the second auxiliary transistor only beginning to conduct at the OBO1 point and not achieving a maximum drain voltage swing, the inefficiency of the second auxiliary transistor causes the overall PA efficiency curve to dip slightly. However, the Star OPA is able to maintain a flatter efficiency versus output power than the 3-Way Doherty given that both auxiliary transistors in the Star OPA achieve a larger drain voltage swing at the OBO1 point, as is illustrated by FIG. 16B.

[0131] Using the equations presented in

[0026] to describe the main and auxiliary transistor's load-modulation in terms of Kfactors ( Kia, Kva, Kim, Kvm) a comparison of variousDocket Number: 103362-097WO1T2025-164 PAs with load-modulated architectures is presented in Table II. All the PAs presented in Table II are configured to exhibit an OBO 2 value of 9.5 dB. One can see that all architectures maintain Kvm=1 ( = 1 for three-way PAs) to provide a high drain efficiency for the main transistor at both peak and backoff (OBO1 and OBO2). However, thecurrent load-modulation for the main transistor ( Kim) varies depending on the architecture considered. In the Chireix architecture,is equal to 9 which corresponds with the main transistor seeing an impedance nine times larger at backoff compared to peak. This large level of load-modulation can be undesirable when designing in high frequency MMICs with short gate length transistors as discussed in the introduction

[0019] , The Asymmetric Doherty, 3-Way Doherty, HDmax, and Star OPA ail have a< 4.5 which is a more favorable current modulation. However, in the Asymmetric Doherty, theis equal to 3, which results in the deep valley observed between peak and backoff in the drain efficiency profile of the Asymmetric Doherty. Therefore, it is desirable to bring Kvacloser to 1 as is realized in the Chireix PA.

[0132] Comparing the Star OPA to the 3-Way Doherty, one can see that both PAs haveK-^ = 2 and = 3 at OBO1 and OBO 2, respectively, Thus both architectures provide low current modulation which is desirable as previously noted. However, the 3-Way Doherty has one of the auxiliary transistors exhibiting a= 4 at OBO1, whereas in the Star OPA both auxiliary transistors have K^a — 1 at OBO1. This lowerin the Star OPA is the reason the Star OPA demonstrates a flatter drain efficiency profile in between OBO1 and peak power as is shown in FIG. 16A. Thus, as shown by the various load-modulation factors in Table II, it results that the desirable behavior of the Star OPA is that it achieves a full drain-voltage swing at OBO1 ( ^va — 1 ) f°rboth auxiliary transistors instead of only one for the 3-Way Doherty. This is achieved in the Star OPA while also maintaining a small current modulation value= 3) for a 9.5 dB output backoff OBO 2 like in the 3-Way Doherty PA.

[0133] Design of the Star Outphasing PA Combiner

[0134] With the use of a nonlinear embedding model, the voltage and current waveforms for the combiner circuit can be obtained by projecting the desired CSRP behavior to the PRP. This enables a designer to know the exact fundamental and harmonic impedances that are needed to be designed at the PRP to directly obtain the theoretical intrinsic behavior.

[0135] Alternatively or additionally, one can use a de-embedding network that includes the output device parasitic network and use this de-embedding network to synthesize eachDocket Number: 103362-097WO1T2025-164 branch of the combiner circuit from the CSRP as shown in FIG. 17A. This device output parasitic model, implemented as a linear L-C network, can be used to de-embed the PRP to the CSRP and absorb the device output parasitic into the combiner circuit as is highlighted in FIG.17B, This method enables a designer to synthesize the combiner in separate parts for each of the transistors initially before a final optimization for the entire combiner circuit is performed.Additionally, this facilitates the combiner to be designed from the CSRP, enabling the targeted intrinsic behavior to be obtained with the synthesized combiner that is connected at the package reference plane of the transistors. The theoretical derivations for the Star OPA are derived at the CSRP, and thus obtaining the targeted CSRP behavior is paramount.

[0136] The transmission lines shown in FIG. 1 are synthesized for each of the transistors. The main branch has been selected to have an electrical length set to= 90° and characteristic impedance of Ropt= 25Ω. Based on the simulations performed in the previous sub-section, the choice for the current modulation ratio set to— 2. This in turn results with— 8 which yields the electrical lengths for the auxiliary branches to be 02=60.8° and 03= 119.2°. Given the three transistors are identical, the characteristic impedance for the auxiliary branches are also set to Ropt= 25Ω. Thus the characteristic impedance and electrical length for each transmission line is obtained. Using the de-embedding L-C network shown in FIG. 17B, the three transmission lines were independently synthesized so that the combination of the device output parasitic and the microstrip lines interacting with the package reference plane approximate the CSRP ideal transmission line behavior with a characteristic impedance of ZQ= Ropt= 25Ω and electrical lengths equal to 0i,2.3- The outphasing combiner synthesis begins with the design goal to independently synthesize the main and auxiliary branches using multi-section transmission line circuits connected to the de-embedding L-C network such that the absolute value of the phase of S21, of the combination of the multi-section transmission line circuits and de-embedding network, be close to the theoretical values of the electrical lengths #1,2,3 listed in Table I for ~ 2, In the design of each branch, the de-embedding L-C network is included in the schematic so that the targeted design goals of the characteristic impedance and electrical length, which are defined for the CSRP, can be obtained.

[0137] Next the output impedance transformation network was synthesized to transform the 50Ω termination load to the necessary load impedance, RL= Ropt / 3 = 8.33Ω. In addition toDocket Number: 103362-097WO1T2025-164 the impedance transformation, the dc drain biasing circuit was included to provide dc biasing to all the transistors since the same drain bias voltage was used for each.

[0138] Experimental Results

[0139] The fabricated Star OPA is shown in FIG. 18. The prototype PA was experimentally evaluated with both continuous wave (CW) and modulated signals. In the measurements, the main transistor was biased in deep Class-AB with a drain voltage

[0140] Continuous Wave Measurements

[0141] Large-signal CW measurements were performed. The PNA-X is equipped with three internal phase locked signal generators. Using one of the three sources as a phase reference, the other two sources were used to control the two outphasing angles on both of the auxiliary devices. The outphasing angles for the Star OPA can be controlled with the main transistor being the reference phasor. All three incident powers to the PA and the output power of the PA were measured by the PNA-X. The DC drain voltage and total drain current are captured by external power supplies. The PNA-X and the external power supplies are controlled via USB and Ethernet connections to a host PC running MATLAB.

[0142] The measurement results are compared against the simulated performance in FIG.19. FIG. 19 shows that the measured drain efficiency across output power is in good agreement with the simulated results. The discrepancy in gain can be attributed to fabrication errors that also manifested in shifting the center frequency down to 1.9 GHz from 2 GHz. The theoretical outphasing angles used at OBO1 are calculated as shown:R1( sinZ|COS 0p- J j. (8)

[0143] The outphasing angles used at OBO 2 are selected to be the same as OBO1 since no outphasing angle is theoretically needed since the auxiliary transistors are off at OBO 2. The outphasing angles at peak power are determined by the difference of electrical lengths between the auxiliary branches and the main branch to maintain the auxiliary currents in phase with the expression:e. G = t>v-Docket Number: 103362-097WO1T2025-164

[0144] for p — 2,3- The measured optimal outphasing angles are in close agreement to the simulated and theoretical outphasing angles, and are particularly close once the auxiliary' devices turn on at the OBO1 point.

[0145] The agreement between the output power, drain efficiency, and outphasing angles indicates that the designed Star OPA is operating as intended, exhibiting a high efficiency across the range of OBO values.

[0146] The frequency dependence of the drain efficiency was measured. Although the Star OPA was not explicitly optimized for wide bandwidth, it exhibits a bandwidth of 8% while delivering more than 44.5 dBm output power at ail frequencies.

[0147] Discussion

[0148] As high data rate wireless communication systems are developed for 5G, satellite communications, and beyond, there is an increasing need for power amplifiers (PAs) capable of achieving high effi ciency at saturated output powers and back-off levels of 10 dB and beyond. To address this challenge, PAs that exhibit the technique of load modulation have been investigated for promising performance with high average efficiency. Architectures such as the Doherty PA (DPA), the load-modulated balanced amplifier (LMBA), and outphasing PAs] have been the subject of significant research in recent years.

[0149] These advanced PA architectures offer high efficiency across varying power levels enhancing the average efficiency when transmitting modulated signals with high peak to average power ratios (PAPR). However, as complex modulation schemes, such as orthogonal frequency division multiplexing (OFDM), are evolving to increase their spectral efficiency, the PAPR levels are reaching 10 dB. This can pose a problem in these PA architectures since in order to achieve these high levels of back-off, the PAs will have to undergo a large level of load¬ modulation. For example, for an outphasing Chireix PA to achieve a back-off power level of 10 dB, the devices will have to undergo a current load-modulation of 10 in order to deliver a tenth of the saturated output power. This can be a problem for MMIC designs at high frequencies, as operation at higher frequencies calls for shorter gate lengths which limits the compatibility of architectures with large load-modulation. Indeed, as the gate lengths of devices decrease, the I-V characteristics significantly degrade at low gate voltages. One such degradation observed is the knee walk-out of the I-V. The knee walk-out that is observed is exacerbated at low gate voltages for short gate lengths devices which can limit the obtainable efficiency of a PA. The availableDocket Number: 103362-097WO1T2025-164 linear drain voltage swing can be limited by several volts due to the knee walk-out of short gate length devices. Thus, architectures in which the RF loadline of a transistor operates at low gate voltages due to a large level of current load-modulation are undesirable in short gate length transistor designs. As a result, using advanced nodes in these PA architectures results in a more complex design with marginal benefit in terms of efficiency.

[0150] Alternatively the traditional two-transistor Doherty architecture with an asymmetric topology can be used to achieve a back-off level of > 9 dB while featuring a reduced load modulation compared to the Chireix PA. The asymmetric Doherty amplifier can achieve back-off levels greater than 6 dB by using an auxiliary (or peaking) device that is larger than the main (or carrier) device. However, this tends to result in an efficiency profile that exhibits a deep valley in between the back-off and saturated power levels for output back-off larger than 6 dB.

[0151] This reduction of efficiency in the asymmetric Doherty PA has led designers to investigate the 3-Way Doherty PA which exhibits a flatter efficiency profile across power levels due to the sequencing of the two auxiliary devices. In the 3-Way (or N-Way) Doherty PA, the main device operates similarly to the main device in the asymmetric Doherty where at the second back-off level, the intrinsic impedance presented to the main device is N x l?optwith i?optthe optimal intrinsic load impedance at peak power. In the asymmetric Doherty PA, the larger auxiliary device begins to conduct and deliver power from the back-off point to the peak power level. Whereas in the 3 -Way Doherty, the first auxiliary device begins to conduct at the second back-off point and the second auxiliary device remains off. Once the first back-off level is reached, the second auxiliary device turns on and all three devices operate at saturated power. The flatter efficiency profile in the 3-Way Doherty can be attributed to the load modulation experienced by the main transistor and first auxiliary transistor as compared to only the main transistor undergoing load modulation in the asymmetric Doherty. Since the first auxiliary device is operating separately from the second auxiliary device, the first auxiliary device is able to reach its maximum voltage swing before the second auxiliary device begins conducting via the load modulation. This enables the first auxiliary device to maintain a drain voltage closer to the maximum swing for a larger region of the output power range. This relative drain voltage swing of the auxili ary device when operating at peak power compared to back-off power is defined as Kva. Maintaining a lower Kva(close to 1 ) leads to a higher drain efficiency for a PA due to itDocket Number: 103362-097WO1T2025-164 maintaining a full drain voltage swing across output power. This explains the typically flatter efficiency profile observed in the traditional Chireix PA due to both transistors maintaining a full drain voltage swing at both peak and back-off power levels.

[0152] In the 3-W y Doherty, not all devices maintain a maximum drain voltage swing across output power. The second auxiliary' device in the 3 -Way Doherty operates similarly to the auxiliary' device in the conventional Doherty PA where its drain voltage swing is not maximized until it saturates at peak power. As a result, the efficiency profile dips slightly between the first back-off point and peak power due to this inefficiency of the second auxiliary' device in the transition.

[0153] The present disclosure therefore presents an improved PA architecture, referred to herein as the Star Outphasing PA (OP A) that exhibits a flatter efficiency profile by enabling the drain voltage swing of the auxiliary devices to be maximized for a larger portion of the power range. By doing this, the efficiency across output power maintains a flatter profile and yields a higher average efficiency doing so. Like the 3-Way Doherty, the 9.5 dB Star OPA will can also feature a current load Kimof 3 for the main PA compared to 9 for the Chireix, thus avoiding the deep load modulation which is detrimental in small gate-length high-frequency MMICs. The present disclosure provides experimental verification of the disclosed Star OPA topology with a practical design at the package reference plane. The theoretical derivations of the design equations are presented fully, alongside an analysis of the design space for the Star OPA in terms of the current load modulation factor K-^. Furthermore, the Star OPA is compared to other widely researched load-modulation PA architectures in terms of the K -factors: Kim, Kva, and Kiato emphasize the characteristics of the Star OPA.

[0154] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

Docket Number: 103362-097WO1T2025-164 WHAT IS CLAIMED;1. An outphasing power amplifier, comprising:a main intrinsic transistor coupled to a load via an effective main transmission line realized by its output matching network and parasitics of the transistors;a first auxiliary intrinsic transistor coupled to the load and the main intrinsic transistor and a second auxiliary transistor via an effective first auxiliary transmission line realized by its output matching network and the parasitics of the transistors;wherein the second auxiliary intrinsic transistor is effectively coupled to the load and the first auxiliary' intrinsic transistor and main intrinsic transistor via an effective second auxiliary transmission realized by its output matching network and parasitics of the transistors, wherein the main intrinsic transistor is coupled to the first auxiliary intrinsic transistor and second auxiliary intrinsic transistor by the effective main transmission line; anda star junction coupling the first auxiliary transistor, second auxiliary transistor, and main intrinsic transistor to a load.

2. The outphasing power amplifier of claim 1, further comprising: a plurality of auxiliary transistors coupled to a respective plurality of auxiliary transmission lines.

3. The outphasing power amplifier of claim 1 or claim 2, wherein the outphasing power amplifier comprises an odd number of transistors.

4. The outphasing power amplifier of any one of claims 1 -3, wherein the main intrinsic transistor, first auxiliary transistor, and second auxiliary transistor can be configured to be driven by a single RF input when using an outphasing power amplifier driver.

5. The outphasing power amplifier of any one of claims 1-4, wherein the first auxiliary transistor and / or second auxiliary transistor are configured as peaking amplifiers which are off for output power levels below a second output pow'er backoff (OBO2) and requireDocket Number: 103362-097WO1T2025-164 specific outphasing angles for the first output power backoff (OBO1) and at peak power for high efficiency operation.

6. The outphasing power amplifier of any one of claims 1-5, wherein the star junction is coupled to the load by a load transmission line.

7. The outphasing power amplifier of claim 6, wherein the load transmission line is a quarter-wavelength line.

8. The outphasing power amplifier of any of claims 1-7, wherein the outphasing power amplifier is configured for use as an injection PA for a 6G communication system.

9. The outphasing power amplifier of claim 8, wherein the 6G communication system comprises a pseudo load-modulated balanced amplifier or a circulator load-modulated amplifier.

10. The outphasing power amplifier of claim 9, wherein an overall output backoff of the power amplifier is between 15.5 and 18.5 dB, inclusive.

11. A communication system comprising:an outphasing power amplifier, comprising:a main intrinsic transistor coupled to a load via an effective main transmission line realized by its output matching network and parasitics of the transistors;a first auxiliary intrinsic transistor coupled to the load and the main intrinsic transistor and a second auxiliary transistor via an effective first auxiliary¬ transmission line realized by its output matching network and the parasitics of the transistors;wherein the second auxiliary intrinsic transistor is effectively coupled to the load and the first auxiliary intrinsic transistor and main intrinsic transistor via an effective second auxiliary' transmission line realized by its output matchingDocket Number: 103362-097WO1T2025-164 network and parasitics of the transistors, wherein the main intrinsic transistor is coupled to the first auxiliary intrinsic transistor and second auxiliary intrinsic transistor by the effective main transmission line; anda star junction coupling the first auxiliary transistor, second auxiliary transistor, and main intrinsic transistor to a load; andan outphasing modulation driver, wherein the outphasing modulation driver is operably coupled to the power amplifier and configured to drive the power amplifier using a single input.

12. The communication system of claim 11, further comprising: a plurality of auxiliary transistors coupled to a respective plurality of auxiliary transmission lines.

13. The communication system of claim 11 or claim 12, wherein the outphasing power amplifier comprises an odd number of transistors.

14. The communication system of any one of claims 11-13, wherein the main intrinsic transistor, first auxiliary transistor, and second auxiliary transistor can be configured to be driven by a single RF input when using the outphasing power amplifier driver.

15. The communication system of any one of claims 11-14, wherein the first auxiliary transistor and / or second auxiliary transistor are configured as peaking amplifiers which are off for output power levels below a second output power backoff (OBO2) and require specific outphasing angles for the first output power backoff (OBO1) and at peak power for high efficiency operation.

16. The communication system of any one of claims 11-15, wherein the star junction is coupled to the load by a load transmission line.

17. The communication system of claim 16, wherein the load transmission line is a quarterwavelength line.Docket Number: 103362-097WO1T2025-164 18. The communication system of any one of claims 11-17, wherein the outphasing power amplifier is configured for use as an injection PA for a 6G communication system.

19. The communication system of claim 18, wherein the 6G communication system comprises a pseudo load-modulated balanced amplifier or a circulator load-modulated amplifier.

20. The communication system of claim 19, wherein an overall output backoff is between 15.5 and 18.5 dB, inclusive.

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