Low-temperature electronic system with superlattice thermal materials

Abstract

A cooled electronic system includes an electronic device, a vacuum chamber, a cryogenic cooling system, and an electrical signal line. The vacuum chamber encloses the electronic device. The cryogenic cooling system cools the electronic device and includes a precooling system and cooling stages. A cooling stage supports the electronic device. The electrical signal line couples to the electronic device and includes a superlattice structure. The superlattice structure is disposed at one or more of the cooling stages, is in a thermal conduction path along the electrical signal line to thermally isolate the electronic device, and transmits signals to or from the electronic device.

Description

LOW-TEMPERATURE ELECTRONIC SYSTEM WITH SUPERLATTICE THERMAL MATERIALS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims benefit under 35 U.S.C. § 119(e) to U.S.Provisional Patent Application No. 63 / 756,600 filed on February 10, 2025, which is hereby incorporated by reference in its entirety.FIELD

[0002] The present disclosure generally relates to ultra-cooled electronic devices, in particular thermal isolation and heat mitigation for stable, error-free operation of electronic devices and overall energy efficiency of ultra-cooled and scalable quantum computing electronic systems.BACKGROUND

[0003] Ultra-cooled electronic devices are important for future generations of electronic devices. An example is a quantum computing device, which uses qubits (or Q-bits) that operate at extremely low temperatures. Operating at less than 4 K (-269 °C) minimizes thermal noise and fluctuations that undesirably interact with the quantum state of the qubit. Hence, minimizing heat flow into the operation of cooled electrical devices, like qubits, is desired for energy efficient and stable, error-free computational systems. In many cases, temperatures near absolute zero are desired to achieve the desired electronic stability for carrying out the electronic operation or computation but such quantum computing systems at extreme cold temperatures (~0.1 K to 4 K) also interact with electronic circuitry at higher temperatures like 50 K, 100 K, 150 K and all the way to 300 K.

[0004] Typically, ultra-low-temperature electronic devices are cooled down in a staged refrigerator. To reach the near-absolute zero temperatures (-273 °C) (such as 0.1 K to 4 K) at which the electronic system operates, cryogenic refrigerators can use liquid helium as a coolant. Examples of staged cryogenic refrigerators include dilution refrigerators and adiabatic demagnetization refrigerators. In a “dry” dilution refrigerator, liquid heliumresides inside a closed cycle system, where it is recycled and recondensed using a pulsetube technology. The less heat these refrigerators have to manage, the more compact and energy-efficient they can be, they can enable a scalable larger qubit-count quantum computing system operating with less electrical power.

[0005] Ultra-cooled electronic devices communicate with other devices that are external to the cryogenic system (and also with intermediate electronic devices that can be located at various points within the cryogenic system). For example, a quantum computing system can be connected to a power supply for receiving electrical power, as well as communication lines for communicating with an external computer that houses the software for controlling the quantum computing system. Such connections are access points through which thermal energy can undesirably leak into the ultra-cooled electronic device, be it at 0. IK or 4K or even at intermediate temperatures like 50K. Thus, signal communication and power carrying structures that exhibit high electrical conductivity with low thermal conductivity are highly desirable.SUMMARY

[0006] In view of the above, it is desirable to develop ultra-cooled electronic systems that exhibit improved electrical performance and low thermal conduction into the ultra-cooled electronic system.

[0007] In some aspects, a cooled electronic system can comprise an electronic device, a vacuum chamber, a cryogenic cooling system, and an electrical signal line. The vacuum chamber can enclose the electronic device. The cryogenic cooling system can cool the electronic device. The cryogenic system can comprise a precooling system and cooling stages. A cooling stage can support the electronic device. The electrical signal line can couple to the electronic device. The electrical signal line can comprise a superlattice structure. The superlattice structure can be disposed at one or more of the cooling stages. The superlattice structure can be in a thermal conduction path along the electrical signal line to thermally isolate the electronic device. The superlattice structure can transmit signals to or from the electronic device.

[0008] In some aspects, a cooled electronic system can comprise a cryogenic cooling system and an electrical signal line. The cryogenic cooling system can cool an electronic device. The cryogenic cooling system can comprise cooling stages. A cooling stage cansupport the electronic device. The electrical signal line can couple to the electronic device. The electrical signal line can comprise a superlattice structure. The superlattice structure can be in a thermal conduction path along the electrical signal line to thermally isolate the electronic device.

[0009] In some aspects, a method for thermally isolating a cryogenically cooled electronic device can comprise disposing an electronic device at a cooling stage of a cryogenic cooling stack comprising a series of cooling stages. The method can also comprise disposing an electrical signal line through the cryogenic cooling stack. The electrical signal line can comprise a superlattice structure disposed at one or more of the cooling stages to reduce thermal conduction along the electrical signal line. The method can also comprise coupling the electrical signal line to the electronic device.BRIEF DESCRIPTION OF THE DRAWINGS / FIGURES

[0010] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the relevant art(s) to make and use aspects described herein.

[0011] FIG. 1 A shows a diagram of a cooled electronic system, according to some aspects.

[0012] FIG. IB shows a diagram of an electrical signal line, according to some aspects.

[0013] FIG. 2 shows a data plot of thermal properties of copper, according to some aspects.

[0014] FIG. 3 shows a data plot of thermal properties of bismuth-antimony -based superlattices, according to some aspects.

[0015] FIG. 4 shows a data plot of thermal properties of bismuth-antimony -based superlattice, according to some aspects.

[0016] FIG. 5 shows a data plot of thermal properties of a controlled hierarchically engineered superlattice structure, according to some aspects.

[0017] FIG. 6 shows a data plot of electrical properties of a bismuth-antimony-based superlattice, according to some aspects.

[0018] FIG. 7 shows a data plot of electrical properties of a bismuth-antimony-based superlattice, according to some aspects.

[0019] FIG. 8 shows a data plot of electrical properties of a given controlled hierarchically engineered superlattice structure configuration, according to some aspects.

[0020] FIG. 9 shows a data plot of electrical properties of a given controlled hierarchically engineered superlattice structure configuration, according to some aspects.

[0021] FIG. 10 shows a diagram of superlattice structures, according to some aspects.

[0022] FIG. 11 shows a diagram of controlled hierarchically engineered superlattice structures, according to some aspects.

[0023] FIG. 12 shows a process flow of a method for thermally isolating a cryogenically cooled electronic device, according to some aspects.

[0024] The features of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. Unless otherwise indicated, the drawings provided throughout the disclosure should not be interpreted as to-scale drawings.DETAILED DESCRIPTION

[0025] The aspects described herein, and references in the specification to “one aspect,” “an aspect,” “an exemplary aspect,” “an example aspect,” etc., indicate that the aspects described can include a particular feature, structure, or characteristic, but every aspect may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same aspect. Further, when a particular feature, structure, or characteristic is described in connection with an aspect, it is understood that it is within the knowledge of those skilled in the art to effect such feature, structure, or characteristic in connection with other aspects whether or not explicitly described.

[0026] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “on,” “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device inuse or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

[0027] The terms “about,” “approximately,” “nearly,” or the like can be used herein indicates the value of a given quantity that can vary based on a particular technology. Based on the particular technology, the terms “about,” “approximately,” “nearly,” or the like can indicate a value of a given quantity that varies within, for example, 1-30% of the value (e.g., ±1%, ±5%, ±10%, ±20%, or ±30% of the value).

[0028] In some aspects, descriptive terms relating to electrical characteristics — such as “electric,” “electrical,” “electronic,” or the like — can be used interchangeably in some contexts. However, it is understood that electronic devices are electrical by nature, but electrical devices may not always electronic. For example, the term “electrical” typically refers to devices that use electricity for power delivery, such as those producing heat, motion, or light. In contrast, “electronic” generally refers to devices that manipulate electrical signals using components like diodes or transistors to process information (e.g., computers, phones, quantum computing systems). Electronic devices often rely on semiconductor materials and represent a subset of electrical systems. In another example, the term “electrical signal line” can refer to a wire or other communication line designed to transmit electrical power or data communication.Ultra-Low-Temperature Electronic System

[0029] Described herein are electronic devices implemented in a cryogenic refrigeration system, electrical power carrying and electronic communication structures with improved thermal isolation, and methods for manufacturing the same.

[0030] Aspects of the present disclosure can reduce thermal burden on cryogenic refrigeration systems by replacing some of the internal electrical structures with superlattice structures that reduce thermal conduction from external heat sources. In typical ultra-cooled electronic systems, electrical power carrying or electronic signal lines are made of electrically conductive material, such as copper, aluminum, silver, or the like. Such electrical conductors, while having excellent electrical conductivity, are accompanied by high thermal conductivities as well. Thus, an important consideration in ultra-low-temperature electronic systems is increasing the electrical conductivity of a conduction line without greatly increasing the line’s thermal conductivity. Aspects of thepresent disclosure can implement nanostructured materials that can scatter lattice vibrations / phonons that transport heat without affecting electronic carrier scattering. For example, superlattice and / or controlled hierarchically engineered superlattice structures (CHESS) can carry electrical power or electronic signal to the cold side electronic devices (be it at 100K or 50K or 4K or 0.1K) efficiently but at the same time minimize transport of heat from 300K to 100K or 50K or 4K or 0. IK.

[0031] FIG. 1 A shows a diagram of a cooled electronic system 100, according to some aspects. In some aspects, cooled electronic system 100 can comprise an electronic device 102, a vacuum chamber 104, a cryogenic cooling system 106, and an electrical signal line 108. Electronic device 102 can be a temperature-sensitive device that is prone to errors (in computation) and poor performance in the presence of thermal energy. For example, electronic device 102 can be a quantum computing device comprising one or more qubits, an anomalous quantum-Hall effect device, a spin-injection device, or the like. Vacuum chamber 104 can enclose electronic device 102 to provide an ultra-clean, particle-free environment for electronic device 102. The vacuum environment can protect fragile portions of electronic device 102 from disturbances (e.g., protect qubits from disturbances, preventing decoherence and promoting precise manipulation of quantum states).

[0032] In some aspects, cryogenic cooling system 106 can be a dilution refrigerator, an adiabatic demagnetization refrigerator, or the like. Cryogenic cooling system 106 can cool electronic device 102 to ultra-low temperatures (e.g., in the order of millikelvins). Cryogenic cooling system 106 comprise a precooling system 110 and cooling stages 112. Cooling stages 112 can comprise one or more cooling stages. The example in FIG. 1 A implements an n number of cooling stages denoted as cooling stages 112-1, 112-2, 112-3, and so on up to the nthcooling stage 112-n (collectively can also be referred to as a cryogenic cooling stack). Cooling stage 112-n can be used as a support platform (e.g., a holder) for electronic device 102. Cooling stages 112 can be held at progressively lower temperatures. For example, cooling stage 112-1 can be at less than 300 K (e.g., 200 K, 150 K, 100 K, 50 K, or the like), cooling stage 112-2 can be at 50 K, cooling stage 112-3 can be at 4 K, and so on down to cooling stage 112-n, which can be at <20 mK).

[0033] In some aspects, precooling system 110 can be a cooling system based on liquid helium, which can also be of the dry variety (e.g., closed cycle pulse-tube cooler) or wetvariety (e.g., immersion in liquid helium). Precooling system 110 can be used to start the cooling process by cooling one or more of the ‘warmer’ cooling stages to liquid helium temperatures (e.g., 4 K). Cryogenic cooling system 106 can comprise a pump 114 for actuating a coolant for subsequent cooling operations that achieve millikelvin temperatures. For example, in the case of a dilution refrigerator, pump 114 can circulate a mixture of3He3 and4He through cooling stages 112.

[0034] In some aspects, cooled electronic system 100 can comprise a controller 116 and a power supply 118 for controlling and providing power to electronic device 102.Controller 116 and power supply 118 can be connected to electronic device 102 via electrical signal line 108. Electrical signal line 108 can comprise one or more power supply lines, one or more data communication lines, or a combination thereof. In some aspects, elements outside of vacuum chamber 104 can be exposed to ambient conditions (e.g., a room with air at room temperature). Therefore, a portion of electrical signal line 108 outside of vacuum chamber 104 can be at about 300 K while other portions of electrical signal line 108 can be at cooler temperatures in accordance with respective ones of cooling stages 112.

[0035] In some aspects, electrical signal line 108 can comprise one or more metal wires (e.g., copper, aluminum, silver, or the like), which can have a desirably high electrical conductivity for transmission of power and data signals. In some aspects, electrical signal line 108 can comprise one or more optical fibers for transmitting data signals. Thermal conductivity of the metal wires or even optical fibers can pose a problem if thermal conductivity is disregarded. Transmission of heat from the 300 K region to the ultracooled cooling stages can disrupt / weaken operation of electronic device 102 or make the whole system energy-inefficient.

[0036] Transport of thermal energy in solids generally has two pathways: free charge carriers (electrons) and phonons (lattice vibrations). Electronic heat conduction can dominate in metals and semiconductors. Phononic heat conduction can be present in metals, semiconductors, and insulators to a varying extent relative to electronic heat conduction. In any case, at ultra-low temperatures, phonon heat conduction (e.g., by phonon boundary scattering) becomes significant regardless of material. Hence, in some aspects, electrical signal line 108 can comprise a superlattice structure 120 disposed along electrical signal line 108. Superlattice structure 120 can be built into the line such that thethermal conduction path is interrupted by the superlattice while allowing electrical signals to pass through. In an optical fiber implementation, superlattice structure 120 can be implemented at an interface where the optical signal is converted to an electrical signal, or vice versa.

[0037] It is not required that electrical signal line 108 be contiguous as it traverses cooling stages 112. Electrical signal line 108 can be segmented, where an end of a segment at one cooling stage can connect to the next segment at another cooling stage, or the end of a segment can connect to an intermediate electronic device, as an input, which then continues at an output of the intermediate electronic device.

[0038] In some aspects, electrical signal line 108 can comprise different portions where one or more portions are metal / optical lines and one or more other portions are superlattice structures. Superlattice structure 120 can be disposed at one of cooling stages 112 (e.g., disposed at cooling stage 112-1). Another superlattice structure 122 can be implemented such that it is disposed at one or more cooling stages (e.g., disposed at an interface between cooling stages). Though not shown, there can be electronic devices at one or more of cooling stages 112 (e.g., to perform other types of processing not handled by electronic device 102 or control cooling stages). More superlattice structures 119 and 121 can be implemented to achieve a desired cooling arrangement. Superlattice structures 119, 120, 121, and / or 122 can be used to thermally isolate the electronic devices. Any suitable number of superlattice structures can be implemented (e.g., one or more, two or more, three or more, etc.). Thermal isolation can be achieved by using superlattice structures to mitigate heat transport from one region to another (via low thermal conductivity) while also allowing other types of signals (e.g., electrical power, electronic communication) to pass through (via high electrical conductivity).

[0039] In some aspects, specific superlattice structures can be chosen based on heat rejection and signal transmission performance. Superlattice materials offer flexibility in design choices for the cryogenic cooling stack. Since temperatures can be different from region to region of the cryogenic cooling stack, different superlattice materials can be more suitable for a given temperature profile. For example, superlattice structures 119 and 120 (in the warmer areas of cryogenic cooling system 106) can be implemented as semiconductor-based superlattice structures. Superlattice structure 121 can be implemented as a semimetal-based superlattice structure. Additional examples ofdifferent arrangements for semiconductors, semimetals, and metals are described below with reference to FIGS. 10 and 11.

[0040] FIG. IB shows a diagram of electrical signal line 108, according to some aspects.In some aspects, electrical signal line 108 can comprise power transfer lines 108-1 and 108-2 and electronic communication lines 108-3 and 108-4. Power transfer line 108-1 can comprise a superlattice structure 124. Power transfer line 108-2 can comprise a superlattice structure 126. Power transfer line 108-3 can comprise a superlattice structure 128. Power transfer line 108-4 can comprise a superlattice structure 130. The positions of superlattice structures 124, 126, 128, and 130 in cryogenic cooling system 106 can correspond to any of the positions of superlattice structures 119, 120, 121, or 122 (e.g., can be disposed prior to or at one of cooling stages 112) (FIG. 1 A).

[0041] In some aspects, two-dimensional (2-D) layered chalcogenide materials like Bi2Te3, Sb2Te3, Bi2Se3 and their alloys, as well as Bi / Sb (bismuth / antimony) materials, can create exceptionally low thermal conductivity structures at very low temperatures, in particular superlattice structures and CHESS made from these materials. More information on these materials and CHESS materials can be found in Lee et al., “Thermal Conductivity of Si-Ge Superlattices,” Applied Physics Letters 70(22), 2957-2959 (1997), Venkatasubramanian, “Lattice Thermal Conductivity Reduction and Phonon Localizationlike Behavior in Superlattice Structures,” Physical Review B, 61(4), 3091 (2000), Venkatasubramanian et al., “Thin-Film Thermoelectric Devices with High Room- Temperature Figures of Merit,” Nature, 413(6856), 597-602 (2001), Osborn et al.“Evoking Natural Thermal Perceptions Using a Thin-Film Thermoelectric Device with High Cooling Power Density and Speed,” Nature Biomedical Engineering, 8(8), 1004- 1017 (2024), Ballard et al., “Nano-Engineered Thin-Film Thermoelectric Materials Enable Practical Solid-State Refrigeration,” Nature Communications, 16(1), 4421 (2025), U.S. Patent No. 10,903,139 B2, and U.S. Patent No. 11,908,769, all of which are incorporated herein by reference in their entirety.

[0042] In some aspects, CHESS is a nano-engineered thin-film material. CHESS can include repeating bands of superlattice periods where layer thicknesses are precisely engineered, generally to achieve a specific thermal and / or electronic performance. For example, p-type CHESS (P-CHESS) can include a first CHESS material including first CHESS periods. Each of the first CHESS periods can include a first p-type semiconductoror semimetal material layer disposed adjacent to a second p-type semiconductor or semimetal material layer. The first and second layers of p-type CHESS will likely have comparable bandgap values. The comparable bandgap values mean the differences are in the range of 1 kT to 3 kT — where T is the absolute temperature of operation. For example, if T-100K, kT is 0.0083 eV and so the bandgap difference between one p-layer and another p-layer is in the range of 1 kT to 3 kT. In some aspects, for each of the first CHESS periods, the first p-type semiconductor material layer can include p-type bismuth telluride (Bi2Tes), and the second p-type semiconductor material layer can include p-type antimony telluride (Sb2Te3) or a p-type bismuth antimony telluride alloy (BixSb2-x Tes). In some aspects, for each of the first CHESS periods, the first p-type semiconductor material layer can include a first periodic table Group V-VI, II- VI, or IV compound doped to form a second p-type semiconductor or semi-metal material, and the second p-type semiconductor material layer can include a second periodic table Group V-VI, II- VI, or IV compound doped to form a second p-type semiconductor material. As used herein, the term “semiconductor material” can include, but is not limited to, Bi2Te3, Sb2Te3, Sb2- xBixTes, Bi, Sb, PbTe, PbSe, PbTei-xSex, PbS, PnSnTe, Si, Ge, SixGei-x, or any other suitable material or combination thereof. Semi-metals can include, Bi, Sb, alloy BixSbi-x, or the like. Semi-metals are semiconductor-like but with bandgaps approaching zero or sometimes negative. Semi-metals can also serve the purpose of good electrical conduction. By engineering semi-metals in a superlattice configuration (e.g., Bi / Sb, BixSbi-x / BiySbl-y, or the like), heat transport can be reduced. These semi-metals, with very small bandgap (e.g., 0 eV to 0.06 eV) are very attractive for ultra-low temperature applications (e.g., below 50K to IK) where the extremely good electrical conductivity of semi-metals can be combined with the ability to build superlattices and CHESS. Using such materials like Bi / Sb, BixSbi-x / BiySbi-y can reduce heat transport.

[0043] In some aspects, n-type CHESS (N-CHESS) can include a second CHESS material including second CHESS periods. In some aspects, each of the second CHESS periods can include a first n-type semiconductor or semi-metal material layer disposed adjacent to a second n-type semiconductor or semi-metal material layer. In some aspects, for each of the second CHESS periods, the first n-type semiconductor material layer can include n-type Bi2Te3, and the second n-type semiconductor material layer can include n- type Bi2Se3 or n-type Bi2Te3-xSex. The comparable bandgap values mean the differencesare in the range of 1 kT to 3 kT — where T is the absolute temperature of operation. For example, if T-100K, kT is 0.0083 eV, then the bandgap difference between one n-layer and another n-layer is in the range of 1 kT to 3 kT. In some aspects, for each of the second CHESS periods, the first n-type semiconductor material layer can include a first periodic table Group V-VI, II- VI, or IV compound doped to form a first n-type semiconductor material, and the second n-type semiconductor material layer can include a second periodic table Group V-VI, II- VI, or IV compound doped to form a second n-type semiconductor material. As used herein, the term “semiconductor material” can include, but is not limited to, Bi2Te3, Bi2Se3,Bi2Te3-xSex, Bi, Sb, PbTe, PbSe, PbTei-xSex, PbS, PnSnTe, Si, Ge, SixGei-x, or any other suitable material or combination thereof. The above-description of semi-metals with respect to P-CHESS is also applicable to N- CHESS. In some aspects, the thermoelectric structures can include P-CHESS and n-type CHESS. In some aspects, the pair of thermoelectric structures can include one P-CHESS and oneN-CHESS. .

[0044] Since high electrical transport is desirable, while minimizing thermal transport, some aspects can include superlattices and CHESS of metals, for example, by combining one or more layers of metals like Cu, Al, Ni, Au, Pt, etc. An example could be Cu / Al or Cu / Au or Cu / Ni or Cu / Pt superlattice, where the electrical conductivity across these metallic superlattice can be maintained but heat transport is degraded across such interfaces based on the engineered nanostructure. Such metallic superlattices (e.g., Cu / Al layers) and CHESS (e.g., Cu / CuxAli-x / CuyAli-y / CuzAli-z, where x, y, and z can be different values) can be used for both good electrical conduction and poor thermal conduction at extremely low temperatures. Such metallic superlattices and their CHESS arrangement can serve as p-type leads or n-type leads in extreme cold conditions. If T is low (~4K) and kT is very small, metallic superlattices / CHESS and semi-metallic superlattices / CHESS can be optimal.Thermal Conductivity and Electrical Conductivity

[0045] For baseline comparisons, FIG. 2 shows a data plot 200 of thermal properties of copper, according to some aspects. In some aspects, data plot 200 is a visual representation of thermal conductivity (in W / (m-K)) as a function of temperature (K). The type of copper represented in data plot 200 is one with a purity that results in a residual resistance ratio (RRR) of about 50. RRR is a measure of copper’s purity andquality — defined as the ratio of electrical resistivity (or resistance) at room temperature to resistivity (or resistance) at a very low temperature (typically the boiling point of liquid helium). A higher RRR value signifies purer copper with fewer impurities and defects, leading to better electrical and thermal conductivity at cryogenic temperatures. Since thermal conductivity can vary as a function of temperature (and electrical signal line 108 (FIGS. 1 A and IB) can be subject to a wide range of temperatures), it is desirable for the chosen material for portions of electrical signal line 108 to exhibit low thermal conductivity throughout the range of expected working temperatures (e.g., about 0 K to 300 K). As shown in data plot 200, the thermal conductivity of copper is in the order of hundreds of W / (m-K). During cooling, as temperatures reach liquid nitrogen temperatures (about 77 K), the thermal conductivity can abruptly jump to almost 1500 W / (m-K). Even after the crest, the thermal conductivity remains above 200 W / (m-K) as temperatures approach liquid helium temperatures (about 4 K) and lower.

[0046] FIG. 3 shows a data plot 300 of thermal properties of bismuth-antimony -based superlattices, according to some aspects. In some aspects, data plot 300 is a visual representation of thermal conductivity (in W / (m-K)) as a function of temperature (K). The two types of superlattices represented are periodic layers of Bi / BiwSbio (3 nm / 3 nm) and periodic layers of Bi / BisoSb2o (3 nm / 3 nm). As shown, thermal conductivity over the temperature range of about 80 K to 323 K is less than 2 W / (m-K), sometimes as low as about 0.2 W / (m-K) (compare to hundreds to thousands of W / (m-K) of copper).Furthermore, thermal conductivity decreases as the material is cooled to lower temperatures, which is a trait that can improve the performance and stability of electronic device 102 (FIG. 1 A) when the superlattice material is used to break the thermal conduction path of electrical signal line 108 (FIGS. 1A and IB).

[0047] In some aspects, superlattice structures can drastically reduce the mean free path of phonons. The reduction of mean free path is achieved via interface scattering at the periodic interfaces in the superlattice. This concept is applicable to CHESS materials as well.

[0048] FIG. 4 shows a data plot 400 of thermal properties of bismuth-antimony -based superlattice, according to some aspects. In some aspects, data plot 300 is a visual representation of thermal conductivity (in W / (m-K)) as a function of temperature (K). A difference from FIG. 3 is that bulk bismuth (Bi, white triangle data) and bulk antimony(Sb, black triangle data) are shown for comparison, as well as different superlattice structures, such as Bi / Sb (10 nm / 10 nm) (white circle data) and Bi / Sb (3 nm / 3 nm) (black circle data). The difference between bulk materials and their superlattice engineered arrangements is stark. While bulk Bi and bulk Sb have relatively low thermal conductivities in the range of 77 K to 300 K, they both exhibit an undesirable increase in thermal conductivity as temperature is reduced. On the other hand, the Bi / Sb (10 nm / 10 nm) superlattice and the Bi / Sb (3 nm / 3 nm) superlattice have lower overall thermal conductivities and a trend of decreasing thermal conductivity as temperature is reduced.

[0049] FIG. 5 shows a data plot 500 of thermal properties of a CHESS, according to some aspects. In some aspects, data plot 300 is a visual representation of thermal conductivity (in W / (m-K)) as a function of temperature (K). Data plot 500 shows data for two classes of bismuth and / or antimony materials: bulk bismuth telluride (Bi2Tes) and CHESS (several superlattice variations of p-type Bi2Te3 / Sb2Te3). As shown, the thermal conductivity of bulk Bi2Te3 is higher (e.g., at least three times greater) than that of CHESS materials engineered from the same Bi2Te3. Furthermore, bulk Bi2Te3 exhibits an undesirable increase in thermal conductivity as temperature is reduced. In contrast, the different CHESS variants exhibit very low and consistent (almost constant) thermal conductivity values across the temperature range 80 K to 300 K.

[0050] In some aspects, based on the data in FIGS. 3-5, superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 (FIG. 1 A) can be engineered to have a thermal conductivity of less than about 10 watt per meter-kelvin at a temperature of 300 K or lower, less than about 5 watt per meter-kelvin at a temperature of 300 K or lower, less than about 2 watt per meter-kelvin at a temperature of 300 K or lower, less than about 1 watt per meter-kelvin at a temperature of 300 K or lower, less than about 0.5 watt per meter-kelvin at a temperature of 300 K or lower, less than about 10 watt per meter-kelvin at a temperature of 100 K or lower, less than about 5 watt per meter-kelvin at a temperature of 100 K or lower, less than about 2 watt per meter-kelvin at a temperature of 100 K or lower, less than about 1 watt per meter-kelvin at a temperature of 100 K or lower, less than about 0.5 watt per meter-kelvin at a temperature of 100 K or lower, less than about 10 watt per meter-kelvin at a temperature of 80 K or lower, less than about 5 watt per meter-kelvin at a temperature of 80 K or lower, less than about 2 watt per meterkelvin at a temperature of 80 K or lower, less than about 1 watt per meter-kelvin at atemperature of 80 K or lower, or less than about 0.5 watt per meter-kelvin at a temperature of 80 K or lower.

[0051] In some aspects, superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 (FIG. 1 A) can be engineered to have a thermal conductivity that does not exceed about 10 watt per meter-kelvin at a temperature range of about 77 K to 300 K, does not exceed about 5 watt per meter-kelvin at a temperature of range of about 77 K to 300 K, does not exceed about 2 watt per meter-kelvin at a temperature range of about 77 K to 300 K, does not exceed about 1 watt per meter-kelvin at a temperature range of about 77 K to 300 K, does not exceed about 0.5 watt per meter-kelvin at a temperature range of about 77 K to 300 K, does not exceed about 10 watt per meter-kelvin at a temperature range of about 77 K to 200 K, does not exceed about 5 watt per meter-kelvin at a temperature of range of about 77 K to 200 K, does not exceed about 2 watt per meterkelvin at a temperature range of about 77 K to 200 K, does not exceed about 1 watt per meter-kelvin at a temperature range of about 77 K to 200 K, does not exceed about 0.5 watt per meter-kelvin at a temperature range of about 77 K to 200 K, does not exceed about 10 watt per meter-kelvin at a temperature range of about 77 K to 150 K, does not exceed about 5 watt per meter-kelvin at a temperature of range of about 77 K to 150 K, does not exceed about 2 watt per meter-kelvin at a temperature range of about 77 K to 150 K, does not exceed about 1 watt per meter-kelvin at a temperature range of about 77 K to 150 K, does not exceed about 0.5 watt per meter-kelvin at a temperature range of about 77 K to 150 K, does not exceed about 10 watt per meter-kelvin at a temperature range of about 77 K to 100 K, does not exceed about 5 watt per meter-kelvin at a temperature of range of about 77 K to 100 K, does not exceed about 2 watt per meterkelvin at a temperature range of about 77 K to 100 K, does not exceed about 1 watt per meter-kelvin at a temperature range of about 77 K to 100 K, or does not exceed about 0.5 watt per meter-kelvin at a temperature range of about 77 K to 100 K.

[0052] FIG. 6 shows a data plot 600 of electrical properties of a bismuth-antimony-based superlattice, according to some aspects. In some aspects, data plot 600 is a visual representation of electrical conductivity (in l / (Q-cm)) as a function of temperature (K). The specific superlattice used for the data uses periodic layers of 1 nm Bi2Te3 / 5 nm Sb2Te3. The overall electrical conductivity across the temperature range 77 K to 300 K is suitably high for transmission of power and data signals. Furthermore, the data shows thatelectrical conductivity increases (becomes a better electrical conductor) as temperature is reduced, which is desirable for more efficient transmission of electrical power and electronic data at lower temperatures.

[0053] FIG. 7 shows a data plot 700 of electrical properties of a bismuth-antimony-based superlattice, according to some aspects. Data plot 700 and 600 (FIG 6) are related in that the specific superlattice is the same, 1 nm Bi2Te3 / 5 nm Sb2Te3, except that data plot 700 is a visual representation of electron mobility (in cm2 / (V-s)) as a function of temperature (K).

[0054] While data plots 600 and 700 are specific to a superlattice comprising 1 nm Bi2Te3 / 5 nm Sb2Te3, the general trend is also expected in similar superlattice configurations (e.g., 1 nm Bi2Te3 / 3 nm Sb2Te3, 1 nm Bi2Te3 / 4 nm Sb2Te3, 1 nm Bi2Te3 / 6 nm Sb2Te3, 1 nm Bi2Te3 / 7 nm Sb2Te3, 2 nm Bi2Te3 / 3 nm Sb2Te3, 3 nm Bi2Te3 / 4 nm Sb2Te3, 2 nm Bi2Te3 / 5 nm Sb2Te3, 2 nm Bi2Te3 / 6 nm Sb2Te3, 2 nm Bi2Te3 / 7 nm Sb2Te3, or the like).

[0055] FIG. 8 shows a data plot 800 of electrical properties of a given CHESS configuration, according to some aspects. In some aspects, data plot 800 is a visual representation of electrical conductivity (in l / (Q-cm)) as a function of temperature (K). The specific CHESS configuration used for the data corresponds to one of the p-type Bi2Te3 / Sb2Te3 CHESS variants represented in FIG. 5. The overall electrical conductivity across the temperature range 77 K to 300 K is suitably high for transmission of power and data signals. Furthermore, the data shows that electrical conductivity increases (becomes a better electrical conductor) as temperature is reduced, which is desirable for more efficient transmission of electrical power and electronic data at lower temperatures.

[0056] FIG. 9 shows a data plot 900 of electrical properties of a given CHESS configuration, according to some aspects. Data plot 900 and 800 (FIG. 8) are related in that the specific CHESS configuration is the same, except that data plot 900 is a visual representation of electron mobility (in cm2 / (V-s)) as a function of temperature (K).

[0057] In some aspects, based on the data in FIGS. 3-5, superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 (FIG. 1 A) can be engineered to have an electrical conductivity of greater than 1000 reciprocal Ohm-cm at a temperature of 300 K or lower, greater than 2000 reciprocal Ohm-cm at a temperature of 300 K or lower, greater than 3000 reciprocal Ohm-cm at a temperature of 300 K or lower, greater than 4000 reciprocal Ohm-cm at a temperature of 300 K or lower, greater than 1000 reciprocal Ohm-cm at atemperature of 200 K or lower, greater than 2000 reciprocal Ohm-cm at a temperature of 200 K or lower, greater than 3000 reciprocal Ohm-cm at a temperature of 200 K or lower, greater than 4000 reciprocal Ohm-cm at a temperature of 200 K or lower, greater than 1000 reciprocal Ohm-cm at a temperature of 100 K or lower, greater than 2000 reciprocal Ohm-cm at a temperature of 100 K or lower, greater than 3000 reciprocal Ohm-cm at a temperature of 100 K or lower, greater than 4000 reciprocal Ohm-cm at a temperature of 100 K or lower, greater than 1000 reciprocal Ohm-cm at a temperature of 77 K or lower, greater than 2000 reciprocal Ohm-cm at a temperature of 77 K or lower, greater than 3000 reciprocal Ohm-cm at a temperature of 77 K or lower, or greater than 4000 reciprocal Ohm-cm at a temperature of 77 K or lower.

[0058] In some aspects, superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 (FIG. 1 A) can be engineered to have an electrical conductivity that is not less than about 500 reciprocal Ohm-cm at a temperature range of about 77 K to 300 K, not less than about 800 reciprocal Ohm-cm at a temperature range of about 77 K to 300 K, not less than about 1000 reciprocal Ohm-cm at a temperature range of about 77 to 300 K, not less than about 500 reciprocal Ohm-cm at a temperature range of about 77 K to 200 K, not less than about 800 reciprocal Ohm-cm at a temperature range of about 77 K to 200 K, not less than about 1000 reciprocal Ohm-cm at a temperature range of about 77 to 200 K, not less than about 1500 reciprocal Ohm-cm at a temperature range of about 77 to 200 K, not less than about 1800 reciprocal Ohm-cm at a temperature range of about 77 to 200 K, not less than about 500 reciprocal Ohm-cm at a temperature range of about 77 K to 100 K, not less than about 800 reciprocal Ohm-cm at a temperature range of about 77 K to 100 K, not less than about 1000 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, not less than about 1500 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, not less than about 1800 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, 2000 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, not less than about 3000 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, not less than about 4000 reciprocal Ohm-cm at a temperature range of about 77 to 100 K, or not less than about 4200 reciprocal Ohm-cm at a temperature range of about 77 to 100 K.

[0059] The combination of desirable thermally insulative behavior shown in FIGS. 3-5 and the electrically conductive behavior shown in FIGS. 6-9 make superlattices — including CHESS materials — suitable for the electrical signal path while thermallyisolating a protected electronic device. Referring to FIG. 1 A, by implementing superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 with the abovedescribed superlattice properties, the performance of electronic device 102 (e.g., qubits, anomalous quantum -Hall effect device, a spin-injection device, or the like) can be substantially improved, as well as improving the energy efficiency of cryogenic cooling system 106.

[0060] Above, aspects were described in which superlattices can be made from semiconductors, semimetals, and / or metals. FIG. 10 shows a diagram of a set of superlattice structures 1000, according to some aspects. The set includes an example of a semiconductor-based superlattice structure 1002, an example of a semimetal -based superlattice structure 1004, and an example of a metal -based superlattice structure 1006.

[0061] In some aspects, semiconductor-based superlattice structure 1002 can be used in cryogenic cooling system 106 (FIG. 1 A) at locations where temperatures are, for example, between about 300 K to about 150 K. Semiconductor-based superlattice structure 1002 can comprise alternating, periodic layers of Bi2Te3 and Sb2Te3. The Bi2Te3 layers can have a thickness of about 1 to 2 nm. The Sb2Te3 layers can have a thickness of about 3 to 6 nm. Thicknesses can be suitably engineered for achieving desired thermal and electronic performance.

[0062] In some aspects, semimetal -based superlattice structure 1004 can be used in cryogenic cooling system 106 (FIG. 1 A) at locations where temperatures are, for example, between about 150 K to about 4 K. Semimetal -based superlattice structure 1004 can comprise alternating, periodic layers of bismuth and antimony. The bismuth layers can have a thickness of about 8 to 16 nm. The antimony layers can have a thickness of about 2 to 4 nm. Thicknesses can be suitably engineered for achieving desired thermal and electronic performance.

[0063] In some aspects, metal -based superlattice structure 1006 can be used in cryogenic cooling system 106 (FIG. 1A) at locations where temperatures are, for example, between about 20 K and below. Metal-based superlattice structure 1006 can comprise alternating, periodic layers of copper and silver. The copper layers can have a thickness of about 1 to 30 nm. The antimony layers can have a thickness of about 1 to 30 nm. Thicknesses can be suitably engineered for achieving desired thermal and electronic performance.

[0064] FIG. 11 shows a diagram of a set of CHESS arrangements 1100, according to some aspects. The set includes an example of a semiconductor-based CHESS 1102, an example of a semimetal-based CHESS 1104, and an example of a metal-based CHESS 1106.

[0065] In some aspects, semiconductor-based CHESS 1102 can be used in cryogenic cooling system 106 (FIG. 1A) at locations where temperatures are, for example, between about 300 K to about 150 K. Semiconductor-based CHESS 1102 can comprise alternating layers of Bi2Te3 and Sb2Te3. In CHESS materials, layer thicknesses are precisely engineered, generally to achieve a specific thermal and / or electronic performance. For example, the Bi2Te3 layers can have a thickness of about 1 nm. The Sb2Te3 layers can have different thicknesses, e.g., starting with about 3 nm for the first of its layers, then about 4 nm for a second one of its layers, then about 5 nm for the next layer, and about 6 nm for the layer thereafter.

[0066] In some aspects, semimetal -based CHESS 1104 can be used in cryogenic cooling system 106 (FIG. 1 A) at locations where temperatures are, for example, between about 150 K to about 4 K. Semimetal-based CHESS 1104 can comprise alternating layers of bismuth and antimony. The bismuth layers can have a thickness of about 16 nm. The antimony layers can have different thicknesses, e.g., starting with about 5 nm for the first of its layers, then about 4 nm for a second one of its layers, then about 3 nm for the next layer, and about 2 nm for the layer thereafter.

[0067] In some aspects, metal -based CHESS 1106 can be used in cryogenic cooling system 106 (FIG. 1 A) at locations where temperatures are, for example, between about 20 K and below. Metal-based CHESS 1106 can comprise alternating, periodic layers of copper and silver. The copper layers can have different thicknesses, e.g., starting with about 30 nm for the first of its layers, then about 25 nm for a second one of its layers, then about 20 nm for the next layer, and about 15 nm for the layer thereafter. The antimony layers can also have different thicknesses, e.g., starting with about 4 nm for the first of its layers, then about 3 nm for a second one of its layers, then about 2 nm for the next layer, and about 1 nm for the layer thereafter.

[0068] The use of a particular material is not limited to the temperature ranges described above. Semiconductor-based superlattices, semimetal-based superlattices, and metalbased superlattices can be used at any suitable temperature range.Method for Isolating a Cryogenically Cooled Electronic Device

[0069] FIG. 12 shows a process flow of a method 1200 for thermally isolating a cryogenically cooled electronic device, according to some aspects. In some aspects, operations of method 1200 may be described with reference to elements of FIGS. 1 A and IB.

[0070] In some aspects, operation 1202 may comprise disposing an electronic device at a cooling stage of a cryogenic cooling stack comprising a series of cooling stages. For example. Electronic device 102 can be disposed at a distal end of cooling stages 112 (e.g., disposed at cooling stage 112-n). In another example, one or more electronic devices can be disposed at any of cooling stages 112.

[0071] In some aspects, operation 1204 may comprise disposing an electrical signal line through the cryogenic cooling stack. For example, electrical signal line 108 can be fed through one or more cooling stages 112. Electrical signal line 108 can comprise one or more superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 disposed at one or more of cooling stages 112. Superlattice structures 119, 120, 121, 122, 124, 126, 128, and / or 130 can reduce thermal conduction to the electronic device along electrical signal line 108 even at refrigeration temperatures (e.g., at about 200 K or lower, at about 100 K or lower, at about 77 K or lower, at about 50 K or lower, at about 20 K or lower, at about 10 K or lower, at about 4 K or lower, at about 1 K or lower, at about 0.2 K or lower, or the like).

[0072] In some aspects, operation 1206 may comprise coupling the electrical signal line to the electronic device (e.g., coupling electronic signal line 108 to electronic device 102).

[0073] Further operations can comprise operating the cryogenic cooling stack to cool the electronic device and transmitting signals to or from the cooled electronic device through the superlattice structure.

[0074] It will be understood that the order of the above operations are merely exemplary, and the operations can be rearranged in any appropriate manner, and that the method can be modified consistent with the present disclosure. Additionally, more or fewer operations may be included in the exemplary method consistent with the disclosure.

[0075] The foregoing description of specific aspects will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications such specific embodiments, withoutundue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0076] The breadth and scope of the present invention should not be limited by any of the above-described exemplary aspects, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A cooled electronic system comprising:an electronic device;a vacuum chamber configured to enclose the electronic device;a cryogenic cooling system configured to cool the electronic device and comprising a precooling system and cooling stages, wherein a cooling stage is configured to support the electronic device;an electrical signal line configured to couple to the electronic device and comprising a superlattice structure, wherein the superlattice structure is:disposed at one or more locations of the cooling stages;in a thermal conduction path along the electrical signal line to thermally isolate the electronic device; andconfigured to transmit signals or power to or from the electronic device.

2. The cooled electronic system of claim 1, wherein the electronic device is a quantum computing device comprising one or more qubits, an anomalous quantum-Hall effect device, or a spin-injection device.

3. The cooled electronic system of claim 1, wherein the superlattice structure comprises a bismuth-antimony superlattice.

4. The cooled electronic system of claim 1, wherein the superlattice structure comprises a controlled hierarchically engineered superlattice structure.

5. The cooled electronic system of claim 4, wherein the controlled hierarchically engineered superlattice structure comprises two-dimensional layered chalcogenide semiconductor material.

6. The cooled electronic system of claim 5, wherein the two-dimensional layered chalcogenide semiconductor material comprises Bi2Te3, an alloy of Bi2Te3, Sb2Te3, an alloy of Sb2Te3, Bi2Se3, or an alloy of Bi2Se3.

7. The cooled electronic system of claim 1, wherein the superlattice structure comprises a semiconductor-based superlattice structure.

8. The cooled electronic system of claim 1, wherein the superlattice structure comprises a semimetal-based superlattice structure.

9. The cooled electronic system of claim 1, wherein the superlattice structure comprises a metal-based superlattice structure.

10. The cooled electronic system of claim 1, wherein the superlattice structure is engineered to have a thermal conductivity of less than 10 watt per meter-kelvin at a temperature of 200 kelvin or lower.

11. The cooled electronic system of claim 1, wherein the superlattice structure is further configured to maintain the electronic device at a temperature of about 200 kelvin or lower, about 100 kelvin or lower, or about 50 kelvin or lower.

12. The cooled electronic system of claim 1, wherein the superlattice structure is engineered to have an electrical conductivity of greater than 3000 reciprocal Ohm-cm at a temperature of 200 kelvin or lower.

13. A cooled electronic system comprising:a cryogenic cooling system configured to cool an electronic device and comprising cooling stages, wherein a cooling stage is configured to support the electronic device; andan electrical signal line configured to couple to the electronic device and comprising a superlattice structure, wherein the superlattice structure is in a thermal conduction path along the electrical signal line to thermally isolate the electronic device.

14. The cooled electronic system of claim 13, wherein the electronic device is a quantum computing device comprising one or more qubits, an anomalous quantum-Hall effect device, or a spin-injection device.

15. The cooled electronic system of claim 13, wherein the superlattice structure comprises a bismuth-antimony superlattice.

16. The cooled electronic system of claim 13, wherein the superlattice structure comprises a controlled hierarchically engineered superlattice structure.

17. The cooled electronic system of claim 16, wherein the controlled hierarchically engineered superlattice structure comprises two-dimensional layered chalcogenide semiconductor material.

18. The cooled electronic system of claim 17, wherein the two-dimensional layered chalcogenide semiconductor material comprises Bi2Te3, an alloy of Bi2Te3, Sb2Te3, an alloy of Sb2Te3, Bi2Se3, or an alloy of Bi2Se3.

19. The cooled electronic system of claim 13, wherein the superlattice structure comprises a semiconductor-based superlattice structure.

20. The cooled electronic system of claim 13, wherein the superlattice structure comprises a semimetal-based superlattice structure.

21. The cooled electronic system of claim 13, wherein the superlattice structure comprises a metal-based superlattice structure.

22. The cooled electronic system of claim 13, wherein the superlattice structure is engineered to have a thermal conductivity of less than 10 watt per meter-kelvin at a temperature of 200 kelvin or lower.

23. The cooled electronic system of claim 13, wherein the superlattice structure is further configured to maintain the electronic device at a temperature of about 200 kelvin or lower, about 100 kelvin or lower, or about 50 kelvin or lower.

24. The cooled electronic system of claim 13, wherein the superlattice structure is engineered to have an electrical conductivity of greater than 3000 reciprocal Ohm-cm at a temperature of 200 kelvin or lower.

25. The cooled electronic system of claim 13, wherein the superlattice structure is configured to reduce thermal conduction to the electronic device at temperatures of about 200 kelvin or lower.

26. A method for thermally isolating a cryogenically cooled electronic device, the method comprising:disposing an electronic device at a cooling stage of a cryogenic cooling stack comprising a series of cooling stages;disposing an electrical signal line through the cryogenic cooling stack, wherein the electrical signal line comprises a superlattice structure disposed at one or more of the cooling stages to reduce thermal conduction along the electrical signal line; and coupling the electrical signal line to the electronic device.

27. The method of claim 26, further comprising:operating the cryogenic cooling stack to cool the electronic device; and transmitting signals to or from the cooled electronic device via the superlattice structure.

28. The method of claim 26, wherein the superlattice structure comprises a semiconductorbased superlattice structure.

29. The method of claim 26, wherein the superlattice structure comprises a semimetal-based superlattice structure.

30. The method of claim 26, wherein the superlattice structure comprises a metal-based superlattice structure.

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