Method and apparatus for mesh generation

Abstract

A mesh generation method and apparatus are disclosed. A mesh generation method according to an embodiment may include: identifying at least one constraint line corresponding to a 2D pattern; dividing and straightening the at least one constraint line; dividing the 2D pattern into at least one patch based on a segmentation graph corresponding to the straightened constraint line; performing quadrangulation for each patch based on a parity of vertices included in a boundary line of the corresponding patch; and generating a quad mesh in which the constraint line is preserved based on a result of the quadrangulation.

Description

METHOD AND APPARATUS FOR MESH GENERATIONBackgroundTechnical Field

[0001] The following embodiments relate to a method and apparatus for mesh generation. Description of the Related Art

[0002] In the fashion industry, computer-based simulation technology is widely used to design fashion items. There is a demand for the development of technology to simulate the realistic appearance of fashion items in a virtual environment, such as designing fashion items or simulating the appearance of virtual characters wearing fashion items in the gaming industry. To realistically simulate 3D fashion items, a method of modeling the surface of a fashion item as a mesh, which is a set of a plurality of polygons, is widely used. As an example of a polygonal mesh, a quad mesh has a regular topology, and thus may have advantages in subdivision, texture mapping, or visual rendering.Summary

[0003] Embodiments relates to mesh generation by at least one processor. A constraint edge set corresponding to at least a portion of a line on a 2D pattern is obtained. A quad mesh corresponding to the 2D pattern is generated based on the constraint edge set. The constraint edge set in the 2D pattern is preserved in the quad mesh.

[0004] In one or more embodiments, a method, the constraint edge set includes one or more interior vertices positioned between both endpoints of the constraint edge set. The preservation of the constraint edge set in the quad mesh includes maintaining a position of each of the one or more interior vertices in the 2D pattern as a position of each of the one or more interior vertices in the quad mesh.

[0005] In one or more embodiments, the preservation of the constraint edge set in the quad mesh includes preserving the constraint edge set in the quad mesh without adding an interior vertex to the constraint edge set.

[0006] In one or more embodiments, the quad mesh includes a first mesh region and a second mesh region adjacent to each other with the constraint edge set as a portion of a boundary. Anedge flow between the first mesh region and the second mesh region includes at least one of a change in geometric direction or topological irregularity.

[0007] In one or more embodiments, the topological irregularity is formed in response to a difference between a grid density of the first mesh region and a grid density of the second mesh region.

[0008] In one or more embodiments, a region including the first mesh region and the second mesh region includes a vertex whose valence is not 4.

[0009] In one or more embodiments, the vertex whose valence is not 4 is not disposed on the constraint edge set except for both endpoints of the constraint edge set.

[0010] In one or more embodiments, the change in geometric direction is formed in response to a difference between a first angle formed by a first edge of the first mesh region and the constraint edge set and a second angle formed by a second edge of the second mesh region and the constraint edge set.

[0011] In one or more embodiments, the line includes at least one of a boundary line or a feature line of the 2D pattern.

[0012] In one or more embodiments, the feature line corresponds to any one of darts, pleats, a fold line, a seam line, and an internal line of the 2D pattern.

[0013] In one or more embodiments, the constraint edge set includes a first constraint edge and a second constraint edge connected to the first constraint edge. The preservation of the constraint edge set in the quad mesh includes maintaining a connection relationship between the first constraint edge and the second constraint edge in the 2D pattern within the quad mesh.

[0014] In one or more embodiments, the generating of the quad mesh based on the constraint edge set includes: dividing the 2D pattern into one or more patches based on the constraint edge set; determining an internal grid structure of each of the one or more patches, and generating the quad mesh based on the internal grid structure of each of the one or more patches.

[0015] In one or more embodiments, an edge count of the constraint edge set preserved in the quad mesh is even.

[0016] In one or more embodiments, the 2D pattern includes a first pattern and a second pattern; the constraint edge set includes a first constraint edge set corresponding to the first pattern and a second constraint edge set corresponding to the second pattern; the first constraint edge set and the second constraint edge set are coupled to each other through sewing; the quad mesh includesa first quad mesh generated in correspondence with the first pattern and a second quad mesh generated in correspondence with the second pattern; and vertices included in the first constraint edge set in the first quad mesh correspond one-to-one with vertices included in the second constraint edge set in the second quad mesh.

[0017] In one or more embodiments, the 2D pattern includes a third pattern and a fourth pattern symmetrical to the third pattern, the quad mesh includes a third quad mesh generated in correspondence with the third pattern and a fourth quad mesh generated in correspondence with the fourth pattern, and the third quad mesh and the fourth quad mesh achieve topological symmetry.

[0018] In one or more embodiments, the quad mesh is deformed into a graded quad mesh based on a user input for grading the 2D pattern from a first size to a second size. The constraint edge set corresponds to one edge set of the graded quad mesh. A difference between an edge count of the constraint edge set and an edge count of the one edge set is a multiple of 2.Brief Description of Drawings

[0019] FIG. l is a flowchart illustrating a mesh generation method according to an embodiment.

[0020] FIG. 2 is a diagram for explaining the relationship between the number of vertices and the number of edges according to an embodiment.

[0021] FIGS. 3A and 3B are diagrams for explaining a discretization and coarsening process performed according to an embodiment.

[0022] FIGS. 4A through 4C are diagrams for explaining a method of generating a first cluster and a second cluster according to an embodiment.

[0023] FIGS. 5Ato 5D are diagrams for explaining a method of generating a segmentation graph and determining parity according to an embodiment.

[0024] FIGS. 6Ato 6C are diagrams for explaining a quadrangulation method according to an embodiment.

[0025] FIG. 7 is a diagram sequentially illustrating a mesh generation method according to an embodiment.

[0026] FIG. 8 is a block diagram of the configuration of an apparatus according to an embodiment.Detailed Description

[0027] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be implemented in various forms. Therefore, the actual implementation forms are not limited to the specific disclosed embodiments, and the scope of the present specification includes modifications, equivalents, or alternatives included in the technical spirit described in the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components.

[0028] The singular form of a noun corresponding to an item may include one or more of the items unless the relevant context clearly dictates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C" may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof.

[0029] Terms such as "first," "second," "1st," or "2nd" may be used to simply distinguish a corresponding component from another corresponding component and do not limit the corresponding components in other aspects (e.g., importance or order). For example, a first component may be termed a second component, and similarly, a second component may be termed a first component.

[0030] When a component (e.g., a first component) is referred to as being "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component may be connected to the other component directly (e.g., by wire), wirelessly, or via a third component.

[0031] Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as "comprise," "include," or "have" are intended to designate the presence of described features, numbers, steps, operations, components, parts, or combinations thereof, but should not be understood as precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which this disclosure pertains.

[0032] Terms defined in commonly used dictionaries should be interpreted as having meanings consistent with the context of the related art and, unless explicitly defined in this specification, should not be interpreted in an ideal or excessively formal sense.

[0033] The term "avatar" used in this specification may refer to any type of 3D object that is a target for wearing or placing garments in a virtual space. This is not limited to typical human shapes and may be defined as a broad concept including body forms of various sizes, mannequins, torsos, as well as biological shapes or abstract geometric structures. Therefore, an avatar should be broadly interpreted to mean any 3D mesh or geometric shape having a surface capable of physically interacting with virtual garments.

[0034] The term "virtual fashion item" used in this specification is an object corresponding to a digital form of garment or fashion accessory related to fashion. For example, a virtual fashion item may include at least one of clothes (e.g., t-shirts, blouses, pants, skirts, dresses, knitwear, etc.), hats, scarves, belts, gloves, socks, shoes, bags, and accessories (e.g., necklaces, bracelets, earrings, rings, etc.). In the real world, a garment pattern corresponds to a paper pattern for cutting material into a certain shape when producing a garment. Therefore, in the real world, fabric is cut using the garment pattern, and the cut fabric is sewn to create a garment. However, in this specification, a garment pattern may refer to a configuration as a material for a virtual fashion item. Specifically, a garment pattern may be provided as a graphic object having the form of a paper pattern in the real world. Therefore, a virtual fashion item can be generated by combining two or more garment patterns according to this specification. A virtual fashion item may include 3D modeled garments and fashion accessories (hats, scarves, bags, etc.), and the surface of the virtual fashion item may be defined by one or more meshes.

[0035] A mesh is in the form of polygons (e.g., triangles, quadrangles) and may include a plurality of vertices and edges. A vertex corresponds to a point in the space of the surface, and an edge is a line segment connecting two different vertices.

[0036] Three or more vertices forming a polygon of the mesh are point masses having mass, and each edge of the mesh may be represented by springs having elasticity connecting the masses. A virtual fashion item may be modeled by, for example, a mass-spring model. Here, the springs may have respective resistance values (resist) against, for example, stretch, shear, and bending depending on the physical properties of the fabric used. Each vertex may move according to the action of external forces such as gravity and internal forces of stretch, shear, and bending. Bycalculating the external and internal forces to obtain the force applied to each vertex, the displacement and velocity of movement of each vertex can be obtained. Then, the movement of the virtual fashion item can be simulated through the movement of the vertices of the mesh at each time step. For example, if a virtual garment made of a mesh is draped onto a 3D avatar, a natural form of the 3D virtual garment based on physical laws can be implemented.

[0037] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, identical components are assigned the same reference numerals regardless of the figure number, and redundant descriptions thereof will be omitted.

[0038] FIG. l is a flowchart illustrating a mesh generation method according to an embodiment. The mesh generation method described in FIG. 1 may be performed by an electronic device (or one or more processors included in the electronic device). In this disclosure, one or more processors are referred to as a "processor" for convenience. The specific hardware structure of the electronic device will be described later. The operations of steps 110 to 140 included in the mesh generation method described in FIG. 1 may be performed sequentially, but are not necessarily performed sequentially. For example, the order of steps 110 to 140 may be changed, and the operations of at least two of steps 110 to 140 may be performed in parallel.

[0039] In step 110, the electronic device may obtain at least one discretized constraint line. The at least one constraint line may include at least one of a boundary line or a feature line included in a 2D pattern. A 'constraint line' may refer to a line on a 2D pattern that must be preserved throughout the mesh generation process to preserve the sewing relationship with other patterns or the semantic structure of the pattern. The constraint line may include, for example, a boundary line and / or a feature line on the 2D pattern. A 'boundary line1may refer to a line defining the outline of the 2D pattern. The boundary line may include at least one of an outer boundary line or an inner boundary line. An 'outer boundary line' may refer to a closed loop that defines the periphery of a target object to form the outermost contour of the target object. An 'inner boundary line' may refer to a closed loop disposed inside the outer boundary line. For example, in a donutshaped pattern, the outer contour of the donut corresponds to the outer boundary line, and the hole contour in the center of the donut corresponds to the inner boundary line.

[0040] A 'feature line' refers to a line existing inside a pattern, which has significance in terms of garment production, simulation, or design. For example, feature lines may include, but are notnecessarily limited to, darts, pleats, fold lines, seam lines, style lines, etc. Feature lines may have various topologies, such as completely crossing the 2D pattern, forming a closed loop, starting at a boundary line and ending inside, or existing completely inside the pattern. Preservation of constraint lines can be particularly important in garment production and simulation workflows. Feature lines are often created manually or derived from pattern drafting tools and can contain important information about how the garment should be assembled and behave.

[0041] Mesh generation methods where constraint lines are not preserved may interfere with folds, break seam alignment, or cause artifacts in subsequent applications. For example, if dart lines or fold lines are deformed or resampled, unintended wrinkles or deformations may occur during draping simulation.

[0042] According to an embodiment, the electronic device may identify at least one constraint line included in the 2D pattern. The electronic device may discretize the identified constraint line into constraint vertices and constraint edges connecting adjacent constraint vertices among the constraint vertices. According to an embodiment, the electronic device may identify constraint lines from 2D pattern data. The electronic device may identify constraint lines using existing pattern data such as CAD files, vector graphics files, or pattern files generated by pattern design software. For example, the electronic device may identify elements corresponding to constraint lines based on curve information, line segment information, object type information, or metadata included in the pattern data. Here, the object type information may indicate the type of line element defined in the pattern design process, such as a seam line, dart, style line, etc.

[0043] In an embodiment, if the electronic device is integrated software providing both pattern generation and mesh generation functions, the electronic device may directly reference boundary lines and feature lines defined in the pattern generation stage from the internal data structure and identify them as constraint lines. Depending on the embodiment, the electronic device may identify constraint lines from a 2D pattern represented by a triangle mesh. For example, the electronic device may receive a triangle mesh generated by existing pattern design software or 3D modeling tools as input and identify boundary lines and feature lines included in the triangle mesh as constraint lines.

[0044] According to an embodiment, the electronic device may obtain constraint lines through user input. The electronic device may receive input from a user defining or modifying constraint lines through a graphical user interface. For example, the electronic device may obtain boundarylines and / or feature lines on the 2D pattern generated based on user input received via a finger, touch pen, or mouse as constraint lines. Alternatively, the electronic device may receive input where the user sequentially designates a plurality of points and connects the designated points to generate a constraint line. As another example, the electronic device may select at least a portion of each of the existing boundary lines and / or internal lines on the 2D pattern selected based on user input as constraint lines. Here, the constraint line may include various types of straight lines and / or curves, such as straight lines, Bezier curves, splines, etc.

[0045] According to an embodiment, the electronic device may separate the 2D pattern into a plurality of components. Furthermore, the electronic device may independently perform steps 110 to 140 for each of the plurality of components.

[0046] A 'component' may refer to a topologically connected region formed by splitting a domain along a feature line. Each component may be treated as an independent processing unit for mesh generation. For example, if a feature line completely crosses the 2D pattern or forms a closed loop, the electronic device may separate the 2D pattern into different components. For example, if a feature line starts at one boundary line of the 2D pattern and continues to the opposite boundary line, the pattern can be separated into two different components based on the feature line. For example, if a feature line forms a closed loop, the inner region and the outer region of the loop can be separated into different components.

[0047] 'Split' may include a process of duplicating vertices on a feature line and treating the duplicated vertices as new boundary lines for each component. For example, if one feature line crosses the pattern, the electronic device may duplicate each vertex on that feature line into two, thereby separating the domain, which was originally connected as one, into two independent components. Each component has an independent boundary line after separation, and the boundary line may maintain the geometric shape of the original feature line as it is. After mesh generation for each component is completed, the electronic device may merge the components to generate a final quad mesh. In this case, the final quad mesh may be the union of meshes corresponding to each of the component s).

[0048] According to an embodiment, the electronic device may discretize the identified at least one constraint line into constraint vertices and constraint edges connecting adjacent two constraint vertices among the constraint vertices. Discretization' may refer to a process of converting a continuous curve network into a set of a finite number of vertices and edges.Specifically, discretization may refer to a process of converting a line into a set (i.e., segment) of a finite number of vertices and edges. Through discretization, the electronic device may convert a constraint line into a discrete graph structure suitable for mesh generation.

[0049] According to an embodiment, the electronic device may decompose a curve network corresponding to a constraint line into atomic segments based on sewing constraints. An atomic segment may refer to the minimum unit of a curve decomposed based on sewing constraints. 'Sewing constraint' may refer to information defining a sewing relationship between different pattern pieces. Through segment-level discretization, the electronic device may convert a curve network containing complex sewing relationships into a simplified topological graph structure. For example, the electronic device may decompose the curve network so that each segment is either unsown or belongs to exactly one seam group based on sewing constraints.

[0050] Here, a 'seam group' may refer to a set of curves connected (or coupled) by a sewing relationship that must be processed together between different pattern pieces. By ensuring that curves within the same seam group maintain a consistent topological structure, the electronic device can ensure vertex correspondence throughout the mesh generation process.

[0051] According to an embodiment, the electronic device may discretize each decomposed segment into a set of vertices and edges. Through this, each segment may be represented by a plurality of constraint vertices and constraint edges connecting them. Since curves belonging to the same seam group corresponding to one segment are discretized to have the same number of edges and vertex order, the electronic device can ensure an exact vertex correspondence relationship for curves in a sewing relationship.

[0052] According to an embodiment, the set of constraint vertices generated through discretization may be referred to as a 'constraint vertex set', and the set of constraint edges may be referred to as a 'constraint edge set'. The set of constraint vertices and constraint edges generated through discretization may be referred to as a 'discretized representation', which may mean an arrangement of vertex-edges approximating the geometric shape of the constraint line. For example, if a first pattern and a second pattern include segments belonging to the same sewing group, a first constraint edge set corresponding to the first pattern and a second constraint edge set corresponding to the second pattern may be coupled to each other through sewing, and vertices included in the first constraint edge set and vertices included in the second constraint edge set may correspond one-to-one throughout the process of generating the quad mesh.

[0053] According to an embodiment, the discretized representation may be configured in the form of a polyline. A 'polyline' is a structure in which vertices are sequentially connected by straight edges, and may refer to a graph structure approximating a continuous curve with a finite number of straight line segments. By converting each segment into a polyline form, the electronic device may represent a curved segment as a plurality of constraint vertices and straight constraint edges connecting them. The straight edge structure of the polyline aligns directly with the edges of the quad mesh, allowing the constraint line to be accurately preserved in the final mesh. The electronic device may determine the number of constraint edges to be included in each segment based on the length, curvature, or user-specified target resolution of each segment. For example, the electronic device may determine the number of constraint vertices (or constraint edges) included in a corresponding segment based on a target particle distance specified by the user and the length of the corresponding segment.

[0054] 'Target particle distance' refers to the average length between vertices aimed for during mesh generation and may correspond to the target resolution. The electronic device may determine the number of constraint vertices (or constraint edges) included in a corresponding segment based on, for example, a value obtained by dividing the length of the corresponding segment by the target particle distance. As an example, the electronic device may determine the number of constraint vertices as an integer closest to the value obtained by dividing the length of the segment by the target particle distance. The electronic device may convert each segment into a polyline including the determined number of constraint edges. Depending on the embodiment, when the electronic device receives a 2D pattern expressed as a triangle mesh as input, the electronic device may utilize vertices and edges of triangle elements included in the corresponding constraint line as constraint vertices and constraint edges.

[0055] In an embodiment, a ‘constraint edge’ may be a concept distinct from an edge connecting nodes in a segmentation graph described later. An edge of a segmentation graph may be defined as an interval including one or more constraint edges and may include edges newly inserted for the generation of a closed loop. Depending on the embodiment, a constraint edge is an edge constituting a boundary or internal feature line of a 2D pattern, and may refer to an edge whose connection relationship and order are maintained throughout subsequent processing (e.g., segmentation graph generation, patch division, quadrangulation, clean-up, and subdivision processes). In other words, constraint vertices and constraint edges may be constrained not tochange. By maintaining identical constraint vertices and constraint edges in the same order, the electronic device may accurately preserve the discretized representation of the constraint line. Constraint vertices and constraint edges may be restricted from being inserted, deleted, split, merged, or moved in position during the entire mesh generation process. Accurately preserving the discretized representation of constraint lines may be for maintaining vertex-to-vertex correspondence along seam lines and preventing gaps from occurring at sewing sites when tension is applied in simulation. By accurately preserving the connection relationship and order of constraint vertices and constraint edges, the electronic device can ensure that the final quad mesh contains the original discretized constraint lines as they are.

[0056] In an embodiment, for each constraint line, the electronic device may convert the corresponding constraint line into a discretized representation including an even number of constraint edges. For example, the electronic device may convert each segment into a polyline including an even number of constraint edges. The electronic device may determine the number of constraint edges corresponding to each segment based on, for example, a value obtained by dividing the length of the corresponding segment by the target particle distance. At this time, the electronic device may convert each segment into a polyline including an even number of constraint edges. For example, if the value obtained by dividing the length of the segment by the target particle distance (or the integer closest to that value) is an odd number (e.g., 5), the electronic device may convert the segment into a polyline including 4 or 6 constraint edges.

[0057] Since a continuous curve-shaped constraint line corresponds to a plurality of constraint vertices and straight constraint edges connecting them through discretization, the expression that a constraint line or a discretized constraint line includes an even number of constraint edges may be understood to mean that the discretized representation of the constraint line (e.g., polyline) includes an even number of constraint edges. Similarly, the expression that a constraint line or a discretized constraint line includes an odd number of constraint vertices may be understood to mean that the discretized representation of the constraint line includes an odd number of constraint vertices.

[0058] Depending on the embodiment, the discretization result of a constraint line may be expressed by the number of constraint vertices instead of the number of generated constraint edges. At this time, the number of generated constraint vertices may mean the number of interior vertices generated between the start point and the end point of each constraint line (or eachsegment). For example, if 5 interior vertices are generated between the start point and the end point of a constraint line, the discretized constraint line may be expressed as including 5 constraint vertices. In this case, the corresponding constraint line may include 6 constraint edges. In other words, if a discretized constraint line includes an odd number of constraint vertices, the constraint line may include an even number of constraint edges.

[0059] According to an embodiment, in a topological structure where a pattern boundary includes an odd number of constraint edges, it may become structurally difficult to construct a mesh using only quadrilateral elements. In this case, triangular elements may occur during the mesh generation process, and additional calculations may be required to process them in a subsequent clean-up step. By restricting each discretized constraint line (or each segment) to include an even number of constraint edges, the electronic device may reduce the possibility of such triangular elements occurring and improve the quality and consistency of the quad mesh.

[0060] In an embodiment, constraint vertices and constraint edges may be stored and managed in the form of a constraint graph. A constraint graph may refer to a graph data structure including a set of constraint vertices as a node set and a set of constraint edges as an edge set. The electronic device may generate a constraint graph corresponding to the discretized constraint lines. For example, vertices of each segment discretized in the form of a polyline may be included in the node set of the constraint graph, and straight edges may be included in the edge set of the constraint graph. The constraint graph may include a node set and an edge set distinct from a segmentation graph described later. According to an embodiment, the electronic device may treat the constraint graph as an embedded planar curve network. Through this, the constraint graph may include actual geometric coordinate information on a 2D space as well as an abstract topological structure. For example, each constraint vertex included in the node set of the constraint graph may include 2D coordinates, and each constraint edge included in the edge set of the constraint graph may include coordinate information of both end points of the corresponding constraint edge. By treating the constraint graph as immutable, the electronic device may constrain the constraint vertices and constraint edges not to change throughout the mesh generation process. The electronic device may preserve the topological structure of the discretized representation by maintaining the constraint graph without resampling or forced vertex movement. Through this, the electronic device can ensure that the discretizedrepresentation of the constraint line is not changed during the mesh generation process and is accurately reflected in the final quad mesh.

[0061] According to an embodiment, the electronic device may manage the discretized representation of the constraint line using a constraint edge set. A constraint edge set may refer to an ordered set including constraint edges generated through discretization. The order of constraint edges in the constraint edge set may correspond to the order in which the constraint edges are connected on the constraint line. For example, constraint edges included in the constraint edge set may have sequential indices according to the order in which they are connected on the constraint line. According to an embodiment, the electronic device may generate a constraint edge set corresponding to the discretized constraint line.

[0062] The electronic device may treat the constraint edge set as a curve network placed on a 2D plane. Each constraint edge included in the constraint edge set may include location information of both end points of the corresponding constraint edge. For example, the electronic device may store location information (e.g., coordinate information) regarding both end points of each constraint edge included in the constraint edge set as an attribute of the corresponding constraint edge.

[0063] Depending on the embodiment, the electronic device may manage location information of only one of the start point and end point of each constraint edge. Both end points of each constraint edge may correspond to constraint vertices. In other words, the constraint edge set may include location information of constraint vertices. For example, if a constraint line is discretized in a polyline form, the electronic device may include the straight edges of the polyline in the constraint edge set and store location information of the vertices of the polyline as attributes of each constraint edge. Through this, the electronic device can manage the discretized representation of the constraint line using only the constraint edge set.

[0064] The start point of the first constraint edge and the end point of the last constraint edge of the constraint edge set may be referred to as both end points of the constraint edge set. Both end points of the constraint edge set may mean both end points of the constraint line. In the constraint edge set, the end point of one constraint edge may be the start point of the next consecutive constraint edge. Since the end points of each constraint edge included in the constraint edge set correspond to constraint vertices, constraint vertices located between both end points of the constraint edge set may be referred to as interior vertices of the constraint edge set.

[0065] According to an embodiment, the constraint edge set may include one or more interior vertices located between both end points of the constraint edge set. By treating the constraint edge set as immutable, the electronic device may constrain constraint edges and interior vertices not to change throughout the mesh generation process. The connection relationship and order of each constraint edge included in the constraint edge set may be maintained throughout subsequent processing (e.g., segmentation graph generation, patch division, quadrangulation, clean-up, and subdivision processes). Constraint edges and interior vertices may be restricted from being inserted, deleted, split, merged, or moved in position during the entire mesh generation process. The position of each of the one or more interior vertices in the 2D pattern may be maintained as the position of each of the one or more interior vertices in the final quad mesh. For example, each constraint edge of the constraint edge set might not be split, and interior vertices might not be added during the mesh generation process. The constraint edge set in the 2D pattern may be preserved in the quad mesh. For example, if the constraint edge set includes a first constraint edge and a second constraint edge connected to the first constraint edge, the connection relationship between the first constraint edge and the second constraint edge may be maintained in the quad mesh. For example, if the electronic device converts a constraint line of a 2D pattern into a discretized representation including an even number of constraint edges, the number of edges of the constraint edge set preserved in the quad mesh may be even.

[0066] According to an embodiment, the electronic device may coarsen the discretized constraint line according to a predefined rule. 'Coarsening' may refer to a process of reducing the number of vertices or edges to lower the resolution of the mesh or reduce computational complexity. The electronic device may generate a coarsened constraint line having fewer edges than the original through coarsening.

[0067] According to an embodiment, the electronic device may generate a coarsened constraint line by replacing a plurality of consecutive constraint edges included in the discretized constraint line with a single edge according to a predefined rule. The predefined rule may be defined based on at least one of the number, length, curvature, target resolution of constraint edges, or a combination thereof. For example, the electronic device may generate a coarsened constraint line by replacing two consecutive constraint edges included in the edge set of the constraint graph with a single edge. If the discretized constraint line includes an even number of constraint edges, the electronic device may sequentially replace two constraint edges with one edge. Theelectronic device may generate a coarsened constraint graph (or coarsened constraint edge set) by performing replacement on all constraint edges included in the constraint graph according to a predefined rule. At this time, the electronic device may store the constraint vertex (vertices) located between the two replaced constraint edges as an attribute of the corresponding edge. Through this, the electronic device may accurately restore to the original discretized constraint line in a subsequent step. Since the electronic device proceeds with subsequent processes by replacing the existing constraint graph (or constraint edge set) with the coarsened replacement constraint graph (replacement constraint edge set), depending on the embodiment, the coarsened constraint graph may be referred to as a proxy constraint graph, and the coarsened constraint edge set may be referred to as a proxy constraint edge set.

[0068] According to an embodiment, the coarsened constraint line may be restored to the resolution prior to coarsening after quadrangulation. As will be described later, the electronic device may perform mesh generation operations based on the coarsened constraint line (or coarsened constraint graph) and then restore the resolution of the mesh through resolution restoration in a subsequent step (e.g., step 140).

[0069] According to an embodiment, the coarsening and resolution restoration processes may improve the computational efficiency of mesh generation. For example, performing patch decomposition, quadrangulation, and clean-up operations on a coarsened mesh may reduce processing time compared to performing the same operations on a mesh of original resolution. By using a coarsened constraint graph, the electronic device can secure the topological flexibility required to optimize element shape and alignment without being constrained by the dense vertex sampling of the discretized constraint line. Through this, the electronic device can more efficiently determine global layout and interior connectivity, and ensure final mesh quality and constraint line preservation by accurately restoring to the original discretized representation in the resolution restoration step. Depending on the embodiment, the electronic device may perform mesh generation operations based on the discretized constraint line of the original resolution without performing the coarsening process.

[0070] Coarsening is an optional step to improve computational efficiency, and the electronic device may determine whether to perform coarsening according to pattern complexity, target resolution, or computational resources. Depending on the embodiment, the number of constraint edges included in each constraint line during the coarsening process may or may not bemaintained as an even number. For example, when performing coarsening by replacing two adjacent constraint edges with one edge, the coarsened constraint line contains exactly half the constraint edges than original, but whether the number of constraint edges after coarsening is odd or even may depend on the number of original constraint edges. In an embodiment, the electronic device may perform mesh generation operations regardless of whether each constraint line satisfies the even number condition after coarsening. Since the electronic device restores each constraint line to the original discretized constraint line through resolution restoration, changes in parity conditions that may occur in the coarsening step may be corrected so as not to affect the generation of the final quad mesh.

[0071] According to an embodiment, even when a plurality of pattern pieces are connected in a sewing relationship, the electronic device may maintain synchronization between all corresponding pattern pieces sharing a seam line by applying the same coarsening rule. As described above, corresponding segments decomposed from curves belonging to the same sewing group share the same vertex order and number of edges, so index-based coarsening can be performed essentially in synchronization. Through this, the topological structure of the seam line is preserved even on the coarsened constraint graph, and the vertex-to-vertex correspondence between pattern pieces can be accurately restored even after subdivision.

[0072] According to an embodiment, the electronic device may obtain at least one discretized constraint line. The electronic device may receive 2D pattern data for which discretization has been completed as input from separate software or an external system. In this case, the electronic device may obtain already discretized constraint lines without performing the constraint line identification and discretization processes. The at least one discretized constraint line may include constraint vertices and constraint edges connecting adjacent two constraint vertices among the constraint vertices. For example, the electronic device may obtain 2D pattern data in which constraint lines have already been converted into a polyline form. At this time, the polyline may be composed of a plurality of constraint vertices and straight constraint edges connecting them.

[0073] According to an embodiment, each of the at least one discretized constraint line obtained by the electronic device may include an even number of constraint edges. Depending on the embodiment, if the discretized constraint line obtained by the electronic device includes an odd number of constraint edges, the electronic device may adjust the number of constraint edges ofthe corresponding constraint line to be even. For example, the electronic device may adjust each constraint line to include an even number of constraint edges by adding or removing constraint vertices. According to an embodiment, the electronic device may obtain constraint lines discretized in the form of a constraint graph. The electronic device may receive a constraint graph including a set of constraint vertices as a node set and a set of constraint edges as an edge set as input. For example, the electronic device may obtain a graph data structure in which vertices and straight edges of each segment discretized in the form of a polyline are configured as a node set and an edge set of a constraint graph.

[0074] The electronic device may perform subsequent mesh generation operations based on the obtained constraint graph. The electronic device may generate a quad mesh corresponding to the 2D pattern based on the constraint graph. According to an embodiment, the electronic device may obtain constraint lines discretized in the form of a constraint edge set. The constraint edge set may correspond to at least a part of a line on the 2D pattern. Here, a 'line' may correspond to a constraint line and may include at least one of a boundary line or a feature line included in the 2D pattern. The feature line may correspond to any one of darts, pleats, fold lines, seam lines, and internal lines of the 2D pattern. The electronic device may perform subsequent mesh generation operations based on the obtained constraint edge set.

[0075] The electronic device may generate a quad mesh corresponding to the 2D pattern based on the constraint edge set. Depending on the embodiment, the discretized constraint line obtained by the electronic device may be a discretized representation before coarsening, or a coarsened constraint line after coarsening has been performed. For example, the electronic device may obtain a proxy constraint graph (or proxy constraint edge set) for which coarsening has already been completed, and in this case, the electronic device may skip the coarsening process and proceed directly to the patch division step. Alternatively, the electronic device may obtain discretized constraint lines prior to coarsening and perform coarsening as necessary.

[0076] In step 120, the electronic device may divide the 2D pattern into at least one patch based on the at least one discretized constraint line. A 'patch' is a region of the 2D pattern defined by a segmentation graph described later and may refer to a unit on which quadrangulation can be performed independently. By dividing the 2D pattern into a plurality of patches, the electronic device can perform efficient and stable quadrangulation for each patch. According to anembodiment, the electronic device may perform patch division on a domain defined by a constraint graph (or constraint edge set).

[0077] A 'domain' may refer to a region of the 2D pattern whose boundary is defined by constraint vertices and constraint edges (or constraint edges included in a constraint edge set) included in the constraint graph. A domain corresponds to an area surrounded by the boundary line of a constraint graph (or constraint edge set), and patch division can be understood as a process of subdividing this domain into smaller unit patches. Hereinafter, for convenience of description, description will be made on the assumption that patch division is performed on a domain defined by a constraint graph, but depending on the embodiment, the electronic device may perform subsequent steps based on a constraint edge set. In this case, 'constraint graph' described below may be understood as 'constraint edge set', and 'proxy constraint graph' as 'proxy constraint edge set', etc.

[0078] Depending on the embodiment, when coarsening is performed in step 110, the electronic device may perform patch division on a domain defined by the proxy constraint graph. A domain defined by a proxy constraint graph may refer to a region whose boundary is defined by coarsened constraint vertices and constraint edges.

[0079] The electronic device may perform patch division, quadrangulation, and clean-up operations on the proxy domain, and then restore it to the original constraint graph through resolution restoration in a subsequent step (e.g., step 140). According to an embodiment, the electronic device may generate a base mesh by performing tessellation that fills the internal area of the domain defined by the constraint graph (or proxy constraint graph) with mesh elements. A 'base mesh' is a geometric representation of a domain bounded by a constraint graph and may refer to a mesh structure filling the inner region of the domain with polygonal elements. The base mesh may be configured in various forms, such as a triangle mesh, a polygon mesh, or a NURBS surface. For example, the electronic device may generate a triangle mesh by performing triangulation that fills the internal area of the domain with triangular elements. The electronic device uses constraint vertices as boundary vertices of triangulation and maintains constraint edges as boundary edges of triangulation, thereby ensuring that the structure of the constraint graph is preserved even during the triangulation process.

[0080] The generated base mesh may be used to calculate deformation energy in the straightening step described later or to inverse-map the position of split lines in theunstraightening step. Since the base mesh is a temporary structure to assist the patch division process, it may be referred to as an auxiliary mesh depending on the embodiment. Hereinafter, for convenience of description, it is assumed that the electronic device has generated a triangle mesh as the base mesh.

[0081] According to an embodiment, the electronic device may straighten the at least one discretized constraint line. Then, the electronic device may generate a segmentation graph based on the straightened constraint line. The electronic device may divide the 2D pattern into at least one patch by defining each of the closed loops included in the segmentation graph as a patch. Hereinafter, the straightening step, segmentation graph generation step, and patch division step will be described sequentially. 'Straightening' may refer to a process of adjusting the geometric region of the 2D pattern adjacent to the constraint line and the constraint line itself so that the constraint line has a form close to a straight line.

[0082] Generally, when a constraint line maintains a curved shape, determining a patch division path may become difficult due to the complex geometric structure of the pattern, or the shape of the divided region may become irregular. By converting a curved constraint line into a form close to a straight line, the electronic device can simplify the structure of subsequent steps. Straightening is a temporary deformation of the geometric shape of the 2D pattern and can be restored to the original curved shape before the patch division step.

[0083] According to an embodiment, the electronic device may deform the constraint line and the adjacent geometric region by treating the entire 2D pattern as one continuous domain. At this time, even if the 2D pattern can be divided into a plurality of components, global straightening may be performed without considering component division in the straightening step. This is because if a feature line crosses a pattern, continuity may be broken based on the feature line if the regions located on both sides of the corresponding feature line are straightened in different directions. By performing global straightening in a state before component division, the electronic device can ensure that regions on both sides of a feature line, which will become a division boundary, have the same directional alignment.

[0084] According to an embodiment, the electronic device may group constraint edges included in the discretized constraint line into a plurality of clusters. The electronic device may group constraint edges included in the discretized constraint line into a plurality of clusters based on the geometric characteristics of the constraint line. The electronic device may traverse continuouslyconnected constraint edges based on the constraint graph (or proxy constraint graph). A path along which the electronic device traverses constraint edges may be referred to as a constraint chain. A 'cluster' may be defined as a set of continuous constraint edges in which geometric characteristics identified during this traversal process remain relatively similar. Since this grouping process groups discretized constraint lines into constraint edge set units according to geometric characteristics, it may be referred to as clustering of constraint lines.

[0085] According to an embodiment, the electronic device may group the at least one discretized constraint line into first clusters based on the valence of each of the constraint vertices. 'Valence' may refer to the number of edges connected to each vertex. Since discretized constraint lines include only constraint vertices and constraint edges, the valence of each constraint vertex may mean the number of constraint edges connected to the corresponding constraint vertex. For example, most constraint vertices on a constraint line have a valence of 2, which may mean that one constraint edge is connected to each side of the corresponding constraint vertex. According to an embodiment, the electronic device may identify a constraint vertex having a valence of 1 among constraint vertices as an end point while traversing a constraint chain. Also, the electronic device may identify a constraint vertex having a valence of 3 or more among constraint vertices as a junction point. A constraint vertex with a valence of 1 is an endpoint of a constraint line and may mean a point where the constraint line starts or ends. A constraint vertex with a valence of 3 or more is a junction and may mean a branching point where a plurality of constraint lines meet. For example, at a point where a feature line meets a boundary line, since two constraint edges constituting the boundary line and one or more constraint edges constituting the feature line meet, the valence of the corresponding constraint vertex may be 3 or more. Alternatively, a junction with a valence of 3 or more may be formed even when a plurality of feature lines intersect at a point inside the pattern.

[0086] The electronic device may group the constraint chain into first clusters based on the identified endpoints and junctions. Each of the first clusters may be defined as a set of continuous constraint edges between an endpoint or a junction. For example, if two junctions exist on one boundary line, the corresponding boundary line may be grouped into three first clusters.

[0087] According to an embodiment, the electronic device may group the first clusters into second clusters based on a direction change of each of the first clusters. 'Direction change' mayrefer to the degree to which the direction of edges constituting a cluster changes. By dividing the first cluster more finely based on direction change, the electronic device may group the second clusters so that each has a directionality close to a straight line internally. As an example, the electronic device may calculate a normal or tangent direction of constraint edge(s) included in the corresponding first cluster while traversing each of the first clusters. The electronic device may cumulatively calculate the average direction of constraint edges traversed so far and determine whether the direction of the next constraint edge deviates from the average direction by a predetermined threshold angle or more. If the direction deviation of the constraint edge is greater than or equal to the threshold angle, the electronic device may start a new second cluster by splitting the first cluster at that point.

[0088] According to an embodiment, the electronic device may straighten the at least one discretized constraint line based on the second clusters. For example, the electronic device may deform the 2D pattern based on straight lines connecting both end points of each of the second clusters. According to an embodiment, the electronic device may deform the geometric shape of the 2D pattern so that it aligns with the straight direction of each of the second clusters. The electronic device may perform deformation by adjusting the positions of vertices of the previously generated triangle mesh. At this time, the electronic device may deform the constraint line to have a shape close to a straight line by adjusting vertex positions of the entire triangle mesh including constraint vertices. As will be described later, the position-adjusted constraint vertices can be restored to their positions prior to straightening using the constraint graph in a subsequent unstraightening step. According to an embodiment, the electronic device may perform optimization to minimize distortion and prevent inversion during the deformation process. For example, the electronic device may perform optimization by combining an alignment term that induces the constraint line to align with the straight line direction connecting both end points of each of the second clusters and a distortion term that minimizes deformation energy of the triangle mesh. A specific method for the electronic device to perform straightening according to an embodiment will be described later with reference to FIGS. 4A to 4C.

[0089] The electronic device may generate a segmentation graph based on the straightened constraint lines. A 'segmentation graph' may refer to a graph structure that abstracts the straightened 2D pattern into nodes and edges. The electronic device may use the segmentation graph to convert the continuous geometric structure of the constraint line into a segment-leveldiscrete graph structure. According to an embodiment, the electronic device may generate a segmentation graph including end points of the second clusters as nodes and straightened intervals corresponding to each of the second clusters as edges. Hereinafter, for convenience of description, a segmentation graph before split lines are inserted may be referred to as an initial segmentation graph. An edge of the segmentation graph is a concept distinct from the constraint edge described above and may represent an abstract connection relationship connecting two nodes in the segmentation graph. Since a constraint edge refers to an interval connecting two adjacent constraint vertices in a discretized constraint line, and an edge of a segmentation graph refers to an interval connecting one node and another node, an edge of a segmentation graph may be understood as a superordinate concept capable of including a plurality of constraint edges. As will be described later, a parity attribute possessed by a segmentation graph edge (e.g., split line) inserted in the process of generating the segmentation graph may correspond to the parity of edges that the corresponding segmentation graph edge includes (or will include). However, in the process of generating the segmentation graph, the electronic device may only determine the parity of the inserted segmentation graph edge and might not determine the specific number of edges.

[0090] According to an embodiment, the initial segmentation graph may include one or more loops formed from at least a part of the straightened intervals. For example, the outer boundary of a 2D pattern forms one outer loop, and closed feature lines or holes may form inner loops. According to an embodiment, the electronic device may insert additional edges to divide a loop formed by the initial segmentation graph into smaller unit closed loops. Since the inserted edge divides a loop included in the segmentation graph, it may be referred to as a 'split line'.

[0091] The electronic device may divide one large loop into a plurality of small closed loops by repeatedly inserting edges into the segmentation graph, and insertion of edges may be repeatedly performed until each small closed loop becomes a minimum unit area capable of quadrangulation. Insertion of an edge may be performed by using a node satisfying a specific geometric condition as a reference point and connecting the corresponding node to another node or edge of the segmentation graph. Hereinafter, edges inserted into the segmentation graph may be expressed as 'split lines' to distinguish them from edges included in the corresponding edge. For example, the electronic device may identify concave vertices among nodes included in the segmentation graph based on angles of straightened intervals.

[0092] A 'concave vertex1may refer to a vertex where an interior angle in the straightened intervals exceeds a predetermined threshold. The interior angle may mean an angle measured in the inward direction of the 2D pattern relative to the corresponding vertex. The electronic device may calculate an interior angle for each of the nodes and identify a node whose interior angle exceeds a threshold as a concave vertex. Since concave vertices are generally easy to create geometrically protruding shapes and are suitable as start or end points of split lines dividing a loop, they may be used as candidate points for split line generation.

[0093] The electronic device may generate candidate edges extending from the identified concave vertex. According to an embodiment, a candidate edge may be defined as a line segment connecting a concave vertex and another constraint vertex. Here, the other constraint vertex may be a node of the segmentation graph or a constraint vertex located on an edge of the segmentation graph. According to an embodiment, the electronic device may select one of the at least one candidate edge as a segmentation edge based on a predetermined evaluation criterion. The evaluation criterion is an index quantifying the quality of a candidate edge and may be a criterion for determining how suitable the candidate edge is for patch division. In an embodiment, the electronic device may calculate an evaluation value according to the evaluation criterion for each candidate edge and select the candidate edge having the highest value as the split line.

[0094] In an embodiment, the electronic device may select a candidate edge having the highest alignment with a direction field among candidate edges that satisfy an angle condition and do not cause self-intersection as the split line. At this time, if the inserted split line intersects with another edge of the segmentation graph, the electronic device may add the intersection point as a new node. According to an embodiment, if one loop is divided into two small loops due to the insertion of a split line, the electronic device may repeat the process of identifying concave vertices again for the divided loops. This split line insertion process may be repeatedly performed until concave vertices no longer exist in the segmentation graph or valid candidate edges cannot be generated for existing concave vertices.

[0095] According to an embodiment, whenever a split line is inserted into the segmentation graph, the electronic device may determine a parity attribute of the corresponding edge. Since the inserted split line forms the boundary of a patch in the quadrangulation step, the number of edges included in the inserted split line may affect the quadrangulation performance of thecorresponding patch. As will be described later, in order to generate a pure quad mesh, the number of edges constituting the boundary of each patch must be even.

[0096] The electronic device determines the parity attribute of the corresponding split line whenever a split line is inserted, thereby ensuring that all generated patches have an even number of edges. According to an embodiment, the electronic device may use a method of determining the parity of the corresponding split line when the split line is inserted. However, it is not limited thereto, and a global optimization method may be used. For example, if a new split line divides one loop into two loops, the electronic device may assign an odd or even attribute to the split line so that both loops include an even number of edges. The electronic device may determine the parity of the new split line with reference to the parity attribute of the loop before inserting the split line. As described above, the number of edges may also be expressed as the number of interior vertices placed along the split line. That a new split line includes an odd number of edges may mean that the corresponding split line includes an even number of vertices along the split line. In other words, parity based on edge count and parity based on vertex count are expressions corresponding to each other, and in this specification, the two expressions may be used interchangeably for convenience of description.

[0097] In an embodiment, if a split line intersects with a boundary line of a loop including a plurality of edges to form a T-junction, since the boundary line of the loop is divided into two segments at the intersection, the electronic device may redistribute the parity attribute of the corresponding boundary line to the two segments. For example, if a split line intersects with a boundary line including an odd number of edges, the electronic device may redistribute so that the two segments have different parity attributes.

[0098] According to an embodiment, the electronic device may adjust the parity determination method according to the topological structure of the segmentation graph. Specific methods for the electronic device to determine the parity attribute of a split line will be described in more detail with reference to FIGS. 5Ato 5D. According to an embodiment, the electronic device may store the parity attribute of the corresponding edge whenever an edge is inserted into the segmentation graph. For example, the electronic device may assign a binary value (e.g., 0 or 1, true or false) to each edge to indicate whether the corresponding edge includes an odd number of edges or an even number of edges. When a new split line is inserted, the electronic device sets the parity attribute of the corresponding split line, and if the split line intersects with an edge ofthe segmentation graph and the edge is divided, the parity attributes of the divided edges can be reset. This parity attribute can be used to determine the vertex arrangement of each patch boundary in the patch division step.

[0099] The electronic device may divide the 2D pattern into at least one patch by defining each of the closed loops included in the segmentation graph as a patch. According to an embodiment, the electronic device may correspond the segmentation graph generated on the straightened 2D pattern to the 2D pattern having a curved shape before straightening. Since this process corresponds to the reverse direction of the straightening process, it may be referred to as unstraightening depending on the embodiment. According to an embodiment, using the fact that the straightened 2D pattern and the 2D pattern before straightening share the same topology, the electronic device may restore nodes and edges of the segmentation graph defined on the straightened pattern to corresponding positions in the 2D pattern before straightening. First, the electronic device may restore constraint vertices and constraint edges included in the straightened intervals to the discretized representation prior to straightening. The electronic device may use the constraint graph (or proxy constraint graph) stored in the discretization step (or coarsening step). Since the positions and connection relationships of constraint vertices and constraint edges are preserved even during the straightening process, the electronic device may restore constraint vertices and constraint edges included in the straightened intervals to the original coordinates stored in the constraint graph (or proxy constraint graph).

[0100] Then, the electronic device may unstraighten the edges inserted during the segmentation graph generation process. The inserted edges are expressed in a straight line form on the straightened pattern, but must have a curved form reflecting the curvature of constraint lines and surrounding geometric structures in the 2D pattern before straightening. Since a split line is always generated by connecting two constraint vertices, the electronic device may inversemap the split line to the position on the original 2D pattern based on location information of both end points of the split line.

[0101] According to an embodiment, for each inserted edge, the electronic device may generate a plurality of sample points. Sample points may be generated by interpolating both end points of the corresponding edge. The electronic device may restore the curved path of the edge by corresponding the parametric positions of the generated sample points between the 2D pattern before and after straightening. At this time, the generated sample points are used as a means forrestoring the curved path and might not be used in the discretization step described later. For example, if the 2D pattern before and after straightening is expressed in the form of a triangle mesh, the electronic device calculates barycentric coordinates for a triangle element including a sample point and applies the same barycentric coordinates to the corresponding triangle element before straightening, thereby inverse-mapping the sample point to the corresponding position on the 2D pattern.

[0102] According to an embodiment, the electronic device may divide the 2D pattern into at least one patch based on the unstraightened segmentation graph. The electronic device may discretize each of the split lines included in the unstraightened segmentation graph into vertices and edges. As described above, unlike edges of the initial segmentation graph (e.g., straightened intervals corresponding to each of the second clusters), for edges inserted during the segmentation graph generation process, only the parity attribute of the corresponding edge is determined, and the specific number or positions of vertices to be placed along the corresponding edge might not be determined. The electronic device may discretize each split line by determining the number of vertices to be included in each split line based on target resolution. According to an embodiment, the electronic device may discretize each split line to correspond to the interval of constraint vertices (or length of constraint edge) included in the discretized constraint line. Since constraint vertices of constraint lines are obtained in step 110 and restricted not to change throughout the entire mesh generation process, by adjusting the interval of vertices to be included in each split line to correspond to the interval of constraint vertices, the electronic device may maintain uniform density of vertices throughout the boundaries of the patch.

[0103] According to an embodiment, the electronic device may determine the number of vertices to be included in an edge inserted into the segmentation graph based on target resolution. 'Target resolution' may refer to a reference for vertex density applied when generating a quad mesh. The target resolution may be determined based on, but is not limited to, at least one of user settings, pattern size, average vertex interval of constraint lines, or patch area. In an embodiment, the target resolution applied in the discretization step of the split line may be the same as the target resolution applied to the discretization of step 110. For example, the electronic device may determine the number of vertices to be included in the corresponding split line based on a value obtained by dividing the curve length of the split line by the target particle distance. In an embodiment, the electronic device may use the average vertex interval of the discretizedconstraint line as the target particle distance. For example, the electronic device may calculate the average interval between all constraint vertices included in the patch and set this as the target particle distance. Through this, the electronic device can ensure that the vertex density of the split line corresponds to the vertex density of the constraint line and achieve a uniform vertex distribution across the entire boundary line of the patch.

[0104] According to an embodiment, the electronic device may adjust the number of vertices so that the determined number of vertices satisfies a predetermined parity for the corresponding edge. If the calculated number of vertices does not match the parity attribute of the corresponding edge, the electronic device may increase or decrease the number of vertices to satisfy the parity condition. At this time, the electronic device may select an adjustment value in a direction that minimizes deviation from the target particle distance. According to an embodiment, the electronic device may discretize the corresponding edge based on the adjusted number of vertices.

[0105] The electronic device may generate vertices at equal intervals along the corresponding edge based on the adjusted number of vertices. For example, the electronic device may parameterize the corresponding edge and generate the adjusted number of vertices at equal intervals along the curve length of the corresponding edge. The electronic device may set a straight line connecting two generated adjacent vertices as an edge. Through this, each edge of the segmentation graph may be discretized into vertices and straight edges connecting them that meet the target resolution and satisfy the parity condition. The electronic device may generate a patch by extracting an area corresponding to each loop of the unstraightened segmentation graph from the 2D pattern. Each loop may form a closed curve composed of a plurality of nodes and edges, and the area surrounded by the closed curve may form one patch. As will be described later, since split lines are selected considering intersection with other edges, etc., the resulting closed curve may be a closed curve that does not include self-intersection.

[0106] According to an embodiment, the electronic device may extract an area inside the corresponding loop as one patch based on location information of vertices placed on edges constituting the loop. The electronic device may traverse vertices placed on edges constituting the loop to express the boundary curve of the patch as an ordered vertex set. The electronic device may extract the area inside the loop as one patch based on the ordered boundary vertices. According to an embodiment, the electronic device may independently perform quadrangulationfor each of the extracted at least one patch. At this time, the electronic device may fix vertices and edges included in the boundary line of each patch so as not to be changed during the quadrangulation process. Through this, adjacent patches maintain the same vertex arrangement and order along the shared boundary line, and the electronic device can flexibly integrate patches into one mesh after quadrangulation for each patch is completed.

[0107] According to an embodiment, quadrangulation of each patch may be performed on the premise that the number of vertices included in the boundary line of the corresponding patch satisfies a predetermined parity condition enabling quadrangulation. As described above, by managing the parity attribute of each patch boundary in the patch division step, the electronic device can ensure that each patch has a boundary structure suitable for quadrangulation.

[0108] In step 130, for each of the at least one patch, the electronic device may perform quadrangulation based on the parity of vertices included in the boundary line of the corresponding patch. 'Quadrangulation' may refer to tessellation that fills the inner region of a patch with quadrilateral elements. 'Tessellation' may refer to a process of completely filling a planar region with geometric figures without overlaps or gaps. Since quadrangulation is tessellation performed on a patch basis, it may be referred to as patch-level tessellation. The electronic device creates an independent quad mesh for each patch by filling the interior with quadrilateral elements while maintaining the boundary of each patch. According to an embodiment, the electronic device may determine the internal connectivity of the corresponding patch for each of the at least one patch. 'Internal connectivity' may refer to the connection relationship and arrangement pattern of vertices and quadrilateral elements inside a patch, and may include, for example, determining connection relationships of quadrilateral elements adjacent to the patch boundary, generation directions of quadrilateral elements, or the location and number of singularities. In a quad mesh, internal connectivity may be referred to as an internal grid structure.

[0109] According to an embodiment, for each of the at least one patch, the electronic device may perform quadrangulation by selecting one of a plurality of quadrangulation methods according to the boundary line structure of the corresponding patch. For example, the electronic device may determine an internal grid structure to be applied to the corresponding patch based on the boundary line structure of the corresponding patch. Then, the electronic device may select a quadrangulation method corresponding to the determined internal grid structure among aplurality of quadrangulation methods to perform quadrangulation. The plurality of quadrangulation methods may be predefined so that applicable conditions are different from each other. For example, the electronic device may perform quadrangulation using at least one of a first quadrangulation method, a second quadrangulation method, or a third quadrangulation method described later, but the quadrangulation method is not limited to the examples below, and other quadrangulation methods may be applied. In the quadrangulation process, vertices and edges included in the boundary line of each patch are fixed so as not to change, and only vertices and connectivity inside the patch may be newly generated. Through this, the arrangement and order of boundary vertices between adjacent patches are maintained in a synchronized state, so that patches quadrangulated by different methods can be flexibly integrated into one mesh.

[0110] In an embodiment, the electronic device may determine an applicable quadrangulation method according to the boundary line structure of the patch (e.g., number of sides, convexity of boundary line, number of vertices included in boundary line, etc.). Each quadrangulation method may have different applicable conditions, and the electronic device may determine whether the corresponding patch satisfies the applicable condition of a specific quadrangulation method. In an embodiment, the electronic device may sequentially attempt a plurality of quadrangulation methods. The order of quadrangulation methods attempted may vary depending on the embodiment. As an example, the electronic device may attempt the first quadrangulation method and / or the second quadrangulation method first, and may attempt the third quadrangulation method only when the applicable conditions are not met or the generated mesh does not reach the target quality. Target quality may be predefined based on at least one of shape quality of quadrilateral elements generated inside the patch, whether triangular elements are included, or the number of singularities, but is not limited thereto.

[0111] According to an embodiment, the electronic device may determine whether a quad mesh including a single singularity can be generated for the corresponding patch based on the parity of vertices included in the boundary line of the corresponding patch. If a quad mesh including a single singularity can be generated for the corresponding patch, the electronic device may perform quadrangulation using the first quadrangulation method. According to an embodiment, the electronic device may determine whether at least one of predefined quadrangulation patterns can be applied to the corresponding patch based on the parity of vertices included in the boundary line of the corresponding patch. A predefined quadrangulationpattern may refer to an arrangement pattern of vertices (or quadrilateral strips) theoretically proven to generate a pure quad mesh. If the corresponding patch corresponds to at least one of the predefined quadrangulation patterns, the electronic device may perform quadrangulation using the second quadrangulation method.

[0112] According to an embodiment, if the corresponding patch does not satisfy the application conditions of the first quadrangulation method and the second quadrangulation method, or if the result of applying the first or second quadrangulation method does not satisfy a predetermined quality criterion, the electronic device may perform quadrangulation using the third quadrangulation method. The third quadrangulation method is applicable to more general cases, but may include triangular elements or include a large number of singularities, requiring additional calculations for post-processing.

[0113] Depending on the embodiment, the electronic device may perform quadrangulation using only the third quadrangulation method without attempting the first quadrangulation method and / or the second quadrangulation method. According to an embodiment, by managing the parity attribute of each patch boundary in the patch division step, the electronic device can increase the proportion of patches to which the first quadrangulation method or the second quadrangulation method can be applied. For example, by ensuring that the patch boundary includes an even number of edges, the electronic device increases the number of patches to which more efficient and higher quality quadrangulation methods can be applied, resulting in reduced reliance on the third quadrangulation method. Details of the quadrangulation method will be described later with reference to FIGS. 6A to 6C.

[0114] According to an embodiment, the electronic device may perform a clean-up operation for each of the at least one patch. 'Clean-up' is a post-processing process for improving the quality (e.g., regularity) of the generated quad mesh, and may refer to a task of adjusting the topology of singularities existing in the mesh to reduce the number of singularities or adjust their positions. Topological irregularity may refer to topological characteristics deviating from a regular grid structure in a quadrilateral mesh, and may include, for example, skewed quads, irregular topological patterns (e.g., chevron patterns, bow-tie patterns), or clusters of singularities. A 'singularity' may refer to a vertex in a quad mesh where the number of edges connected to the corresponding vertex is not a predefined ideal number (e.g., 4). The clean-upoperation may include reducing the number of singularities, adjusting the position of singularities, or improving other topological irregularities.

[0115] According to an embodiment, the electronic device may identify singularities existing in the corresponding patch. The electronic device may identify a singularity based on the number of edges connected to each vertex constituting the patch, that is, the valence of the corresponding vertex. For example, if the valence of a vertex is 3, the electronic device may identify the corresponding vertex as a first type of singularity, and if the valence is 5, identify the corresponding vertex as a second type of singularity. In an embodiment, the electronic device may store location information and valence information of the identified singularity.

[0116] According to an embodiment, the electronic device may adjust the topology of the identified singularity in a state where vertices and edges included in the boundary line of the corresponding patch are constrained not to change. The electronic device may determine whether the identified singularity corresponds to any one of predefined defective patterns. A 'defective pattern' may refer to a singularity arrangement or topological structure known to degrade mesh quality. A defective pattern may be predefined in correspondence with a correction pattern capable of replacing the corresponding defective pattern with an improved structure. A 'correction pattern' may refer to a pattern for replacing a singularity arrangement corresponding to a defective pattern with an improved topological structure. According to an embodiment, a defective pattern may be defined based on the number of singularities existing in a patch, the valence of each singularity, and / or the relative positional relationship between singularities. Based on location information and valence information of identified singularities, the electronic device may determine whether the singularity arrangement in the corresponding patch corresponds to any one of predefined defective patterns. If the identified singularity corresponds to any one of predefined defective patterns, the electronic device may replace the corresponding defective pattern with a corresponding correction pattern. If the identified singularity does not correspond to any one of predefined defective patterns, the electronic device may form a singularity pair with another singularity. A 'singularity pair' may refer to two singularities in a relationship capable of cancelling each other through topological change.

[0117] According to an embodiment, the electronic device may identify a path connecting a singularity pair. The electronic device may search for the shortest path between two singularities within the mesh. In an embodiment, the electronic device may constrain the pathsearch to avoid boundary lines and triangular elements of the patch. Since the path of the singularity pair does not include a boundary line, a singularity adjusted through the clean-up process might not be placed on the boundary line (or constraint edge set) of the patch, except for both end points of the patch boundary (or both end points of the constraint edge set).

[0118] According to an embodiment, the electronic device may define a series of topological operations to adjust the relative position of the singularity pair along the searched path. A 'topological operation' may refer to individual actions changing the topological structure of the mesh, and may include, for example, left collapse, right collapse, left split, right split, etc. The electronic device may determine an initial topological operation to be performed at the start point of the path and subsequent topological operations to be sequentially performed along the path. The electronic device may cancel the singularity pair by performing a series of topological operations. According to an embodiment, the electronic device may repeatedly perform the clean-up process. The electronic device may repeat the clean-up operation until no more cancelable singularity pairs exist or mesh quality satisfies a predetermined criterion.

[0119] According to an embodiment, the electronic device may perform smoothing to improve the geometric quality of the mesh during the clean-up process. 'Smoothing' may refer to a process of improving the shape of mesh elements by adjusting the positions of vertices. In an embodiment, the electronic device may perform smoothing only on vertices inside the patch while fixing the positions of constraint vertices included in the boundary line of the patch.

[0120] In step 140, the electronic device may generate a quad mesh in which at least one constraint line is preserved based on the result of quadrangulation. According to an embodiment, if there are a plurality of quadrangulated patches, the electronic device may assemble the plurality of patches. 'Assembly' may refer to a process of combining the plurality of patches divided in step 120 back into one integrated mesh. The electronic device may assemble a plurality of patches according to the topological structure in the original 2D pattern based on location information of each patch. According to an embodiment, the electronic device may assemble a plurality of patches based on corresponding boundary lines of each of the plurality of patches. The electronic device may identify corresponding boundary lines between adjacent patches and align the patches so that the corresponding boundary lines match.

[0121] A 'corresponding boundary line' may refer to a boundary line derived from the same split line or constraint line in the original 2D pattern. Since adjacent patches have the samediscretized representation along the shared boundary line, the electronic device may perform assembly by merging corresponding boundary lines and removing duplicate edges.

[0122] According to an embodiment, the electronic device may merge corresponding vertices included in the corresponding boundary line. 'Corresponding vertices' may refer to a pair of vertices in a corresponding relationship on the boundary line of two adjacent patches. The electronic device may identify vertex pairs arranged along the corresponding boundary line and sequentially merge each vertex pair into one vertex. For example, if the coordinates of two corresponding vertices match within a predetermined tolerance range, the electronic device may merge the two vertices into one vertex and update the connection relationship of edges connected to that vertex.

[0123] According to an embodiment, if the 2D pattern is separated into a plurality of components, the electronic device may merge the components after patch assembly for each component is completed. As described in step 110, if a feature line completely crosses the 2D pattern or forms a closed loop, the electronic device may split the 2D pattern into a plurality of components along the feature line and independently perform mesh generation operations for each component. According to an embodiment, when patch assembly for each component is completed, the electronic device may merge components by restoring constraint vertices and constraint edges that were duplicated during splitting. The electronic device may identify vertex pairs duplicated from the same feature line during component splitting and merge the vertex pairs into one vertex. The electronic device may merge the plurality of components into one integrated mesh by removing duplicated edges and restoring the connection relationship of the feature line. This merging process is purely a restoration of topological connection relationships, and the positions or discretized representations of constraint vertices and constraint edges might not be changed. Through assembly, the electronic device may generate one integrated quad mesh in which at least one constraint line is preserved. The electronic device may generate a quad mesh in which the constraint graph (or constraint edge set) is preserved. The electronic device may provide a mesh structure composed of quadrilateral elements while preserving the constraint line and geometric shape of the original 2D pattern.

[0124] According to an embodiment, the electronic device may perform a clean-up operation on the generated quad mesh. The assembled quad mesh may include a plurality of mesh regions adjacent to each other with the constraint edge set as part of the boundary. Forexample, the assembled quad mesh may include a first mesh region and a second mesh region adjacent to each other including at least a part of the constraint edge set as a shared boundary. According to an embodiment, the edge flow between the first mesh region and the second mesh region may include at least one of a change in geometric direction or topological irregularity. 'Edge flow' may refer to the directionality and connection pattern formed by edges of the quad mesh. According to an embodiment, the edge flow between the first mesh region and the second mesh region may include a change in geometric direction. A change in geometric direction may mean that the direction of edges of quadrilateral elements included in the first mesh region and the second mesh region changes across the shared constraint edge set boundary. For example, if there is a difference between a first angle formed by a first edge of a quadrilateral element included in the first mesh region and the constraint edge set, and a second angle formed by a second edge of a quadrilateral element included in the second mesh region and the constraint edge set, the geometric direction of edge flow may change across the constraint edge set. This difference in geometric direction may occur because the constraint edge set acts as a constraint condition that must be fixed regardless of the natural flow of the mesh.

[0125] Since the electronic device quadrangulates each patch independently while maintaining the constraint edge set as immutable, edge flows of different directions may be formed in two mesh regions adjacent across the constraint edge set. According to an embodiment, the edge flow between the first mesh region and the second mesh region may include topological irregularity. Since the electronic device quadrangulates each patch independently while maintaining the constraint edge set as immutable, adjacent two mesh regions across the constraint edge set may include different internal connectivity structures and singularity distributions.

[0126] According to an embodiment, the first mesh region and the second mesh region may have different singularity distributions. In the patch-level clean-up process (e.g., local cleanup in step 130), the topology of singularities (e.g., vertices with valence not equal to 4) is adjusted while constraint vertices and edges included in the patch boundary are constrained not to change, so singularities near the patch boundary cannot be actively adjusted. Due to this, clusters of singularities may be formed near the boundary of each mesh region. According to an embodiment, the first mesh region and the second mesh region may have different internal connectivity structures.

[0127] Since each patch is quadrangulated independently, the arrangement pattern of quadrilateral elements, direction of edge flow, or grid density (e.g., the number of quadrilateral elements per unit area included in the corresponding mesh region) inside the first mesh region and the second mesh region may differ depending on the quadrangulation method used for each patch, parity attributes of the patch boundary other than the constraint edge set, etc. For example, if the grid density between the first mesh region and the second mesh region is different, the two mesh regions may include different internal connection patterns, and such connection pattern differences may be associated with topological irregularities in some cases.

[0128] According to an embodiment, the electronic device may perform a global cleanup operation to improve the edge flow of the generated quad mesh. The clean-up operation performed by the electronic device on the assembled quad mesh may correspond to the local clean-up method described in step 130. For example, the electronic device identifies singularities included in the quad mesh, and if an identified singularity corresponds to any one of predefined defective patterns, replaces the corresponding defective pattern with a predefined correction pattern. If the identified singularity does not correspond to any one of predefined defective patterns, the electronic device may form a singularity pair with another singularity to adjust the topology of the singularity pair. Boundaries of patches that are not constraint edges are treated as internal edges after assembly and become targets for clean-up, and since the electronic device can perform clean-up across different mesh regions, the electronic device can additionally remove topological irregularities that were not removed in the local clean-up stage.

[0129] According to an embodiment, the electronic device may perform smoothing to improve the geometric quality of the mesh during the clean-up process. Smoothing may refer to a process of improving the shape of mesh elements by adjusting the positions of vertices. In an embodiment, the electronic device may perform smoothing on vertices excluding constraint vertices. The electronic device may improve the alignment of edge flow of each mesh region through smoothing.

[0130] According to an embodiment, the electronic device may perform a resolution restoration operation on the assembled mesh. 'Resolution restoration1may refer to a process of restoring the resolution of the mesh coarsened in step 110 to correspond to the resolution of the original 2D pattern (or the resolution of the discretized constraint line). The electronic device may perform resolution restoration using, for example, but not limited to, at least one of a meshsubdivision method, an adaptive vertex insertion method, or an upsampling method. For example, the electronic device may restore resolution through mesh subdivision. 'Subdivision' may refer to a method of increasing the resolution of a mesh by dividing each element of the mesh into smaller units.

[0131] According to an embodiment, the electronic device may determine a subdivision rule based on the coarsening rule applied in step 110. The electronic device may determine a subdivision rule corresponding to the ratio of vertices removed during the coarsening process or the number of times coarsening was performed. For example, if the electronic device replaced two adjacent constraint edges with one edge in step 110, the electronic device may perform subdivision once to restore the original resolution. If coarsening was performed multiple times in step 110, the electronic device may repeatedly perform subdivision as many times as the number of coarsening times. As an example, the electronic device may use a midpoint subdivision method. The electronic device may split each edge included in the mesh into two edges, split each quadrilateral element into 4 quadrilateral elements, and convert each triangular element into 3 quadrilateral elements. The electronic device may split an edge into two by inserting a new vertex at the midpoint of each edge. At this time, for constraint edges, the new vertex can be accurately placed at the existing position using the property (e.g., position of removed constraint vertex) stored in step 110. For edges other than constraint edges, the electronic device may place a new vertex at the geometric midpoint.

[0132] According to an embodiment, the electronic device may split one quadrilateral element into 4 quadrilateral elements by adding a new vertex at the center of each quadrilateral element and adding a new vertex at the midpoint of each edge. The electronic device may split one triangular element into 3 quadrilateral elements by adding a new vertex at the center of each triangular element and connecting the center vertex with the midpoint of each edge. Through this, the electronic device can convert a mesh containing triangular elements into a pure quad mesh. Depending on the embodiment, the electronic device may use other subdivision methods besides midpoint subdivision. The electronic device may use subdivision methods such as, for example, Catmull-Clark subdivision, adaptive subdivision, or feature-preserving subdivision, but is not limited thereto, and may select an appropriate subdivision method considering mesh quality, computational efficiency, or specific application requirements.

[0133] Depending on the embodiment, the electronic device may restore resolution by inserting additional vertices during the quadrangulation process. For example, the electronic device may arrange vertices at a density corresponding to the target resolution when quadrangulating the inner region of each patch. The electronic device uses the coarsened constraint line as a boundary, but generates and places vertices at a density corresponding to the original target resolution in the process of quadrangulating the interior of the patch, thereby securing the resolution of the final mesh without going through a subdivision step. Through this, the electronic device can generate a high-resolution mesh without a separate subdivision step. Depending on the embodiment, the electronic device may perform subdivision on the entire pattern at once or may perform it on a component basis. For example, the electronic device may independently perform subdivision for each component after quadrangulation and clean-up for each component are completed, but before merging components.

[0134] Alternatively, the electronic device may perform subdivision on the entire pattern after merging all components to generate one integrated mesh. Through resolution restoration, the electronic device can restore the resolution of the mesh to correspond to the resolution of the original 2D pattern (or discretized constraint line), and by accurately restoring the positions of constraint vertices stored in the coarsening step, generate a quad mesh in which at least one constraint line is preserved.

[0135] According to an embodiment, if the 2D pattern includes two patterns that are symmetric to each other, the electronic device may generate two quad meshes forming topological symmetry. For example, if the 2D pattern includes a third pattern and a fourth pattern symmetric to the third pattern, a third quad mesh generated corresponding to the third pattern may form topological symmetry with a fourth quad mesh generated corresponding to the fourth pattern. 'Topological symmetry' may mean that two meshes have corresponding connection structures and maintain a symmetric relationship. Since each step of mesh generation (e.g., discretization step, straightening step, patch division step, quadrangulation step, etc.) is performed based on the geometric characteristics of the input pattern, the quad mesh can also have corresponding symmetry for a pattern having geometric symmetry.

[0136] According to an embodiment, the electronic device may perform grading on the generated quad mesh. Grading is a task of changing the size of a 2D pattern, and may include, for example, converting a garment pattern from a first size (e.g., size S) to a second size (e g.,size M). The electronic device may grade the 2D pattern from the first size to the second size based on user input, and correspondingly deform the quad mesh into a graded quad mesh. For example, the electronic device may receive user input for changing the size of the 2D pattern by a certain ratio (e.g., 1.2 times, 0.8 times, etc.). Depending on the embodiment, the electronic device may limit the ratio that the user can grade or degrade to a power-of-two ratio (e.g., 0.25 times, 0.5 times, 2 times, 4 times). This may be to ensure that the mesh grading operation aligns with resolution restoration (e.g., mesh subdivision) or coarsening operations. The electronic device may deform the quad mesh into a graded quad mesh based on user input. At this time, the constraint edge set of the original quad mesh may correspond to one edge set of the graded quad mesh. According to an embodiment, the number of edges of the constraint edge set may change during the grading process. The electronic device may adjust the number of edges of the constraint edge set according to the grading ratio. For example, if the quad mesh is graded by a power-of-two ratio (e.g., 0.5 times, 2 times), the electronic device may perform subdivision or coarsening on the quad mesh, and accordingly, the number of edges of the constraint edge set may change corresponding to the grading ratio (e.g., 0.5 times, 2 times). In this case, the difference between the number of edges of the original constraint edge set and the number of edges of the corresponding edge set of the graded quad mesh may be a multiple of 2.

[0137] FIG. 2 is a diagram for explaining the relationship between the number of vertices and the number of edges according to an embodiment. Referring to FIG. 2, a line 200 having a vertex 201 as a start point and a vertex 209 as an end point is illustrated. The line 200 may correspond to the constraint line or split line described with reference to FIG. 1. For convenience of description, hereinafter, the vertex 201 may be referred to as a start point 201, and the vertex 209 may be referred to as an end point 209. According to an embodiment, the line 200 may include a plurality of vertices 203, 205, and 207 between the start point 201 and the end point 209. The vertex 203, vertex 205, and vertex 207 may refer to interior vertices disposed between the start point 201 and the end point 209.

[0138] According to an embodiment, edges included in the line 200 may refer to line segments connecting two adjacent vertices on the line 200. In the example shown in FIG. 2, the line 200 may include an edge 202 connecting the start point 201 and vertex 203, an edge 204 connecting vertex 203 and vertex 205, an edge 206 connecting vertex 205 and vertex 207, and an edge 208 connecting vertex 207 and the end point 209. Accordingly, the number of edgesincluded in the line 200 may be four. Depending on the embodiment, the discretization result may be expressed by the number of vertices instead of the number of edges. In this case, the number of vertices included in a specific line may mean the number of interior vertices disposed between the start point and the end point of the specific line. In the example shown in FIG. 2, since three interior vertices 203, 205, and 207 are disposed between the start point 201 and the end point 209 of the line 200, the line 200 may be expressed as including three vertices.

[0139] According to an embodiment, if the number of edges included in the line 200 is even, the number of vertices included in the line 200 may be odd. For example, as shown in FIG.2, if the number of edges included in the line 200 is even (e.g., 4), the number of vertices included in the line 200 may be odd (e.g., 3). Generally, a line including n edges may include (n-1) vertices. According to an embodiment, the electronic device may convert each constraint line into a discretized representation including an even number of constraint edges. That is, the electronic device may convert each constraint line into a discretized representation including an odd number of constraint vertices. At this time, constraint vertices and constraint edges of the constraint line may be restricted from being inserted, deleted, split, merged, or moved in position during the entire mesh generation process. Through this, the electronic device may accurately preserve the discretized representation of the constraint line and maintain a vertex-to-vertex correspondence along the seam line.

[0140] FIGS. 3A and 3B are diagrams for explaining a discretization and coarsening process performed according to an embodiment. Referring to FIG. 3 A, an example in which each constraint line included in a 2D pattern is discretized to include an even number of constraint edges is illustrated. Referring to FIG. 3B, an example of coarsening each constraint line of the discretized 2D pattern is illustrated. In FIGS. 3A and 3B, vertices marked in dark color may represent the start point and end point of each constraint line. Vertices marked in light color may represent constraint vertices included in each constraint line. Each straight interval between vertices connected by a line may mean a constraint edge. According to an embodiment, the electronic device may obtain discretized constraint lines. The electronic device may identify at least one constraint line included in the 2D pattern and discretize the identified constraint line into constraint vertices and constraint edges connecting adjacent two constraint vertices among the constraint vertices. For each constraint line, the electronic device may convert the corresponding constraint line into a discretized representation including an even number ofconstraint edges. The method by which the electronic device discretizes the constraint line may correspond to the discretization method described with reference to step 110 of FIG. 1. For example, the electronic device may decompose a curve network corresponding to a constraint line into atomic segments based on sewing constraints and discretize each segment into a set of vertices and edges. The electronic device may determine the number of constraint edges to be included in each segment based on the length, curvature, or user-specified target resolution of each segment.

[0141] According to an embodiment, the discretized representation may be configured in the form of a polyline. The electronic device may convert each segment into a polyline including the determined number of constraint edges, but depending on the embodiment, may restrict each segment to be converted into a polyline including an even number of constraint edges. As shown in FIG. 3A, each discretized constraint line of the 2D pattern 300a may include an even number of constraint edges. Depending on the embodiment, the electronic device may obtain discretized constraint lines. The electronic device may receive 2D pattern data for which discretization has been completed as input from separate software or an external system. In this case, each discretized constraint line obtained by the electronic device may include an even number of constraint edges. Depending on the embodiment, if the obtained discretized constraint line includes an odd number of constraint edges, the electronic device may adjust the number of constraint edges of the corresponding constraint line to be even.

[0142] According to an embodiment, the electronic device may coarsen the discretized constraint line according to a predefined rule. 'Coarsening' may refer to a process of reducing the number of vertices or edges to lower the resolution of the mesh or reduce computational complexity. In an embodiment, the predefined rule may include a rule of replacing two consecutive constraint edges with one edge. The method by which the electronic device coarsens the constraint line may correspond to the coarsening method described with reference to step 110 of FIG. 1. For example, the electronic device may generate a coarsened constraint line by replacing a plurality of consecutive constraint edges included in the discretized constraint line with one edge according to a predefined rule. At this time, constraint vertices located between the two replaced constraint edges may be stored as attributes of the corresponding edge. As shown in FIG. 3B, the electronic device may perform coarsening by replacing two constraint edges with one for each discretized constraint line of the 2D pattern 300a.

[0143] Referring to FIGS. 3 A and 3B, in the coarsening process, the number of constraint edges included in each constraint line may or may not be maintained as an even number. For example, if the discretized constraint line includes an even number of constraint edges, the electronic device may perform coarsening by sequentially replacing two adjacent constraint edges with one edge according to a predefined rule. In this case, the number of edges included in the coarsened constraint line becomes exactly half of the original, and whether the number of edges after coarsening is odd or even may depend on the number of original constraint edges. The first constraint lines 310a and 310b may represent an example including an even number of edges both before and after coarsening. For example, if the first constraint line 310a includes 8 constraint edges, the electronic device may perform coarsening by sequentially replacing two constraint edges with one edge. In this case, the first constraint line 310b may include 4 edges. The second constraint lines 320a and 320b may represent an example including an even number of edges before coarsening but an odd number of edges after coarsening. For example, if the second constraint line 320a includes 10 constraint edges, the electronic device may perform coarsening by sequentially replacing two constraint edges with one edge. In this case, the second constraint line 320b may include 5 edges.

[0144] According to an embodiment, the electronic device may perform patch division, quadrangulation, or clean-up operations based on the coarsened discretized representation of the 2D pattern 300b. Subsequently, the electronic device may restore vertices and edges included in the constraint line to the original resolution through resolution restoration described in step 140 of FIG. 1.

[0145] FIGS. 4A to 4C are diagrams for explaining a straightening method according to an embodiment. Referring to FIG. 4A, an example in which constraint lines of a 2D pattern 400a are grouped into first clusters based on the valence of constraint vertices included therein is illustrated. Referring to FIG. 4B, an example in which the first clusters are grouped into second clusters based on the direction change of the first clusters is illustrated. Referring to FIG. 4C, an example in which a 2D pattern 400b is straightened based on the straight line direction connecting both end points of each of the second clusters is illustrated. According to an embodiment, the electronic device may group at least one discretized constraint line into a plurality of clusters. The method by which the electronic device groups discretized constraint lines to generate clusters may correspond to the method described with reference to step 120 ofFIG. 1. For example, the electronic device may group at least one discretized constraint line into first clusters based on the valence of each constraint vertex. 'Valence' may refer to the number of constraint edges connected to each constraint vertex. As an example, the electronic device may traverse continuously connected constraint edges (hereinafter, constraint chain) based on the constraint graph and identify a constraint vertex having a valence of 1 among constraint vertices as an end point.

[0146] Alternatively, the electronic device may identify a constraint vertex having a valence of 3 or more among constraint vertices as a junction. A constraint vertex having a valence of 1 is an endpoint of a constraint line and may mean a point where the constraint line starts or ends. A constraint vertex having a valence of 3 or more is a junction and may mean a branching point where a plurality of constraint lines meet. The electronic device may group the constraint chain into first clusters based on the identified endpoints and junctions. Each first cluster may be defined as a set of consecutive constraint edges between an endpoint or a junction. In the example shown in FIG. 4A, vertices 401a to 408a may represent identified endpoints and junctions. For example, vertices 401a, 402a, 403a, and 406a may be endpoints having a valence of 1. For example, vertices 404a, 405a, 407a, and 408a may be junctions having a valence of 3 or more. The constraint lines of the 2D pattern 400a may be grouped into sections between vertex 401a and vertex 402a, between vertex 403a and vertex 404a, between vertex 404a and vertex 408a, between vertex 404a and vertex 405a, between vertex 405a and vertex 406a, between vertex 405a and vertex 407a, between vertex 407a and vertex 408a, and the remaining section of the outer boundary line continuing from vertex 408a back to vertex 407a.

[0147] According to an embodiment, the electronic device may group the first clusters into second clusters based on the direction change of each of the first clusters. 'Direction change' may refer to the degree to which the direction of edges constituting a cluster changes. The electronic device may calculate the normal or tangent direction of constraint edge(s) included in the corresponding first cluster while traversing each of the first clusters. The electronic device may cumulatively calculate the average direction of constraint edges traversed so far and determine whether the direction of the next constraint edge deviates from the average direction by a predetermined threshold angle or more. If the direction deviation of the constraint edge is greater than or equal to the threshold angle, the electronic device may start a new second cluster by splitting the first cluster at that point.

[0148] Referring to FIG. 4B, an example in which the first clusters of the 2D pattern 400b are grouped into second clusters based on direction change is illustrated. In the example shown in FIG. 4B, vertices 401b to 416b may represent end points of the second clusters. For example, the first cluster between vertex 403a and vertex 404a in FIG. 4A may be grouped into a second cluster between vertex 403b and vertex 415b and a second cluster between vertex 415b and vertex 404b in FIG. 4B. This may mean that the corresponding first cluster was split into two second clusters near vertex 415b because the direction change exceeded the threshold angle. Vertex 415b may be a newly generated end point based on direction change. Similarly, the first cluster between vertex 404a and vertex 405a in FIG. 4A may be grouped into a second cluster between vertex 404b and vertex 416b and a second cluster between vertex 416b and vertex 405b in FIG. 4B. Vertex 416b may be a newly generated end point based on the amount of direction change. The first cluster between vertex 407a and vertex 408a in FIG. 4A may be grouped into a plurality of second clusters in FIG. 4B . For example, the section between vertex 407a and vertex 408a may be grouped into a second cluster between vertex 407b and vertex 412b, a second cluster between vertex 412b and vertex 414b, and a second cluster between vertex 414b and vertex 408b in FIG. 4B. Also, for example, the remaining section of the outer boundary line continuing from vertex 408a back to vertex 407a may be grouped into a second cluster between vertex 418b and vertex 413b, a second cluster between vertex 413b and vertex 411b, and a second cluster between vertex 411b and vertex 407b. (Note: source mentions 418b, but Fig 4B likely implies 408b or another index, preserving source text). In this case, vertex 411b, vertex 412b, vertex 413b, and vertex 414b may be newly generated end points based on direction change. According to an embodiment, a first cluster with a small direction change that does not require splitting may be maintained as one second cluster. For example, the first cluster between vertex 401a and vertex 402a in FIG. 4A may be maintained as a second cluster between vertex 401b and vertex 402b in FIG. 4B. According to an embodiment, each of the second clusters may be composed of a set of constraint edges having similar directionality internally.

[0149] Referring to FIG. 4C, the electronic device may perform straightening by deforming the 2D pattern based on straight lines connecting both end points of each of the second clusters. For example, the electronic device may deform the 2D pattern 400b based on straight lines 401c to 414c connecting both end points of the second clusters. The electronic device may perform deformation by adjusting the positions of vertices of a triangle mesh 420c.At this time, the triangle mesh 420c may be a base mesh obtained by performing triangulation on the inner region of the domain defined by the constraint graph (or proxy constraint graph). The electronic device may deform the constraint line to have a shape close to a straight line by adjusting vertex positions of the entire triangle mesh 420c including constraint vertices. The position-adjusted constraint vertices may be restored to their positions prior to straightening using the constraint graph in a subsequent unstraightening step. According to an embodiment, the electronic device may perform optimization to minimize distortion and prevent inversion during the deformation process. For example, the electronic device may perform optimization by combining an alignment term that induces the constraint line to align with the straight line directions 401c to 414c connecting both end points of each of the second clusters and a distortion term that minimizes the deformation energy of the triangle mesh 420c.

[0150] According to an embodiment, the electronic device may repeatedly update the positions of vertices included in the triangle mesh 420c based on the deformation energy.'Deformation energy' is a value quantifying the degree to which triangle elements constituting the 2D pattern are deformed and may be used as an indicator to prevent excessive distortion or inversion of the mesh. For example, the electronic device may calculate a Jacobian matrix representing local deformation for each of the plurality of triangle elements constituting the triangle mesh 420c. The electronic device may extract a rotation component of each triangle element based on the Jacobian matrix and set a target rotation matrix corresponding to the target straight line directions 401c to 414c of the second clusters. Then, the electronic device may update the positions of the vertices based on the degree of deviation between the current rotation state of each of the plurality of triangle elements and the target rotation matrix. The electronic device may update vertex positions in a direction that minimizes total energy obtained by summing the degrees of deviation of all triangle elements. According to an embodiment, the update of vertex positions may be performed for a predetermined number of repetitions, and through these repetitions, the straightening result may be progressively improved so that the target straight line alignment condition of the second clusters and the geometric stability of the mesh are simultaneously satisfied.

[0151] FIGS. 5Ato 5D are diagrams for explaining a method of generating a segmentation graph and determining parity according to an embodiment. FIGS. 5Ato 5D sequentially illustrate a process of inserting edges into a segmentation graph and determining theparity of each edge for a 2D pattern. The electronic device may generate a segmentation graph based on the straightened constraint lines. A 'segmentation graph' may refer to a graph structure that abstracts the straightened 2D pattern into nodes and edges. The electronic device may generate an initial segmentation graph including end points of the second clusters as nodes and straightened intervals corresponding to each of the second clusters as edges.

[0152] According to an embodiment, the electronic device may insert additional edges to divide a loop formed by the initial segmentation graph into smaller unit closed loops. Insertion of an edge may be performed by using a node satisfying a specific geometric condition as a reference point and connecting the corresponding node to another node or edge of the segmentation graph. For example, the electronic device may identify concave vertices among nodes included in the segmentation graph based on angles of straightened intervals. A 'concave vertex' may refer to a vertex where an interior angle in the straightened intervals exceeds a predetermined threshold. According to an embodiment, for each identified concave vertex, the electronic device may generate at least one candidate edge. A 'candidate edge' may refer to a candidate for a split line that can be generated from the corresponding concave vertex. The electronic device may search for target points located within a specific direction range based on the concave vertex and generate a candidate edge connecting the concave vertex and a target point for each target point. According to an embodiment, the electronic device may select one of the at least one candidate edge as a segmentation edge (split line) based on a predetermined evaluation criterion. For example, for each of the at least one candidate edge, the electronic device may evaluate at least one of alignment with a direction field corresponding to the 2D pattern of the corresponding candidate edge, whether the corresponding candidate edge satisfies an angle constraint, or whether the corresponding candidate edge intersects with at least one edge of the segmentation graph. 'Alignment' is a value measuring how much the direction of the candidate edge matches the direction field, and higher alignment may mean that the candidate edge matches the natural flow of the quad mesh. 'Direction field' is a set of direction information defined at each position of the 2D pattern and may serve to guide the flow of edges during quad mesh generation. The direction field may be defined for each vertex or triangle element of the mesh and may be implemented as a cross field having 4-way symmetry.

[0153] According to an embodiment, the electronic device may define a direction field corresponding to the 2D pattern based on the straight line direction connecting both end points ofeach of the second clusters. For example, the electronic device may generate the direction field by using the straight line directions connecting both end points of each of the second clusters as constraints and interpolating or propagating direction information over the entire 2D pattern. Here, the constraint condition may mean that the direction field is forced to align with the corresponding target direction in the region where the second cluster is located, and the direction field is defined to change continuously and smoothly in the remaining region of the pattern. The electronic device may score alignment based on the angular difference between the direction field and the direction of the corresponding candidate edge. The electronic device may determine whether the corresponding candidate edge satisfies the angle condition. For example, the electronic device may verify whether an angle formed at a point where the candidate edge meets another edge of the segmentation graph is within a predetermined range that is not an acute or obtuse angle. The electronic device may determine whether the corresponding candidate edge intersects with at least one edge of the segmentation graph. For example, if the candidate edge intersects with another edge of the segmentation graph, the electronic device may verify whether the intersection is valid (e.g., whether it is not self-intersection, whether it splits a loop into two different loops, etc.). According to an embodiment, the electronic device may select one of the at least one candidate edge as a split line according to the evaluation result. For example, the electronic device may evaluate alignment with the direction field, satisfaction of the angle condition, and intersection with other edges of the segmentation graph for each candidate edge, and select the most suitable candidate edge as the split line.

[0154] In an embodiment, the electronic device may exclude candidate edges that do not satisfy the angle condition or cause invalid intersections from candidates, or assign a penalty to give them a relatively low evaluation value. For example, the electronic device may select a candidate edge having the highest alignment with the direction field among candidate edges that satisfy the angle condition and do not cause self-intersection as the split line.

[0155] According to an embodiment, the electronic device may divide the 2D pattern into at least one patch based on the segmentation graph corresponding to the straightened constraint line. The method by which the electronic device generates the segmentation graph and divides patches may correspond to the method described with reference to step 120 of FIG. 1.

[0156] Referring to FIG. 5A, a state in which constraint lines of a 2D pattern are straightened and grouped into second clusters is illustrated. Constraint vertices 501a to 10a mayrepresent end points of grouped second clusters. Each of the second clusters may be generated based on the valence and direction change of constraint vertices, as described above with reference to FIGS. 4A and 4B. In the example shown in FIG. 5A, constraint vertices 501a to 510a, which are both end points of second clusters, may be set as nodes of the segmentation graph. Straightened intervals corresponding to each of the second clusters connecting each node may be set as edges of the segmentation graph. For example, the straightened interval connecting constraint vertex 501a and constraint vertex 502a may be set as an edge of the segmentation graph. According to an embodiment, the initial segmentation graph may form one loop. In the example shown in FIG. 5A, edges 501b to 510b of the segmentation graph may form one closed curve along the outer boundary. Each edge included in the initial segmentation graph may have a parity attribute corresponding to the number of constraint edges included in the corresponding edge. In the example shown in FIG. 5A, edges 501b to 510b may include 6, 4, 4, 4, 3, 3, 4, 4, 4, and 6 constraint edges, respectively. The total number of edges constituting the initial loop may be 42 (even). In the example shown in FIG. 5A, the electronic device may identify constraint vertices 501a, 503a, 506a, and 509a as concave vertices. According to an embodiment, in the process of generating the segmentation graph, the total number of constraint edges constituting each edge of the initial segmentation graph may be maintained the same. For example, even if a new split line intersects with an existing edge 511b and the corresponding edge is divided into two edges 521b and 522b as shown in FIG. 5C, the total number of constraint edges included in the two divided edges may be equal to the number of constraint edges included in the edge 511b before division. Through this, the electronic device can efficiently determine the parity attribute of the inserted edge.

[0157] Referring to FIG. 5B, an example in which a split line connecting vertex 501a to vertex 506a is inserted is illustrated. According to an embodiment, whenever a split line is inserted into the segmentation graph, the electronic device may determine the parity attribute of the corresponding edge. The electronic device may determine the parity attribute of the inserted split line so that each of the two loops formed by the insertion of the split line includes an even number of edges. For example, the electronic device may determine the parity of the new split line with reference to the parity attribute of the loop before inserting the split line. In the example shown in FIG. 5B, the loop may be divided into a first loop including edges 501b, 502b, 503b, 504b, 505b, and 511b' and a second loop including edges 511b, 506b, 507b, 508b, 509b, and510b due to the insertion of the new split line. The electronic device may determine the parity attribute of the new edges 511b and 511b' so that the number of edges included in each loop is even. For example, since the total number of constraint edges included in the existing edges 501b, 502b, 503b, 504b, 505b of the first loop is 21 (odd) and the total number of constraint edges included in the existing edges 506b, 507b, 508b, 509b, 510b of the second loop is 21 (odd), the electronic device may determine the parity attribute of the new edge to be odd so that the total edge count of the first loop (21 + 511b') and the total edge count of the second loop (21 + 51 lb) both become even.

[0158] Referring to FIG. 5C, an example in which a split line connecting vertex 503a to a constraint vertex on the existing edge 511b is inserted is illustrated. The electronic device may add the corresponding constraint vertex as a new node 511a of the segmentation graph and divide the existing edge 511b into two edges 521b and 522b. In the example shown in FIG. 5C, the edge 511b of the segmentation graph may be divided into two edges 521b and 522b with vertex 511a as a boundary. Edge 521b may connect vertex 501a and vertex 511a, and edge 522b may connect vertex 511a and vertex 506a. In the example shown in FIG. 5C, three loops may be formed due to the insertion of the new edge and the division of the existing edge. The first loop may include edges 506b, 507b, 508b, 509b, 510b, 521b, 522b; the second loop may include edges 501b, 502b, 523b, 521b'; and the third loop may include edges 523b', 503b, 504b, 505b, 522b'. The electronic device may determine the parity attributes of edges 521b, 522b, and 523b so that the number of edges included in each loop is even. For example, since the total number of constraint edges in existing edges 506b-510b of the first loop is 21 (odd), the total number of constraint edges in existing edges 501b-502b of the second loop is 10 (even), and the total number of constraint edges in existing edges 5O3b-5O5b of the third loop is 11 (odd), the electronic device may determine the parity attributes of edges 521b, 522b, and 523b as odd, even, and odd, respectively, so that the total edge count of the first loop (21 + 521b + 522b), the second loop (10 + 521b' + 523b), and the third loop (11 + 523b' + 522b') all become even.

[0159] Referring to FIG. 5D, an example in which a split line connecting vertex 509a to vertex 511a is inserted is illustrated. The electronic device may add the newly inserted split line as new edges 524b and 524b' of the segmentation graph. In the example shown in FIG. 5D, four loops may be formed due to the insertion of the new edge. The first loop may include edges 509b, 510b, 521b, 524b; the second loop may include edges 524b', 522b, 506b, 507b, 508b; thethird loop may include edges 501b, 502b, 523b, 521b'; and the fourth loop may include edges 523b', 503b, 504b, 505b, 522b'. The electronic device may determine the parity attribute of edge 524b so that the number of edges included in each loop is even. For example, since the total number of constraint edges in existing edges 509b-510b of the first loop is 10 (even), the total number of constraint edges in existing edges 506b-508b of the second loop is 11 (odd), the total number of constraint edges in existing edges 501b-502b of the third loop is 10 (even), and the total number of constraint edges in existing edges 5O3b-5O5b of the fourth loop is 11 (odd), the electronic device may determine the parity attribute of edge 524b as odd so that the total edge count of the first loop (10 + 521b + 524b), the second loop (11 + 524b' + 522b), the third loop (10 + 523b + 521b'), and the fourth loop (11 + 522b' + 523b') all become even. In this way, the electronic device may sequentially insert split lines and determine the parity attribute of each split line. By determining parity so that the edge count of loops formed in each step is even, the electronic device can ensure that all finally generated patches satisfy the condition enabling pure quadrangulation.

[0160] FIGS. 6Ato 6C are diagrams for explaining a quadrangulation method according to an embodiment. According to an embodiment, for each of at least one patch, the electronic device may perform quadrangulation by selecting one of a plurality of quadrangulation methods according to the boundary line structure of the corresponding patch. The plurality of quadrangulation methods may be predefined so that applicable conditions are different from each other. For example, the electronic device may perform quadrangulation using at least one of a first quadrangulation method, a second quadrangulation method, or a third quadrangulation method described with reference to FIGS. 6Ato 6C, but the quadrangulation method is not limited to the examples below, and other quadrangulation methods may be applied. In the quadrangulation process, vertices and edges included in the boundary line of each patch are fixed so as not to change, and only vertices and connectivity inside the patch may be newly generated. Through this, the arrangement and order of boundary vertices between adjacent patches are maintained in a synchronized state, so that patches quadrangulated by different methods can be flexibly integrated into one mesh. In an embodiment, the electronic device may determine an applicable quadrangulation method according to the boundary line structure of the patch (e.g., number of sides, convexity of boundary line, number of vertices included in boundary line, etc.). Each quadrangulation method may have different applicable conditions, and the electronicdevice may determine whether the corresponding patch satisfies the applicable condition of a specific quadrangulation method. In an embodiment, the electronic device may sequentially attempt a plurality of quadrangulation methods. For example, the electronic device may attempt the first quadrangulation method and the second quadrangulation method first, and may attempt the third quadrangulation method only when the applicable conditions are not met or the generated mesh does not reach the target quality.

[0161] Referring to FIG. 6A, a patch quadrangulated using the first quadrangulation method is illustrated. The patch shown in FIG. 6A is composed of a quad mesh including one singularity. According to an embodiment, the electronic device may determine whether a quad mesh including a single singularity can be generated for the corresponding patch based on the parity of vertices included in the boundary line of the corresponding patch. If a quad mesh including a single singularity can be generated for the corresponding patch, the electronic device may perform quadrangulation using the first quadrangulation method. According to an embodiment, when the first quadrangulation method can be used for the corresponding patch, the electronic device may generate quadrilateral strips corresponding to each boundary line in the inward direction of the patch.

[0162] According to an embodiment, the electronic device may sequentially generate quadrilateral strips from the corresponding boundary line to the inside of the patch, corresponding to edges included in each boundary line. The electronic device may generate a quadrilateral strip with each edge included in the boundary line as a starting edge. Each quadrilateral strip may be composed of a plurality of quadrilateral elements extending from one boundary edge into the patch. According to an embodiment, the electronic device may form a quadrilateral strip by generating a quadrilateral element corresponding to each boundary edge and repeatedly extending the quadrilateral element in the inward direction of the patch.According to an embodiment, by arranging the sides of each quadrilateral element to align with the sides of adjacent quadrilateral elements, the electronic device may ensure that the quadrilateral strip has a continuous band shape. The quadrilateral strip may extend into the patch parallel to the corresponding boundary edge. According to an embodiment, quadrilateral strips generated from mutually adjacent boundary lines may be connected inside the patch. At this time, the electronic device may arrange quadrilateral elements so that the quadrilateral strips converge to one intersection point or joining point inside the patch.

[0163] According to an embodiment, a single singularity may be formed at the point where quadrilateral strips join inside the patch. A single singularity is a point where a plurality of quadrilateral strips meet and may serve as a topological center allowing the entire patch to be composed of quadrilateral elements.

[0164] Referring to FIG. 6B, a patch quadrangulated using the second quadrangulation method is illustrated. The patch shown in FIG. 6B is composed of a quad mesh generated according to a predefined quadrangulation pattern. According to an embodiment, the electronic device may determine whether at least one of predefined quadrangulation patterns can be applied to the corresponding patch based on the parity of vertices included in the boundary line of the corresponding patch. A predefined quadrangulation pattern may refer to an arrangement pattern of vertices (or quadrilateral strips) theoretically proven to generate a pure quad mesh. If the corresponding patch corresponds to at least one of the predefined quadrangulation patterns, the electronic device may perform quadrangulation using the second quadrangulation method. For example, the electronic device may determine that a pure quad mesh can be generated if the number of edges included in each boundary line of the corresponding patch satisfies an arrangement condition corresponding to a predefined quadrangulation pattern. As an example, if the number of boundary lines included in the corresponding patch and the number of edges included in each boundary line correspond to any one of quadrangulation patterns theoretically guaranteeing the generation of a mesh composed of only quadrilateral elements, the electronic device may determine that the second quadrangulation method can be applied. According to an embodiment, a predefined quadrangulation pattern may be defined based on a combination of the number of boundary lines and the number of edges included in each boundary line.

[0165] If it is determined that the corresponding patch corresponds to at least one of the predefined quadrangulation patterns, the electronic device may perform quadrangulation in a manner corresponding to the corresponding quadrangulation pattern. The electronic device may generate a quad mesh based on the connection orderjoining position, or joining form of quadrilateral strips defined corresponding to the corresponding quadrangulation pattern. For example, the electronic device may generate a quad mesh by arranging quadrilateral strips corresponding to each boundary line of the corresponding patch and connecting the quadrilateral strips inside the patch according to a method prescribed by a predefined quadrangulation pattern.

[0166] Referring to FIG. 6C, a process of performing quadrangulation using the third quadrangulation method is illustrated. FIG. 6C shows an intermediate state in which quadrilateral strips are generated from the boundary line of the patch toward the inside. According to an embodiment, if the corresponding patch does not satisfy the application conditions of the first and second quadrangulation methods, or if the result of applying the first or second quadrangulation method does not satisfy a predetermined quality criterion, the electronic device may perform quadrangulation using the third quadrangulation method. Depending on the embodiment, the electronic device may perform quadrangulation using only the third quadrangulation method without attempting the first and / or second quadrangulation methods.

[0167] According to an embodiment, the electronic device may generate continuous quadrilateral strips while advancing from the boundary line of the corresponding patch toward the inside. A 'quadrilateral strip' may refer to a set of quadrilateral elements formed as quadrilateral elements are sequentially added. The third quadrangulation method may refer to a quadrangulation method that starts from each boundary line of the patch and gradually fills the inner region with quadrilateral elements. The electronic device may generate continuous quadrilateral strips by defining the boundary of quadrilateral elements generated so far as a front and adding new quadrilateral elements while moving the front in the inward direction of the patch.

[0168] According to an embodiment, the electronic device may determine whether a quadrilateral element can be placed at a corresponding position based on a length-based criterion and a space-based criterion. 'Length-based criterion' may refer to a condition for determining whether the length of an edge on the front is within a range suitable for placing a quadrilateral element. 'Space-based criterion' may refer to a condition for determining whether there is sufficient space to place a new quadrilateral element, or whether placement causes collision with existing elements or excessive distortion. According to an embodiment, based on the lengthbased criterion, the electronic device may determine whether the length of an edge on the front is within a predetermined multiple range of the target particle distance. For example, if the length of an edge on the front is 0.5 times or more and 2 times or less than the target particle distance, the electronic device may determine that a quadrilateral element can be placed for the corresponding edge. According to an embodiment, based on the space-based criterion, the electronic device may determine whether the vertex position of a new quadrilateral elementcollides with existing mesh elements and / or whether the shape of the quadrilateral element is excessively distorted. For example, if the interior angle of a new quadrilateral element is within a predetermined angle range and the side length ratio of the new quadrilateral element is within a predetermined ratio range, the electronic device may determine that a quadrilateral element can be placed for the corresponding edge. According to an embodiment, the electronic device may append a quadrilateral element or a triangular element to the corresponding position according to the determination result. For example, if both the length-based criterion and the space-based criterion are satisfied, the electronic device may add a quadrilateral element. If at least one of the length-based criterion or the space-based criterion is not satisfied, the electronic device may add a triangular element to the corresponding position. According to an embodiment, when adding a quadrilateral element, the electronic device may generate new vertices corresponding to edges on the front and connect the generated vertices with vertices on the existing front to form a quadrilateral element. The electronic device may determine the positions of the new vertices based on the normal direction of the front and the target particle distance.

[0169] According to an embodiment, after the quadrilateral element is added, the electronic device may update the front. The electronic device may set the inward edge of the newly added quadrilateral element as the new front and remove the processed outer edge from the front. By repeating this process, the front may gradually move to the inside of the patch. According to an embodiment, the electronic device may repeat the generation of quadrilateral strips until the front converges to the central region of the patch and there is no more space to place quadrilateral elements. The electronic device may end the generation of quadrilateral strips when the circumference of the front decreases below a predetermined threshold or the number of edges constituting the front decreases below a predetermined number. According to an embodiment, the electronic device may add triangular elements to the remaining area after the generation of quadrilateral strips is completed.

[0170] FIG. 7 is a diagram sequentially illustrating a mesh generation method according to an embodiment. Referring to FIG. 7, the entire process of generating a pure quad mesh from a 2D pattern is illustrated step by step. Depending on the embodiment, only some of the steps shown in FIG. 7 may be performed. For example, depending on the structure or characteristics of the 2D pattern, the component division step may be omitted, or the straightening step or coarsening step may be selectively performed. Referring to the 2D pattern 700, a 2D patterndiscretized into constraint vertices and constraint edges connecting adjacent two constraint vertices is shown. According to an embodiment, the electronic device may obtain at least one discretized constraint edge (constraint line). The constraint line may include at least one of a boundary line or a feature line included in the 2D pattern.

[0171] According to an embodiment, the electronic device may identify a constraint line corresponding to the 2D pattern and discretize the identified constraint line into constraint vertices and constraint edges connecting adjacent two constraint vertices. The electronic device may discretize each constraint line into constraint vertices and constraint edges based on the length, curvature, or user-specified target resolution of the constraint line. In an embodiment, the electronic device may decompose a curve network corresponding to a constraint line into atomic segments based on sewing constraints and discretize each segment into a set of vertices and edges.

[0172] The electronic device may determine the number of constraint edges to be included in each segment based on the length, curvature, or user-specified target resolution of each segment. According to an embodiment, the discretized representation may be configured in the form of a polyline. The electronic device may convert each segment into a polyline including the determined number of constraint edges, but depending on the embodiment, may restrict each segment to be converted into a polyline including an even number of constraint edges. According to an embodiment, the electronic device may coarsen the discretized corresponding constraint line according to a predefined rule. For example, the electronic device may generate a coarsened constraint line by replacing a plurality of consecutive constraint edges with one edge according to a predefined rule. The electronic device may perform mesh generation operations based on the coarsened constraint line, and then restore the resolution of the mesh through resolution restoration in a subsequent step. The electronic device may store constraint vertex (vertices) located between two replaced constraint edges as attributes of the corresponding edge to accurately restore to the original discretized constraint line in a subsequent step.

[0173] According to an embodiment, the electronic device may separate the 2D pattern into a plurality of components. The electronic device may independently perform quadrangulation for each of the plurality of components. For example, if a feature line completely crosses the 2D pattern or forms a closed loop, the electronic device may separate the 2D pattern into different components. Referring to the 2D pattern 700, since the feature lineincluded in the 2D pattern starts from one boundary line of the 2D pattern and continues to the opposite boundary line, the 2D pattern 600 (note: likely refers to 700) can be separated into three different components based on the corresponding feature line.

[0174] Referring to the 2D pattern 710, a state in which discretized constraint lines are grouped into second clusters is shown. According to an embodiment, the electronic device may group discretized constraint lines into a plurality of clusters. A cluster may be defined as a set of constraint edges in which geometric characteristics are maintained relatively similar. According to an embodiment, the electronic device may group at least one discretized constraint line into first clusters based on the valence of each constraint vertex. Then, the electronic device may group the first clusters into second clusters based on the direction change of each of the first clusters.

[0175] Referring to the 2D pattern 720, a state in which the 2D pattern 710 is straightened is shown. According to an embodiment, the electronic device may straighten the at least one discretized constraint line based on the second clusters. For example, the electronic device may deform the 2D pattern based on straight lines connecting both end points of each of the second clusters. According to an embodiment, the electronic device may perform optimization to minimize distortion and prevent inversion during the deformation process. For example, the electronic device may perform optimization by combining an alignment term that induces the constraint line to align with the straight line direction connecting both end points of each of the second clusters and a distortion term that minimizes the deformation energy of the triangle mesh.

[0176] Referring to the 2D pattern 730, a state in which a segmentation graph is generated based on the straightened constraint lines is shown. According to an embodiment, the electronic device may generate a segmentation graph based on the straightened constraint lines. Based on the angle of the straightened intervals, the electronic device may identify concave vertices among nodes of the segmentation graph and insert split lines extending from the concave vertices. The electronic device may generate at least one candidate edge for each identified concave vertex and select one of the at least one candidate edge as a split line based on a predetermined evaluation criterion. Whenever inserting a split line, the electronic device determines the parity attribute of the corresponding split line so that each loop of the segmentation graph includes an even number of edges.

[0177] Referring to the 2D pattern 740, a state in which the 2D pattern is divided into a plurality of patches based on the segmentation graph is shown. The electronic device may divide the 2D pattern into at least one patch by defining each of the closed loops included in the segmentation graph as a patch. Using the fact that the straightened 2D pattern and the 2D pattern before straightening share the same topology, the electronic device may restore nodes and edges of the segmentation graph defined on the straightened pattern to corresponding positions in the 2D pattern before straightening. According to an embodiment, the electronic device may divide the 2D pattern into at least one patch based on the unstraightened segmentation graph. The electronic device may generate a patch by extracting an area corresponding to each loop of the unstraightened segmentation graph from the 2D pattern.

[0178] Referring to the 2D pattern 750, a state in which quadrangulation has been performed for each patch is shown. According to an embodiment, for each of the at least one patch, the electronic device may perform quadrangulation based on the parity of vertices included in the boundary line of the corresponding patch. The electronic device may select one of a plurality of quadrangulation methods according to the boundary line structure of the corresponding patch. For example, the electronic device may perform quadrangulation using at least one of the first, second, or third quadrangulation methods according to the boundary line structure of the corresponding patch. According to an embodiment, the electronic device may perform a clean-up operation for each of the at least one patch. 'Clean-up' is a post-processing process for improving the quality of the generated quad mesh, and may refer to a task of reducing the number of singularities existing in the mesh or adjusting their positions.

[0179] Referring to the 2D pattern 760, a state in which quad meshes generated on a patch basis are merged is shown. According to an embodiment, if there are a plurality of quadrangulated patches, the electronic device may assemble the plurality of patches. 'Assembly' may refer to a process of combining a plurality of divided patches back into one integrated mesh. Since adjacent patches have the same discretized representation along the shared boundary line, the electronic device may perform assembly by merging corresponding boundary lines and removing duplicate edges. According to an embodiment, the electronic device may merge corresponding vertices included in the corresponding boundary line. 'Corresponding vertices' may refer to a pair of vertices in a corresponding relationship on the boundary line of two adjacent patches. The electronic device may identify vertex pairs arranged along thecorresponding boundary line and sequentially merge each vertex pair into one vertex. According to an embodiment, the assembled 2D pattern 760 may include a plurality of mesh regions adjacent to each other with the constraint edge set as part of the boundary. For example, the assembled quad mesh may include a first mesh region and a second mesh region adjacent to each other including at least a part of the constraint edge set as a shared boundary. According to an embodiment, the edge flow between the first mesh region and the second mesh region may include at least one of a change in geometric direction or topological irregularity. The electronic device may perform a global clean-up operation to improve the edge flow of the generated quad mesh. Boundaries of patches that are not constraint edges are treated as internal edges after assembly and become targets for clean-up, and since the electronic device can perform clean-up across different mesh regions, the electronic device can additionally remove topological irregularities that were not removed in the local clean-up stage. Depending on the embodiment, the electronic device may additionally perform smoothing to improve the geometric quality of the mesh. The electronic device may improve the alignment of edge flow of each mesh region through smoothing.

[0180] Referring to the 2D pattern 770, a state in which quad meshes generated for different components are merged to generate a final quad mesh is shown. According to an embodiment, the electronic device may generate a final quad mesh by merging quad meshes generated for different components. The electronic device may match vertices on the component boundary line and combine component meshes to generate a final quad mesh for the entire 2D pattern. According to an embodiment, the electronic device may perform resolution restoration on the assembled mesh. The electronic device may perform resolution restoration using, for example, but not limited to, at least one of a mesh subdivision method, an adaptive vertex insertion method, or an upsampling method. For example, the electronic device may restore resolution through mesh subdivision. The electronic device may determine a subdivision rule corresponding to the ratio of vertices removed during the coarsening process or the number of times coarsening was performed. As an example, the electronic device may use a midpoint subdivision method. At this time, for constraint edges, the electronic device may place a new vertex accurately at the existing position using the property (e.g., position of removed constraint vertex) stored in the coarsening step. For edges other than constraint edges, the electronic device may place a new vertex at the geometric midpoint.

[0181] FIG. 8 is a block diagram of the configuration of an apparatus according to an embodiment. Referring to FIG. 8, an electronic device 800 according to an embodiment includes one or more processors 810 and a memory 830. The electronic device 800 may further include an output device 850. One or more processors 810, memory 830, and output device 850 may be connected to each other via a communication bus 805. The electronic device 800 may be a PC (Personal Computer), User Equipment such as a smart phone, a Server, and / or a cloud server or cloud computing model providing SaaS (Software as a Service) services.

[0182] The output device 850 indicated by a dotted line in FIG. 8 may be selectively included depending on the type of electronic device 800.

[0183] The one or more processors 810 include processing circuitry.

[0184] The memory 830 stores instructions executed by the one or more processors 810. When the instructions are executed individually or collectively by the one or more processors 810, they cause the electronic device 800 to perform the aforementioned mesh generation method.

[0185] The electronic device 800 may obtain at least one discretized constraint line. The at least one constraint line may include at least one of a boundary line or a feature line included in a 2D pattern. The electronic device 800 may identify at least one constraint line and discretize the identified at least one constraint line into constraint vertices and constraint edges connecting adjacent two constraint vertices.

[0186] The electronic device 800 may divide the 2D pattern into at least one patch based on the at least one discretized constraint line. For each of the at least one patch, the electronic device 800 may perform quadrangulation based on the parity of vertices included in the boundary line of the corresponding patch. Based on the result of quadrangulation, the electronic device 800 may generate a quad mesh in which at least one constraint line is preserved. At this time, data necessary for performing the mesh generation method and intermediate data generated during the mesh generation process may be stored inside the electronic device 800, such as in the memory 830, or may be stored externally to the electronic device 800, such as in a cloud server, cloud storage, or external hard drive.

[0187] The output device 850 may output (display) the mesh generated by the one or more processors 810. In addition, the memory 830 may store various information generated during the processing of the one or more processors 810 described above. According to anembodiment, the memory 830 may store a program in which the mesh generation method described above with reference to FIGS. 1 to 7 is implemented. In addition, the memory 830 may store various data and programs. The memory 830 may include volatile memory or non-volatile memory. The memory 830 may include a large-capacity storage medium such as a hard disk to store various data. Also, the one or more processors 810 may perform at least one method or an algorithm corresponding to at least one method described above with reference to FIGS. 1 to 7.

[0188] The one or more processors 810 may be data processing devices implemented in hardware having a circuit with a physical structure for executing desired operations. For example, desired operations may include codes or instructions included in a program. The one or more processors 810 may be composed of, for example, a CPU (Central Processing Unit), GPU (Graphics Processing Unit), or NPU (Neural network Processing Unit). For example, the electronic device 800 implemented in hardware may include a microprocessor, a central processing unit, a processor core, a multi-core processor, a multiprocessor, an ASIC (Application-Specific Integrated Circuit), and an FPGA (Field Programmable Gate Array).

[0189] The one or more processors 810 may execute a program and control the electronic device 800. Program codes executed by the one or more processors 810 may be stored in the memory 830. Also, the electronic device 800 according to an embodiment may receive data from a user via an input / output device (I / O) and output generated data. For example, the electronic device 800 may receive input from a user defining or modifying constraint lines through the input / output device. The electronic device 800 may be connected to an external device (e.g., a personal computer or a network) via the input / output device and exchange data.

[0190] The electronic device 800 according to an embodiment may further include other components not shown. For example, the electronic device 800 may further include a communication module providing a function for the electronic device 800 to communicate with other electronic devices or other servers over a network. Also, for example, the electronic device 800 may further include other components such as a transceiver, various sensors, a database, etc. The embodiments described above may be implemented with hardware components, software components, and / or combinations of hardware components and software components. For example, the apparatuses, methods, and components described in the embodiments may be implemented using a general-purpose computer or special-purpose computer, such as, for example, a processor, a controller, an ALU (arithmetic logic unit), a digital signal processor, amicrocomputer, an FPGA (field programmable gate array), a PLU (programmable logic unit), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications running on the operating system. Also, the processing device may access, store, manipulate, process, and generate data in response to the execution of software. For convenience of understanding, there may be cases where one processing device is described as being used, but those of ordinary skill in the art will recognize that the processing device may include a plurality of processing elements and / or a plurality of types of processing elements. For example, the processing device may include a plurality of processors or one processor and one controller. Also, other processing configurations such as parallel processors are possible.

[0191] The software may include a computer program, code, instructions, or a combination of one or more of these, and may configure the processing device to operate as desired or instruct the processing device independently or collectively. Software and / or data may be stored in any type of machine, component, physical device, virtual equipment, computer storage medium, or device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored in a computer-readable recording medium.

[0192] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may store program instructions, data files, data structures, etc., alone or in combination, and the program instructions recorded on the medium may be those specially designed and configured for the embodiment or may be known and available to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions such as ROM, RAM, flash memory, etc.

[0193] Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, etc., as well as machine language codes such as those produced by a compiler.

[0194] The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

[0195] As described above, although the embodiments have been described with reference to limited drawings, those of ordinary skill in the art may apply various technical modifications and variations based thereon. For example, appropriate results may be achieved even if the described techniques are performed in a different order than the described method, and / or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the following claims.

Claims

ClaimsWhat is claimed is:

1. A mesh generation method performed by at least one processor, comprising:obtaining a constraint edge set corresponding to at least a portion of a line on a 2D pattern; andgenerating a quad mesh corresponding to the 2D pattern based on the constraint edge set, wherein the constraint edge set in the 2D pattern is preserved in the quad mesh.

2. The method of claim 1, wherein the constraint edge set includes one or more interior vertices positioned between both endpoints of the constraint edge set, and wherein the preservation of the constraint edge set in the quad mesh comprises maintaining a position of each of the one or more interior vertices in the 2D pattern as a position of each of the one or more interior vertices in the quad mesh.

3. The method of claim 1, wherein the preservation of the constraint edge set in the quad mesh comprises preserving the constraint edge set in the quad mesh without adding an interior vertex to the constraint edge set.

4. The method of claim 1, wherein the quad mesh includes a first mesh region and a second mesh region adjacent to each other with the constraint edge set as a portion of a boundary , and wherein an edge flow between the first mesh region and the second mesh region includes at least one of a change in geometric direction or topological irregularity.

5. The method of claim 4, wherein the topological irregularity is formed in response to a difference between a grid density of the first mesh region and a grid density of the second mesh region.

6. The method of claim 4, wherein a region including the first mesh region and the second mesh region includes a vertex whose valence is not 4.

7. The method of claim 6, wherein the vertex whose valence is not 4 is not disposed on the constraint edge set except for both endpoints of the constraint edge set.

8. The method of claim 4, wherein the change in geometric direction is formed in response to a difference between a first angle formed by a first edge of the first mesh region and the constraint edge set and a second angle formed by a second edge of the second mesh region and the constraint edge set.

9. The method of claim 1, wherein the line includes at least one of a boundary line or a feature line of the 2D pattern.

10. The method of claim 9, wherein the feature line corresponds to any one of darts, pleats, a fold line, a seam line, and an internal line of the 2D pattern.

11. The method of claim 1, wherein the constraint edge set includes a first constraint edge and a second constraint edge connected to the first constraint edge, and wherein the preservation of the constraint edge set in the quad mesh comprises maintaining a connection relationship between the first constraint edge and the second constraint edge in the 2D pattern within the quad mesh.

12. The method of claim 1, wherein the generating of the quad mesh based on the constraint edge set comprises:dividing the 2D pattern into one or more patches based on the constraint edge set; determining an internal grid structure of each of the one or more patches; and generating the quad mesh based on the internal grid structure of each of the one or more patches.

13. The method of claim 1, wherein an edge count of the constraint edge set preserved in the quad mesh is even.

14. The method of claim 1, wherein: the 2D pattern includes a first pattern and a second pattern; the constraint edge set includes a first constraint edge set corresponding to the first pattern and asecond constraint edge set corresponding to the second pattern; the first constraint edge set and the second constraint edge set are coupled to each other through sewing; the quad mesh includes a first quad mesh generated in correspondence with the first pattern and a second quad mesh generated in correspondence with the second pattern; and vertices included in the first constraint edge set in the first quad mesh correspond one-to-one with vertices included in the second constraint edge set in the second quad mesh.

15. The method of claim 1, wherein the 2D pattern includes a third pattern and a fourth pattern symmetrical to the third pattern, the quad mesh includes a third quad mesh generated in correspondence with the third pattern and a fourth quad mesh generated in correspondence with the fourth pattern, and the third quad mesh and the fourth quad mesh achieve topological symmetry.

16. The method of claim 1, further comprising deforming the quad mesh into a graded quad mesh based on a user input for grading the 2D pattern from a first size to a second size, wherein the constraint edge set corresponds to one edge set of the graded quad mesh, and a difference between an edge count of the constraint edge set and an edge count of the one edge set is a multiple of 2.

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