Display substrate, preparation method therefor, and display apparatus

Abstract

Provided is a display substrate, comprising: a base substrate; a drive circuit layer; a conductive layer, comprising a plurality of conductive portions and a plurality of power supply traces; a first planarization layer, comprising a plurality of first via holes; a bonding layer, located on the side of the conductive layer away from the base substrate, comprising a plurality of first bonding pads arranged at intervals, each first bonding pad being electrically connected to one of the conductive portions and power supply traces by means of a first via hole; and a plurality of light-emitting devices, the light-emitting devices being electrically connected to the first bonding pads. The material of the first planarization layer comprises an organic material. Each first bonding pad comprises a pad body portion and a pad connection portion that are integrally connected. The pad body portion is located on the surface of the first planarization layer away from the base substrate, and the pad connection portion is directly connected to one of the conductive portions and the power supply traces by means of a first via hole. Each light-emitting device is electrically connected to a pad body portion.

Description

Display substrate, its preparation method, and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Micro light-emitting diodes (LEDs) are light-emitting diodes with dimensions on the micrometer scale. Due to their small size, Micro LEDs can be used as pixels on display panels, and display panels made using Micro LEDs are called Micro LED display panels. Micro LED technology involves miniaturizing existing LEDs to below 100µm, approximately 1% of the current LED size, and then using mass transfer technology to transfer these micrometer-sized Micro / mini-LEDs onto a driving substrate, thereby forming Micro LED displays of various sizes. Improving the bonding yield between LEDs and the driving substrate is one of the important research topics for researchers.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, comprising:

[0005] Substrate;

[0006] The driving circuit layer is located on the substrate.

[0007] A conductive layer is located on the side of the driving circuit layer away from the substrate. The conductive layer includes multiple conductive parts and multiple power lines. The conductive parts are electrically connected to the driving circuit layer, and at least one power line is electrically connected to the driving circuit layer.

[0008] A first planarization layer is located on the side of the driving circuit layer away from the substrate. The first planarization layer includes a plurality of first vias, each of which exposes a portion of a plurality of conductive portions. Additionally, each of the first vias exposes a portion of a plurality of power traces.

[0009] A bonding layer, located on the side of the conductive layer away from the substrate, includes a plurality of spaced-apart first bonding pads, the first bonding pads being electrically connected to one of the conductive portion and the power trace via the first via; and

[0010] A light-emitting device layer is located on the side of the bonding layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices spaced apart, and the light-emitting devices are electrically connected to the first bonding pads.

[0011] The material of the first planarization layer includes organic materials;

[0012] The first bonding pad includes a pad body portion and a pad connection portion integrally connected. The pad body portion is located on the surface of the first planarization layer away from the substrate. The pad connection portion is directly connected to one of the conductive portion and the power trace through the first via. The orthographic projection of the pad body portion on the substrate is located within the orthographic projection of the first planarization layer on the substrate. The orthographic projection of the pad connection portion on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0013] The light-emitting device is electrically connected to the main body of the pad.

[0014] According to some exemplary embodiments, the substrate includes a first surface facing the driving circuit layer, and the thickness of the bonding layer is less than the thickness of the conductive layer along a direction perpendicular to the first surface.

[0015] According to some exemplary embodiments, the thickness of the bonding layer is less than 2 micrometers; and / or,

[0016] The thickness of the conductive layer is greater than or equal to 2 micrometers.

[0017] According to some exemplary embodiments, the portion of the pad connection located within the first via includes a recessed structure that is recessed toward the side closer to the substrate.

[0018] According to some exemplary embodiments, the substrate includes a first surface facing the driving circuit layer, and the conductive portion has a cross-sectional shape that includes an inverted trapezoid along a direction perpendicular to the first surface; and / or,

[0019] The shape of the cross-section of the power trace along the direction perpendicular to the first surface includes an inverted trapezoid.

[0020] According to some exemplary embodiments, the display substrate further includes a support pillar layer located on the side of the first planarization layer away from the substrate, the support pillar layer comprising a plurality of spaced-apart support pillars; and

[0021] The surface of the support pillar furthest from the substrate is further from the substrate than the surface of the first bonding pad furthest from the substrate, and the surface of the support pillar closest to the substrate is further from the substrate than the surface of the conductive layer furthest from the substrate.

[0022] According to some exemplary embodiments, the display substrate further includes a first passivation layer located between the first planarization layer and the bonding layer, the first passivation layer including a second via, and the first bonding pad being electrically connected to one of the conductive portion and the power trace through the second via and the first via; and

[0023] The support column is located between the first planarization layer and the first passivation layer.

[0024] According to some exemplary embodiments, the display substrate further includes a first passivation layer located between the first planarization layer and the bonding layer, the first passivation layer including a second via, and the first bonding pad being electrically connected to one of the conductive portion and the power trace through the second via and the first via; and

[0025] The support column is located on the side of the first passivation layer away from the first planarization layer.

[0026] According to some exemplary embodiments, the portion of the pad connection located within the first via includes a recessed structure, the recessed structure being recessed towards the side closest to the substrate; and

[0027] The support column layer also includes a filling portion, which is located within the recessed structure.

[0028] According to some exemplary embodiments, at least one of the filling portions is flush with the surface of the substrate away from the substrate and the surface of the pad body portion away from the substrate; and / or,

[0029] At least one of the filling portions is flush with the surface of the substrate away from the substrate and the surface of the first passivation layer away from the substrate; and / or,

[0030] At least one of the filling portions has a virtual extension surface away from the surface of the substrate located between the surface of the pad body portion away from the substrate and the surface of the first passivation layer away from the substrate.

[0031] According to some exemplary embodiments, the display substrate further includes a second passivation layer located between the conductive layer and the first planarization layer; and

[0032] The second passivation layer includes a third via, through which the first bonding pad is electrically connected to one of the conductive portion and the power trace.

[0033] According to some exemplary embodiments, the conductive layer and the first planarization layer are in direct contact.

[0034] According to some exemplary embodiments, the material of the first planarization layer includes polysilazane.

[0035] According to some exemplary embodiments, the orthographic projection of the second via on the substrate lies within the orthographic projection of the first via on the substrate; and

[0036] The first planarization layer includes a first sidewall located at the first via, and the first passivation layer covers the first sidewall.

[0037] According to some exemplary embodiments, the first planarization layer includes a first sidewall located at the first via, and the first passivation layer includes a second sidewall located at the second via, the second sidewall being located on the side of the first sidewall away from the substrate; and

[0038] The first bonding pad covers at least a portion of the first sidewall, and the first bonding pad covers at least a portion of the second sidewall.

[0039] According to some exemplary embodiments, the orthographic projection of the second via on the substrate lies within the orthographic projection of the first via on the substrate, and the orthographic projection of the third via on the substrate lies within the orthographic projection of the first via on the substrate; and

[0040] The first planarization layer includes a first sidewall located at the first via, and the first passivation layer covers the first sidewall;

[0041] The first passivation layer includes a second sidewall located at the second via, and the second passivation layer includes a third sidewall located at the third via, wherein the second sidewall and the third sidewall are connected.

[0042] According to some exemplary embodiments, the first planarization layer includes a first sidewall located at the first via, the first passivation layer includes a second sidewall located at the second via, the second passivation layer includes a third sidewall located at the third via, the second sidewall being located on the side of the first sidewall away from the substrate, and the first sidewall being located on the side of the third sidewall away from the substrate; and

[0043] The first bonding pad covers at least a portion of the first sidewall, the first bonding pad covers at least a portion of the second sidewall, and the first bonding pad covers at least a portion of the third sidewall.

[0044] According to some exemplary embodiments, the light-emitting device includes a first electrode, a light-emitting functional layer located on the side of the first electrode away from the substrate, and a second electrode located on the side of the light-emitting functional layer away from the substrate; and

[0045] The first electrode and the first bonding pad are electrically connected.

[0046] According to some exemplary embodiments, the substrate includes a first surface facing the driving circuit layer, and the distance between the surface of the first planarization layer away from the substrate and the surface of the conductive layer away from the substrate is greater than or equal to 1 micrometer along a direction perpendicular to the first surface.

[0047] According to some exemplary embodiments, the substrate includes a first surface facing the driving circuit layer. In two adjacent bonding pads, the distance between the surface of one pad body away from the substrate and the first surface in a direction perpendicular to the first surface is a first distance, and the distance between the surface of the other pad body away from the substrate and the first surface in a direction perpendicular to the first surface is a second distance. The difference between the first distance and the second distance is less than or equal to 0.2 μm.

[0048] In another aspect, a method for preparing a display substrate is provided, the method comprising:

[0049] A driving circuit layer is formed on the substrate.

[0050] A conductive layer is formed on the side of the driving circuit layer away from the substrate. The conductive layer includes a plurality of conductive parts and a plurality of power lines. The conductive parts are electrically connected to the driving circuit layer, and at least one of the power lines is electrically connected to the driving circuit layer.

[0051] A first planarization layer is formed on the side of the driving circuit layer away from the substrate. The material of the first planarization layer includes an organic material. The first planarization layer includes a plurality of first vias, each of which exposes a portion of a plurality of conductive portions. In addition, each of the plurality of first vias exposes a portion of a plurality of power lines.

[0052] A bonding layer is formed on the side of the conductive layer away from the substrate. The bonding layer includes a plurality of first bonding pads spaced apart. Each first bonding pad includes a pad body portion and a pad connection portion integrally connected. The pad body portion is located on the surface of the first planarization layer away from the substrate. The pad connection portion is directly connected to one of the conductive portion and the power trace through a first via. The orthographic projection of the pad body portion on the substrate is located within the orthographic projection of the first planarization layer on the substrate. The orthographic projection of the pad connection portion on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0053] A light-emitting device layer is formed on the side of the bonding layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices spaced apart, and the light-emitting devices are electrically connected to the pad body portion.

[0054] According to some exemplary embodiments, the step of forming the conductive layer includes:

[0055] A photoresist layer is formed on the side of the driving circuit layer away from the substrate, the photoresist layer including multiple cutouts; and

[0056] Multiple conductive parts and multiple power lines are formed within the multiple cutouts using an additive electroplating process.

[0057] According to some exemplary embodiments, the step of forming the bonding layer includes:

[0058] A bonded conductive thin film is formed on the side of the conductive layer away from the substrate by a sputtering deposition process; and

[0059] The bonding conductive film is patterned using a patterning process to obtain multiple first bonding pads.

[0060] In another aspect, a display device is provided, comprising a display substrate as described in any of the preceding claims. Attached Figure Description

[0061] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0062] Figures 1A-1D schematically illustrate the mass transfer process of a light-emitting device in the related art.

[0063] Figure 2 schematically shows a cross-sectional view of a display substrate in the related art.

[0064] Figure 3 schematically illustrates the bonding process of a display substrate in the related art.

[0065] Figure 4 schematically shows a cross-sectional view of another display substrate in the related art.

[0066] Figure 5 schematically shows a microscopic cross-sectional view of a display substrate in the related art.

[0067] Figure 6 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0068] Figure 7 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0069] Figure 8 schematically shows a cross-sectional view of the driving circuit layer of a display substrate according to some embodiments of the present disclosure.

[0070] Figure 9 schematically shows a plan view of the conductive layer of a display substrate according to some embodiments of the present disclosure.

[0071] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0072] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0073] Figures 12A-12B schematically illustrate the formation principle of the support pillar layer in a display substrate according to some embodiments of the present disclosure.

[0074] Figure 13 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0075] Figure 14 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0076] Figure 15 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0077] Figure 16 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0078] Figure 17 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0079] Figure 18 schematically illustrates a flowchart of a method for fabricating a display substrate according to some embodiments of the present disclosure.

[0080] Figures 19A-19N schematically illustrate flowcharts of methods for fabricating a display substrate according to some embodiments of the present disclosure. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0082] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0083] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0084] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0085] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0086] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0087] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0088] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0089] Micro LED technology involves miniaturizing existing LEDs to below 100µm, approximately 1% the size of existing LEDs, and then using mass transfer technology to transfer these micron-sized Micro LEDs onto a driving substrate, thereby forming Micro LED displays of various sizes.

[0090] Figures 1A-1D schematically illustrate the mass transfer process of a light-emitting device in the related art.

[0091] In related technologies, the process of transferring a Micro LED to a driving substrate may include the following steps.

[0092] Referring to FIG1A, a light-emitting device substrate 900' is provided, the light-emitting device substrate 900' includes a plurality of light-emitting devices 310' spaced apart, and a second bonding pad PAD2' is provided on the light-emitting device 310'.

[0093] Referring to FIG1B, a driving substrate is provided, on which a plurality of first bonding pads PAD1' are disposed at intervals.

[0094] Referring to Figures 1A, 1B, and 1C, the carrier substrate 900' of the light-emitting device is assembled with the driving substrate, such that the second bonding pad PAD2' of the carrier substrate 900' of the light-emitting device comes into contact with the first bonding pad PAD1' of the driving substrate, and the first bonding pad PAD1' and the second bonding pad PAD2' are bonded together in a high-temperature environment.

[0095] Referring to FIG1D, the light-emitting device 310' that needs to be transferred to the driving substrate is selectively detached from the light-emitting device carrier substrate 900'.

[0096] It should be noted that the multiple light-emitting devices 310' are formed by epitaxial growth on a substrate 100' (such as sapphire or gallium nitride), and then the epitaxial layer is patterned to form multiple light-emitting devices 310' spaced apart. In order to improve the utilization rate of the epitaxial layer, the arrangement density of the light-emitting devices 310' in the carrier substrate 900' is greater than the arrangement density of the first bonding pad PAD1' in the driving substrate. Therefore, after bonding, it is necessary to selectively disassemble the light-emitting devices 310' in the carrier substrate 900'.

[0097] Figure 2 schematically shows a cross-sectional view of a display substrate in the related art.

[0098] Referring to FIG2, the display substrate includes a substrate 100', a driving circuit layer 200' and a light-emitting device layer 300' located on the substrate 100'.

[0099] Along the direction away from the substrate 100', the light-emitting device layer 300' and the substrate 100' may sequentially include a light-shielding layer LS', a first buffer layer Buf1', a first active layer Act1', a first gate insulating layer GI1', a first gate metal layer Gate1', a second gate insulating layer GI2', a second gate metal layer Gate2', a first interlayer dielectric layer ILD1', a second buffer layer Buf2', a second active layer Act2', a third gate insulating layer GI3', a third gate metal layer Gate3', a second interlayer dielectric layer ILD2', a first source / drain metal layer SD1', a first planarization layer PLN1', a first passivation layer PVX1', a second source / drain metal layer SD2', a second planarization layer PLN2', a second passivation layer PVX2', a third source / drain metal layer SD3', a third planarization layer PLN3', a third passivation layer PVX3', and a fourth source / drain metal layer SD4'. The first power trace VDD' is located on the second source / drain metal layer SD2', the second power trace VSS' is located on the third source / drain metal layer SD3', and the first bonding pad PAD1' is located on the fourth source / drain metal layer SD4'.

[0100] In these film layers, each of the following requires a mask patterning process: light-shielding layer LS', first active layer Act1', first gate metal layer Gate1', second gate metal layer Gate2', second active layer Act2', third gate metal layer Gate3', second interlayer dielectric layer ILD2', first source / drain metal layer SD1', first planarization layer PLN1', first passivation layer PVX1', second source / drain metal layer SD2', second planarization layer PLN2', second passivation layer PVX2', third source / drain metal layer SD3', third planarization layer PLN3', third passivation layer PVX3', and fourth source / drain metal layer SD4'. In total, 17 masks are required, resulting in high manufacturing costs.

[0101] Figure 3 schematically illustrates the bonding process of a display substrate in the related art.

[0102] Referring to Figure 3, the inventors discovered that the first bonding pad PAD1' and the power trace PL' (including the first power trace and the second power trace) in the driving substrate can be placed on the same layer, thereby simplifying the fabrication process of the display substrate and reducing the manufacturing cost of the display substrate. However, when the first bonding pad PAD1' and the power trace PL' are located on the same layer, during the transfer bonding process, the power trace PL' on the driving substrate will come into contact with and be bonded to the light-emitting device 310' in the carrier substrate 900' that does not require transfer bonding, thus causing defects.

[0103] Figure 4 schematically shows a cross-sectional view of another display substrate in the related art.

[0104] Referring to Figure 4, to avoid the problem of the power trace PL' on the driving substrate coming into contact with and being bonded to the light-emitting device 310' in the carrier substrate that does not require transfer bonding during the transfer bonding process, a shim B' can be provided on the side of the first bonding pad PAD1' closest to the substrate 100', so that the upper surface of the first bonding pad PAD1' is higher than the upper surface of the power trace PL'. The first bonding pad PAD1' and the power trace PL' can still be formed by the same film deposition process and patterning process, thereby simplifying the fabrication process of the display substrate and reducing the manufacturing cost of the display substrate.

[0105] However, in this display substrate, the heights of the different first bonding pads PAD1' away from the surface of the substrate 100' are inconsistent, with a height difference ranging from 0.2μm to 0.5μm. Given current bonding process capabilities, this height difference needs to be less than 0.17μm; otherwise, bonding defects are likely to occur.

[0106] The inventors discovered that the significant height difference between the surfaces of the different first bonding pads PAD1' and the substrate 100' is due to the fact that the film deposition process for forming the first bonding pads PAD1' and the power traces PL' is an additive electroplating process. This additive electroplating process is patterned plating (i.e., forming a film layer with a specific pattern through a plating process). The specific pattern design directly affects the distribution of electric field lines in the plating bath during electroplating; uneven electric field line distribution results in uneven plating thickness. Furthermore, the shim B' located below the first bonding pads PAD1' is an independent block structure, making its upper surface uneven and roughly arched, further increasing the height difference between the upper surfaces of the different first bonding pads.

[0107] Figure 5 schematically shows a microscopic cross-sectional view of a display substrate in the related art.

[0108] Referring to Figures 4 and 5, the inventors also discovered that an organic insulating portion ORG' exists within the via connecting the first bonding pad PAD1' and the first source / drain metal layer SD1'. This organic insulating portion ORG' causes poor overlap between the first bonding pad PAD1' and the first source / drain metal layer SD1'. Testing revealed that the material of the organic insulating portion ORG' is the same as the material of the support pillar PS', meaning that the organic insulating portion ORG' is a residual structure from the formation of the support pillar PS'. The inventors' research found that the main cause of this residue is the excessive height of the support pillar PS' (≥4.5µm), making it particularly prone to residue formation at via locations during patterning processes.

[0109] Figure 6 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure. Figure 7 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure, wherein Figure 7 schematically shows a cross-sectional view taken along line A1-A2 in Figure 6. Figure 8 schematically shows a cross-sectional view of the driving circuit layer of a display substrate according to some embodiments of the present disclosure.

[0110] Referring to Figures 6, 7, and 8, the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display substrate includes a substrate 100, a driving circuit layer 200 on the substrate 100, a conductive layer 400 on the side of the driving circuit layer 200 away from the substrate 100, a first planarization layer PLN1 on the side of the conductive layer 400 away from the substrate 100, a bonding layer 500 on the side of the first planarization layer PLN1 away from the substrate 100, and a light-emitting device layer 300 on the side of the bonding layer 500 away from the substrate 100.

[0111] The driving circuit layer 200 includes stacked multilayer films to form multiple pixel driving circuits located within the display area AA. These multiple pixel driving circuits are arranged along a first direction X and a second direction Y. Along a direction away from the substrate 100, the driving circuit layer 200 may sequentially include a light-shielding layer LS, a first buffer layer Buf1, a first active layer Act1, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a first interlayer dielectric layer ILD1, a second buffer layer Buf2, a second active layer Act2, a third gate insulating layer GI3, a third gate metal layer Gate3, a second interlayer dielectric layer ILD2, a source / drain metal layer SD, and a second planarization layer PLN2. The material of the first active layer Act1 may include low-temperature polysilicon, and the material of the second active layer Act2 may include an oxide semiconductor material, such as indium gallium zinc oxide. Of course, Figure 8 only schematically shows a cross-sectional structure of a driving circuit layer 200. Depending on the actual needs, the driving circuit layer 200 may include only some of the film layers shown in Figure 8, or it may include other film layers.

[0112] The conductive layer 400 includes multiple conductive portions 410 and multiple power lines 420. The conductive portions 410 are electrically connected to the driving circuit layer 200, and at least one power line 420 is electrically connected to the driving circuit layer 200. For example, the power line 420 may include a first power line 421 and a second power line 422. The first power line 421 is electrically connected to the pixel driving circuit, and the second power line 422 is used to electrically connect to an electrode of the light-emitting device 310. In the conductive layer 400, the multiple conductive portions 410 are independent block structures, arranged at intervals along the first direction X and the second direction Y. The multiple power lines 420 may extend along the second direction Y and be arranged along the first direction X. Multiple conductive portions 410 distributed at intervals along the second direction Y may be provided between two adjacent power lines 420.

[0113] The driving circuit layer 200 includes a source / drain metal layer SD on the side away from the substrate 100. The source / drain metal layer SD includes a second planarization layer PLN2 on the side away from the substrate 100. The second planarization layer PLN2 includes a third passivation layer PVX3 on the side away from the substrate 100. The second planarization layer PLN2 includes a fourth via VO4, and the third passivation layer PVX3 includes a fifth via VO5. The fifth via VO5 and the fourth via VO4 are connected, exposing a portion of the source / drain metal layer SD. The conductive portion 410 is electrically connected to the source / drain metal layer SD through the fourth via VO4 and the fifth via VO5. At least one power trace 420 is electrically connected to the source / drain metal layer SD through the fourth via VO4 and the fifth via VO5.

[0114] The material of the first planarization layer PLN1 includes an organic material. The formation process of the first planarization layer PLN1 may include: coating an organic liquid film on the side of the conductive layer 400 away from the substrate 100; after the organic liquid film has leveled, subjecting the organic liquid film to exposure, development, and curing processes in sequence to form a first planarization layer PLN1 having multiple first vias VO1. The multiple first vias VO1 expose multiple conductive portions 410, and the other multiple first vias VO1 expose multiple power lines 420, for example, the multiple first vias VO1 expose multiple second power lines 422.

[0115] Figure 9 schematically shows a plan view of the conductive layer of a display substrate according to some embodiments of the present disclosure.

[0116] Referring to Figures 6, 7, and 9, the bonding layer 500 includes a plurality of first bonding pads 510 spaced apart. These bonding pads are arranged at intervals along a first direction X and a second direction Y within the display area AA. The first bonding pads 510 are used for bonding connections with the light-emitting device 310. The first bonding pads 510 are electrically connected to either the conductive portion 410 or the power trace 420 via a first via V01. That is, the first bonding pads 510 can be electrically connected to the conductive portion 410 via V01, or they can be electrically connected to the power trace 420 via V01. Specific connection methods are described later.

[0117] The first bonding pad 510 includes a pad body portion 511 and a pad connection portion 512 connected as one piece. The pad body portion 511 is located on the surface of the first planarization layer PLN1 away from the substrate 100. The pad connection portion 512 is directly connected to one of the conductive portion 410 and the power trace 420 through the first via VO1. The orthographic projection of the pad body portion 511 on the substrate 100 is located within the orthographic projection of the first planarization layer PLN1 on the substrate 100. The orthographic projection of the pad connection portion 512 on the substrate 100 at least partially overlaps with the orthographic projection of the first via VO1 on the substrate 100.

[0118] For example, if the first bonding pad 510 is electrically connected to the conductive part 410, then one electrode in the light-emitting device 310 that is electrically connected to the first bonding pad 510 is electrically connected to the pixel driving circuit through the first bonding pad 510 and the conductive part 410. The other electrode in the light-emitting device 310 can be electrically connected to the power trace 420 (e.g., the second power trace 422) through the first via V01. The structure of the other electrode in the light-emitting device 310 being connected to the power trace 420 is not shown in Figure 7. The connection can be achieved by forming a connection part after the light-emitting device 310 is bonded to the first bonding pad 510.

[0119] For example, if the first bonding pad 510 is electrically connected to the power trace 420 (e.g., the second power trace 422), then one electrode in the light-emitting device 310 that is electrically connected to the first bonding pad 510 is electrically connected to the power trace 420 through the first bonding pad 510 and the conductive part 410. The other electrode in the light-emitting device 310 can be electrically connected to the conductive part 410 through the first via VO1, and further electrically connected to the pixel driving circuit through the conductive part 410.

[0120] Figure 7 only schematically shows the structure in which the first bonding pad 510 is connected to the conductive part 410. Depending on the actual needs, the first bonding pad 510 can also be connected to the power trace 420.

[0121] It should be noted that in this article, "connected as one" should be understood as a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different. The pad body portion 511 and the pad connection portion 512 in the first bonding pad 510 are connected structures formed in one process, and there is no physical boundary between the pad body portion 511 and the pad connection portion 512. The orthographic projection of the pad body portion 511 onto the substrate 100 is, for example, a relatively regular shape such as a circle, rectangle, or hexagon, while the orthographic projection of the pad connection portion 512 onto the substrate 100 is a straight line or a broken line strip. The dimension of the pad connection portion 512 along its extension direction is smaller than the dimension of the pad body portion 511 along the first direction X and the second direction Y. The location in the first bonding pad 510 where the size and edge contour change abruptly should be considered as the dividing line between the pad body portion 511 and the pad connection portion 512 (for example, the dashed line shown in FIG9).

[0122] It should be noted that due to factors such as the precision of the manufacturing process, the actual position and shape of the first bonding pad 510 may deviate from the design value to a certain extent, and the actual position and shape of the first via V01 may also deviate from the design value to a certain extent. According to the boundary division method of the pad body 511 and the pad connection portion 512 shown in Figure 9, a part of the pad body 511 may fall into the first via V01. In this case, the part located in the first via V01 should be regarded as part of the pad connection portion 512. The entire pad body 511 is located on the side of the first planarization layer PLN1 away from the substrate 100.

[0123] The light-emitting device layer 300 includes a plurality of light-emitting devices 310 spaced apart, which are arranged at intervals along a first direction X and a second direction Y. The light-emitting devices 310 are electrically connected to the pad body portion 511 in the first bonding pad 510. For example, the side of the light-emitting device 310 closest to the substrate 100 includes a second bonding pad PAD2, which is bonded to the pad body portion 511, thereby electrically connecting the light-emitting device 310 to the first bonding pad 510.

[0124] The multiple light-emitting devices 310 may include multiple first light-emitting devices, multiple second light-emitting devices, and multiple third light-emitting devices. The first light-emitting devices can emit red light, the second light-emitting devices can emit green light, and the third light-emitting devices can emit blue light, thereby realizing the color display of the display substrate.

[0125] Optionally, the multiple light-emitting devices 310 can all emit blue light, and a light color conversion structure can be further provided on the side of the multiple light-emitting devices 310 away from the substrate 100 to convert the blue light emitted by a portion of the light-emitting devices 310 into red light, convert the blue light emitted by another portion of the light-emitting devices 310 into green light, and leave the blue light emitted by the remaining portion of the light-emitting devices 310 unconverted, thereby realizing the color display of the display substrate.

[0126] Multiple light-emitting devices 310 can be electrically connected to the driving circuit layer 200 independently, or the multiple light-emitting devices 310 can be divided into multiple light-emitting device groups, each light-emitting device group including at least two light-emitting devices 310. The multiple light-emitting device groups are electrically connected to the driving circuit layer 200 independently, and the multiple light-emitting devices 310 in the light-emitting device group are connected in series sequentially.

[0127] In the display substrate of this embodiment, the power line 420 and the first bonding pad 510 are respectively disposed in two film layers (conductive layer 400 and bonding layer 500), and a first planarization layer PLN1 including organic material is disposed between the conductive layer 400 and the bonding layer 500. The first planarization layer PLN1 undergoes a leveling process during its formation, and the surface of the first planarization layer PLN1 away from the substrate 100 has high flatness, so that the height difference of the surface of the substrate 100 near the pad body portion 511 in different first bonding pads 510 is small. In this way, the height difference of the surface of the substrate 100 away from the pad body portion 511 in different first bonding pads 510 can be small, so as to ensure the bonding yield between the light-emitting device 310 and the first bonding pad 510.

[0128] It should be noted that, in this document, the height of a surface of a structure refers to the distance between that surface and the first surface 100a of the substrate 100 in a direction perpendicular to the first surface 100a, where the first surface 100a is the surface of the substrate 100 including the driving circuit layer 200.

[0129] According to some exemplary embodiments, referring to FIG7, in two adjacent bonding pads, the distance between the surface of one pad body portion 511 away from the substrate 100 and the first surface 100a in a direction perpendicular to the first surface 100a is a first distance D1, and the distance between the surface of the other pad body portion 511 away from the substrate 100 and the first surface 100a in a direction perpendicular to the first surface 100a is a second distance D2, and the difference between the first distance D1 and the second distance D2 is less than or equal to 0.2 μm.

[0130] According to some exemplary embodiments, the conductive layer 400 may be formed by an addition electroplating process, and the bonding layer 500 may be formed by a sputtering deposition process.

[0131] The process of forming the conductive layer 400 using the additive electroplating process includes: first, forming a photoresist layer with a specific shape through a patterning process, and then forming the conductive layer 400 by additive electroplating within the cutouts of the photoresist layer. The additive electroplating process offers higher precision, thereby improving the accuracy of the conductive portions 410 and power traces 420 in the conductive layer 400 to meet the requirements of higher resolution. The specific formation process is described in detail below.

[0132] The process of forming the bonding layer 500 by sputtering deposition includes: depositing a bonding conductive film over the entire surface by sputtering deposition, and then patterning the bonding conductive film into a bonding layer by a patterning process. The bonding layer 500 formed by sputtering deposition has good thickness uniformity, which is beneficial for further reducing the height difference between the surface of the substrate 100 and the surface of the pad body portion 511 in different first bonding pads 510.

[0133] Furthermore, in order to ensure the uniformity of the thickness of the bonding layer 500 and the precision of the conductive layer 400, the thickness of the bonding layer 500 in the direction perpendicular to the first surface 100a can be set to be smaller than that of the conductive layer 400.

[0134] According to some exemplary embodiments, along the direction perpendicular to the first surface 100a, the thickness THK1 of the bonding layer 500 is less than 2 micrometers, and the thickness THK2 of the conductive layer 400 is greater than or equal to 2 micrometers.

[0135] It should be noted that the thickness THK1 of the conductive layer 400 should be understood as the thickness of the portion of the conductive layer 400 outside the first via V01, for example, the thickness of the second power trace 422 that is not electrically connected to the drive circuit layer 200. The thickness of the bonding layer 500 should be understood as the thickness of the pad body portion 511.

[0136] According to some exemplary embodiments, in order to improve the thickness uniformity of the conductive layer 400 formed by the addition electroplating process, a plating area can be provided in the region not used to form the conductive layer 400, for example, a plating area can be provided in the peripheral region. During the formation of the conductive layer 400 by the addition electroplating process, the plating area is also plated. After the addition electroplating process is completed, the film structure formed in the plating area is removed. In this way, the thickness uniformity of the conductive layer 400 can be improved.

[0137] According to some exemplary embodiments, the material of the conductive layer 400 includes copper.

[0138] According to some exemplary embodiments, the material of the bonding layer 500 includes at least one of molybdenum, aluminum, copper, or an alloy of the aforementioned metals. For example, the bonding layer 500 may include a first sublayer and a second sublayer located on the side of the first sublayer away from the substrate 100. The material of the first sublayer may include a molybdenum alloy, and the material of the second sublayer may include copper.

[0139] According to some exemplary embodiments, referring to FIG7, considering that the uniformity of the film thickness of the conductive layer 400 formed by the addition electroplating process is relatively poor compared with the uniformity of the film thickness of the bonding layer 500 formed by the sputtering deposition process, in order to ensure the flatness of the surface of the first planarization layer PLN1 away from the substrate 100, the thickness of the first planarization layer PLN1 can be set to be slightly thicker. For example, along the direction perpendicular to the first surface 100a, the distance D3 between the surface of the first planarization layer PLN1 away from the substrate 100 and the surface of the conductive layer 400 away from the substrate 100 is greater than or equal to 1 micrometer.

[0140] According to some exemplary embodiments, referring to FIG7, the shape of the cross section of the conductive portion 410 along the direction perpendicular to the first surface 100a includes an inverted trapezoid, and the shape of the cross section of the power trace 420 along the direction perpendicular to the first surface 100a includes an inverted trapezoid.

[0141] The conductive portion 410 includes a first portion located within the fourth via VO4 and the fifth via VO5, and a second portion located on the side of the first portion away from the substrate 100. The second portion is located on the side of the third passivation layer PVX3 away from the substrate 100. The cross-sectional shape of the second portion is an inverted trapezoid. The area of ​​the surface of the second portion near the substrate 100 is smaller than the area of ​​the surface of the second portion away from the substrate 100.

[0142] The first power supply trace 421 is located on the side of the third passivation layer PVX3 away from the substrate 100, and the cross-sectional shape of the first power supply trace 421 is an inverted trapezoid.

[0143] The second power trace 422 includes a first portion located within the fourth via V04 and the fifth via V05, and a second portion located on the side of the first portion away from the substrate 100. The second portion is located on the side of the third passivation layer PVX3 away from the substrate 100, and the cross-sectional shape of the second portion is an inverted trapezoid.

[0144] According to some exemplary embodiments, referring to FIG7, the light-emitting device 310 can be a vertical LED. The light-emitting device 310 includes a first electrode 311, a light-emitting functional layer 312 located on the side of the first electrode 311 away from the substrate 100, and a second electrode 313 located on the side of the light-emitting functional layer 312 away from the substrate 100. The first electrode 311 and the first bonding pad 510 are electrically connected.

[0145] According to some exemplary embodiments, referring to FIG7, the portion of the pad connection portion 512 located within the first via VO1 forms a recessed structure 5121 that matches the shape of the first via VO1, the recessed structure 5121 being recessed toward the side closer to the substrate 100.

[0146] According to some exemplary embodiments, referring to FIG7, the display substrate further includes a support pillar layer 600, which is located on the side of the first planarization layer PLN1 away from the substrate 100. The support pillar layer 600 includes a plurality of support pillars PS spaced apart. The surface of the support pillars PS away from the substrate 100 is further away from the substrate 100 than the surface of the first bonding pad 510 away from the substrate 100, and the surface of the support pillars PS near the substrate 100 is further away from the substrate 100 than the surface of the conductive layer 400 away from the substrate 100. The function of the support pillars PS is to support the carrier substrate in the light-emitting device during the transfer bonding process. Therefore, the height difference between the surface of the support pillars PS away from the substrate 100 and the surface of the pad body portion 511 away from the substrate 100 needs to be within a specific range.

[0147] Compared to the structure shown in Figure 4, since the surface of the support pillar PS near the substrate 100 is set to be further away from the substrate 100 than the surface of the conductive layer 400 away from the substrate 100, the height of the support pillar PS in the direction perpendicular to the first surface 100a can be greatly reduced. This can effectively avoid the problem of residual parts forming at the first via V01 during the formation of the support pillar layer 600, which would affect the poor connection between the conductive layer 400 and the driving circuit layer 200.

[0148] According to some exemplary embodiments, referring to FIG7, the display substrate further includes a first passivation layer PVX1 located between the first planarization layer PLN1 and the bonding layer 500. The first passivation layer PVX1 includes a second via VO2. The first bonding pad 510 is electrically connected to one of the conductive portion 410 and the power trace 420 through the second via VO2 and the first via VO1.

[0149] The support pillar PS is located between the first planarization layer PLN1 and the first passivation layer PVX1. That is, during the fabrication process of the display substrate, the support pillar PS is formed after the first planarization layer PLN1 is formed, and the first passivation layer PVX1 is formed after the support pillar PS is formed.

[0150] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0151] According to some exemplary embodiments, referring to FIG10, the display substrate further includes a first passivation layer PVX1 located between the first planarization layer PLN1 and the bonding layer 500. The first passivation layer PVX1 includes a second via VO2. The first bonding pad 510 is electrically connected to one of the conductive portion 410 and the power trace 420 through the second via VO2 and the first via VO1.

[0152] The support pillar PS is located on the side of the first passivation layer PVX1 away from the first planarization layer PLN1. That is, during the fabrication of the display substrate, the first passivation layer PVX1 is formed after the first planarization layer PLN1, the bonding layer 500 is formed after the first passivation layer PVX1, and the support pillar PS is formed after the bonding layer 500. In other words, the support pillar layer 600 is formed after the first bonding pad 510 is electrically connected to the conductive layer 400 through the first via VO1 and the second via VO2. Therefore, even if there are residual problems at the first via VO1 during the formation of the support pillar layer 600, it will not affect the connection between the first bonding pad 510 and the conductive layer 400.

[0153] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0154] According to some exemplary embodiments, referring to FIG11, the portion of the pad connection portion 512 located within the first via VO1 includes a recessed structure 5121. The recessed structure 5121 is recessed towards the side close to the substrate 100. The support pillar layer 600 also includes a filling portion 610 located within the recessed structure 5121. Both the filling portion 610 and the support pillar PS are located within the support pillar layer 600. That is, while forming the support pillar PS, the filling portion 610 is formed by filling the recessed structure 5121 within the first via VO1 of the pad connection portion 512. This allows for the display of the substrate surface flatness during the transfer bonding process of the light-emitting device 310, thereby further improving the bonding yield.

[0155] According to some exemplary embodiments, referring to FIG11, at least one filling portion 610 is flush with the surface of the substrate 100 away from the pad body portion 511 away from the substrate 100; and / or, at least one filling portion 610 is flush with the surface of the first passivation layer PVX1 away from the substrate 100; and / or, a virtual extension surface of the surface of at least one filling portion 610 away from the substrate 100 is located between the surface of the pad body portion 511 away from the substrate 100 and the surface of the first passivation layer PVX1 away from the substrate 100.

[0156] Figures 12A-12B schematically illustrate the formation principle of the support pillar layer in a display substrate according to some embodiments of the present disclosure.

[0157] Referring to FIG12A, a photoresist liquid film layer 600' is formed by coating the bonding layer 500 on the side away from the substrate 100.

[0158] Referring to Figure 12B, a mask with a specific pattern is placed above the photoresist liquid film layer 600', and the photoresist liquid film layer 600' is exposed under the cover of the mask. After the exposure is completed, a development process and a curing process are performed to form the support pillar layer 600 shown in Figure 11.

[0159] For example, if the photoresist in the photoresist liquid film layer 600' is a positive photoresist, then the mask can transmit light in the area corresponding to the support pillar PS and the filling part 610, while other areas are opaque. The light transmittance of the mask in the area corresponding to the support pillar PS and the area corresponding to the filling part 610 can be adjusted respectively, so that support pillar PS and filling part 610 with a specific height can be formed, that is, the support pillar layer 600 shown in FIG11 is formed.

[0160] According to some exemplary embodiments, referring to FIG7, FIG10 or FIG11, the display substrate further includes a second passivation layer PVX2 located between the conductive layer 400 and the first planarization layer PLN1. The second passivation layer PVX2 includes a third via VO3. The first bonding pad 510 is electrically connected to one of the conductive portion 410 and the power trace 420 through the second via VO2, the first via VO1 and the third via VO3.

[0161] The material of the second passivation layer PVX2 includes an inorganic insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second passivation layer PVX2 is used to isolate the conductive layer 400 and the first planarization layer PLN1, preventing the first planarization layer PLN1 from contacting the conductive layer 400 and causing oxidation of the conductive layer 400.

[0162] Figure 13 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure. Figure 14 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure. Figure 15 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0163] According to some exemplary embodiments, referring to Figures 13, 14 or 15, the conductive layer 400 and the first planarization layer PLN1 are in direct contact, that is, the second passivation layer between the conductive layer 400 and the first planarization layer PLN1 is eliminated, thereby reducing one film deposition process and one patterning process, which helps to simplify the preparation process of the display substrate and reduce the manufacturing cost of the display substrate.

[0164] It should be noted that the structure of the display substrate shown in Figure 13 is roughly the same as that of the display substrate shown in Figure 7, the only difference being that the second passivation layer PVX2 is omitted in the display substrate shown in Figure 13. The structure of the display substrate shown in Figure 14 is roughly the same as that of the display substrate shown in Figure 10, the only difference being that the second passivation layer PVX2 is omitted in the display substrate shown in Figure 14. The structure of the display substrate shown in Figure 15 is roughly the same as that of the display substrate shown in Figure 11, the only difference being that the second passivation layer PVX2 is omitted in the display substrate shown in Figure 15.

[0165] According to some exemplary embodiments, referring to Figures 13, 14, or 15, the material of the first planarization layer PLN1 can be selected to avoid oxidation of the conductive layer 400 due to the removal of the second passivation layer PVX2. For example, the material of the first planarization layer PLN1 may include polysilazane.

[0166] According to some exemplary embodiments, referring to FIG14, the first via VO1 of the first planarization layer PLN1 and the second via VO2 of the first passivation layer PVX1 are formed in two patterning processes. The first via VO1 of the first planarization layer PLN1 is formed by an exposure process and a development process in one patterning process, and the second via VO2 of the first passivation layer PVX1 is formed by etching in another patterning process. In this way, by controlling the two patterning processes separately, the orthographic projection of the second via VO2 on the substrate 100 is located within the orthographic projection of the first via VO1 on the substrate 100. The first planarization layer PLN1 includes a first sidewall CB1 located at the first via VO1, and the first passivation layer PVX1 covers the first sidewall CB1. The portion of the first passivation layer PVX1 located on the first sidewall CB1 isolates the first planarization layer PLN1 and the first bonding pad 510, avoiding the problem of the first planarization layer PLN1 oxidizing the first bonding pad 510.

[0167] According to some exemplary embodiments, referring to FIG14, the second via VO2 in the first passivation layer PVX1 can be etched by the following etching steps:

[0168] First step etching: source power 2500w, bias power 900w, process gases are CF4 and O2, CF4 flow rate is 400sccm, O2 flow rate is 80sccm, etching time is 0-50s.

[0169] The second etching step: source power 1500w, bias power 800w, process gases are CHF3, Ar and H2, CHF3 flow rate is 200sccm, Ar flow rate is 200sccm, H2 flow rate is 25sccm, etching time is 0-100s.

[0170] Figure 16 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0171] According to some exemplary embodiments, referring to FIG16, the first via V01 of the first planarization layer PLN1 and the second via V02 of the first passivation layer PVX1 can be formed by a single patterning process, that is, the first via V01 of the first planarization layer PLN1 and the second via V02 of the first passivation layer PVX1 are etched together in the same patterning process. This can further save a patterning process, thereby simplifying the fabrication process of the display substrate and reducing the manufacturing cost of the display substrate.

[0172] The first planarization layer PLN1 includes a first sidewall CB1 located at the first via VO1, and the first passivation layer PVX1 includes a second sidewall CB2 located at the second via VO2. Since the first via VO1 of the first planarization layer PLN1 and the second via VO2 of the first passivation layer PVX1 are formed by a patterning process, the second sidewall CB2 is located on the side of the first sidewall CB1 away from the substrate 100. The first passivation layer PVX1 does not cover the first sidewall CB1 of the first planarization layer PLN1. The first bonding pad 510 covers at least a portion of the first sidewall CB1 and covers at least a portion of the second sidewall CB2.

[0173] Furthermore, since the first bonding pad 510 is in contact with the first planarization layer PLN1 at the first sidewall CB1, the material of the first planarization layer PLN1 can be selected as a material that is not likely to cause oxidation of the first bonding pad 510.

[0174] According to some exemplary embodiments, referring to FIG16, the first via V01 of the first planarization layer PLN1 and the second via V02 of the first passivation layer PVX1 can be etched by the following etching steps:

[0175] First step etching: source power 2500w, bias power 900w, process gases are CF4 and O2, CF4 flow rate is 400sccm, O2 flow rate is 40sccm, etching time is 0-70s.

[0176] The second etching step: source power 3000w, bias power 1000w, process gases are O2 and CHF3, O2 flow rate is 500sccm, CHF3 flow rate is 50sccm, and etching time is 0-270s.

[0177] According to some exemplary embodiments, referring to FIG7, the first via V01 of the first planarization layer PLN1, the second via V02 of the first passivation layer PVX1, and the third via V03 of the second passivation layer PVX2 are formed in two patterning processes. The first via V01 of the first planarization layer PLN1 is formed in one patterning process by exposure and development processes. The second via V02 in the first passivation layer PVX1 and the third via V03 in the second passivation layer PVX2 are etched together in another patterning process.

[0178] In this way, by controlling the two patterning processes separately, the orthographic projection of the second via VO2 on the substrate 100 is located within the orthographic projection of the first via VO1 on the substrate 100, and the orthographic projection of the third via VO3 on the substrate 100 is located within the orthographic projection of the first via VO1 on the substrate 100. The first planarization layer PLN1 includes a first sidewall CB1 located at the first via VO1, and the first passivation layer PVX1 covers the first sidewall CB1. The first passivation layer PVX1 includes a second sidewall CB2 located at the second via VO2, and the second passivation layer PVX2 includes a third sidewall CB3 located at the third via VO3, with the second sidewall CB2 and the third sidewall CB3 connected. The portion of the first passivation layer PVX1 located on the first sidewall CB1 isolates the first planarization layer PLN1 and the first bonding pad 510, preventing the first planarization layer PLN1 from oxidizing the first bonding pad 510.

[0179] According to some exemplary embodiments, referring to FIG7, the second via VO2 in the first passivation layer PVX1 and the third via VO3 in the second passivation layer PVX2 can be obtained by etching the following etching steps:

[0180] First step etching: source power 2500w, bias power 900w, process gases are CF4 and O2, CF4 flow rate is 400sccm, O2 flow rate is 80sccm, etching time is 0-50s.

[0181] The second etching step: source power 1500w, bias power 800w, process gases are CHF3, Ar and H2, CHF3 flow rate is 200sccm, Ar flow rate is 200sccm, H2 flow rate is 25sccm, etching time is 0-100s.

[0182] Figure 17 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0183] According to some exemplary embodiments, referring to FIG17, the first via V01 of the first planarization layer PLN1, the second via V02 of the first passivation layer PVX1, and the third via V03 of the second passivation layer PVX2 can be formed in a single patterning process. That is, the first via V01 of the first planarization layer PLN1, the second via V02 of the first passivation layer PVX1, and the third via V03 of the second passivation layer PVX2 are etched together in a single patterning process. This can further save one patterning process, thereby simplifying the fabrication process of the display substrate and reducing the manufacturing cost of the display substrate.

[0184] The first planarization layer PLN1 includes a first sidewall CB1 located at the first via VO1, the first passivation layer PVX1 includes a second sidewall CB2 located at the second via VO2, and the second passivation layer PVX2 includes a third sidewall CB3 located at the third via VO3. Since the first via VO1 of the first planarization layer PLN1, the second via VO2 of the first passivation layer PVX1, and the third via VO3 of the second passivation layer PVX2 are etched together in a single patterning process, the second sidewall CB2 is located on the side of the first sidewall CB1 away from the substrate 100, and the first sidewall CB1 is located on the side of the third sidewall CB3 away from the substrate 100. The first passivation layer PVX1 does not cover the first sidewall CB1 of the first planarization layer PLN1. The first bonding pad 510 covers at least a portion of the first sidewall CB1, covers at least a portion of the second sidewall CB2, and covers at least a portion of the third sidewall CB3.

[0185] According to some exemplary embodiments, referring to FIG17, the first via V01 of the first planarization layer PLN1, the second via V02 of the first passivation layer PVX1, and the third via V03 of the second passivation layer PVX2 can be obtained by etching the following etching steps:

[0186] First step etching: source power 2500w, bias power 900w, process gases are CF4 and O2, CF4 flow rate is 400sccm, O2 flow rate is 40sccm, etching time is 0-70s.

[0187] The second etching step: source power 3000w, bias power 1000w, process gases are O2 and CHF3, O2 flow rate is 500sccm, CHF3 flow rate is 50sccm, etching time is 0-270s.

[0188] The third step of etching: source power 1500w, bias power 800w, process gases are CHF3 and Ar, CHF3 flow rate is 200sccm, Ar flow rate is 200sccm, etching time is 0-50s.

[0189] Figure 18 schematically illustrates a flowchart of a method for fabricating a display substrate according to some embodiments of the present disclosure.

[0190] At least some embodiments of this disclosure also provide a method for preparing a display substrate. Referring to FIG18, the preparation method includes the following steps S10-S50.

[0191] In step S10, a driving circuit layer is formed on the substrate.

[0192] In step S20, a conductive layer is formed on the side of the driving circuit layer away from the substrate. The conductive layer includes multiple conductive parts and multiple power lines. The conductive parts are electrically connected to the driving circuit layer, and at least one power line is electrically connected to the driving circuit layer.

[0193] In step S30, a first planarization layer is formed on the side of the driving circuit layer away from the substrate. The material of the first planarization layer includes an organic material. The first planarization layer includes a plurality of first vias, each of which exposes a portion of a plurality of conductive parts. In addition, each of the plurality of first vias exposes a portion of a plurality of power lines.

[0194] In step S40, a bonding layer is formed on the side of the conductive layer away from the substrate. The bonding layer includes a plurality of first bonding pads spaced apart. Each first bonding pad includes a pad body portion and a pad connection portion connected as one unit. The pad body portion is located on the surface of the first planarization layer away from the substrate. The pad connection portion is directly connected to one of the conductive portion and the power trace through a first via. The orthographic projection of the pad body portion on the substrate is located within the orthographic projection of the first planarization layer on the substrate. The orthographic projection of the pad connection portion on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

[0195] In step S50, a light-emitting device layer is formed on the side of the bonding layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices spaced apart, and the light-emitting devices are electrically connected to the pad body.

[0196] Figures 19A-19N schematically illustrate flowcharts of methods for fabricating a display substrate according to some embodiments of the present disclosure.

[0197] Referring to FIG19A, a driving circuit layer 200 is formed on the substrate 100. The cross-sectional structure of the driving circuit layer 200 can be referred to FIG8. The side of the driving circuit layer 200 away from the substrate 100 includes a source / drain metal layer SD. The side of the source / drain metal layer SD away from the substrate 100 includes a second planarization layer PLN2. The second planarization layer PLN2 includes a fourth via VO4. The fourth via VO4 exposes a portion of the source / drain metal layer SD.

[0198] Referring to FIG19B, a third passivation layer PVX3 is formed on the side of the second planarization layer PLN2 away from the substrate 100. The third passivation layer PVX3 includes a fifth via VO5, and the fifth via VO5 and the fourth via VO4 are connected.

[0199] It should be noted that the fifth via V05 of the third passivation layer PVX3 and the fourth via V04 of the second planarization layer PLN2 can be formed by two separate patterning processes, or they can be etched together in one patterning process.

[0200] Referring to FIG19C, a conductive layer 400 is formed on the side of the third passivation layer PVX3 away from the substrate 100. The conductive layer 400 includes a plurality of conductive portions 410 and a plurality of power lines 420. The conductive portions 410 are electrically connected to the source / drain metal layer SD through the fifth via VO5 and the fourth via VO4. At least one power line 420 is electrically connected to the source / drain metal layer SD through the fifth via VO5 and the fourth via VO4.

[0201] For example, the conductive layer 400 can be formed by an addition electroplating process, the steps of which include:

[0202] Referring to FIG19D, a first photoresist layer PR1 is formed on the side of the third passivation layer PVX3 away from the substrate 100. The first photoresist layer PR1 includes a plurality of cutout portions PR1a, and a portion of the cutout portions PR1a exposes the fifth via V05 and the fourth via V04.

[0203] Referring to Figure 19E, multiple conductive parts 410 and multiple power lines 420 are formed in multiple cutouts PR1a using an additive electroplating process.

[0204] Referring to Figures 19E and 19C, the first photoresist layer PR1 is peeled off to obtain the conductive layer 400.

[0205] Referring to FIG19F, a second passivation film PVX2a is formed on the side of the conductive layer 400 away from the substrate 100.

[0206] Referring to FIG19G, a first planarization layer PLN1 is formed on the side of the second passivation film PVX2a away from the substrate 100. The first planarization layer PLN1 includes a first via VO1. The orthographic projection of the first via VO1 on the substrate 100 is located within the orthographic projection of the conductive layer 400 on the substrate 100.

[0207] Referring to FIG19H, a support pillar layer 600 is formed on the side of the first planarization layer PLN1 away from the substrate 100, and the support pillar layer 600 includes a plurality of support pillars PS.

[0208] Referring to FIG19I, a first passivation film PVX1a is formed on the side of the support pillar layer 600 and the first planarization layer PLN1 away from the substrate 100.

[0209] Referring to Figures 19I and 19J, in a single patterning process, the first passivation film PVX1a and the second passivation film PVX2a are etched together to form the first passivation layer PVX1 and the second passivation layer PVX2. The first passivation layer PVX1 includes a second via VO2, and the second passivation layer PVX2 includes a third via VO3.

[0210] Referring to FIG19K, a bonding layer 500 is formed on the side of the first passivation layer PVX1 away from the substrate 100. The bonding layer 500 includes a plurality of first bonding pads 510 spaced apart. The first bonding pads 510 are electrically connected to one of the conductive portion 410 and the power trace 420 through a first via VO1, a second via VO2 and a third via VO3. The first bonding pad 510 includes a pad body portion 511 and a pad connection portion 512 connected as one piece. The pad body portion 511 is located on the surface of the first planarization layer PLN1 away from the substrate 100. The pad connection portion 512 is directly connected to one of the conductive portion 410 and the power trace 420 through the first via VO1, the second via VO2 and the third via VO3. The orthographic projection of the pad body portion 511 on the substrate 100 is located within the orthographic projection of the first planarization layer PLN1 on the substrate 100. The orthographic projection of the pad connection portion 512 on the substrate 100 at least partially overlaps with the orthographic projection of the first via VO1 on the substrate 100.

[0211] For example, the steps of forming the bonding layer 500 include:

[0212] Referring to Figure 19L, a bonded conductive thin film 500' is formed on the side of the first passivation layer PVX1 away from the substrate 100 by a sputtering deposition process.

[0213] Referring to FIG19M, a second photoresist layer PR2 is formed on the side of the bonding conductive film 500' away from the substrate 100. Under the shielding of the second photoresist layer PR2, the bonding conductive film 500' is etched. After etching is completed, the second photoresist layer PR2 is peeled off, thus forming the bonding layer 500 shown in FIG19K.

[0214] Referring to FIG19N, a plurality of light-emitting devices 310 are transferred and bonded to a plurality of first bonding pads 510 on the side away from the substrate 100. The side of the light-emitting device 310 close to the substrate 100 has a second bonding pad PAD2, and the second bonding pad PAD2 and the first bonding pad 510 are bonded together.

[0215] At least some embodiments of this disclosure also provide a display device. The display device includes a display substrate as described above or a display panel as described above.

[0216] The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0217] It should be understood that the display panel and display device according to the embodiments of this disclosure have all the features and advantages of the display substrate described above, as detailed in the above description, which will not be repeated here. Although some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; The driving circuit layer is located on the substrate. A conductive layer is located on the side of the driving circuit layer away from the substrate. The conductive layer includes multiple conductive parts and multiple power lines. The conductive parts are electrically connected to the driving circuit layer, and at least one power line is electrically connected to the driving circuit layer. A first planarization layer is located on the side of the driving circuit layer away from the substrate. The first planarization layer includes a plurality of first vias, each of which exposes a portion of a plurality of conductive portions. Additionally, each of the first vias exposes a portion of a plurality of power traces. A bonding layer, located on the side of the conductive layer away from the substrate, includes a plurality of spaced-apart first bonding pads, the first bonding pads being electrically connected to one of the conductive portion and the power trace via the first via; and A light-emitting device layer is located on the side of the bonding layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices spaced apart, and the light-emitting devices are electrically connected to the first bonding pads. The material of the first planarization layer includes organic materials; The first bonding pad includes a pad body portion and a pad connection portion integrally connected. The pad body portion is located on the surface of the first planarization layer away from the substrate. The pad connection portion is directly connected to one of the conductive portion and the power trace through the first via. The orthographic projection of the pad body portion on the substrate is located within the orthographic projection of the first planarization layer on the substrate. The orthographic projection of the pad connection portion on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate. The light-emitting device is electrically connected to the main body of the pad.

2. The display substrate according to claim 1, wherein, The substrate includes a first surface facing the driving circuit layer, and the thickness of the bonding layer is less than the thickness of the conductive layer along a direction perpendicular to the first surface.

3. The display substrate according to claim 2, wherein, The thickness of the bonding layer is less than 2 micrometers; and / or, The thickness of the conductive layer is greater than or equal to 2 micrometers.

4. The display substrate according to any one of claims 1-3, wherein, The portion of the pad connection located within the first via includes a recessed structure, which is recessed toward the side closer to the substrate.

5. The display substrate according to any one of claims 1-4, wherein, The substrate includes a first surface facing the driving circuit layer, and the conductive portion has an inverted trapezoidal shape in its cross-section along a direction perpendicular to the first surface; and / or, The shape of the cross-section of the power trace along the direction perpendicular to the first surface includes an inverted trapezoid.

6. The display substrate according to any one of claims 1-5, wherein, The display substrate further includes a support pillar layer, which is located on the side of the first planarization layer away from the substrate. The support pillar layer includes a plurality of support pillars spaced apart. The surface of the support pillar furthest from the substrate is further from the substrate than the surface of the first bonding pad furthest from the substrate, and the surface of the support pillar closest to the substrate is further from the substrate than the surface of the conductive layer furthest from the substrate.

7. The display substrate according to claim 6, wherein, The display substrate further includes a first passivation layer located between the first planarization layer and the bonding layer. The first passivation layer includes a second via. The first bonding pad is electrically connected to one of the conductive portion and the power trace through the second via and the first via. as well as The support column is located between the first planarization layer and the first passivation layer.

8. The display substrate according to claim 6, wherein, The display substrate further includes a first passivation layer located between the first planarization layer and the bonding layer. The first passivation layer includes a second via. The first bonding pad is electrically connected to one of the conductive portion and the power trace through the second via and the first via. as well as The support column is located on the side of the first passivation layer away from the first planarization layer.

9. The display substrate according to claim 8, wherein, The portion of the pad connection located within the first via includes a recessed structure, which is recessed toward the side closer to the substrate. as well as The support column layer also includes a filling portion, which is located within the recessed structure.

10. The display substrate according to claim 9, wherein, At least one of the filling portions is flush with the surface of the substrate away from the substrate and the surface of the pad body portion is flush with the surface of the substrate away from the substrate; and / or, At least one of the filling portions is flush with the surface of the substrate away from the substrate and the surface of the first passivation layer away from the substrate; and / or, At least one of the filling portions has a virtual extension surface away from the surface of the substrate located between the surface of the pad body portion away from the substrate and the surface of the first passivation layer away from the substrate.

11. The display substrate according to any one of claims 7-10, wherein, The display substrate also includes a second passivation layer located between the conductive layer and the first planarization layer; as well as The second passivation layer includes a third via, through which the first bonding pad is electrically connected to one of the conductive portion and the power trace.

12. The display substrate according to any one of claims 7-10, wherein, The conductive layer and the first planarization layer are in direct contact.

13. The display substrate according to claim 12, wherein, The material of the first planarization layer includes polysilazane.

14. The display substrate according to claim 12 or 13, wherein, The orthographic projection of the second via on the substrate lies within the orthographic projection of the first via on the substrate; and The first planarization layer includes a first sidewall located at the first via, and the first passivation layer covers the first sidewall.

15. The display substrate according to claim 12 or 13, wherein, The first planarization layer includes a first sidewall located at the first via, and the first passivation layer includes a second sidewall located at the second via, the second sidewall being located on the side of the first sidewall away from the substrate. as well as The first bonding pad covers at least a portion of the first sidewall, and the first bonding pad covers at least a portion of the second sidewall.

16. The display substrate according to claim 11, wherein, The orthographic projection of the second via on the substrate is located within the orthographic projection of the first via on the substrate, and the orthographic projection of the third via on the substrate is located within the orthographic projection of the first via on the substrate. as well as The first planarization layer includes a first sidewall located at the first via, and the first passivation layer covers the first sidewall; The first passivation layer includes a second sidewall located at the second via, and the second passivation layer includes a third sidewall located at the third via, wherein the second sidewall and the third sidewall are connected.

17. The display substrate according to claim 11, wherein, The first planarization layer includes a first sidewall located at the first via, the first passivation layer includes a second sidewall located at the second via, the second passivation layer includes a third sidewall located at the third via, the second sidewall is located on the side of the first sidewall away from the substrate, and the first sidewall is located on the side of the third sidewall away from the substrate. as well as The first bonding pad covers at least a portion of the first sidewall, the first bonding pad covers at least a portion of the second sidewall, and the first bonding pad covers at least a portion of the third sidewall.

18. The display substrate according to any one of claims 1-17, wherein, The light-emitting device includes a first electrode, a light-emitting functional layer located on the side of the first electrode away from the substrate, and a second electrode located on the side of the light-emitting functional layer away from the substrate; and The first electrode and the first bonding pad are electrically connected.

19. The display substrate according to any one of claims 1-17, wherein, The substrate includes a first surface facing the driving circuit layer, and the distance between the surface of the first planarization layer away from the substrate and the surface of the conductive layer away from the substrate is greater than or equal to 1 micrometer along a direction perpendicular to the first surface.

20. The display substrate according to any one of claims 1-17, wherein, The substrate includes a first surface facing the driving circuit layer. In two adjacent bonding pads, the distance between the surface of one pad body away from the substrate and the first surface in a direction perpendicular to the first surface is a first distance, and the distance between the surface of the other pad body away from the substrate and the first surface in a direction perpendicular to the first surface is a second distance. The difference between the first distance and the second distance is less than or equal to 0.2 μm.

21. A method for preparing a display substrate, wherein, The preparation method includes: A driving circuit layer is formed on the substrate. A conductive layer is formed on the side of the driving circuit layer away from the substrate. The conductive layer includes a plurality of conductive parts and a plurality of power lines. The conductive parts are electrically connected to the driving circuit layer, and at least one of the power lines is electrically connected to the driving circuit layer. A first planarization layer is formed on the side of the driving circuit layer away from the substrate. The material of the first planarization layer includes an organic material. The first planarization layer includes a plurality of first vias, each of which exposes a portion of a plurality of conductive portions. In addition, each of the plurality of first vias exposes a portion of a plurality of power lines. A bonding layer is formed on the side of the conductive layer away from the substrate. The bonding layer includes a plurality of first bonding pads spaced apart. Each first bonding pad includes a pad body portion and a pad connection portion integrally connected. The pad body portion is located on the surface of the first planarization layer away from the substrate. The pad connection portion is directly connected to one of the conductive portion and the power trace through a first via. The orthographic projection of the pad body portion on the substrate is located within the orthographic projection of the first planarization layer on the substrate. The orthographic projection of the pad connection portion on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate. A light-emitting device layer is formed on the side of the bonding layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices spaced apart, and the light-emitting devices are electrically connected to the pad body portion.

22. The preparation method according to claim 21, wherein, The steps for forming the conductive layer include: A photoresist layer is formed on the side of the driving circuit layer away from the substrate, the photoresist layer including multiple cutouts; and Multiple conductive parts and multiple power lines are formed within the multiple cutouts using an additive electroplating process.

23. The preparation method according to claim 21, wherein, The steps for forming the bonding layer include: A bonded conductive thin film is formed on the side of the conductive layer away from the substrate by a sputtering deposition process; and The bonding conductive film is patterned using a patterning process to obtain multiple first bonding pads.

24. A display device, wherein, The display device includes a display substrate according to any one of claims 1-20.

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