Pixel driving circuit, display apparatus, and driving method

Abstract

Provided are a pixel driving circuit, a display apparatus, and a driving method. The pixel driving circuit comprises: a driving transistor (DTFT), bias sub-circuits (10, 101-104), a connection control sub-circuit (20), a first capacitor (C1), a first light-emitting control sub-circuit (30), and a light-emitting device (LED). The connection control sub-circuit (20), in response to a signal of a connection control terminal (GateN7), connects a first node (N1) to a set terminal of the driving transistor (DTFT). A first terminal of the first capacitor (C1) is coupled to a control terminal of the driving transistor (DTFT). A second terminal of the first capacitor (C1) is coupled to the first node (N1). The first light-emitting control sub-circuit (30) provides a signal of a first power supply terminal (VDD) to a second terminal of the driving transistor (DTFT). The bias sub-circuits (10, 101-104) couple signals of bias signal terminals (COBS1, COBS2) to at least one of the first node (N1), the control terminal of the driving transistor (DTFT), and the set terminal of the driving transistor (DTFT). The process of biasing the driving transistor (DTFT) can improve the properties of the driving transistor (DTFT), thereby improving the display performance.

Description

A pixel driving circuit, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and provides a pixel driving circuit, a display device, and a driving method. Background Technology

[0002] In related technologies, when writing data voltage, the control terminal of the driving transistor in the pixel driving circuit will cause the threshold voltage of the driving transistor to have an abnormal negative bias. Especially when the pixel driving circuit is used for low-frequency (e.g., 1Hz) display, since the transistor controlling the writing of data voltage is in a normally closed state, the control terminal of the driving transistor will remain at the same fixed potential for a long time. In this case, the threshold voltage of the driving transistor will have a large negative bias, resulting in display problems such as image retention and flickering. Summary of the Invention

[0003] This disclosure provides a pixel driving circuit, a display device, and a driving method to correct the negative bias voltage of the threshold voltage of the driving transistor, thereby improving the display effect.

[0004] The specific technical solution provided in this disclosure is as follows:

[0005] In a first aspect, embodiments of this disclosure provide a pixel driving circuit, including: a driving transistor, a bias sub-circuit, a conduction control sub-circuit, a first capacitor, a first light emission control sub-circuit, and a light emission device;

[0006] The first terminal of the driving transistor is coupled to the light-emitting device;

[0007] The turn-on control subcircuit is coupled between the first node and the setting terminal of the driving transistor, and is configured to turn on the first node and the setting terminal of the driving transistor in response to a signal from the turn-on control terminal, wherein the setting terminal is the first terminal or the second terminal of the driving transistor.

[0008] The first light-emitting control sub-circuit is coupled between the first power supply terminal and the second terminal of the driving transistor, and is configured to provide the signal of the first power supply terminal to the second terminal of the driving transistor in response to the signal of the first light-emitting control terminal.

[0009] The first terminal of the first capacitor is coupled to the control terminal of the driving transistor, and the second terminal of the first capacitor is coupled to the first node. It is configured to store the data voltage and the threshold voltage of the driving transistor when the signal of the second light-emitting control terminal is valid.

[0010] The bias sub-circuit is coupled to the bias signal terminal and is also coupled to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor. It is configured to couple the signal of the bias signal terminal to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor.

[0011] In some possible embodiments, the bias sub-circuit is coupled to the first node, the bias signal terminal includes a first bias signal terminal, and the bias sub-circuit includes a second capacitor;

[0012] The first terminal of the second capacitor is coupled to the first bias signal terminal, and the second terminal of the second capacitor is coupled to the first node.

[0013] In some possible embodiments, the bias sub-circuit is coupled to the control terminal of the driving transistor, the bias signal terminal includes a first bias signal terminal, and the bias sub-circuit includes a third capacitor;

[0014] The first terminal of the third capacitor is coupled to the first bias signal terminal, and the second terminal of the third capacitor is coupled to the control terminal of the driving transistor.

[0015] In some possible embodiments, the effective signal at the first bias signal terminal is a negative voltage.

[0016] In some possible embodiments, the bias sub-circuit is coupled to the setting terminal of the driving transistor, the setting terminal being the first terminal of the driving transistor, the bias signal terminal including the second bias signal terminal, and the bias sub-circuit including: a fourth capacitor;

[0017] The first terminal of the fourth capacitor is coupled to the second bias signal terminal, and the second terminal of the fourth capacitor is coupled to the first terminal of the driving transistor.

[0018] In some possible embodiments, the bias sub-circuit is coupled to the setting terminal of the driving transistor, the setting terminal being the second terminal of the driving transistor, the bias signal terminal including the second bias signal terminal, and the bias sub-circuit including: a fifth capacitor;

[0019] The first terminal of the fifth capacitor is coupled to the second bias signal terminal, and the second terminal of the fifth capacitor is coupled to the second terminal of the driving transistor.

[0020] In some possible embodiments, the effective signal at the second bias signal terminal is a positive voltage.

[0021] In some possible embodiments, the effective timing of the bias signal terminal is activated after the effective timing of the conduction control signal terminates; and / or

[0022] The effective time of the bias signal terminal is activated after the effective time of the first reset control terminal signal ends.

[0023] In some possible embodiments, the turn-on control subcircuit includes: a first switching transistor;

[0024] The control terminal of the first switching transistor is coupled to the conduction control terminal, the first terminal of the first switching transistor is coupled to the first node, and the second terminal of the first switching transistor is coupled to the first terminal of the driving transistor.

[0025] In some possible embodiments, the turn-on control sub-circuit includes: a second switching transistor;

[0026] The control terminal of the second switching transistor is coupled to the conduction control terminal, the first terminal of the second switching transistor is coupled to the first node, and the second terminal of the second switching transistor is coupled to the second terminal of the driving transistor.

[0027] In some possible embodiments, the first light-emitting control sub-circuit includes: a third switching transistor;

[0028] The control terminal of the third switching transistor is coupled to the first light-emitting control terminal, the first terminal of the third switching transistor is coupled to the first power supply terminal, and the second terminal of the third switching transistor is coupled to the second terminal of the driving transistor.

[0029] In some possible embodiments, a first reset circuit is also included, which is coupled between the first initialization signal terminal and the control terminal of the driving transistor;

[0030] The first reset sub-circuit is configured to provide a signal from the first initialization signal terminal to the control terminal of the driving transistor in response to a signal from the first reset control terminal.

[0031] In some possible embodiments, the first reset circuit includes: a fourth switching transistor;

[0032] The control terminal of the fourth switching transistor is coupled to the first reset control terminal, the first terminal of the fourth switching transistor is coupled to the first initialization signal terminal, and the second terminal of the fourth switching transistor is coupled to the control terminal of the driving transistor.

[0033] In some possible embodiments, a data writing sub-circuit is also included, which is coupled between the setting terminal and the data signal terminal of the driving transistor.

[0034] The data writing sub-circuit is configured to provide the data signal terminal to the setting terminal of the driving transistor in response to the signal at the scan signal terminal.

[0035] In some possible embodiments, the data writing sub-circuit includes: a fifth switching transistor;

[0036] The control terminal of the fifth switching transistor is coupled to the scan signal terminal, the first terminal of the fifth switching transistor is coupled to the first terminal of the drive transistor, and the second terminal of the fifth switching transistor is coupled to the data signal terminal.

[0037] In some possible embodiments, the data writing sub-circuit includes: a sixth switching transistor;

[0038] The control terminal of the sixth switching transistor is coupled to the scan signal terminal, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the data signal terminal.

[0039] In some possible embodiments, a second light-emitting control sub-circuit is further included, which is coupled between the first terminal of the driving transistor and the anode of the light-emitting device;

[0040] The second light-emitting control sub-circuit is configured to, in response to a signal from the second light-emitting control terminal, connect the first terminal of the driving transistor to the anode of the light-emitting device.

[0041] In some possible embodiments, the second light-emitting control sub-circuit includes: a seventh switching transistor;

[0042] The control terminal of the seventh switching transistor is coupled to the second light-emitting control terminal, the first terminal of the seventh switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the anode of the light-emitting device.

[0043] In some possible embodiments, a second reset circuit is also included, which is coupled between the anode of the light-emitting device and the second initialization signal terminal;

[0044] The second reset sub-circuit is configured to provide a signal from the second initialization signal terminal to the anode of the light-emitting device in response to a signal from the second reset control terminal.

[0045] In some possible embodiments, the second reset circuit includes: an eighth switching transistor;

[0046] The control terminal of the eighth switching transistor is coupled to the second reset control terminal, the first terminal of the eighth switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the eighth switching transistor is coupled to the second initialization signal terminal.

[0047] In some possible embodiments, a third reset circuit is also included, which is coupled between the setting terminal of the driving transistor and the third initialization signal terminal, wherein the signal of the third initialization signal terminal is a negative voltage.

[0048] The third reset sub-circuit is configured to provide the signal from the third initialization signal terminal to the setting terminal of the driving transistor in response to the signal from the third reset control terminal.

[0049] In some possible embodiments, the third reset circuit includes: a ninth switching transistor;

[0050] The control terminal of the ninth switching transistor is coupled to the third reset control terminal, the first terminal of the ninth switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the ninth switching transistor is coupled to the third initialization signal terminal.

[0051] In some possible embodiments, the third reset circuit includes: a tenth switching transistor;

[0052] The control terminal of the tenth switching transistor is coupled to the third reset control terminal, the first terminal of the tenth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the third initialization signal terminal.

[0053] In some possible embodiments, a sixth capacitor is also included;

[0054] The first terminal of the sixth capacitor is coupled to the first node, and the second terminal of the sixth capacitor is coupled to the first power supply terminal.

[0055] In some possible embodiments, a seventh capacitor is also included;

[0056] The first terminal of the seventh capacitor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh capacitor is coupled to the reference power supply terminal.

[0057] Secondly, embodiments of this disclosure also provide a display device including the pixel driving circuit of any of the above.

[0058] Thirdly, embodiments of this disclosure also provide a driving method for the pixel driving circuit of any of the above claims, comprising:

[0059] The conduction control sub-circuit responds to the signal at the conduction control terminal and connects the first node to the setting terminal of the driving transistor;

[0060] The first light-emitting control sub-circuit responds to the signal at the first light-emitting control terminal by providing the signal at the first power supply terminal to the second terminal of the driving transistor.

[0061] The bias sub-circuit couples the signal from the bias signal terminal to the first node, the first capacitor provides the signal from the first node to the control terminal of the driving transistor, and / or, the bias sub-circuit couples the signal from the bias signal terminal to the control terminal of the driving transistor, and / or, the bias sub-circuit couples the signal from the bias signal terminal to the setting terminal of the driving transistor.

[0062] The beneficial effects of this disclosure are as follows:

[0063] In summary, this disclosure provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes: a driving transistor, a bias sub-circuit, a conduction control sub-circuit, a first capacitor, a first light-emitting control sub-circuit, and a light-emitting device. A first terminal of the driving transistor is coupled to the light-emitting device. The conduction control sub-circuit is coupled between a first node and a setting terminal of the driving transistor and is configured to conduct the first node and the setting terminal of the driving transistor in response to a signal from the conduction control terminal. The setting terminal is either the first terminal or the second terminal of the driving transistor. A first terminal of the first capacitor is coupled to a control terminal of the driving transistor, and a second terminal of the first capacitor is coupled to the first node. The first light-emitting device... The control sub-circuit is coupled between the first power supply terminal and the second terminal of the driving transistor, and is configured to provide the signal from the first power supply terminal to the second terminal of the driving transistor in response to the signal from the first light-emitting control terminal. The bias sub-circuit is coupled to the bias signal terminal, and is also coupled to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor, and is configured to couple the signal from the bias signal terminal to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor. The above-described biasing process of the driving transistor can correct the negative bias voltage of the threshold voltage of the driving transistor, thereby improving the characteristics of the driving transistor and making the display effect better.

[0064] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0065] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0066] Figure 1 is a circuit connection diagram of the pixel driving circuit in the related technology;

[0067] Figure 2 is a connection diagram of the first pixel driving circuit in an embodiment of this disclosure;

[0068] Figure 3 is a circuit connection diagram of the first pixel driving circuit in the embodiment of this disclosure;

[0069] Figure 4 is a connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0070] Figure 5 is a circuit connection diagram of the second pixel driving circuit in the embodiments of this disclosure;

[0071] Figure 6 is a circuit connection diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0072] Figure 7 is a connection diagram of the third pixel driving circuit in an embodiment of this disclosure;

[0073] Figure 8 is a circuit connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0074] Figure 9 is a circuit connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0075] Figure 10 is a circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0076] Figure 11 is a connection diagram of the fourth pixel driving circuit in the embodiment of this disclosure;

[0077] Figure 12 is a circuit connection diagram of the seventh pixel driving circuit in the embodiments of this disclosure;

[0078] Figure 13 is a connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0079] Figure 14 is a circuit connection diagram of the eighth pixel driving circuit in the embodiments of this disclosure;

[0080] Figure 15 is a connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0081] Figure 16 is a circuit connection diagram of the ninth pixel driving circuit in the embodiments of this disclosure;

[0082] Figure 17 is a connection diagram of the seventh pixel driving circuit in the embodiments of this disclosure;

[0083] Figure 18 is a circuit connection diagram of the tenth pixel driving circuit in the embodiments of this disclosure;

[0084] Figure 19 is a connection diagram of the eighth pixel driving circuit in the embodiments of this disclosure;

[0085] Figure 20 is a circuit connection diagram of the eleventh pixel driving circuit in the embodiments of this disclosure;

[0086] Figure 21 is a connection diagram of the ninth pixel driving circuit in the embodiment of this disclosure;

[0087] Figure 22 is a circuit connection diagram of the twelfth pixel driving circuit in the embodiments of this disclosure;

[0088] Figure 23 is a connection diagram of the tenth pixel driving circuit in the embodiment of this disclosure;

[0089] Figure 24 is a circuit connection diagram of the thirteenth pixel driving circuit in this embodiment of the present disclosure;

[0090] Figure 25 is a connection diagram of the eleventh pixel driving circuit in the embodiment of this disclosure;

[0091] Figure 26 is a circuit connection diagram of the fourteenth pixel driving circuit in this embodiment of the present disclosure;

[0092] Figure 27 is a circuit connection diagram of the twelfth pixel driving circuit in the embodiments of this disclosure;

[0093] Figure 28 is a circuit connection diagram of the fifteenth pixel driving circuit in the embodiments of this disclosure;

[0094] Figure 29 is a timing diagram of the first pixel driving circuit in the embodiments of this disclosure;

[0095] Figure 30 is a timing diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0096] Figure 31 is a timing diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0097] Figure 32 is a timing diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0098] Figure 33 is a simulation diagram of a pixel driving circuit according to an embodiment of this disclosure;

[0099] Figure 34 is a flowchart of a pixel driving circuit driving method according to an embodiment of the present disclosure. Detailed Implementation

[0100] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments described in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0101] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0102] In related technologies, when writing data voltage, the control terminal of the driving transistor in the pixel driving circuit will cause the threshold voltage of the driving transistor to have an abnormal negative bias. Especially when the pixel driving circuit is used for low-frequency (e.g., 1Hz) display, since the transistor controlling the writing of data voltage is in a normally closed state, the control terminal of the driving transistor will remain at the same fixed potential for a long time. In this case, the threshold voltage of the driving transistor will have a large negative bias, resulting in display problems such as image retention and flickering.

[0103] Referring to Figure 1, the pixel driving circuit shown in Figure 1 will be described in detail. The transistor DTFT in Figure 1 is the driving transistor. During the display process, in order to achieve high and low frequency switching, after the data voltage DATA is written by transistor M2, the on-state frequency of transistor M4 is controlled to determine whether the data voltage DATA is written to the control terminal of the driving transistor, thereby achieving high and low frequency display. However, during the process of writing the data voltage DATA to the control terminal, it affects the negative voltage of the threshold voltage of the driving transistor. Especially during low-frequency writing, the normally closed state of transistor M4 can cause a large negative bias voltage in the threshold voltage of the driving transistor, thus affecting the display effect.

[0104] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0105] Referring to Figure 2, a pixel driving circuit proposed in this application embodiment includes: a driving transistor DTFT, a bias sub-circuit 10, a conduction control sub-circuit 20, a first capacitor C1, a first light emission control sub-circuit 30, and a light emission device LED.

[0106] The working process of the pixel driving circuit is described below with reference to Figure 3. As shown in Figure 3, the first terminal of the driving transistor DTFT is coupled to the light-emitting device LED.

[0107] The conduction control sub-circuit 20 is coupled between the first node N1 and the setting terminal of the driving transistor DTFT, and is configured to conduct the first node N1 and the setting terminal of the driving transistor DTFT in response to the signal of the conduction control terminal GateN7, wherein the setting terminal is the first terminal or the second terminal of the driving transistor DTFT.

[0108] During implementation, when the signal of the gate control terminal GateN7 is valid, the conduction control sub-circuit 20 is turned on, and the first node N1 is turned on by the first or second terminal of the driving transistor DTFT through the conduction control sub-circuit 20.

[0109] The first light-emitting control sub-circuit 30 is coupled between the first power supply terminal VDD and the second terminal of the driving transistor DTFT, and is configured to provide the signal of the first power supply terminal VDD to the second terminal of the driving transistor DTFT in response to the signal of the first light-emitting control terminal EM1.

[0110] During implementation, when the signal of the first light-emitting control terminal EM1 is valid, the first light-emitting control sub-circuit 30 is turned on, and the signal of the first power supply terminal VDD is provided to the second terminal of the driving transistor DTFT through the turned-on first light-emitting control sub-circuit 30.

[0111] The first terminal of the first capacitor C1 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the first capacitor C1 is coupled to the first node N1. It is configured to store the data voltage and the threshold voltage of the driving transistor when the signal of the second light-emitting control terminal is valid.

[0112] During implementation, the voltage across the first capacitor C1 changes with the voltage of the first node N1, thereby completing operations such as data writing and biasing of the control terminal of the driving transistor DTFT. Especially during the effective light-emitting stage of the signal at the second light-emitting control terminal, the first capacitor C1 can maintain the data voltage and the threshold voltage of the driving transistor. In this way, the driving transistor can generate a stable driving current under the action of the data voltage and the threshold voltage of the driving transistor, thereby enabling the LED to emit light stably.

[0113] The bias sub-circuit 10 is coupled to a bias signal terminal (COBS1 and / or COBS2), and the bias sub-circuit 10 is also coupled to at least one of the first node N1, the control terminal of the driving transistor DTFT, and the setting terminal of the driving transistor DTFT. It is configured to couple the signal of the bias signal terminal (COBS1 and / or COBS2) to at least one of the first node N1, the control terminal of the driving transistor DTFT, and the setting terminal of the driving transistor DTFT.

[0114] During implementation, the signals in the bias signal terminals (COBS1 and / or COBS2) are coupled to at least one of the first node N1, the control terminal of the driving transistor DTFT, and the setting terminal of the driving transistor DTFT via the bias sub-circuit 10.

[0115] It should be noted that the bias sub-circuit 10 connected in Figure 2 represents four different connection positions of the bias sub-circuit 10 in the pixel driving circuit. The first case is that the bias sub-circuit 10 is connected to the conduction control sub-circuit 20 via the first node N1. The second case is that the bias sub-circuit 10 is connected to the control terminal of the driving transistor DTFT. The third case is that the bias sub-circuit 10 is connected to the first terminal of the driving transistor DTFT. The fourth case is that the bias sub-circuit 10 is connected to the second terminal of the driving transistor DTFT.

[0116] To distinguish the bias sub-circuit 10 mentioned above, the bias sub-circuit in the first case mentioned above will be referred to as bias sub-circuit 101, the bias sub-circuit in the second case mentioned above will be referred to as bias sub-circuit 102, the bias sub-circuit in the third case mentioned above will be referred to as bias sub-circuit 103, and the bias sub-circuit in the fourth case mentioned above will be referred to as bias sub-circuit 104.

[0117] Referring to Figures 4, 5 and 6, the bias sub-circuit 101 is coupled to the first node N1, the bias signal terminal includes the first bias signal terminal COBS1, and the bias sub-circuit 101 includes the second capacitor C2.

[0118] The first terminal of the second capacitor C2 is coupled to the first bias signal terminal COBS1, and the second terminal of the second capacitor C2 is coupled to the first node N1.

[0119] During implementation, the voltage at the first terminal of the second capacitor C2 changes with the signal of the first bias signal terminal COBS1, thereby causing the voltage at the first node N1 to change accordingly.

[0120] Referring to Figures 7 and 8, the bias sub-circuit 102 is coupled to the control terminal of the driving transistor DTFT, and the bias signal terminal includes the first bias signal terminal COBS1. The bias sub-circuit 102 includes a third capacitor C3.

[0121] The first terminal of the third capacitor C3 is coupled to the first bias signal terminal COBS1, and the second terminal of the third capacitor C3 is coupled to the control terminal of the driving transistor DTFT.

[0122] During implementation, the voltage at the first terminal of the third capacitor C3 changes with the signal of the first bias signal terminal COBS1, thereby causing the voltage at the control terminal of the driving transistor DTFT to change accordingly and biasing the driving transistor DTFT.

[0123] It should be further noted that the signal at the first bias signal terminal COBS1 is typically the output signal of the shift register unit. This output signal inevitably contains noise, which can cause fluctuations in the potential of the control terminal of the driving transistor DTFT, and even display-related malfunctions. To eliminate the influence of this noise, in this embodiment, a noise-eliminating transistor or similar device is incorporated into the shift register unit to obtain a stable signal at the first bias signal terminal COBS1, thereby achieving a better biasing effect.

[0124] In this embodiment of the application, in Figures 5, 6 and 8, the effective signal of the first bias signal terminal COBS1 is a negative voltage.

[0125] It should be noted that, in the scheme where the signal of the first bias signal terminal COBS1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1 or the conduction control sub-circuit 20, and / or the signal of the first bias signal terminal COBS1 is provided to the control terminal of the driving transistor DTFT via the third capacitor C3, in order to achieve the purpose of biasing the threshold voltage Vth of the driving transistor DTFT, the effective signal of the first bias signal terminal COBS1 is a negative voltage, that is, the control terminal of the driving transistor DTFT is negatively biased by the effective signal of the first bias signal terminal COBS1.

[0126] Referring to Figure 9, the bias sub-circuit 103 is coupled to the setting terminal of the driving transistor DTFT. The setting terminal is the first terminal of the driving transistor DTFT. The bias signal terminal includes the second bias signal terminal COBS2. The bias sub-circuit 103 includes a fourth capacitor C4.

[0127] The first terminal of the fourth capacitor C4 is coupled to the second bias signal terminal COBS2, and the second terminal of the fourth capacitor C4 is coupled to the first terminal of the driving transistor DTFT.

[0128] During implementation, the voltage at the first terminal of the fourth capacitor C4 changes with the signal of the second bias signal terminal COBS2, thereby causing the voltage at the first terminal of the driving transistor DTFT to change accordingly.

[0129] Referring to Figure 10, the bias sub-circuit 104 is coupled to the setting terminal of the driving transistor DTFT. The setting terminal is the second terminal of the driving transistor DTFT. The bias signal terminal includes the second bias signal terminal COBS2. The bias sub-circuit 104 includes a fifth capacitor C5.

[0130] The first terminal of the fifth capacitor C5 is coupled to the second bias signal terminal COBS2, and the second terminal of the fifth capacitor C5 is coupled to the second terminal of the driving transistor DTFT.

[0131] During implementation, the voltage at the first terminal of the fifth capacitor C5 changes with the signal of the second bias signal terminal COBS2, thereby causing the voltage at the second terminal of the driving transistor DTFT to change accordingly.

[0132] In this embodiment of the application, in Figures 9 and 10, the effective signal of the second bias signal terminal COBS2 is a positive voltage.

[0133] When the fourth capacitor C4 is connected to the first terminal of the driving transistor DTFT and / or when the fifth capacitor C5 is connected to the second terminal of the driving transistor DTFT, the signal of the second bias signal terminal COBS2 is provided to the first or second terminal of the driving transistor DTFT through the fourth capacitor C4 and / or the fifth capacitor C5. In order to achieve the purpose of biasing the threshold voltage Vth of the driving transistor DTFT, the effective signal of the second bias signal terminal COBS2 is a positive voltage. That is, the first or second terminal of the driving transistor DTFT is positively biased by the effective signal of the second bias signal terminal COBS2, thereby correcting the negative bias voltage of the threshold voltage of the driving transistor.

[0134] Furthermore, during implementation, in order to better achieve the purpose of biasing the threshold voltage Vth of the driving transistor DTFT, within one display cycle, the effective signal of the first bias signal terminal COBS1 or the effective signal of the second bias signal terminal COBS2 can be one or more. For example, within one display cycle, the effective signal of the first bias signal terminal COBS1 is one or more low-level pulses, and the effective signal of the second bias signal terminal COBS2 within one display cycle is one or more high-level pulses.

[0135] Additionally, it should be noted that the effective timing of the bias signal terminals (COBS1 and / or COBS2) is activated after the effective timing of the signal at the gate control terminal (GateN7) has ended.

[0136] The validity period of the bias signal terminals (COBS1 and / or COBS2) is activated after the validity period of the signal at the first reset control terminal GateN1 has ended.

[0137] During implementation, to ensure the normal operation of the pixel driving circuit, i.e., to avoid affecting the data writing and light emission processes of the pixel driving circuit, the signals at the aforementioned bias signal terminals (COBS1 and / or COBS2) become effective after the effective time of the signal at the gate control terminal (GateN7) has ended. That is, after the bias sub-circuit 10 writes data voltage to the control terminal of the driving transistor, it can correct the negative bias voltage of the driving transistor through the signals at the bias signal terminals (COBS1 and / or COBS2).

[0138] The signals at the aforementioned bias signal terminals (COBS1 and / or COBS2) become effective after the effective time of the first reset control terminal GateN1 has ended. That is, after initialization at the control terminal of the driving transistor, the bias sub-circuit 10 can correct the negative bias voltage of the driving transistor through the signals at the bias signal terminals (COBS1 and / or COBS2).

[0139] It should be noted that the aforementioned bias signal terminals (COBS1 and / or COBS2) include the first bias signal terminal COBS1 and / or the second bias signal terminal COBS2. That is, the first bias signal terminal COBS1 and the second bias signal terminal COBS2 can be effective simultaneously within the same effective time period, or they can be effective separately within different effective time periods.

[0140] Accordingly, in this embodiment, two bias sub-circuits can also be configured simultaneously. Referring to Figures 11 and 12, bias sub-circuit 101 and bias sub-circuit 104 can be configured simultaneously, meaning that the first bias signal terminal COBS1 and the second bias signal terminal COBS2 simultaneously operate during the pixel driving circuit's operation. Furthermore, bias sub-circuit 101 and bias sub-circuit 103 can also be configured simultaneously, as can bias sub-circuit 102 and bias sub-circuit 103, and bias sub-circuit 103 and bias sub-circuit 104; these will not be elaborated upon further here.

[0141] The following section, with reference to the accompanying diagram, will introduce the other transistors in the pixel driving circuit.

[0142] In one embodiment, referring to FIG3, the conduction control sub-circuit 20 includes a first switching transistor T1.

[0143] The control terminal of the first switching transistor T1 is coupled to the conduction control terminal GateN7, the first terminal of the first switching transistor T1 is coupled to the first node N1, and the second terminal of the first switching transistor T1 is coupled to the first terminal of the driving transistor DTFT.

[0144] For example, the first switching transistor T1 can be turned on under the control of an active level of the turn-on control terminal GateN7, and can be turned off under the control of an inactive level of the turn-on control terminal GateN7. For example, if the first switching transistor T1 is configured as an N-type transistor, then the active level of the signal at the turn-on control terminal GateN7 is a high level, and the inactive level of the signal at the turn-on control terminal GateN7 is a low level. Alternatively, if the first switching transistor T1 is configured as a P-type transistor, then the active level of the signal at the turn-on control terminal GateN7 is a low level, and the inactive level of the signal at the turn-on control terminal GateN7 is a high level.

[0145] Referring to Figure 3, the first switching transistor T1 is an N-type transistor. When the signal at the control terminal GateN7 is high, the first switching transistor T1 is turned on, and the first node N1 is connected to the first terminal of the driving transistor DTFT through the turned-on first switching transistor T1.

[0146] In another embodiment, referring to FIG5, the conduction control sub-circuit 20 includes a second switching transistor T2.

[0147] The control terminal of the second switching transistor T2 is coupled to the conduction control terminal GateN7, the first terminal of the second switching transistor T2 is coupled to the first node N1, and the second terminal of the second switching transistor T2 is coupled to the second terminal of the driving transistor DTFT.

[0148] For example, the second switching transistor T2 can be turned on under the control of an active level of the turn-on control terminal GateN7, and can be turned off under the control of an inactive level of the turn-on control terminal GateN7. For example, if the second switching transistor T2 is configured as an N-type transistor, then the active level of the signal at the turn-on control terminal GateN7 is a high level, and the inactive level of the signal at the turn-on control terminal GateN7 is a low level. Alternatively, if the second switching transistor T2 is configured as a P-type transistor, then the active level of the signal at the turn-on control terminal GateN7 is a low level, and the inactive level of the signal at the turn-on control terminal GateN7 is a high level.

[0149] Referring to Figure 5, the second switching transistor T2 is an N-type transistor. When the signal at the control terminal GateN7 is high, the second switching transistor T2 is turned on, and the first node N1 is connected to the second terminal of the driving transistor DTFT through the turned-on second switching transistor T2.

[0150] Referring to Figure 6, the first light-emitting control sub-circuit 30 includes a third switching transistor T3.

[0151] The control terminal of the third switching transistor T3 is coupled to the first light-emitting control terminal EM1, the first terminal of the third switching transistor T3 is coupled to the first power supply terminal VDD, and the second terminal of the third switching transistor T3 is coupled to the second terminal of the driving transistor DTFT.

[0152] For example, the third switching transistor T3 can be turned on under the control of the effective level of the first light-emitting control terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control terminal EM1. For example, if the third switching transistor T3 is set as an N-type transistor, then the effective level of the signal of the first light-emitting control terminal EM1 is a high level, and the ineffective level of the signal of the first light-emitting control terminal EM1 is a low level. Alternatively, if the third switching transistor T3 is set as a P-type transistor, then the effective level of the signal of the first light-emitting control terminal EM1 is a low level, and the ineffective level of the signal of the first light-emitting control terminal EM1 is a high level.

[0153] Referring to Figure 6, the third switching transistor T3 is a P-type transistor. When the signal of the first light-emitting control terminal EM1 is low, the third switching transistor T3 is turned on, and the signal of the first power supply terminal VDD is provided to the second terminal of the driving transistor DTFT through the turned-on third switching transistor T3.

[0154] In addition, as shown in Figure 13, the pixel driving circuit also includes a first reset circuit 40, which is coupled between the first initialization signal terminal Vinit1 and the control terminal of the driving transistor DTFT.

[0155] The first reset sub-circuit 40 is configured to provide the signal of the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT in response to the signal of the first reset control terminal GateN1.

[0156] During implementation, when the signal of the first reset control terminal GateN1 is valid, the first reset sub-circuit 40 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT through the turned-on first reset sub-circuit 40.

[0157] Referring to Figure 14, the first reset circuit 40 includes a fourth switching transistor T4.

[0158] The control terminal of the fourth switching transistor T4 is coupled to the first reset control terminal GateN1, the first terminal of the fourth switching transistor T4 is coupled to the first initialization signal terminal Vinit1, and the second terminal of the fourth switching transistor T4 is coupled to the control terminal of the driving transistor DTFT.

[0159] For example, the fourth switching transistor T4 can be turned on under the control of the effective level of the first reset control terminal GateN1, and can be turned off under the control of the ineffective level of the first reset control terminal GateN1. For example, if the fourth switching transistor T4 is set as an N-type transistor, then the effective level of the signal of the first reset control terminal GateN1 is a high level, and the ineffective level of the signal of the first reset control terminal GateN1 is a low level. Alternatively, if the fourth switching transistor T4 is set as a P-type transistor, then the effective level of the signal of the first reset control terminal GateN1 is a low level, and the ineffective level of the signal of the first reset control terminal GateN1 is a high level.

[0160] Referring to Figure 14, the fourth switching transistor T4 is an N-type transistor. When the signal of the first reset control terminal GateN1 is high, the fourth switching transistor T4 is turned on, and the signal of the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT through the turned-on fourth switching transistor T4.

[0161] Referring to Figure 15, the pixel driving circuit also includes a data writing sub-circuit 50, which is coupled between the setting terminal of the driving transistor DTFT and the data signal terminal Vdata.

[0162] The data writing sub-circuit 50 is configured to provide the data signal Vdata to the setting terminal of the driving transistor DTFT in response to the signal of the scan signal terminal Gate.

[0163] During implementation, when the signal at the Gate terminal is valid, the data writing sub-circuit 50 is turned on, and the signal at the Vdata terminal is provided to the setting terminal of the driving transistor DTFT through the turned-on data writing sub-circuit 50.

[0164] In one embodiment, referring to FIG16, the data writing sub-circuit 50 includes a fifth switching transistor T5.

[0165] The control terminal of the fifth switching transistor T5 is coupled to the scan signal terminal Gate, the first terminal of the fifth switching transistor T5 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the fifth switching transistor T5 is coupled to the data signal terminal Vdata.

[0166] For example, the fifth switching transistor T5 can be turned on under the control of the effective level of the scan signal terminal Gate, and can be turned off under the control of the ineffective level of the scan signal terminal Gate. For example, if the fifth switching transistor T5 is set as an N-type transistor, then the effective level of the signal at the scan signal terminal Gate is a high level, and the ineffective level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the fifth switching transistor T5 is set as a P-type transistor, then the effective level of the signal at the scan signal terminal Gate is a low level, and the ineffective level of the signal at the scan signal terminal Gate is a high level.

[0167] Referring to Figure 16, the fifth switching transistor T5 is a P-type transistor. When the signal at the scan signal terminal Gate is low, the fifth switching transistor T5 is turned on, and the signal at the data signal terminal Vdata is provided to the first terminal of the driving transistor DTFT through the turned-on fifth switching transistor T5.

[0168] In another embodiment, referring to Figures 17 and 18, the data writing sub-circuit 50 includes a sixth switching transistor T6.

[0169] The control terminal of the sixth switching transistor T6 is coupled to the scan signal terminal Gate, the first terminal of the sixth switching transistor T6 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the sixth switching transistor T6 is coupled to the data signal terminal Vdata.

[0170] For example, the sixth switching transistor T6 can be turned on under the control of the effective level of the scan signal terminal Gate, and can be turned off under the control of the ineffective level of the scan signal terminal Gate. For example, if the sixth switching transistor T6 is set as an N-type transistor, then the effective level of the signal at the scan signal terminal Gate is a high level, and the ineffective level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the sixth switching transistor T6 is set as a P-type transistor, then the effective level of the signal at the scan signal terminal Gate is a low level, and the ineffective level of the signal at the scan signal terminal Gate is a high level.

[0171] Referring to Figure 18, the sixth switching transistor T6 is a P-type transistor. When the signal at the scan signal terminal Gate is low, the sixth switching transistor T6 is turned on, and the signal at the data signal terminal Vdata is provided to the second terminal of the driving transistor DTFT through the turned-on sixth switching transistor T6.

[0172] In addition, as shown in Figure 19, the pixel driving circuit also includes a second light-emitting control sub-circuit 60, which is coupled between the first terminal of the driving transistor DTFT and the anode of the light-emitting device LED.

[0173] The second light-emitting control sub-circuit 60 is configured to, in response to the signal of the second light-emitting control terminal EM2, connect the first terminal of the driving transistor DTFT to the anode of the light-emitting device LED.

[0174] During implementation, when the signal of the second light-emitting control terminal EM2 is valid, the second light-emitting control sub-circuit 60 is turned on, and the first terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the second light-emitting control sub-circuit 60.

[0175] Referring to Figure 20, the second light-emitting control sub-circuit 60 includes a seventh switching transistor T7.

[0176] The control terminal of the seventh switching transistor T7 is coupled to the second light-emitting control terminal EM2, the first terminal of the seventh switching transistor T7 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the seventh switching transistor T7 is coupled to the anode of the light-emitting device LED.

[0177] For example, the seventh switching transistor T7 can be turned on under the control of the effective level of the second light-emitting control terminal EM2, and can be turned off under the control of the ineffective level of the second light-emitting control terminal EM2. For example, if the seventh switching transistor T7 is set as an N-type transistor, then the effective level of the signal of the second light-emitting control terminal EM2 is a high level, and the ineffective level of the signal of the second light-emitting control terminal EM2 is a low level. Alternatively, if the seventh switching transistor T7 is set as a P-type transistor, then the effective level of the signal of the second light-emitting control terminal EM2 is a low level, and the ineffective level of the signal of the second light-emitting control terminal EM2 is a high level.

[0178] Referring to Figure 20, the seventh switching transistor T7 is a P-type transistor. When the signal of the second light-emitting control terminal EM2 is low, the seventh switching transistor T7 is turned on, and the first terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the turned-on seventh switching transistor T7.

[0179] Referring to Figure 21, the pixel driving circuit mentioned above also includes a second reset circuit 70, which is coupled between the anode of the light-emitting device LED and the second initialization signal terminal Vinit2.

[0180] The second reset sub-circuit 70 is configured to provide the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device LED in response to the signal of the second reset control terminal ResetH.

[0181] During implementation, when the signal of the second reset control terminal ResetH is valid, the second reset sub-circuit 70 is turned on, and the signal of the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device LED through the turned-on second reset sub-circuit 70.

[0182] Referring to Figure 22, the second reset circuit 70 includes an eighth switching transistor T8.

[0183] The control terminal of the eighth switching transistor T8 is coupled to the second reset control terminal ResetH, the first terminal of the eighth switching transistor T8 is coupled to the anode of the light-emitting device LED, and the second terminal of the eighth switching transistor T8 is coupled to the second initialization signal terminal Vinit2.

[0184] For example, the eighth switching transistor T8 can be turned on under the control of the active level of the second reset control terminal ResetH, and can be turned off under the control of the inactive level of the second reset control terminal ResetH. For example, if the eighth switching transistor T8 is set as an N-type transistor, then the active level of the signal at the second reset control terminal ResetH is a high level, and the inactive level of the signal at the second reset control terminal ResetH is a low level. Alternatively, if the eighth switching transistor T8 is set as a P-type transistor, then the active level of the signal at the second reset control terminal ResetH is a low level, and the inactive level of the signal at the second reset control terminal ResetH is a high level.

[0185] Referring to Figure 22, the eighth switching transistor T8 is a P-type transistor. When the signal of the second reset control terminal ResetH is low, the eighth switching transistor T8 is turned on, and the signal of the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device LED through the turned-on eighth switching transistor T8.

[0186] In addition, referring to Figure 23, the above-mentioned pixel driving circuit also includes a third reset circuit 80, which is coupled between the setting terminal of the driving transistor DTFT and the third initialization signal terminal Vinit3, wherein the signal of the third initialization signal terminal Vinit3 is a negative voltage.

[0187] It should be noted that, in the case that the signal of the third initialization signal terminal Vinit3 is a negative voltage, the process of threshold voltage Vth compensation for the driving transistor DTFT in this embodiment of the application is different from the related technology. In this embodiment of the application, the voltage of the first power supply terminal VDD is first used to adjust the third node N3, the second node N2 and the first node N1 to positive voltage. Then, the negative voltage signal of the third initialization signal terminal Vinit3 is written to the third node N3, and the source of the driving transistor DTFT is switched to the second node N2. At the same time, the negative voltage signal of the third initialization signal terminal Vinit3 charges the third node N3. When the gate-source voltage Vg of the driving transistor DTFT is equal to the threshold voltage Vth, the threshold voltage Vth compensation charging is completed. At this time, the voltage of the second node N2 VN2 = Vinit1 - Vth.

[0188] The third reset sub-circuit 80 is configured to provide the signal of the third initialization signal terminal Vinit3 to the setting terminal of the driving transistor DTFT in response to the signal of the third reset control terminal ResetH.

[0189] During implementation, when the signal of the third reset control terminal ResetH is valid, the signal of the third initialization signal terminal Vinit3 is provided to the setting terminal of the driving transistor DTFT through the activated third reset sub-circuit 80.

[0190] In one embodiment, referring to FIG24, the third reset circuit 80 includes a ninth switching transistor T9.

[0191] The control terminal of the ninth switching transistor T9 is coupled to the third reset control terminal ResetH, the first terminal of the ninth switching transistor T9 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the ninth switching transistor T9 is coupled to the third initialization signal terminal Vinit3.

[0192] For example, the ninth switching transistor T9 can be turned on under the control of the active level of the third reset control terminal ResetH, and turned off under the control of the inactive level of the third reset control terminal ResetH. For example, if the ninth switching transistor T9 is set as an N-type transistor, then the active level of the signal at the third reset control terminal ResetH is a high level, and the inactive level of the signal at the third reset control terminal ResetH is a low level. Alternatively, if the ninth switching transistor T9 is set as a P-type transistor, then the active level of the signal at the third reset control terminal ResetH is a low level, and the inactive level of the signal at the third reset control terminal ResetH is a high level.

[0193] Referring to Figure 24, the ninth switching transistor T9 is a P-type transistor. When the signal of the third reset control terminal ResetH is low, the ninth switching transistor T9 is turned on, and the signal of the third initialization signal terminal Vinit3 is provided to the first terminal of the driving transistor DTFT through the turned-on ninth switching transistor T9.

[0194] In another embodiment, referring to Figures 25 and 26, the third reset circuit 80 includes a tenth switching transistor T10.

[0195] The control terminal of the tenth switching transistor T10 is coupled to the third reset control terminal ResetH, the first terminal of the tenth switching transistor T10 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the tenth switching transistor T10 is coupled to the third initialization signal terminal Vinit3.

[0196] For example, the tenth switching transistor T10 can be turned on under the control of the active level of the third reset control terminal ResetH, and can be turned off under the control of the inactive level of the third reset control terminal ResetH. For example, if the tenth switching transistor T10 is set as an N-type transistor, then the active level of the signal of the third reset control terminal ResetH is a high level, and the inactive level of the signal of the third reset control terminal ResetH is a low level. Alternatively, if the tenth switching transistor T10 is set as a P-type transistor, then the active level of the signal of the third reset control terminal ResetH is a low level, and the inactive level of the signal of the third reset control terminal ResetH is a high level.

[0197] Referring to Figure 26, the tenth switching transistor T10 is a P-type transistor. When the signal of the third reset control terminal ResetH is low, the tenth switching transistor T10 is turned on, and the signal of the third initialization signal terminal Vinit3 is provided to the second terminal of the driving transistor DTFT through the turned-on tenth switching transistor T10.

[0198] In addition, as shown in Figure 27, the pixel driving circuit also includes a sixth capacitor C6.

[0199] The first terminal of the sixth capacitor C6 is coupled to the first node N1, and the second terminal of the sixth capacitor C6 is coupled to the first power supply terminal VDD.

[0200] During implementation, the second terminal of the sixth capacitor C6 maintains a stable potential through the first power supply terminal VDD, thereby making the potential of the first node N1 more stable. Furthermore, during the negative biasing of the first node N1 by the bias sub-circuit 101, the sixth capacitor C6 does not divide the signal at the first bias signal terminal COBS1. That is, the potential change of the first node N1, ΔN1 = C1 / (C2+C1)*(VGH-VGL), where the signal at the first bias signal terminal COBS1 is VGH-VGL. The potential level of (VGH-VGL) can be controlled by adjusting the output voltage level of the signal shift register unit that generates the first bias signal terminal COBS1.

[0201] In addition, as shown in Figure 28, the pixel driving circuit also includes a seventh capacitor C7.

[0202] The first terminal of the seventh capacitor C7 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the seventh capacitor C7 is coupled to the reference power supply terminal Vref.

[0203] During implementation, the second terminal of the seventh capacitor C7 maintains a stable potential through the reference power supply terminal Vref, thereby making the potential of the first capacitor C1 more stable. However, during the process of the bias sub-circuit 101 applying a negative voltage bias to the first node N1, the seventh capacitor C7 will divide the signal of the first bias signal terminal COBS1, that is, the potential change of the first node N1 ΔN1=C1 / (C2+C1+C7)*(VGH-VGL), where the signal of the first bias signal terminal COBS1 is VGH-VGL. The potential level of the above (VGH-VGL) can be controlled by adjusting the output voltage level of the signal shift register unit that generates the first bias signal terminal COBS1.

[0204] In addition, it should be noted that the voltage of the reference power supply terminal Vref can be equal to or different from the voltage of the first power supply terminal VDD.

[0205] The operation of the pixel driving circuit in the embodiments of this application will be described in detail below with reference to timing diagrams 29, 30, 31 and 32.

[0206] In this context, 0 represents a low signal level, and 1 represents a high signal level.

[0207] (1) The working process of the pixel driving circuit will be introduced by referring to Figures 26 and 29:

[0208] Timing t1 stage: EM2 = 1, EM1 = from 1 to 0, GateN1 = 1, GateN7 = from 0 to 1, ResetH = 1, Gate = 1, COBS1 = 1

[0209] In response to the signal from the first reset control terminal GateN1, the first reset sub-circuit 40 provides the signal from the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT. Subsequently, in response to the signal from the first light emission control terminal EM1, the first light emission control sub-circuit 30 provides the signal from the first power supply terminal VDD to the second and first terminals of the driving transistor DTFT. In response to the signal from the turn-on control terminal GateN7, the turn-on control sub-circuit 20 continues to provide the signal from the first power supply terminal VDD to the first node N1.

[0210] Timing t2 stage: EM2=1, EM1=1, GateN1=1, GateN7=1, ResetH=0, Gate=1, COBS1=1

[0211] The second reset circuit 70 responds to the signal of the second reset control terminal ResetH by providing the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device LED. The third reset circuit 80 responds to the signal of the third reset control terminal ResetH by providing the negative voltage signal of the third initialization signal terminal Vinit3 to the first or second terminal of the driving transistor DTFT. When the gate-source voltage Vgs of the driving transistor DTFT is equal to the threshold voltage Vth, the driving transistor DTFT is turned off, and the acquired threshold voltage Vth is stored in the first capacitor C1.

[0212] Timing t3 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=0, COBS1=1

[0213] The data writing sub-circuit 50 responds to the signal at the scan signal terminal Gate by providing the signal at the data signal terminal Vdata to the first or second terminal of the driving transistor DTFT. The turn-on control sub-circuit 20 responds to the signal at the turn-on control terminal GateN7 by providing the data voltage at the data signal terminal Vdata to the first node N1. The data voltage at the first node N1 and the threshold voltage Vth are provided to the control terminal of the driving transistor DTFT via the first capacitor C1.

[0214] Timing t4 stage: EM2=1, EM1=1, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=0

[0215] A low-potential active signal from the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, enabling low-potential coupling to the first node N1. The pull-down coupling amount of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, enabling negative voltage biasing of the driving transistor DTFT. The rising edge high-potential signal from the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, enabling high-potential coupling between the first node N1 and the control terminal, thereby restoring the potential of the first node N1 and the control terminal to the potential indicated by the data voltage and the threshold voltage Vth.

[0216] Timing t5 stage: EM2=0, EM1=0, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=1

[0217] In response to the signal from the first light-emitting control sub-circuit 30, the first power supply terminal VDD is turned on and the second terminal of the driving transistor DTFT is turned on. In response to the signal from the second light-emitting control terminal EM2, the second light-emitting control sub-circuit 60 is turned on and the first terminal of the driving transistor DTFT is turned on and the anode of the light-emitting device LED is turned on.

[0218] (2) The working process of the pixel driving circuit will be introduced by referring to Figures 26 and 30:

[0219] Timing t1 stage: EM2 = 1, EM1 = from 1 to 0, GateN1 = 1, GateN7 = from 0 to 1, ResetH = 1, Gate = 1, COBS1 = 1

[0220] In response to the signal from the first reset control terminal GateN1, the first reset sub-circuit 40 provides the signal from the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT. Subsequently, in response to the signal from the first light emission control terminal EM1, the first light emission control sub-circuit 30 provides the signal from the first power supply terminal VDD to the second and first terminals of the driving transistor DTFT. In response to the signal from the turn-on control terminal GateN7, the turn-on control sub-circuit 20 continues to provide the signal from the first power supply terminal VDD to the first node N1.

[0221] Timing t2 stage: EM2=1, EM1=1, GateN1=1, GateN7=1, ResetH=0, Gate=1, COBS1=1

[0222] The second reset circuit 70 responds to the signal of the second reset control terminal ResetH by providing the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device LED. The third reset circuit 80 responds to the signal of the third reset control terminal ResetH by providing the negative voltage signal of the third initialization signal terminal Vinit3 to the first or second terminal of the driving transistor DTFT. When the gate-source voltage Vgs of the driving transistor DTFT is equal to the threshold voltage Vth, the driving transistor DTFT is turned off, and the acquired threshold voltage Vth is stored in the first capacitor C1.

[0223] Timing t3 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=1, COBS1=0

[0224] A low-potential active signal from the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, enabling low-potential coupling to the first node N1. The pull-down coupling of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, enabling negative voltage biasing of the driving transistor DTFT. A rising-edge high-potential signal from the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, enabling high-potential coupling between the first node N1 and the control terminal, thereby restoring the potentials of the first node N1 and the control terminal to the potentials indicated by the data voltage and the threshold voltage Vth.

[0225] Timing t4 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=0, COBS1=1

[0226] The data writing sub-circuit 50 responds to the signal at the scan signal terminal Gate by providing the signal at the data signal terminal Vdata to the first or second terminal of the driving transistor DTFT. The turn-on control sub-circuit 20 responds to the signal at the turn-on control terminal GateN7 by providing the data voltage at the data signal terminal Vdata to the first node N1. The data voltage at the first node N1 and the threshold voltage Vth are provided to the control terminal of the driving transistor DTFT via the first capacitor C1.

[0227] Timing t5 stage: EM2=1, EM1=1, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=from 0 to 1 and then from 0 to 1

[0228] The first low-potential active signal of the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, thereby coupling the first node N1 at a low potential. The pull-down coupling amount of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, thereby biasing the driving transistor DTFT at a negative voltage. The first rising edge high-potential signal of the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, thereby coupling the first node N1 and the control terminal at a high potential, so that the potential of the first node N1 and the control terminal is restored to the potential indicated by the data voltage and threshold voltage signals.

[0229] The second low-potential active signal of the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, which performs low-potential coupling on the first node N1. The pull-down coupling amount of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, which further performs negative voltage bias on the driving transistor DTFT. In order not to affect the writing of data voltage and threshold voltage Vth, the second rising edge high-potential signal of the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, which performs high-potential coupling on the first node N1 and the control terminal, so that the potential of the first node N1 and the control terminal is restored to the potential indicated by data voltage and threshold voltage Vth.

[0230] Timing t6 stage: EM2=0, EM1=0, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=1

[0231] In response to the signal from the first light-emitting control sub-circuit 30, the first power supply terminal VDD is turned on and the second terminal of the driving transistor DTFT is turned on. In response to the signal from the second light-emitting control terminal EM2, the second light-emitting control sub-circuit 60 is turned on and the first terminal of the driving transistor DTFT is turned on and the anode of the light-emitting device LED is turned on.

[0232] (3) The working process of the pixel driving circuit will be introduced by referring to Figures 27 and 31:

[0233] Timing t1 stage: EM2 = 1, EM1 = from 1 to 0, GateN1 = 1, GateN7 = from 0 to 1, ResetH = 1, Gate = 1, COBS2 = 0

[0234] In response to the signal from the first reset control terminal GateN1, the first reset sub-circuit 40 provides the signal from the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT. Subsequently, in response to the signal from the first light emission control terminal EM1, the first light emission control sub-circuit 30 provides the signal from the first power supply terminal VDD to the second and first terminals of the driving transistor DTFT. In response to the signal from the turn-on control terminal GateN7, the first power supply terminal VDD provides the signal from the first node N1.

[0235] Timing t2 stage: EM2=1, EM1=1, GateN1=1, GateN7=1, ResetH=0, Gate=1, COBS2=0

[0236] The second reset circuit 70 responds to the signal of the second reset control terminal ResetH by providing the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device LED. The third reset circuit 80 responds to the signal of the third reset control terminal ResetH by providing the negative voltage signal of the third initialization signal terminal Vinit3 to the first or second terminal of the driving transistor DTFT. When the gate-source voltage Vgs of the driving transistor DTFT is equal to the threshold voltage Vth, the driving transistor DTFT is turned off, and the acquired threshold voltage Vth is stored in the first capacitor C1.

[0237] Timing t3 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=0, COBS2=0

[0238] The data writing sub-circuit 50 responds to the signal at the scan signal terminal Gate by providing the data voltage at the data signal terminal Vdata to the first or second terminal of the driving transistor DTFT. The conduction control sub-circuit 20 responds to the signal at the conduction control terminal GateN7 by providing the data voltage at the data signal terminal Vdata to the first node N1. The data voltage at the first node N1 and the threshold voltage Vth are provided to the control terminal of the driving transistor DTFT via the first capacitor C1.

[0239] Timing t4 stage: EM2=1, EM1=1, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS2=1

[0240] A high-potential active signal from the second bias signal terminal COBS2 is provided to the second terminal of the driving transistor DTFT via the bias sub-circuit 104. This high-potential coupling of the second terminal enables a positive bias process for the second terminal of the driving transistor DTFT, thereby correcting the negative bias of the threshold voltage of the driving transistor.

[0241] Timing t5 stage: EM2=0, EM1=0, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS2=0

[0242] In response to the signal from the first light-emitting control sub-circuit 30, the first power supply terminal VDD is turned on and the second terminal of the driving transistor DTFT is turned on. In response to the signal from the second light-emitting control terminal EM2, the second light-emitting control sub-circuit 60 is turned on and the first terminal of the driving transistor DTFT is turned on and the anode of the light-emitting device LED is turned on.

[0243] (4) The working process of the pixel driving circuit will be introduced by referring to Figures 27 and 32:

[0244] Timing t1 stage: EM2 = 1, EM1 = from 1 to 0, GateN1 = 1, GateN7 = from 0 to 1, ResetH = 1, Gate = 1, COBS1 = 1, COBS2 = 0

[0245] In response to the signal from the first reset control terminal GateN1, the first reset sub-circuit 40 provides the signal from the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT. Subsequently, in response to the signal from the first light emission control terminal EM1, the first light emission control sub-circuit 30 provides the signal from the first power supply terminal VDD to the second and first terminals of the driving transistor DTFT. In response to the signal from the turn-on control terminal GateN7, the first power supply terminal VDD provides the signal from the first node N1.

[0246] Timing t2 stage: EM2=1, EM1=1, GateN1=1, GateN7=1, ResetH=0, Gate=1, COBS1=1, COBS2=0

[0247] The second reset circuit 70 responds to the signal of the second reset control terminal ResetH by providing the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device LED. The third reset circuit 80 responds to the signal of the third reset control terminal ResetH by providing the negative voltage signal of the third initialization signal terminal Vinit3 to the first or second terminal of the driving transistor DTFT. When the gate-source voltage Vgs of the driving transistor DTFT is equal to the threshold voltage Vth, the driving transistor DTFT is turned off, and the acquired threshold voltage Vth is stored in the first capacitor C1.

[0248] Timing t3 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=1, COBS1=0, COBS2=1

[0249] A low-potential active signal from the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, enabling low-potential coupling to the first node N1. The pull-down coupling of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, enabling negative voltage biasing of the driving transistor DTFT. A rising-edge high-potential signal from the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, enabling high-potential coupling between the first node N1 and the control terminal, thereby restoring the potentials of the first node N1 and the control terminal to the potentials indicated by the data voltage and the threshold voltage Vth.

[0250] A high-potential active signal from the second bias signal terminal COBS2 is provided to the second terminal of the driving transistor DTFT via the bias sub-circuit 104. This high-potential coupling of the second terminal enables a positive bias process for the second terminal of the driving transistor DTFT, thereby correcting the negative bias of the threshold voltage of the driving transistor.

[0251] Timing t4 stage: EM2=1, EM1=1, GateN1=0, GateN7=1, ResetH=1, Gate=0, COBS1=1, COBS2=0

[0252] The data writing sub-circuit 50 responds to the signal at the scan signal terminal Gate by providing the signal at the data signal terminal Vdata to the first or second terminal of the driving transistor DTFT. The turn-on control sub-circuit 20 responds to the signal at the turn-on control terminal GateN7 by providing the data voltage at the data signal terminal Vdata to the first node N1. The data voltage at the first node N1 and the threshold voltage Vth are provided to the control terminal of the driving transistor DTFT via the first capacitor C1.

[0253] Timing t5 stage: EM2=1, EM1=1, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=from 0 to 1 and then from 0 to 1 again, COBS2=from 1 to 0 and then from 1 to 0 again.

[0254] The second low-potential active signal of the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, which performs low-potential coupling on the first node N1. The pull-down coupling amount of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, which performs negative voltage bias on the driving transistor DTFT. The first rising edge high-potential signal of the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, which performs high-potential coupling on the first node N1 and the control terminal, so that the potential of the first node N1 and the control terminal is restored to the potential indicated by the data voltage and the threshold voltage Vth.

[0255] The third low-potential active signal of the first bias signal terminal COBS1 is provided to the first node N1 via the bias sub-circuit 101, which performs low-potential coupling on the first node N1. The pull-down coupling amount of the first node N1 is provided to the control terminal of the driving transistor DTFT via the first capacitor C1, which further performs negative voltage bias on the driving transistor DTFT. In order not to affect the writing of data voltage and threshold voltage Vth, the second rising edge high-potential signal of the first bias signal terminal COBS1 is provided to the control terminal of the first node N1 and the driving transistor DTFT via the bias sub-circuit 101, which performs high-potential coupling on the first node N1 and the control terminal, so that the potential of the first node N1 and the control terminal is restored to the potential indicated by data voltage and threshold voltage Vth.

[0256] The second high-potential active signal of the second bias signal terminal COBS2 is provided to the second terminal of the driving transistor DTFT through the bias sub-circuit 104, and the second terminal is coupled to a high potential for the first time, which is the positive bias process of the second terminal of the driving transistor DTFT.

[0257] The third high-potential active signal of the second bias signal terminal COBS2 is provided to the second terminal of the driving transistor DTFT through the bias sub-circuit 104, and the second terminal is coupled to a second high-potential, further performing a positive voltage bias process on the second terminal of the driving transistor DTFT.

[0258] Timing t6 stage: EM2=0, EM1=0, GateN1=0, GateN7=0, ResetH=1, Gate=1, COBS1=1, COBS2=0

[0259] In response to the signal from the first light-emitting control sub-circuit 30, the first power supply terminal VDD is turned on and the second terminal of the driving transistor DTFT is turned on. In response to the signal from the second light-emitting control terminal EM2, the second light-emitting control sub-circuit 60 is turned on and the first terminal of the driving transistor DTFT is turned on and the anode of the light-emitting device LED is turned on.

[0260] In this embodiment of the application, timing diagram 29 is applied to circuit connection diagram 26, and the resulting simulation diagram is shown in Figure 33.

[0261] Based on the same inventive concept, this disclosure provides a display device including any of the pixel driving circuits described above.

[0262] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0263] Based on the same inventive concept, this disclosure provides a driving method for a pixel driving circuit, as shown in Figure 34, including:

[0264] Step 201: In response to the signal from the turn-on control terminal GateN7, the turn-on control sub-circuit 20 turns on the first node N1 and the setting terminal of the driving transistor DTFT.

[0265] During implementation, when the signal of the gate control terminal GateN7 is valid, the conduction control sub-circuit 20 is turned on, and the first node N1 is turned on by the first or second terminal of the driving transistor DTFT through the conduction control sub-circuit 20.

[0266] Step 202: In response to the signal from the first light-emitting control terminal EM1, the first light-emitting control sub-circuit 30 provides the signal from the first power supply terminal VDD to the second terminal of the driving transistor DTFT.

[0267] During implementation, when the signal of the first light-emitting control terminal EM1 is valid, the first light-emitting control sub-circuit 30 is turned on, and the signal of the first power supply terminal VDD is provided to the second terminal of the driving transistor DTFT through the turned-on first light-emitting control sub-circuit 30.

[0268] Step 203: The bias sub-circuit couples the signal from the bias signal terminal to the first node N1, the first capacitor C1 provides the signal from the first node N1 to the control terminal of the driving transistor DTFT, and / or, the bias sub-circuit couples the signal from the bias signal terminal to at least one of the setting terminals of the driving transistor DTFT.

[0269] In the first implementation, the bias sub-circuit couples the negative bias signal of the bias signal terminal to the first node N1, and then the first capacitor C1 provides the signal of the first node N1 to the control terminal of the driving transistor DTFT.

[0270] In the second implementation, the bias sub-circuit couples the positive bias signal of the bias signal terminal to at least one of the first and second terminals of the driving transistor DTFT.

[0271] In the third implementation, the bias sub-circuit couples the negative bias signal from the bias signal terminal to the first node N1, and then the first capacitor C1 provides the signal from the first node N1 to the control terminal of the driving transistor DTFT. Simultaneously, the bias sub-circuit couples the positive bias signal from the bias signal terminal to at least one of the first and second terminals of the driving transistor DTFT.

[0272] In summary, the pixel driving circuit, display device, and driving method provided in this disclosure include: a driving transistor, a bias sub-circuit, a conduction control sub-circuit, a first capacitor, a first light-emitting control sub-circuit, and a light-emitting device; a first terminal of the driving transistor is coupled to the light-emitting device; the conduction control sub-circuit is coupled between a first node and a setting terminal of the driving transistor, and is configured to conduct the first node and the setting terminal of the driving transistor in response to a signal from the conduction control terminal, wherein the setting terminal is either the first terminal or the second terminal of the driving transistor; a first terminal of the first capacitor is coupled to the control terminal of the driving transistor, and a second terminal of the first capacitor is coupled to the first node; the first light-emitting device... The control sub-circuit is coupled between the first power supply terminal and the second terminal of the driving transistor, and is configured to provide the signal from the first power supply terminal to the second terminal of the driving transistor in response to the signal from the first light-emitting control terminal. The bias sub-circuit is coupled to the bias signal terminal, and is also coupled to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor, and is configured to couple the signal from the bias signal terminal to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor. The above-described biasing process of the driving transistor can correct the negative bias voltage of the threshold voltage of the driving transistor, thereby improving the characteristics of the driving transistor and making the display effect better.

[0273] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0274] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0275] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0276] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0277] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A pixel driving circuit, wherein, include: A driving transistor, a bias sub-circuit, a conduction control sub-circuit, a first capacitor, a first light-emitting control sub-circuit, and a light-emitting device; The first terminal of the driving transistor is coupled to the light-emitting device; The conduction control subcircuit is coupled between the first node and the setting terminal of the driving transistor, and is configured to conduct the first node and the setting terminal of the driving transistor in response to a signal from the conduction control terminal, wherein the setting terminal is the first terminal or the second terminal of the driving transistor. The first light-emitting control sub-circuit is coupled between the first power supply terminal and the second terminal of the driving transistor, and is configured to provide the signal from the first power supply terminal to the second terminal of the driving transistor in response to the signal from the first light-emitting control terminal. The first terminal of the first capacitor is coupled to the control terminal of the driving transistor, and the second terminal of the first capacitor is coupled to the first node. It is configured to store the data voltage and the threshold voltage of the driving transistor when the signal of the second light-emitting control terminal is valid. The bias sub-circuit is coupled to a bias signal terminal, and the bias sub-circuit is also coupled to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor, and is configured to couple the signal of the bias signal terminal to at least one of the first node, the control terminal of the driving transistor, and the setting terminal of the driving transistor.

2. The pixel driving circuit as described in claim 1, wherein, The bias sub-circuit is coupled to the first node, the bias signal terminal includes a first bias signal terminal, and the bias sub-circuit includes a second capacitor; The first end of the second capacitor is coupled to the first bias signal terminal, and the second end of the second capacitor is coupled to the first node.

3. The pixel driving circuit as described in claim 1, wherein, The bias sub-circuit is coupled to the control terminal of the driving transistor, the bias signal terminal includes a first bias signal terminal, and the bias sub-circuit includes a third capacitor. The first end of the third capacitor is coupled to the first bias signal terminal, and the second end of the third capacitor is coupled to the control terminal of the driving transistor.

4. The pixel driving circuit as described in claim 2 or 3, wherein, in, The effective signal at the first bias signal terminal is a negative voltage.

5. The pixel driving circuit as described in claim 1, wherein, The bias sub-circuit is coupled to the setting terminal of the driving transistor, the setting terminal being the first terminal of the driving transistor, the bias signal terminal including a second bias signal terminal, and the bias sub-circuit including a fourth capacitor. The first end of the fourth capacitor is coupled to the second bias signal terminal, and the second end of the fourth capacitor is coupled to the first end of the driving transistor.

6. The pixel driving circuit as described in claim 1, wherein, The bias sub-circuit is coupled to the setting terminal of the driving transistor, the setting terminal being the second terminal of the driving transistor, the bias signal terminal including the second bias signal terminal, and the bias sub-circuit including: a fifth capacitor; The first terminal of the fifth capacitor is coupled to the second bias signal terminal, and the second terminal of the fifth capacitor is coupled to the second terminal of the driving transistor.

7. The pixel driving circuit as described in claim 5 or 6, wherein, in, The effective signal at the second bias signal terminal is a positive voltage.

8. The pixel driving circuit according to any one of claims 1 to 7, wherein, The effective time of the signal at the bias signal terminal is activated after the effective time of the signal at the conduction control terminal is terminated. and / or The effective time of the bias signal terminal is activated after the effective time of the first reset control terminal signal terminates.

9. The pixel driving circuit according to any one of claims 1 to 8, wherein, The conduction control sub-circuit includes: a first switching transistor; The control terminal of the first switching transistor is coupled to the conduction control terminal, the first terminal of the first switching transistor is coupled to the first node, and the second terminal of the first switching transistor is coupled to the first terminal of the driving transistor.

10. The pixel driving circuit according to any one of claims 1 to 8, wherein, The conduction control sub-circuit includes: a second switching transistor; The control terminal of the second switching transistor is coupled to the conduction control terminal, the first terminal of the second switching transistor is coupled to the first node, and the second terminal of the second switching transistor is coupled to the second terminal of the driving transistor.

11. The pixel driving circuit according to any one of claims 1 to 10, wherein, The first light-emitting control sub-circuit includes: a third switching transistor; The control terminal of the third switching transistor is coupled to the first light-emitting control terminal, the first terminal of the third switching transistor is coupled to the first power supply terminal, and the second terminal of the third switching transistor is coupled to the second terminal of the driving transistor.

12. The pixel driving circuit according to any one of claims 1 to 11, wherein, It also includes a first reset circuit, which is coupled between the first initialization signal terminal and the control terminal of the driving transistor; The first reset sub-circuit is configured to provide the signal from the first initialization signal terminal to the control terminal of the driving transistor in response to the signal from the first reset control terminal.

13. The pixel driving circuit as described in claim 12, wherein, The first reset circuit includes: a fourth switching transistor; The control terminal of the fourth switching transistor is coupled to the first reset control terminal, the first terminal of the fourth switching transistor is coupled to the first initialization signal terminal, and the second terminal of the fourth switching transistor is coupled to the control terminal of the driving transistor.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein, It also includes a data writing sub-circuit, which is coupled between the setting terminal and the data signal terminal of the driving transistor; The data writing sub-circuit is configured to provide the signal from the data signal terminal to the setting terminal of the driving transistor in response to the signal from the scan signal terminal.

15. The pixel driving circuit as described in claim 14, wherein, The data writing sub-circuit includes: a fifth switching transistor; The control terminal of the fifth switching transistor is coupled to the scan signal terminal, the first terminal of the fifth switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the fifth switching transistor is coupled to the data signal terminal.

16. The pixel driving circuit as described in claim 14, wherein, The data writing sub-circuit includes: a sixth switching transistor; The control terminal of the sixth switching transistor is coupled to the scan signal terminal, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the data signal terminal.

17. The pixel driving circuit according to any one of claims 1 to 16, wherein, It also includes a second light-emitting control sub-circuit, which is coupled between the first terminal of the driving transistor and the anode of the light-emitting device; The second light-emitting control sub-circuit is configured to, in response to a signal from the second light-emitting control terminal, connect the first terminal of the driving transistor to the anode of the light-emitting device.

18. The pixel driving circuit as described in claim 17, wherein, The second light-emitting control sub-circuit includes: a seventh switching transistor; The control terminal of the seventh switching transistor is coupled to the second light-emitting control terminal, the first terminal of the seventh switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the anode of the light-emitting device.

19. The pixel driving circuit according to any one of claims 1 to 18, wherein, It also includes a second reset circuit, which is coupled between the anode of the light-emitting device and the second initialization signal terminal; The second reset sub-circuit is configured to provide the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the second reset control terminal.

20. The pixel driving circuit as described in claim 19, wherein, The second reset circuit includes: an eighth switching transistor; The control terminal of the eighth switching transistor is coupled to the second reset control terminal, the first terminal of the eighth switching transistor is coupled to the anode of the light-emitting device, and the second terminal of the eighth switching transistor is coupled to the second initialization signal terminal.

21. The pixel driving circuit according to any one of claims 1 to 20, wherein, It also includes a third reset circuit, which is coupled between the setting terminal and the third initialization signal terminal of the driving transistor, wherein the signal of the third initialization signal terminal is a negative voltage; The third reset sub-circuit is configured to provide the signal of the third initialization signal terminal to the setting terminal of the driving transistor in response to the signal of the third reset control terminal.

22. The pixel driving circuit as described in claim 21, wherein, The third reset circuit includes: a ninth switching transistor; The control terminal of the ninth switching transistor is coupled to the third reset control terminal, the first terminal of the ninth switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the ninth switching transistor is coupled to the third initialization signal terminal.

23. The pixel driving circuit as described in claim 21, wherein, The third reset circuit includes: a tenth switching transistor; The control terminal of the tenth switching transistor is coupled to the third reset control terminal, the first terminal of the tenth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the third initialization signal terminal.

24. The pixel driving circuit according to any one of claims 1 to 23, wherein, It also includes: the sixth capacitor; The first end of the sixth capacitor is coupled to the first node, and the second end of the sixth capacitor is coupled to the first power supply terminal.

25. The pixel driving circuit according to any one of claims 1 to 24, wherein, It also includes: the seventh capacitor; The first terminal of the seventh capacitor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh capacitor is coupled to the reference power supply terminal.

26. A display device, wherein, include: The pixel driving circuit as described in any one of claims 1 to 25.

27. A driving control method applied to a pixel driving circuit as described in any one of claims 1 to 25, wherein, include: The conduction control sub-circuit responds to the signal at the conduction control terminal and connects the first node to the setting terminal of the driving transistor. The first light-emitting control sub-circuit responds to the signal at the first light-emitting control terminal by providing the signal at the first power supply terminal to the second terminal of the driving transistor. The bias sub-circuit couples the signal from the bias signal terminal to the first node, the first capacitor provides the signal from the first node to the control terminal of the driving transistor, and / or, the bias sub-circuit couples the signal from the bias signal terminal to the control terminal of the driving transistor, and / or, the bias sub-circuit couples the signal from the bias signal terminal to the setting terminal of the driving transistor.

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