Circular buffer storage format that maximizes a quantity of shaped bits for multiple redundancy version index selections
Patent Information
- Application Number
- PCT/CN2025/079455
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2026-09-03
Smart Images

Figure CN2025079455_03092026_PF_FP_ABST
Abstract
Description
CIRCULAR BUFFER STORAGE FORMAT THAT MAXIMIZES A QUANTITY OF SHAPED BITS FOR MULTIPLE REDUNDANCY VERSION INDEX SELECTIONSFIELD OF THE DISCLOSURE
[0001] Aspects of the present disclosure generally relate to wireless communication and specifically relate to techniques, apparatuses, and methods associated with a circular buffer storage format that maximizes a quantity of shaped bits for multiple redundancy version index selections. DESCRIPTION OF THE RELATED TECHNOLOGY
[0002] Wireless communication systems are widely deployed to provide various services, which may involve carrying or supporting voice, text, other messaging, video, data, or other traffic. Typical wireless communication systems may employ multiple-access radio access technologies (RATs) capable of supporting communication among multiple wireless communication devices including user devices or other devices by sharing the available system resources (for example, time domain resources, frequency domain resources, spatial domain resources, or device transmit power, among other examples) . Such multiple-access RATs are supported by technological advancements that have been adopted in various telecommunication standards, which define common protocols that enable different wireless communication devices to communicate on a local, municipal, national, regional, or global level. An example telecommunication standard is New Radio (NR) . NR, which also may be referred to as 5G, is part of a continuous mobile broadband evolution promulgated by the Third Generation Partnership Project (3GPP) . As the demand for connectivity continues to increase, further improvements in NR may be implemented, and other RATs, such as 6G and beyond, may be introduced to enable new applications and facilitate new use cases.
[0003] Probabilistic amplitude shaping (PAS) is a technique used in wireless communication systems to improve the spectral efficiency and power efficiency of data transmission. In some examples, PAS leverages the concept of shaping the probability distribution of transmitted signal amplitudes to match the characteristics of the communication channel, often aligning with the channel’s capacity-achieving distribution. PAS may be associated with constellation shaping, such as by modifying the probability of the occurrence of constellation symbols. For example, instead of a transmitter transmitting all symbols with equal probability, a transmitter implementing PAS may bias the transmission to favor symbols with lower energy. This may reduce the average transmit power, which is beneficial for power-constrained systems. Additionally, or alternatively, PAS may align the transmitted signal’s distribution closer to the optimal distribution predicted by information theory, such as for a purpose of enabling a system to operate closer to the Shannon capacity limit and thus improving spectral efficiency, power efficiency, or a combination of the two. In some examples, PAS may be associated with bit-to-amplitude mapping techniques that may result in data bits being separated into shaped bits (e.g., bits with amplitude shaping) and unshaped bits (e.g., bits without amplitude shaping) .SUMMARY
[0004] The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
[0005] Some aspects described herein relate to a method of wireless communication performed by a transmitter. The method may include generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The method may include storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first redundancy version (RV) index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0006] Some aspects described herein relate to a method of wireless communication performed by a receiver. The method may include receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The method may include reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0007] Some aspects described herein relate to a non-transitory computer-readable medium that stores a set of instructions for wireless communication by a transmitter. The set of instructions, when executed by one or more processors of the transmitter, may cause the transmitter to generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping, store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0008] Some aspects described herein relate to a non-transitory computer-readable medium that stores a set of instructions for wireless communication by a receiver. The set of instructions, when executed by one or more processors of the receiver, may cause the receiver to receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The set of instructions, when executed by one or more processors of the receiver, may cause the receiver to reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0009] Some aspects described herein relate to a transmitter. The transmitter may include a processing system. The processing system may include one or more processors and one or more code-storing memories coupled with the one or more processors. The processing system may be configured to cause the transmitter to generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping, store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0010] Some aspects described herein relate to a receiver. The receiver may include a processing system. The processing system may include one or more processors and one or more code-storing memories coupled with the one or more processors. The processing system may be configured to cause the receiver to receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The processing system may be configured to cause the receiver to reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0011] Some aspects described herein relate to an apparatus for wireless communication. The apparatus may include means for generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The apparatus may include means for storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0012] Some aspects described herein relate to an apparatus for wireless communication. The apparatus may include means for receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The apparatus may include means for reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0013] Aspects of the present disclosure may generally be implemented by or as a method, apparatus, system, computer program product, non-transitory computer-readable medium, user equipment, network node, wireless communication device, or processing system as substantially described in the Detailed Description with reference to, and as illustrated by, the accompanying drawings. Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
[0014] While aspects and embodiments are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases may come about in many different arrangements and scenarios. Innovations described herein may be implemented across many differing platform types, devices, systems, shapes, sizes, packaging arrangements. For example, embodiments and / or uses may come about via integrated chip embodiments and other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc. ) . While some examples may or may not be specifically directed to use cases or applications, a wide assortment of applicability of described innovations may occur. Implementations may range in spectrum from chip-level or modular components to non-modular, non-chip-level implementations and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating described aspects and features may also necessarily include additional components and features for implementation and practice of claimed and described embodiments. For example, transmission and reception of wireless signals necessarily includes a number of components for analog and digital purposes (e.g., hardware components including antennas, RF-chains, power amplifiers, modulators, buffers, processor (s) , interleavers, adders / summers, etc. ) . It is intended that innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc. of varying sizes, shapes, and constitution.BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Fig. 1 is a diagram illustrating an example of a wireless communication network.
[0016] Fig. 2 is a diagram illustrating an example disaggregated network node architecture.
[0017] Figs. 3A and 3B are diagrams illustrating a first example of a probabilistic amplitude shaping (PAS) architecture and a second example of a partial PAS architecture.
[0018] Fig. 4 is a diagram illustrating an example of a rate matching block.
[0019] Fig. 5 is a diagram illustrating an example of redundancy version cycling that may be used as at least part of a hybrid automatic repeat request process.
[0020] Fig. 6 is a diagram illustrating an example of redundancy version (RV) index mapping relative to bit storage in a circular buffer.
[0021] Figs. 7A, 7B, and 7C are diagrams illustrating a first example of a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections, a second example of a pre-forward error correction (FEC) bit adjustment scheme, and a third example of a post-FEC bit adjustment scheme.
[0022] Figs. 8A, 8B, and 8C are diagrams illustrating a first example, a second example, and a third example of bit mapping for a sliding block permutation mapping inter-leaver matrix.
[0023] Figs. 9A and 9B are diagrams illustrating a first example and a second example, respectively, of receiver-side processing for reordered bits.
[0024] Fig. 10 is a diagram illustrating an example of a wireless communication process between a transmitter and a receiver.
[0025] Fig. 11 is a diagram illustrating an example process performed, for example, at a transmitter or an apparatus of a transmitter.
[0026] Fig. 12 is a diagram illustrating an example process performed, for example, at a receiver or an apparatus of a receiver.
[0027] Fig. 13 is a diagram of an example apparatus for wireless communication.
[0028] Fig. 14 is a diagram of an example apparatus for wireless communication.DETAILED DESCRIPTION
[0029] Probabilistic amplitude shaping (PAS) is a technique used in wireless communication systems to improve the spectral efficiency and power efficiency of data transmission. In some examples, PAS leverages the concept of shaping the probability distribution of transmitted signal amplitudes to match the characteristics of the communication channel, often aligning with the channel’s capacity-achieving distribution. PAS may be associated with constellation shaping, such as by modifying the probability of the occurrence of constellation symbols. For example, instead of a transmitter transmitting all symbols with equal probability, a transmitter implementing PAS may bias the transmission to favor symbols with lower energy. This may reduce the average transmit power, which is beneficial for power-constrained systems. Additionally, or alternatively, PAS may align the transmitted signal’s distribution closer to the optimal distribution predicted by information theory, such as for a purpose of enabling a system to operate closer to the Shannon capacity limit and thus improving spectral efficiency, power efficiency, or a combination of the two. In some examples, PAS may be associated with bit-to-amplitude mapping techniques that may result in data bits being separated into shaped bits (e.g., bits with amplitude shaping) and unshaped bits (e.g., bits without amplitude shaping) .
[0030] “Redundancy version” (RV) denotes a retransmission mechanism that increases a retransmission reliability. For instance, a hybrid automatic repeat request (HARQ) process may use forward error correction (FEC) based at least in part on a low-density parity-check (LDPC) code or polar encoding. A transmitter may store an original transmission that includes data bits and parity bits in a circular buffer. With regard to bits that are processed using PAS, the circular buffer may store shaped bits and unshaped bits. Based at least in part on a receiving device indicating a request for a retransmission, a transmitter may use an RV index and RV cycling to select a subset of the bits stored in the circular buffer. However, some RV indices may result in the transmitter selecting a subset of bits that include fewer shaped bits than available for the retransmission, resulting in a transmission that has reduced power efficiency, reduced spectral efficiency, or a combination of the two, relative to a power efficiency, a spectral efficiency, or a combination of the two, for a transmission that includes more shaped bits. Reduced power efficiency may shorten a battery life for some devices, and reduced spectral efficiency may result in reduced data throughput, increased data transfer latencies, or a combination of the two, in a wireless network.
[0031] Various aspects relate generally to a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV selections. Some aspects more specifically relate to a transmitter storing PAS-based encoded bits in a circular buffer using a storage format that increases a number of shaped bits that are included in a subset of bits. In some aspects, a transmitter (e.g., a user equipment (UE) or a network node) may generate encoded bits based at least in part on PAS such that the encoded bits include one or more shaped bits, one or more unshaped bits, and one or more parity bits. The transmitter may store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are asssociated with a second RV index selection. An example of a first RV index selection may be a first selection that is based at least in part on an RV index 0 (RV0) , and an example of a second RV index selection may be a second selection that is based at least in part on an RV index 3 (RV3) .
[0032] Particular aspects of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some examples, by using a circular buffer storage format that maximizes a quantity of shaped bits in multiple subsets of bits that are based at least in part on respective RV indices, the described techniques can be used to enable a transmitter to generate a transmission that includes more shaping bits and, consequently, generate a transmission that increases power efficiency, increases spectral efficiency, or a combination of both. To illustrate, including more shaped bits may reduce an average transmit power level for a transmission, may enable the use of a higher MCS for the transmission, or a combination of the two, resulting in increased power efficiency, increased spectral efficiency, or a combination of the two. Increased power efficiency may extend a battery life for some devices, and increased spectral efficiency may result in increased data throughput, reduced data transfer latencies, or a combination of the two.
[0033] 5G New Radio (NR) may support enhanced mobile broadband (eMBB) access, Internet of Things (IoT) networks or reduced capability (RedCap) device deployments, ultra-reliable low-latency communication (URLLC) applications, or massive machine-type communication (mMTC) , among other examples. To support these and other target verticals, a wireless communication system may be designed to implement a modularized functional infrastructure, a disaggregated and service-based network architecture, network function virtualization, network slicing, multi-access edge computing, millimeter wave (mmWave) technologies including massive multiple-input multiple-output (MIMO) , beamforming, IoT device or RedCap device connectivity and management, industrial connectivity, licensed and unlicensed spectrum access, sidelink and other device-to-device direct communication (for example, cellular vehicle-to-everything (CV2X) communication) , frequency spectrum expansion, overlapping spectrum use, small cell deployments, non-terrestrial network (NTN) deployments, device aggregation, advanced duplex communication (for example, sub-band full-duplex (SBFD) ) , multiple-subscriber implementations, high-precision positioning, radio frequency (RF) sensing, network energy savings (NES) , low-power signaling and radios, or artificial intelligence or machine learning (AI / ML) , among other examples.
[0034] The foregoing and other technological improvements may support use cases, such as wireless fronthauls, wireless midhauls, wireless backhauls, wireless data centers, extended reality (XR) and metaverse applications, meta services for supporting vehicle connectivity, holographic and mixed reality communication, autonomous and collaborative robots, vehicle platooning and cooperative maneuvering, sensing networks, gesture monitoring, human-brain interfacing, digital twin applications, asset management, and universal coverage applications using non-terrestrial or aerial platforms, among other examples.
[0035] The methods, operations, apparatuses, and techniques described herein may enable one or more of the foregoing technologies or new technologies or support one or more of the foregoing use cases or new use cases.
[0036] Fig. 1 is a diagram illustrating an example of a wireless communication network 100. The wireless communication network 100 may be or may include elements of a 5G network or a 6G network, among other examples. The wireless communication network 100 may include multiple network nodes 110. For example, in Fig. 1, the wireless communication network 100 includes multiple network nodes 110, including a network node 110a and a network node 110b (each of which also may be referred to herein simply as a “network node 110” ) . The network nodes 110 may support communications with multiple UEs 120. For example, in Fig. 1, the network nodes 110 support communication with a UE 120a, a UE 120b, and a UE 120c (each of which also may be referred to herein simply as a “UE 120” ) . In some examples, a UE 120 also may communicate with other UEs 120 and a network node 110 also may communicate with a core network and with other network nodes 110.
[0037] The network nodes 110 and the UEs 120 of the wireless communication network 100 communicate using the electromagnetic spectrum, which may be subdivided into various licensed or unlicensed operating bands, frequency ranges, component carriers, or channels that define associated frequencies available for communications. In some examples, each of the network nodes 110 and the UEs 120 may communicate using one or multiple component carriers in one or more operating bands or ranges. Typically, various operating bands are defined as frequency range designations FR1 (410 MHz through 7.125 GHz) , FR2 (24.25 GHz through 52.6 GHz) , FR3 (7.125 GHz through 24.25 GHz) , FR4a or FR4-1 (52.6 GHz through 71 GHz) , FR4 (52.6 GHz through 114.25 GHz) , and FR5 (114.25 GHz through 300 GHz) . Although a portion of FR1 is greater than 6 GHz, FR1 is often referred to (interchangeably) as a “sub-6 GHz” band in some documents and articles. Similarly, FR2 is often referred to (interchangeably) as a “millimeter wave” band in some documents and articles.
[0038] A network node 110 or a UE 120 may include one or more devices, components, or systems that enable communication with other devices, components, or systems of the wireless communication network 100. For example, a UE 120 and a network node 110 may each include one or more chips, system-on-chips (SoCs) , chipsets, packages, or devices that individually or collectively constitute or comprise a processing system. As shown in Fig. 1, each UE 120 includes a processing system 140 and each network node 110 includes a processing system 145. A processing system (for example, the processing system 140 or the processing system 145) includes processor (or “processing” ) circuitry in the form of one or multiple processors, microprocessors, processing units (such as central processing units (CPUs) , graphics processing units (GPUs) , neural processing units (NPUs) (also referred to as neural network processors or deep learning processors (DLPs) ) , or digital signal processors (DSPs) ) , processing blocks, application-specific integrated circuits (ASICs) , programmable logic devices (PLDs) , or other discrete gate or transistor logic or circuitry (any one or more of which may be generally referred to herein individually as a “processor” or collectively as “the processor” or “the processor circuitry” ) . Such processors may be individually or collectively configurable or configured to perform various functions or operations described herein. A group of processors collectively configurable or configured to perform a set of functions may include a first processor configurable or configured to perform a first function of the set and a second processor configurable or configured to perform a second function of the set. In some other examples, each of a group of processors may be configurable or configured to perform a same set of functions.
[0039] The processing system 140 and the processing system 145 may each include memory circuitry in the form of one or multiple memory devices, memory blocks, memory elements, or other discrete gate or transistor logic or circuitry, each of which may include or implement tangible storage media, such as random-access memory, or read-only memory, or combinations thereof (any one or more of which may be generally referred to herein individually as a “memory” or collectively as “the memory” or “the memory circuitry” ) . One or more of the memories may be coupled (for example, operatively coupled, communicatively coupled, electronically coupled, or electrically coupled) with one or more of the processors. One or more of the memories may individually or collectively store processor-executable code or instructions (such as software) (for example, which may be referred to as “one or more code-storing memories” or “code-storing memory circuitry” ) . For example, “code-storing memory” or “code-storing memory circuitry” refers to memory (or memory circuitry) that is configured to store processor-executable code or instructions. The processor-executable code or instructions, when executed by one or more of the processors, may configure one or more of the processors (or processing circuitry) to perform various functions or operations described herein. Additionally, or alternatively, in some examples, one or more of the processors may be configured to perform various functions or operations described herein without requiring configuration by software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, or functions, among other examples, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
[0040] The processing system 140 and the processing system 145 may each include or be coupled with one or more modems (such as a cellular (for example, a 5G or 6G compliant) modem) . In some examples, one or more processors of the processing system 140 or the processing system 145 may include or implement one or more of the modems. The processing system 140 and the processing system 145 also may include or be coupled with multiple radios (collectively “the radio” ) , multiple RF chains, or multiple transceivers, each of which may in turn be coupled with one or more of multiple antennas. In some examples, one or more processors of the processing system 140 or the processing system 145 may include or implement one or more of the radios, RF chains, or transceivers. An RF chain may include one or more filters, mixers, oscillators, amplifiers, analog-to-digital converters (ADCs) , or other devices that convert between an analog signal (such as for transmission or reception via an air interface) and a digital signal (such as for processing by the processing system 140 or by the processing system 145) .
[0041] A network node 110 and a UE 120 may each include one or multiple antennas or antenna arrays. Typical network nodes 110 and UEs 120 may include multiple antennas, which may be organized or structured into one or more antenna panels, one or more antenna groups, one or more sets of antenna elements, or one or more antenna arrays, among other examples. As used herein, the term “antenna” can refer to one or more antennas, one or more antenna panels, one or more antenna groups, one or more sets of antenna elements, or one or more antenna arrays. The term “antenna panel” can refer to a group of antennas (such as antenna elements) arranged in an array or panel, which may facilitate beamforming by manipulating parameters associated with the group of antennas. The term “antenna module” may refer to circuitry including one or more antennas as well as one or more other components (such as filters, amplifiers, or processors) associated with integrating the antenna module into a wireless communication device, such as the network node 110 and the UE 120.
[0042] A network node 110 may be, may include, or also may be referred to as an NR network node, a 5G network node, a 6G network node, a Node B, a gNB, an access point (AP) , a transmission reception point (TRP) , a network entity, a network element, a network equipment, or another type of device, component, or system included in a radio access network (RAN) . In various deployments, a network node 110 may be implemented as a single physical node (for example, a single physical structure) or may be implemented as two or more physical nodes (for example, two or more distinct physical structures) . For example, a network node 110 may be a device or system that implements a part of a radio protocol stack, a device or system that implements a full radio protocol stack (such as a full gNB protocol stack) , or a collection of devices or systems that collectively implement the full radio protocol stack. For example, and as shown, a network node 110 may be an aggregated network node having an aggregated architecture, meaning that the network node 110 may implement a full radio protocol stack that is physically and logically integrated within a single physical structure in the wireless communication network 100. For example, an aggregated network node 110 may include a single standalone base station or a single TRP that operates with a full radio protocol stack to enable or facilitate communication between a UE 120 and a core network of the wireless communication network 100.
[0043] Alternatively, and as also shown, a network node 110 may be a disaggregated network node 110 (sometimes referred to as a disaggregated base station) , having a disaggregated architecture, meaning that the network node 110 may operate with a radio protocol stack that is physically distributed or logically distributed among two or more nodes in the same geographic location or in different geographic locations. In some deployments, disaggregated network nodes 110 may be used in an integrated access and backhaul (IAB) network, in an open radio access network (O-RAN) (such as a network configuration in compliance with the O-RAN Alliance) , or in a virtualized radio access network (vRAN) , also known as a cloud radio access network (C-RAN) , to facilitate scaling by separating network functionality into multiple units or modules that can be individually deployed.
[0044] The disaggregated network nodes 110 of the wireless communication network 100 may include one or more central units (CUs) , one or more distributed units (DUs) , and one or more radio units (RUs) . A CU may host one or more higher layers, such as a radio resource control (RRC) layer, a packet data convergence protocol (PDCP) layer, and a service data adaptation protocol (SDAP) layer, among other examples. A DU may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, or one or more higher physical (PHY) layers depending, at least in part, on a functional split, such as a functional split defined by the 3GPP. In some examples, a DU also may host a lower PHY layer that is configured to perform functions, such as a fast Fourier transform (FFT) , an inverse FFT (IFFT) , beamforming, or physical random access channel (PRACH) extraction and filtering, among other examples. An RU may perform RF processing functions or lower PHY layer functions, such as an FFT, an IFFT, beamforming, or PRACH extraction and filtering, among other examples, according to a functional split, such as a lower layer split (LLS) . In such an architecture, each RU can be operated to handle over the air (OTA) communication with one or more UEs 120. In some examples, a single network node 110 may include a combination of one or more CUs, one or more DUs, or one or more RUs. In some examples, a CU, a DU, or an RU may be implemented as a virtual unit, such as a virtual central unit (VCU) , a virtual distributed unit (VDU) , or a virtual radio unit (VRU) , among other examples, which may be implemented as a virtual network function, such as in a cloud deployment.
[0045] In some examples, the wireless communication network 100 may be a heterogeneous network that includes network nodes 110 of various types. Different types of network nodes 110 may generally operate on the same or different operating bands, transmit at different power levels, or serve different coverage areas, each of which may be referred to as or associated with a particular cell 130 (for example, a cell 130a and a cell 130b) .
[0046] The UEs 120 may be physically dispersed throughout the coverage area of the wireless communication network 100, and each UE 120 may be stationary or mobile. A UE 120 may be, may include, or also may be referred to as an access terminal, a mobile station, a client device, or a subscriber unit. A UE 120 may be, include, or be coupled with a cellular phone (for example, a smart phone) , a personal digital assistant (PDA) , a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless phone, a wireless local loop (WLL) station, a tablet, a camera, a netbook, a smartbook, an ultrabook, a medical device, a biometric device, a wearable device (for example, a smart watch, smart clothing, smart glasses, a smart wristband, or smart jewelry) , a gaming device, an entertainment device (for example, a music device, a video device, or a satellite radio) , an XR device, a vehicular component or sensor, a smart meter or sensor, industrial manufacturing equipment, a Global Navigation Satellite System (GNSS) device (such as a Global Positioning System device or another type of positioning device) , an artificially intelligent robot or other device implementing artificial intelligence, a UE function of a network node, or any other suitable device or function that may communicate in the wireless communication network 100.
[0047] Some UEs 120 may be classified according to different categories in association with different complexities or different capabilities. UEs 120 in a first category may be associated with relatively low complexity or cost such as NB-IoT devices or eMTC UEs. UEs 120 in a second category may include higher complexity or cost devices, such as mission-critical IoT devices, baseline UEs, high-tier UEs, advanced UEs, full-capability UEs, or premium UEs that are capable of URLLC, eMBB, or precise positioning in the wireless communication network 100. A third category of UEs 120 may have mid-tier complexity or capabilities (for example, capabilities between that of the UEs 120 of the first category and the UEs 120 of the second category) . A UE 120 of the third category may be referred to as a reduced capability UE ( “RedCap UE” ) , a mid-tier UE, an NR-Light UE, or an NR-Lite UE, among other examples.
[0048] In some examples, a network node 110 may be, may include, or may operate as an RU, a TRP, or a base station that communicates with one or more UEs 120 via a radio access link (which may be referred to as a “Uu” link) . The radio access link may include a downlink and an uplink. “Downlink” (or “DL” ) refers to a communication direction from a network node 110 to a UE 120, and “uplink” (or “UL” ) refers to a communication direction from a UE 120 to a network node 110. Downlink and uplink resources may include time domain resources (for example, frames, subframes, slots, and symbols) , frequency domain resources (for example, frequency bands, component carriers (CCs) , subcarriers, resource blocks, and resource elements) , and spatial domain resources (for example, particular transmit directions or beams) .
[0049] Frequency domain resources may be subdivided into bandwidth parts (BWPs) . A BWP may be a block of frequency domain resources (for example, a continuous set of resource blocks (RBs) within a full component carrier bandwidth) that may be configured at a UE-specific level. A UE 120 may be configured with both an uplink BWP and a downlink BWP (which may be the same or different) . Each BWP may be associated with its own numerology (indicating a sub-carrier spacing (SCS) and cyclic prefix (CP) ) . A BWP may be dynamically configured or activated (for example, by a network node 110 transmitting a downlink control information (DCI) configuration to the one or more UEs 120) or reconfigured (for example, in real-time or near-real-time) according to changing network conditions in the wireless communication network 100 or specific requirements of one or more UEs 120. An active BWP defines the operating bandwidth of the UE 120 within the operating bandwidth of the serving cell.
[0050] As used herein, a downlink signal may be or include a reference signal, control information, or data. For example, downlink reference signals include a primary synchronization signal (PSS) , a secondary SS (SSS) , an SS block (SSB) (for example, that includes a PSS, an SSS, and a physical broadcast channel (PBCH) ) , a demodulation reference signal (DMRS) , a phase tracking reference signal (PTRS) , a tracking reference signal (TRS) , and a channel state information (CSI) reference signal (CSI-RS) , among other examples. A downlink signal carrying control information or data may be transmitted via a downlink channel. Downlink channels may include one or more control channels for transmitting control information and one or more data channels for transmitting data. Downlink reference signals may be transmitted in addition to, or multiplexed with, downlink control channel communications or downlink data channel communications. A downlink control channel may be specifically used to transmit DCI from a network node 110 to a UE 120. DCI generally contains the information the UE 120 needs to identify RBs in a subsequent subframe and how to decode them, including a modulation and coding scheme (MCS) or redundancy version parameters. Different DCI formats carry different information, such as scheduling information in the form of downlink or uplink grants, slot format indicators (SFIs) , preemption indicators (PIs) , transmit power control (TPC) commands, hybrid automatic repeat request (HARQ) information, new data indicators (NDIs) , among other examples. A downlink data channel may be used to transmit downlink data (for example, user data associated with a UE 120) from a network node 110 to a UE 120. Downlink control channels may include physical downlink control channels (PDCCHs) , and downlink data channels may include physical downlink shared channels (PDSCHs) . Control information or data communications may be transmitted on a PDCCH and PDSCH, respectively. For example, a PDCCH can carry DCI, while a PDSCH can carry a MAC control element (CE) , an RRC message, or user data, among other examples. Each PDSCH may carry one or more transport blocks (TBs) of data.
[0051] As used herein, an uplink signal may include a reference signal, control information, or data. For example, uplink reference signals include a sounding reference signal (SRS) , a PTRS, and a DMRS, among other examples. An uplink signal carrying control information or data may be transmitted via an uplink channel. An uplink channel may include one or more control channels for transmitting control information and one or more data channels for transmitting data. Uplink reference signals may be transmitted in addition to, or multiplexed with, uplink control channel communications or uplink data channel communications. An uplink control channel may be specifically used to transmit uplink control information (UCI) from a UE 120 to a network node 110. An uplink data channel may be used to transmit uplink data (for example, user data associated with a UE 120) from a UE 120 to a network node 110. Uplink control channels may include physical uplink control channels (PUCCHs) , and uplink data channels may include physical uplink shared channels (PUSCHs) . Control information or data communications may be transmitted on a PUCCH and PUSCH, respectively. For example, a PUCCH can carry UCI, while a PUSCH can carry a MAC-CE, an RRC message, or user data, among other examples. UCI can include a scheduling request (SR) , HARQ feedback information (for example, a HARQ acknowledgement (ACK) indication or a HARQ negative acknowledgement (NACK) indication) , uplink power control information (for example, an uplink TPC parameter) , or CSI, among other examples. CSI can include a channel quality indicator (CQI) (indicative of downlink channel conditions to facilitate selection of transmission parameters, such as an MCS, by a network node 110) , a precoding matrix indicator (PMI) , a CSI-RS resource indicator (CRI) (for example, indicative of a beam used to transmit a CSI-RS) , an SS / PBCH resource block indicator (SSBRI) (for example, indicative of a beam used to transmit an SSB) , a layer indicator (LI) , a rank indicator (RI) , or measurement information (for example, a layer 1 (L1) -reference signal received power (RSRP) parameter, a received signal strength indicator (RSSI) parameter, a reference signal received quality (RSRQ) parameter, among other examples) which can be used for beam management, among other examples. Each PUSCH may carry one or more TBs of data.
[0052] The information (for example, data, control information, or reference signal information) transmitted by a network node 110 to a UE 120, or vice versa, may be represented as a sequence of binary bits that are mapped (for example, modulated) to an analog signal waveform (for example, a discrete Fourier transform (DFT) -spread-orthogonal frequency division multiplexing (OFDM) (DFT-s-OFDM) waveform or a CP-OFDM waveform) that is transmitted by the network node 110 or UE 120 over a wireless communication channel. In some examples, the network node 110 or the UE 120 (for example, using the processing system 145 or the processing system 140, respectively) may select an MCS (for example, an order of quadrature amplitude modulation (QAM) , such as 64-QAM, 128-QAM, or 256-QAM, among other examples) for a downlink signal or an uplink signal. For example, the network node 110 may select an MCS for a downlink signal in accordance with UCI received from the UE 120 or may transmit, to the UE 120, an indication of an MCS to be applied for an uplink signal.
[0053] A network node 110 or a UE 120 (such as by using the processing system 145 or the processing system 140, respectively, or one or more coupled modems) may perform signal processing on the information (such as filtering, amplification, modulation, digital-to-analog conversion, an IFFT operation, multiplexing, interleaving, mapping, or encoding, among other examples) to generate a processed signal in accordance with the selected MCS. In some examples, the network node 110 or the UE 120 (for example, using the processing system 145 or the processing system 140, respectively, or one or more coupled encoders or modems) may perform a channel coding operation or a forward error correction (FEC) operation to control errors in transmitted information. For example, the network node 110 or the UE 120 may perform an encoding operation to generate encoded information (such as by selectively introducing redundancy into the information, typically using an error correction code (ECC) , such as a polar code or a low-density parity-check (LDPC) code) . The network node 110 or the UE 120 (for example, using the processing system 145 or one or more modems) may further perform spatial processing (for example, precoding) on the encoded information to generate one or more processed or precoded signals for downlink or uplink transmission, respectively. In some examples, the network node 110a or the UE 120a may perform codebook-based precoding or non-codebook-based precoding. Codebook-based precoding may involve selecting a precoder (for example, a precoding matrix) using a codebook. For example, the network node 110a may provide precoding information indicating which precoder, defined by the codebook, is to be used by the UE 120a. Non-codebook-based precoding may involve selecting or deriving a precoder based on, or otherwise associated with, one or more downlink or uplink signal measurements. The network node 110a or the UE 120a may transmit the processed downlink or uplink signals, respectively, via one or more antennas.
[0054] The network node 110a or the UE 120a may receive uplink signals or downlink signals, respectively, via one or more antennas. The network node 110a or the UE 120a (for example, using the processing system 145 or the processing system 140, respectively, or one or more coupled modems) may perform signal processing (for example, in accordance with the MCS) on the received uplink or downlink signals, respectively (such as filtering, amplification, demodulation, analog-to-digital conversion, an FFT operation, demultiplexing, deinterleaving, de-mapping, equalization, interference cancellation, or decoding, among other examples) , to map the received signal (s) to a sequence of binary bits (for example, received information) that estimates the information transmitted by the network node 110 or the UE 120 via the downlink or uplink signals. The network node 110a or the UE 120a (for example, using the processing system 145 or the processing system 140, respectively, or a coupled decoder or one or more modems) may decode the received information (such as by using an ECC, a decoding operation, or an FEC operation) to detect errors or correct bit errors in the received information to generate decoded information. The decoded information may estimate the information transmitted via the downlink or uplink signals.
[0055] In some examples, a UE 120 and a network node 110 may perform MIMO communication. MIMO communication generally refers to transmitting or receiving multiple signals (such as multiple layers or multiple data streams) simultaneously over the same time and frequency resources. A network node 110 or a UE 120 may communicate using single-user MIMO or multi-user MIMO (MU-MIMO) , the latter of which being used by a network node 110 to simultaneously transmit signals to multiple UEs 120. MIMO techniques may involve spatial multiplexing (multi-layer transmission) or beamforming. To implement beamforming, the amplitudes or phases of signals transmitted via antenna elements may be modulated and shifted relative to each other (such as by manipulating a phase shift, a phase offset, or an amplitude) to generate one or more beams. For example, a network node 110 may generate one or more beams 160a, and a UE 120 may generate one or more beams 160b. The term “beam” may refer to a directional transmission of a wireless signal toward a receiving device or otherwise in a desired direction, a directional reception of a wireless signal from a transmitting device or otherwise in a desired direction, a direction associated with such a directional transmission or directional reception, a set of directional resources associated with a signal transmission or signal reception (for example, an angle of arrival, a horizontal direction, or a vertical direction) , or a set of parameters or resources associated with one or more aspects of a directional signal, among other examples.
[0056] In some examples, a network node 110 or a UE 120 may implement massive MIMO, which may be associated with an increased (for example, “massive” ) quantity of antennas at the network node 110 or at the UE 120, such as in a network implementing mmWave technology, which enables more precise beamforming or reduced interference. In some examples, the wireless communication network 100 may implement multi-TRP (mTRP) operation (including redundant transmission or reception on multiple TRPs) or non-coherent joint transmission (NC-JT) .
[0057] The network node 110 and the UE 120 may establish a communication link or beam pair, and otherwise increase reliability, throughput, signal strength, or other signal properties for MIMO communications, by performing beam management operations, such as an initial beam acquisition operation, a beam refinement operation, or a beam recovery operation. For example, an initial beam acquisition operation may involve the network node 110 transmitting signals (for example, SSBs or other signals) via respective beams (for example, of the beams 160 of the network node 110) and the UE 120 receiving and measuring the signal (s) via respective beams of multiple beams (for example, from the beams 160 of the UE 120) to identify a best beam (or beam pair) for communication between the UE 120 and the network node 110. A beam refinement operation may involve a first device (for example, the UE 120 or the network node 110) transmitting signal (s) via a subset of beams (for example, identified based on, or otherwise associated with, measurements reported as part of one or more other beam management operations) . A second device (for example, the network node 110 or the UE 120) may receive the signal (s) via a single beam (for example, to identify the best beam for communication from the subset of beams) . The beam (s) may be identified or defined via one or more spatial parameters, such as a transmission configuration indicator (TCI) state or a quasi co-location (QCL) parameter, among other examples.
[0058] Some aspects and techniques as described herein may be implemented, at least in part, using an artificial intelligence (AI) program (for example, referred to herein as an “AI / ML model” ) , such as a program that includes a machine learning (ML) model or an artificial neural network (ANN) model. The AI / ML model may be deployed at one or more devices 165 (for example, one or more network nodes 110, one or more UEs 120, one or more servers, or one or more components of a cloud computing network, among other examples) . For example, in a deployment in which AI / ML functionality is performed independently at a device 165, sometimes referred to as “overlay AI / ML, ” the AI / ML model (or an instance or portion of the AI / ML model) may be deployed at a UE 120 (for example, by the processing system 140) , a network node 110 (for example, by the processing system 145) , one or more servers, or one or more components of a cloud computing network, among other examples. Additionally, or alternatively, in a deployment where AI / ML functionality is coordinated between different devices 165, sometimes referred to as “coordinated AI / ML, ” or performed at all device and network layers, sometimes referred to as “native AI / ML, ” the AI / ML model (or an instance of the AI / ML model) may be deployed at multiple devices 165 (for example, a first portion of the AI / ML model may be deployed at a UE 120 and a second portion of the AI / ML model may be deployed at a network node 110) . In other examples of coordinated AI / ML or native AI / ML, a first AI / ML model may be deployed at a UE 120 and a second AI / ML model may be deployed at a network node 110. The AI / ML model (s) may be configured to enhance various aspects of the wireless communication network 100 (for example, to increase privacy, reliability, or efficient use of network bandwidth, or to reduce latency, among other examples) . For example, the AI / ML model (s) may be trained to identify patterns or relationships in data corresponding to the wireless communication network 100, a device, or an air interface, among other examples. The AI / ML model (s) may support operational decisions relating to one or more aspects associated with wireless communications devices, networks, or services.
[0059] Accordingly, in some examples, the AI / ML model (s) may enable AI-as-a-Service (for example, an end-to-end AI / ML service via a user plane) for use cases, such as a self-organizing network (SON) , minimization of drive test (MDT) , quality of experience (QoE) , positioning, sensing, predictive mobility, or traffic prediction, among other examples. In some examples, AI-as-a-Service use cases may include measurement collection reporting by a UE 120, device selection criteria (for example, according to a geographical area where measurements are to be collected or UE capabilities to be used to collected measurements) , or reporting configurations (for example, reporting parameters such as location, time, or sensor information, among other examples) . Additionally, or alternatively, the AI / ML model (s) may enable AI / ML procedures (for example, RAN-triggered service establishment, configuration, inferencing using UE-side or network-side models, performance monitoring or management, or capability signaling, among other examples) . Additionally, or alternatively, the AI / ML model (s) may enable RAN-based AI / ML services via one or more application program interfaces (APIs) or management interfaces for use cases, such as beam management, radio resource monitoring (RRM) relaxation, mobility prediction, load prediction, network energy savings, or coverage and capacity improvements, among other examples) .
[0060] In some aspects, a network node (e.g., a network node 110) may include a communication manager 155. Based at least in part on the network node being a transmitter, the communication manager 155 may generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0061] Alternatively, or additionally, based at least in part on the network node being a receiver, the communication manager 155 may receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission. Additionally, or alternatively, the communication manager 155 may perform one or more other operations described herein
[0062] In some aspects, a UE (e.g., a UE 120) may include a communication manager 150. As described in more detail elsewhere herein, based at least in part on the UE being a transmitter, the communication manager 150 may generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0063] Alternatively, or additionally, based at least in part on the UE being a receiver, the communication manager 150 may receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission. Additionally, or alternatively, the communication manager 150 may perform one or more other operations described herein.
[0064] Fig. 2 is a diagram illustrating an example disaggregated network node architecture 200. One or more components of the example disaggregated network node architecture 200 may be, may include, or may be included in one or more network nodes (such one or more network nodes 110) . The disaggregated network node architecture 200 may include a CU 210 that can communicate directly with a core network 220 via a backhaul link, or that can communicate indirectly with the core network 220 via one or more disaggregated control units, such as a non-real-time (Non-RT) RAN intelligent controller (RIC) 250 associated with a Service Management and Orchestration (SMO) Framework 260 or a near-real-time (Near-RT) RIC 270 (for example, via an E2 link) . The CU 210 may communicate with one or more DUs 230 via respective midhaul links, such as via F1 interfaces. Each of the DUs 230 may communicate with one or more RUs 240 via respective fronthaul links. Each of the RUs 240 may communicate with one or more UEs 120 via respective RF access links. In some deployments, a UE 120 may be simultaneously served by multiple RUs 240.
[0065] Each of the components of the disaggregated network node architecture 200, including the CUs 210, the DUs 230, the RUs 240, the Near-RT RICs 270, the Non-RT RICs 250, and the SMO Framework 260, may include one or more interfaces or may be coupled with one or more interfaces for transmitting or receiving signals, such as data, control information, or reference signals via a wired or wireless transmission medium.
[0066] In some aspects, the CU 210 may be logically split into one or more CU user plane (CU-UP) units and one or more CU control plane (CU-CP) units. A CU-UP unit may communicate bidirectionally with a CU-CP unit via an interface, such as the E1 interface when implemented in an O-RAN configuration. The CU 210 may be deployed to communicate with one or more DUs 230, as necessary, for network control and signaling. Each DU 230 may correspond to a logical unit that includes one or more base station functions to control the operation of one or more RUs 240. For example, a DU 230 may host various layers, such as an RLC layer, a MAC layer, or one or more PHY layers, such as one or more high PHY layers or one or more low PHY layers. Each layer (which also may be referred to as a module) may be implemented with an interface for communicating signals with other layers (and modules) hosted by the DU 230, or for communicating signals with the control functions hosted by the CU 210. Each RU 240 may implement lower layer functionality. In some aspects, real-time and non-real-time aspects of control and user plane communication with the RU (s) 240 may be controlled by the corresponding DU 230.
[0067] The SMO Framework 260 may support RAN deployment and provisioning of non-virtualized and virtualized network elements. For non-virtualized network elements, the SMO Framework 260 may support the deployment of dedicated physical resources for RAN coverage requirements, which may be managed via an operations and maintenance interface, such as an O1 interface. For virtualized network elements, the SMO Framework 260 may interact with a cloud computing platform (such as an open cloud (O-Cloud) platform 290) to perform network element life cycle management (such as to instantiate virtualized network elements) via a cloud computing platform interface, such as an O2 interface. A virtualized network element may include, but is not limited to, a CU 210, a DU 230, an RU 240, a non-RT RIC 250, or a Near-RT RIC 270. In some aspects, the SMO Framework 260 may communicate with a hardware aspect of a 4G RAN, a 5G NR RAN, or a 6G RAN, such as an open eNB (O-eNB) 280, via an O1 interface. Additionally, or alternatively, the SMO Framework 260 may communicate directly with each of one or more RUs 240 via a respective O1 interface. In some deployments, this configuration can enable each DU 230 and the CU 210 to be implemented in a cloud-based RAN architecture, such as a vRAN architecture.
[0068] The Non-RT RIC 250 may include or may implement a logical function that enables non-real-time control and optimization of RAN elements and resources, AI / ML workflows including model training and updates, or policy-based guidance of applications or features in the Near-RT RIC 270. The Non-RT RIC 250 may be coupled to or may communicate with (such as via an A1 interface) the Near-RT RIC 270. The Near-RT RIC 270 may include or may implement a logical function that enables near-real-time control and optimization of RAN elements and resources via data collection and actions via an interface (such as via an E2 interface) connecting one or more CUs 210, one or more DUs 230, or an O-eNB 280 with the Near-RT RIC 270. In some aspects, to generate AI / ML models to be deployed in the Near-RT RIC 270, the Non-RT RIC 250 may receive parameters or external enrichment information from external servers. Such information may be utilized by the Near-RT RIC 270 and may be received at the SMO Framework 260 or the Non-RT RIC 250 from non-network data sources or from network functions. In some examples, the Non-RT RIC 250 or the Near-RT RIC 270 may tune RAN behavior or performance. For example, the Non-RT RIC 250 may monitor long-term trends and patterns for performance and may employ AI / ML models to perform corrective actions via the SMO Framework 260 (such as reconfiguration via an O1 interface) or via creation of RAN management policies (such as A1 interface policies) .
[0069] The network node 110, the processing system 145 of the network node 110, the UE 120, the processing system 140 of the UE 120, the CU 210, the DU 230, the RU 240, or any other component (s) of Fig. 1 or Fig. 2 may implement one or more techniques or perform one or more operations associated with a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections, as described in more detail elsewhere herein. For example, the processing system 145 of the network node 110, the processing system 140 of the UE 120, the CU 210, the DU 230, or the RU 240 may perform or direct operations of, for example, process 1100 of Fig. 11, process 1200 of Fig. 12, or other processes as described herein (alone or in conjunction with one or more other processors) . In some aspects, the transmitter described herein is the network node 110, is included in the network node 110, or includes one or more components of the network node 110 shown in Figure 1. Alternatively, or additionally, in some aspects, the transmitter described herein is the UE 120, is included in the UE 120, or includes one or more components of the UE 120 shown in Figure 1. In some aspects, the receiver described herein is the network node 110, is included in the network node 110, or includes one or more components of the network node 110 shown in Figure 1. Alternatively, or additionally, in some aspects, the receiver described herein is the UE 120, is included in the UE 120, or includes one or more components of the UE 120 shown in Figure 1.
[0070] Memory of the network node 110 may store data and program code (or instructions) for the network node 110, the CU 210, the DU 230, or the RU 240. In some examples, the memory of the network node 110 may store data relating to a UE 120, such as RRC state information or a UE context. Memory of a UE 120 may store data and program code (or instructions) for the UE 120, such as context information. In some examples, the memory of the UE 120 or the memory of the network node 110 may include a non-transitory computer-readable medium storing a set of instructions for wireless communication. For example, the set of instructions, when executed by one or more processors (for example, of the processing system 145 or the processing system 140) of the network node 110, the UE 120, the CU 210, the DU 230, or the RU 240, may cause the one or more processors to perform process 1100 of Fig. 11, process 1200 of Fig. 12, or other processes as described herein. In some examples, executing instructions may include running the instructions, converting the instructions, compiling the instructions, or interpreting the instructions, among other examples.
[0071] In some aspects, a network node (e.g., a network node 110) is a transmitter. Based at least in part on being a transmitter, the network node includes means for generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and / or means for storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0072] Alternatively, or additionally, the network node is a receiver. Based at least in part on being a receiver, the network node includes means for receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and / or means for reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission. In some aspects, the means for the network node to perform operations described herein may include, for example, one or more of communication manager 155, processing system 145, a radio, one or more RF chains, one or more transceivers, one or more antennas, one or more modems, a reception component (for example, reception component 1302 depicted and described in connection with Fig. 13) , or a transmission component (for example, transmission component 1304 depicted and described in connection with Fig. 13) , among other examples
[0073] In some aspects, a UE (e.g., a UE 120) is a transmitter. Based at least in part on being a transmitter, the UE includes means for generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and / or means for storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0074] Alternatively, or additionally, the UE is a receiver. Based at least in part on being a receiver, the UE includes means for receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and / or means for reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission. In some aspects, the means for the UE to perform operations described herein may include, for example, one or more of communication manager 150, processing system 140, a radio, one or more RF chains, one or more transceivers, one or more antennas, one or more modems, a reception component (for example, reception component 1402 depicted and described in connection with Fig. 14) , or a transmission component (for example, transmission component 1404 depicted and described in connection with Fig. 14) , among other examples.
[0075] Figs. 3A and 3B are diagrams illustrating a first example 300 of a PAS architecture and a second example 350 of a partial PAS architecture.
[0076] PAS is a technique used in wireless communication systems to improve the spectral efficiency and power efficiency of data transmission. In some examples, PAS leverages the concept of shaping the probability distribution of transmitted signal amplitudes to match the characteristics of the communication channel, often aligning with the channel’s capacity-achieving distribution. PAS may be associated with constellation shaping, such as by modifying the probability of the occurrence of constellation symbols (e.g., points in a QAM constellation) . For example, instead of a transmitter transmitting all symbols with equal probability, a transmitter implementing PAS may bias the transmission to favor symbols with lower energy. This may reduce the average transmit power, which is beneficial for power-constrained systems. Additionally, or alternatively, PAS may align the transmitted signal’s distribution closer to the optimal distribution predicted by information theory, such as for a purpose of enabling a system to operate closer to the Shannon capacity limit and thus improving spectral efficiency, power efficiency, or a combination of the two. In some examples, PAS may be associated with bit-to-amplitude mapping techniques, in which data bits are separated into shaped bits (e.g., bits responsible for determining the amplitude levels according to a predefined probability distribution) and parity bits (e.g., bits derived from error correction coding) . In some examples, PAS may implement a shaping algorithm, such as a constant composition distribution matching (CCDM) processing, in order to generate sequences with the desired probabilistic characteristics. Additionally, or alternatively, PAS may be implemented alongside FEC codes (e.g., LDPC or polar codes) , such as by feeding shaped data into the FEC encoder (sometimes referred to as a pre-FEC design) to protect against errors during transmission.
[0077] For example, Fig. 3A shows a first example 300 of a PAS technique associated with a pre-FEC design. As shown in Fig. 3A, a sequence of the uniform bits 302 may be input into a demultiplexer 304, which may divide the sequence of the uniform bits 302 into a first quantity of bits 306 (shown as “k” in connection with Fig. 3A) and a second quantity of bypass bits 310 (shown as “yn” in connection with Fig. 3A) . The bits 306 may be fed to a distribution matching block 308, which may implement a shaping algorithm, such as a CCDM scheme or a similar scheme, resulting in a quantity (n) of non-uniform amplitudes 312. In this regard, the distribution matching block 308 may induce non-uniform distributions over amplitude sequences. The non-uniform amplitudes 312 may be fed to an amplitude-bit mapping block 314, resulting in a quantity (n) of amplitude bits 316. For instance, in examples in which the amplitude bits include M-1 bits, the amplitude-bit mapping block may output n (M-1) bits. The amplitude bits 316 (e.g., the n (M-1) bits) and the bypass bits 310 (e.g., the yn bits) may be fed into a systematic FEC encoding block 318, which may implement an FEC code (e.g., LDPC or polar codes, among other examples) and / or which may output systematic bits 320, bypass bits 322 (e.g., yn bits) , and parity check bits 324 (e.g., n (1-y) parity check bits) . The systematic bits 320 may be fed to a bit-amplitude mapping block 326, resulting in modulation symbols 328. The bypass bits 322 and the parity check bits 324 may be fed into a sign mapping block 330, resulting in a quantity (n) of sign bits 332. The modulation symbols 328 may be multiplied with the sign bits 332, resulting in non-uniform constellations 334 to be transmitted by the transmitter to a receiver. Some examples may use an M2-QAM mapping scheme (M being an integer) . In this way, the induced non-uniform distributions may be closer to a capacity-achieving distribution than a uniform distribution (e.g., the non-uniform distribution may be more Gaussian-like in an additive white Gaussian noise (AWGN) setting) . An effective code rate of RFEC that is introduced via the architecture shown by the example 300 may be represented by: where L is an integer that represents a number of HARQ transmissions (and y is an adjustment factor that is based at least in part on an amount of redundancy introduced by a HARQ.
[0078] The second example 350 shown by Fig. 3B is a partial PAS architecture. In the first example 300 described with regard to Fig. 3A, the PAS architecture receives uniformly distributed data bits (e.g., the uniform bits 302) and demultiplexes the uniformly distributed data bits into two branches: a first quantity of bits that are processed via a distribution matching block (e.g., the distribution matching block 308) and an amplitude-bit mapping block (e.g., the amplitude-bit mapping block 314) , and a second quantity of bits that bypass the distribution matching block and an amplitude-bit mapping block. Splitting the uniform bits in such a manner may increase spectral efficiency and reduce power consumption while maintaining a transmission rate. In the second example 350 of the partial-PAS architecture, the uniform data may be partitioned into three branches: uniformly distributed data bits, non-uniformly distributed data bits, and unshaped information bits for amplitude.
[0079] To illustrate, the uniform bits 352 are fed into a demultiplexer 354 that partitions the uniform bits. A first portion of bits 356 are fed into a partial probabilistic amplitude (PA) encoder 358 that applies probabilistic shaping to the first portion of bits 356 in a similar manner as the distribution matching block 308 described with regard to Fig. 3A, resulting in non-uniform amplitudes. The non-uniform amplitudes are fed into a partial symbol-to-bit mapping block 360 that maps the non-uniform amplitudes to symbols based at least in part on a probabilistic distribution, resulting in bits that are shaped for amplitudes (e.g., shaped bits for the amplitude 362) .
[0080] Returning to the demultiplexer 354, the demultiplexer 354 may output, from the uniform bits 352, a second portion of bits 366 that bypass the shaping process performed by the partial PA encoder 358 and the partial symbol-to-bit mapping block 360. The second portion of bits 366 may be uniformly mapped to amplitude values, and may also be referred to as unshaped bits for amplitude. The demultiplexer 354 may also output a third portion of bits 368 that bypass the shaping process performed by the partial PA encoder 358 and the partial symbol-to-bit mapping block 360. The third portion of bits 368 may be mapped to sign bits of symbols, and may be alternatively referred to as unshaped bits for sign.
[0081] The shaped bits for the amplitude 362, the second portion of bits 366 (e.g., the unshaped bits for amplitude) , and the third portion of bits 368 (e.g., the unshaped bits for sign) may be input into an FEC encoding block 370 that applies encoding to the bits, such as LDPC encoding or polar encoding. As shown by Fig. 3B, the FEC encoding block 370 may output a first set of encoded bits 372 that are encoded shaped bits for amplitude, a second set of encoded bits 374 that are encoded unshaped bits for amplitude, a third set of bits 376 that are parity bits, and a fourth set of bits 378 that are unshaped bits for sign. The first set of encoded bits 372, the second set of encoded bits 374, the third set of bits 376, and the fourth set of bits 378 are fed into a sign and amplitude generator block 380 that uses the input bits to generate one or more amplitudes 382 and one or more signs 384 that are fed into a constellation mapper 386. The constellation mapper 386 then uses the amplitudes 382 and the signs 384 to output one or more modulated symbols 388.
[0082] The non-uniformly distributed bits that are generated by the partial PA encoder 358 shape a partial level of amplitude bits as shown by Fig. 3B. As an example, the partial PAs architecture shown by the second example 350 may not shape one or more bits that are associated with least significant bit (LSB) levels. To illustrate, for 1024 QAM for PAS, there are five bit levels for each in-phase / quadrature (I / Q) dimension, one sign bit level, and four amplitude bit levels. In a partial PAS architecture, the first two amplitude bit levels are shaped (e.g., the first two bit levels are non-uniform) and the last two amplitude bit levels are not shaped (e.g., the last two bit levels are uniform) .
[0083] In some cases, a PAS architecture may not shape a most significant bit (MSB) of the amplitude bits to maintain a uniform distribution for the MSB and increase a likelihood of successful detection. That is, the MSB of the amplitude bits may have the most impact on a symbol placement on a constellation, and maintaining the uniform distribution increases the likelihood of a successful detection. The PAS architecture may instead shape mid-level amplitude bits that have less impact on the symbol placement relative to the MSB of the amplitude bits, to balance power efficiency gained through the use of PAS with detection reliability.
[0084] As indicated above, Figs. 3A and 3B are provided as examples. Other examples may differ from what is described with regard to Figs. 3A and 3B.
[0085] Fig. 4 is a diagram illustrating an example 400 of a rate matching block.
[0086] Some transmitters may include a rate matching block that adapts an output data rate of a channel encoder to match the available resources that are allocated to a transmission. To illustrate, information bits, shown as input bits 402, may be fed into an FEC encoding block 404, where the input bits 402 may include the uniform bits 302 described with regard to Fig. 3A or the uniform bits 352 described with regard to Fig. 3B. Alternatively, or additionally, the FEC encoding block 404 may be the systematic FEC encoding block 318 described with regard to Fig. 3A or the FEC encoding block 370 described with regard to Fig. 3B. As shown by Fig. 4, the FEC encoding block 404 may output a total of N encoded bits that include K encoded data bits 406 and (N –K) parity bits 408, N and K being integers. In some aspects, the encoded data bits 406 may be the input bits 402 (e.g., unchanged) , such as in a scenario in which the FEC encoding block is an LDPC encoder. The encoded data bits 406 and the parity bits 408 may be fed as input to a rate matching block 410.
[0087] In the example 400, the rate matching block 410 includes a bit collection block 412, a bit selection block 414, and a sliding block permutation mapping (SBPM) inter-leaver block 416. The bit collection block 412 may store the encoded bits, shown by Fig. 4 as being the N encoded bits (e.g., the encoded data bits 406 and the parity bits 408) in a circular buffer that may operate as a temporary storage area with a fixed size. Based at least in part on using a circular buffer, the bit collection block 412 may continuously store data without overflow by starting the storage of the encoded bits at a start of the circular buffer to an end of the circular buffer, wrapping around to the start of the circular buffer, and overwriting the oldest data with newer data (e.g., newer encoded bits) . The use of a circular buffer may enable efficient bit storage and efficient bit selection through the use of pointers instead of data shifting.
[0088] Based at least in part on an amount of air interface resources that are available and allocated to a transmission, the bit selection block 414 may select encoded bits from the bit collection block 412 in a manner that expands or truncates the encoded data (e.g., by adding repetition or discarding bits, respectively) to match a code rate and align the encoded bits with a transport block size. For instance, as shown by Fig. 4, the bit selection block 414 may output E bits that are based at least in part on the N encoded bits stored in the bit collection block 412. In some cases, the bit collection block 412 may store LDPC-encoded bits in the circular buffer, and the LDPC-encoded bits may be based at least in part on a lifting size (Zc) . In such a scenario, the bit selection block 414 may puncture the first 2Zc encoded bits, prune filler bits, or a combination of the two. For HARQ processes that are based at least in part on an RV as described with regard to Fig. 5, a transmitter may select retransmission bits from the selected bits by the bit selection block 414 (e.g., using a different RV index) .
[0089] The SBPM inter-leaver block 416 may rearrange an order of the E bits output by the bit selection block 414 to increase a robustness against burst errors during transmission. For instance, the SBPM inter-leaver block 416 may map the E bits to a matrix as described with regard to Figs. 8A-8C below, and may apply a structured permutation across the rows and columns of the matrix. Examples of a structured permutation may include a row-based cyclic shift that shifts each row in a circular manner by one or more offsets, or column-based bit scrambling that reorders each column using a predetermined pattern.
[0090] As shown by Fig. 4, the rate matching block 410 may output a set of bits 418 that are fed into a mapping block 420. In some cases, the mapping block 420 may be or include any combination of the bit-amplitude mapping block 326, the sign mapping block 330, the sign and amplitude generator block 380, or the constellation mapper 386 described with regard to Fig. 3A and Fig. 3B. The mapped symbols may then be transmitted in a wireless channel 422.
[0091] As indicated above, Fig. 4 is provided as an example. Other examples may differ from what is described with regard to Fig. 4.
[0092] Fig. 5 is a diagram illustrating an example 500 of redundancy version cycling that may be used as at least part of a HARQ process.
[0093] An RV is a retransmission mechanism that increases a retransmission reliability. For instance, a HARQ process may use FEC based at least in part on an LDPC code or polar encoding as described above. Based at least in part on a receiving device indicating a request for a retransmission (e.g., via a NACK) , a transmitter may use an RV index and RV cycling to select data, parity bits, or a combination, that is included in a transmission. For example, the transmitter may store bits for a transmission in a circular buffer 505 (e.g., stored in memory at the transmitter) . In the example 500, the circular buffer 505 stores information bits 510 and parity bits 515 (alternatively referred to as parity-check bits) . The information bits 510 may include the data to be transmitted, and the parity bits 515 may include linear combinations of the data (e.g., of the information bits 510) . The transmitter may encode the information bits 510, the parity bits 515, or a combination of the information bits 510 and the parity bits 515 into a set of encoded bits, and may transmit the set of encoded bits. The particular bits that are selected to be included in the set of encoded bits may depend on (or are defined by) the RV associated with the transmission.
[0094] For example, for a first transmission that is configured with or assigned an RV index of RV0, the transmitter may transmit a sequence of encoded bits (e.g., a particular number of encoded bits) starting at a first location 520 in the circular buffer 505 (e.g., bit 0, or a first information bit) . Similarly, the transmitter may transmit a sequence of encoded bits starting at a second location 525 in the circular buffer 505 for a second transmission that is configured with or assigned RV index 1 (RV1) , may transmit a sequence of encoded bits starting at a third location 530 in the circular buffer 505 for a third transmission that is configured with or assigned RV index 2 (RV2) , and may transmit a sequence of encoded bits starting at a fourth location 535 in the circular buffer 505 for a fourth transmission that is configured with or assigned an RV index of RV3.
[0095] In some cases, the starting bit locations may be defined by a table 540, such as for NR HARQ that uses an LDPC code. The table 540 defines starting bit locations in the circular buffer 505 for a first base graph (BG1) and a second base graph (BG2) . A base graph is a parameter for determining parity bits 515 for a transmission based at least in part on a transport block (TB) size and a code rate (with BG1 being intended for TBs with a larger TB size, and BG2 being intended for TBs with a smaller TB size) . Referring to the table, Ncb represents the length of the circular buffer 505 (e.g., the number of bits included in the circular buffer 505) , and Zc represents a lifting size, which is based at least in part on the number of information bits 510 and the number of base graph (BG) columns corresponding to information bits 510.
[0096] As indicated above, Fig. 5 is provided as an example. Other examples may differ from what is described with respect to Fig. 5.
[0097] Fig. 6 is a diagram illustrating an example 600 of RV index mapping relative to bit storage in a circular buffer.
[0098] The example 600 includes a storage format 602 for storing a combination of shaped bits 604 that are based at least in part on amplitude shaping as described with regard to Figs. 3A and 3B, unshaped bits 606 that do not include amplitude shaping, and parity bits 608 that do not include amplitude shaping in a circular buffer. In some cases, the bits stored via the storage format 602 may be based at least in part on PAS, and may be stored in the bit collection block 412 as described with regard to Fig. 4 (e.g., the E bits) . In the example 600, the storage format 602 divides the unshaped bits 606 into two segments that are positioned adjacent to and on each side of the shaped bits 604. In some aspects, the storage format 602 may be based at least in part on the associated symbol bit levels of the shaped bits 604 and the unshaped bits 606. For instance, a first portion of the unshaped bits 606 that precedes the shaped bits 604 may be associated with a more significant bit level of a symbol relative to the shaped bits 604, and the shaped bits 604 may have a more significant bit level of the symbol relative to the second portion of the unshaped bits 606 that follow the shaped bits 604. Alternatively, or additionally, the storage format 602 that is shown by Fig. 6 may be defined by a communication standard (e.g., a 5G NR communication standard) . A physical position of the shaped bits 604, the unshaped bits 606, and the parity bits 608 in the circular buffer may change from transmission to transmission, but the storage format 602 may remain unchanged.
[0099] Collectively, the shaped bits 604 and the unshaped bits 606 may be systematic bits 610 (e.g., shaped systematic bits and unshaped systematic bits) that carry encoded information (e.g., via LDPC encoding or polar encoding) . In other examples, the shaped bits 604 may not be systematic bits, the unshaped bits 606 may not be systematic bits, or a combination of the two. As described above, the unshaped bits 606 may be unaltered via PAS and the shaped bits 604 may be altered via PAS. The parity bits 608, which may be unshaped bits, provide error correction information that enables a receiver to recover the systematic bits 610.
[0100] In an RV-based HARQ process, a transmitter may select a subset of encoded bits from a circular buffer based at least in part on an RV index, and each RV index may be associated with a respective subset of bits or a respective subset of bits. For instance, as part of a retransmission, the transmitter may select (e.g., via the bit selection block 414) a first subset of bits 612 from the circular buffer using RV0that has a selection index that begins at a first bit level of the storage format. Alternatively, or additionally, the use of RV0 may be associated with the particular combination of the systematic bits 610 and the portion of the parity bits 608 shown by Fig. 6 with regard to the first subset of bits 612. To illustrate, based at least in part on various factors (e.g., scheduling, rate matching, or HARQ policies) , the systematic bits 610 and the parity bits 608 may be stored in different physical locations of the circular buffer (e.g., different physical indices of the circular buffer) for different transmissions. The use of RV0 indicates to use the particular subset of bits that include the particular combination of the systematic bits 610 and the portion of the parity bits 608 shown by Fig. 6 as the first subset of bits 612 regardless of the physical storage location within the circular buffer. Accordingly, to select the first subset of bits 612 shown by Fig. 6, the transmitter (e.g., via the bit selection block 414) may pull from different physical indices of the circular buffer to ensure that the proper combination of the systematic bits 610 and the portion of the parity bits 608 are selected.
[0101] As another example, as part of a retransmission, the transmitter may select a second subset of bits 614 using RV3 that has a different selection index relative to RV0 and is associated with a different combination of the systematic bits 610 and the parity bits 608. In the example 600, the second subset of bits 614 includes an end portion of the parity bits 608, and wraps from an end of the parity bits 608 (and the end of the encoded bits for a transmission) to a beginning of the stored bits such that the second subset of bits 614 includes one or more of the parity bits 608, one or more of the unshaped bits 606, and one or more of the shaped bits 604. In contrast, the first subset of bits 612 includes an entirety of the systematic bits 610 and, more particularly, an entirety of the shaped bits 604. Based at least in part on the first subset of bits 612 including an entirety of the shaped bits 604, a first retransmission that uses the first subset of bits 612 may have increased power efficiency, increased spectral efficiency, or a combination of the two, relative to a second transmission that uses the second subset of bits 614 that uses fewer of the shaped bits 604. Thus, the second retransmission may have reduced power efficiency, reduced spectral efficiency, or a combination of the two, relative to the first retransmission. Reduced power efficiency may shorten a battery life for some devices, and reduced spectral efficiency may result in reduced data throughput, increased data transfer latencies, or a combination of the two.
[0102] Various aspects relate generally to a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV selections. Some aspects more specifically relate to a transmitter storing PAS-based encoded bits in a circular buffer using a storage format that increases a number of shaped bits that are included in a subset of bits. In some aspects, a transmitter may generate encoded bits based at least in part on PAS such that the encoded bits include one or more shaped bits, one or more unshaped bits, and one or more parity bits. For example, the transmitter may generate the encoded bits using a PAS architecture as described with regard to Fig. 3A, a partial PAS architecture as described with regard to Fig. 3B, a rate matching block as described with regard to Fig. 4, or any combination thereof. The transmitter may store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are asssociated with a second RV index selection. An example of a first RV index selection may be a first selection that is based at least in part on RV0, and an example of a second RV index selection may be a second selection that is based at least in part on RV3.
[0103] Particular aspects of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some examples, by using a circular buffer storage format that maximizes a quantity of shaped bits in multiple subsets of bits that are based at least in part on respective RV indices, the described techniques can be used to enable a transmitter to generate a transmission that includes more shaping bits and, consequently, generate a transmission that increases power efficiency, increases spectral efficiency, or a combination of both. To illustrate, including more shaped bits may reduce an average transmit power level for a transmission, may enable the use of a higher MCS for the transmission, or a combination of the two, resulting in increased power efficiency, increased spectral efficiency, or a combination of the two. Increased power efficiency may extend a battery life for some devices, and increased spectral efficiency may result in increased data throughput, reduced data transfer latencies, or a combination of the two.
[0104] As indicated above, Fig. 6 is provided as an example. Other examples may differ from what is described with regard to Fig. 6.
[0105] Figs. 7A, 7B, and 7C are diagrams illustrating a first example 700 of a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections, a second example 730 of a pre-FEC bit adjustment scheme, and a third example 760 of a post-FEC bit adjustment scheme.
[0106] The first example 700 includes a storage format 702 for storing encoded bits in a circular buffer (e.g., a circular buffer storage format) . In some aspects, the encoded bits may be based at least in part on PAS such that the encoded bits include one or more shaped bits 704, one or more unshaped bits 706, one or more parity bits 708, or any combination thereof. The shaped bits 704 and the unshaped bits 706 in the example 700 are systematic bits 710, but in other examples, the shaped bits 704 may not be systematic bits, the unshaped bits 706 may not be systematic bits, or a combination of the two. In a similar manner as described with regard to Fig. 6, the shaped bit (s) 704, the unshaped bit (s) , and the parity bit (s) 708 may be stored in different physical locations of the circular buffer (e.g., different physical indices of the circular buffer) for different transmissions based at least in part on various factors, but may be stored as the storage format 702 (e.g., regardless of a physical location within the circular buffer) . Alternatively, or additionally, a transmitter (e.g., via the bit selection block 414) may pull from different physical indices of the circular buffer to ensure that a particular combination of the shaped bit (s) 704, the unshaped bit (s) , and the parity bit (s) 708 are selected as specified by the associated RV index.
[0107] In the example 700, the storage format 702 positions an entirety of the shaped bits 704 at a first bit level position of the circular buffer, where “first bit level position” denotes a starting position of the storage format 702 (e.g., index 0) or a starting position of an MSB for a symbol. As shown by Fig. 7A, positioning an entirety of the shaped bits 704 at the first bit level position of the storage format 702 results in an entirety of the shaped bits 704 being included in a first subset of bits 712 that are associated with an RV0 selection. Positioning the entirety of the shaped bits 704 at the first bit level also results in a majority of the shaped bits 704 being included in a second subset of bits 714 that are associated with an RV3 selection. More particularly, the storage format 702 maximizes a quantity of shaped bits included in both the first subset of bits 712 and in the second subset of bits 714 using a same storage location for the shaped bits 704.
[0108] The second example 730 shown by Fig. 7B is an example of bit position adjustments that a transmitter may perform prior to FEC encoding to generate and store encoded bits in a circular buffer using the storage format 702. The second example 730 includes shaped bits (shown with a dense dotted pattern) and unshaped bits (shown with a light dotted pattern) that may be output by a PAS-based architecture as described above. In the second example 730, the shaped bits and the unshaped bits are systematic bits 732, but in other examples, the shaped bits may not be systematic bits, the unshaped bits may not be systematic bits, or a combination of the two. In a similar manner as described with regard to Fig. 6, the systematic bits 732 are ordered in a format that positions a first portion of the unshaped bits at a front of the systematic bits 732 (e.g., at a first bit level position) . The first portion of the unshaped bits is followed by an entirety of the shaped bits, and the entirety of the shaped bits is followed by a second portion of the unshaped bits. As part of a bit processing procedure, the systematic bits 732 may undergo a rate matching process as described with regard to Fig. 4 in which 2Zc punctate bits 734 (shown in solid white) that precede the systematic bits 732 are thrown away. In other examples, the systematic bits 732 may not be preceded by the 2Zc punctate bits 734.
[0109] In the second example 730, a transmitter may perform a reorder operation 736 that adjusts or repositions the systematic bits 732 to generate a bit sequence that is shown as modified bits 738 in combination with the 2Zc punctate bits 734. While the reorder operation 736 is described with regard to reordering systematic bits, other examples may include the reorder operation 736 repositioning shaped bits that are not systematic bits, repositioning unshaped bits that are not systematic bits, or a combination of the two. In the modified bits 738, the shaped bits are repositioned to be located in front of the first portion of the unshaped bits and the second portion of the unshaped bits. The reorder operation 736 may not adjust the 2Zc punctate bits 734 such that the 2Zc punctate bits 734 precede the modified bits 738 and, consequently, the systematic bits. In other examples, the modified bits 738 may not be preceded the 2Zc punctate bits 734. That is, the bit sequence may include the modified bits 738 and not the 2Zc punctate bits 734.
[0110] The modified bits 738 are fed into an FEC encoding block 740 (e.g., a systematic encoding block) , and an output of the FEC encoding block 740 is fed into a rate matching block 742 in a similar manner as described with regard to Fig. 4. In some aspects, the 2Zc punctate bits 734 may be removed from the bit sequence prior to the FEC encoding block 740 (e.g., not fed into the FEC encoding block 740) . A bit collection block within the rate matching block 742 may store the shaped bits and unshaped bits in a circular buffer using a storing format 744 that positions the shaped bits at the first level (e.g., index 0) of the circular buffer and maximizes a quantity of shaped bits for multiple redundancy version index selections (e.g., RV0-based selection and RV3-based selection) . As shown by Fig. 7B, the storing format 744 may include one or more parity bits (shown with vertical stripes) that are output by the FEC encoding block 740.
[0111] The third example 760 shown by Fig. 7C is an example of bit position adjustments that a transmitter may perform after FEC encoding. The third example 760 includes systematic bits 762 that includes unshaped bits (shown with a light dotted pattern) and shaped bits (shown with a dense dotted pattern) that may be output by a PAS-based architecture. However, in other examples, the shaped bits may not be systematic bits, the unshaped bits may not be systematic bits, or a combination of the two. In similar manner as described with regard to Fig. 6 and 7B, the shaped bits and the unshaped bits of the systematic bits 762 are ordered in a format that positions a first portion of the unshaped bits at a front of the systematic bits 762 (e.g., in a first bit level position) , followed by an entirety of the shaped bits, followed by a second portion of the unshaped bits. The systematic bits 762 and 2Zc punctate bits 764 (shown in solid white) may form a bit sequence, where the 2Zc punctate bits 764 precede the systematic bits 762 as shown by Fig. 7C.
[0112] In the third example 760, the systematic bits 762 are fed into an FEC encoding block 766 (e.g., a systematic FEC encoding block) that outputs encoded bits 768. In some aspects, the 2Zc punctate bits 764 may be removed from the bit sequence prior to the FEC encoding block 740 (e.g., not fed into the FEC encoding block 740) . The encoded bits may include one or more parity bits (shown with vertical stripes) . As shown by Fig. 7C, the encoded bits 768 do not reposition the unshaped bits and the shaped bits, such that the unshaped bits and the shaped bits are in the same locations as the respective input locations.
[0113] In the third example 760, the transmitter performs a reorder operation 770 after the FEC encoding block 766. In a similar manner as described with regard to the second example 730, the reorder operation 770 may adjust or reposition the unshaped bits and the shaped bits to generate modified bits 772. In the modified bits 772, the shaped bits are repositioned to be located in front of the first portion of the unshaped bits and the second portion of the unshaped bits. That is, the shaped bits may be positioned at a first bit level position. In some aspects, the reorder operation 770 may reposition the shaped bits and the unshaped bits into the storage format described by Fig. 7A.
[0114] The modified bits 772 are fed into a rate matching block 774 in a similar manner as described with regard to Fig. 4 and Fig. 7B. A bit collection block within the rate matching block 774 may store the shaped bits and unshaped bits in a circular buffer using a storage format (e.g., the storage format as shown with regard to Fig. 7A) that positions the shaped bits at the first bit level position of the circular buffer. The storage format used to store the shaped bits, the unshaped bits, and the parity bits in the circular buffer may maximize a quantity of shaped bits for multiple redundancy version index selections (e.g., RV0-based selection and RV3-based selection) .
[0115] As indicated above, Figs. 7A, 7B, and 7C are provided as examples. Other examples may differ from what is described with regard to Figs. 7A, 7B, and 7C.
[0116] Figs. 8A, 8B, and 8C are diagrams illustrating a first example 800, a second example 830, and a third example 860 of bit mapping for an SBPM matrix.
[0117] A rate matching block may include an SBPM inter-leaver (e.g., the SBPM inter-leaver block 416) that rearranges an order of bits to increase a robustness of a transmission against burst errors during transmission. As described with regard to Fig. 6, the rearrangement of the bits may be based at least in part on a matrix.
[0118] To illustrate, the first example 800 shown by Fig. 8A includes a matrix 802 that may alternatively be referred to as an SBPM matrix. The size of the matrix 802 may be based at least in part on a modulation order (Qm) , which is a number of bits per symbol, and a number of encoded bits that are selected for transmission (e.g., E) . More particularly, the matrix 802 includes Qm rows (shown by Fig. 8A as being Qm = 5) , columns, and has a size of Each column of the matrix 802 may correspond to a symbol that has Qm bits, and each row may be a respective bit level within the symbol. To illustrate, a first row of the matrix 802 may be associated with a first bit level of a symbol, a second row of the matrix 802 may be associated with a second bit level of the symbol, up to a Qm-th row of the matrix being associated with a Qm-th bit level of the symbol.
[0119] As at least part of the interleaving process, an SBPM inter-leaver may fill the matrix 802 with bits row by row, such as by writing a first set of bits from E bits being transmitted to a first row (shown by Fig. 8A as row 1) , writing a second set of bits from the E bits to a second row (shown by Fig. 8A as row 2) , up to writing a last set of bits from the E bits to a last row (shown by Fig. 8A as row 5) . In the example 800, the write execution order may be row 1, row 2, row 3, row 4, and row 5. The SBPM inter-leaver may apply a permutation that repositions bits within the matrix 802 to different locations such that the bits within a row or column are separated from one another. The SBPM inter-leaver may then generate output bits based at least in part on reading bits out of the matrix 802 column by column. For example, the SBPM inter leaver may initially read out of a first column (shown by Fig. 8A as column 1) , followed by a second column (shown by Fig. 8A as column 2) , up to a last column (shown by Fig. 8A as column 6) . In the example 800, the read execution order is column 1, column, column 3, column 4, column 5, and column 6. For transmissions that reorder shaped bits and unshaped bits to maximize a quantity of shaped bits for a first subset of bits that are selected using an RV0 and a second subset of bits that are selected using an RV3 index, some aspects may write to an SBPM inter-leaver matrix (e.g., the matrix 802) using a row sequence that is based at least in part on a shaped order and an unshaped order of the E bits to position the shaped bits and the unshaped bits at the correct bit levels.
[0120] To illustrate, the second example 830 shown by Fig. 8B is an example of a row sequence to a matrix 832 that may be used for a segment of bits that are selected by a transmitter for retransmission using an RV0 index (e.g., the first subset of bits 612) . Segments of bits in the second example 830 include shaped bits (shown with a dense dotted pattern) and unshaped bits (shown with a light dotted pattern) in a similar manner as described with regard to Fig. 7A (e.g., the first subset of bits 712) . The shaped bits may be systematic bits, other bits that are not systematic bits, or a combination of the two. The unshaped bits may be unshaped systematic bits, unshaped parity bits, other bits that are not systematic bits or parity bits, or any combination thereof. As described with regard to Figs. 7A-7C, the shaped bits may be positioned at a first bit level of the circular buffer and the segment of bits (e.g., based at least in part on the transmitter performing a reposition operation) . An SBPM inter-leaver block at a transmitter may use a row sequence to map or write the segment of bits to the matrix, and the row sequence may be based at least in part on a shaped order of the E transmission bits and an unshaped order of the E transmission bits.
[0121] “Shaped order” denotes an order of bits in a symbol that are shaped bits (e.g., via PAS) , and “unshaped order” denotes an order of bits in a symbol that are unshaped bits. As an example, for a symbol that has a modulation order of Qm = 5, a transmitter may apply shaping to two bit levels of the symbols and may not apply shaping to the remaining three bit levels, resulting in a shaped order = 2 and an unshaped order = 3. Alternatively, or additionally, as described above, the shaped bits may be mid-level amplitude bits (e.g., bit level 2 and bit level 3) within a symbol and the MSB amplitude bit (e.g., bit level 1) and remaining bit levels (e.g., bit level 4 and bit level 5) may be unshaped bits. Accordingly, with reference to the rows of the matrix 832, the row sequence of the shaped bits in may be expressed as [2, 3] (e.g., row 2, followed by row 3) , and the row sequence of the unshaped bits may be expressed as [1, 4, 5] (e.g., row 1, followed by row 4, followed by row 5) . For a segment of bits that are selected using RV0, the shaped bits are positioned at the start of the segments such that the SBPM inter-leaver may write the bits into the matrix 832 using a row sequence of [shaped order, unshaped order] = [2, 3, 1, 4, 5] , and the write execution order for the second example 830 is row 2, followed by row 3, row 1, row 4, and row 5.
[0122] As shown by reference number 834, row 2 and row 3 of the matrix 832 include shaped bits, and the remaining rows of the matrix 832 (e.g., row 1, row 4, and row 5) include unshaped bits. A transmitter may transmit an indication of the row sequence used to write bits of the matrix 832, such as by signaling selection of a preconfigured row sequence (e.g., selection of a particular row sequence in a preconfigured table of row sequences or signaling selection of a particular row sequence that is specified by a communication standard) . The row sequence indicated by the transmitter may specify which rows of the matrix 832 include shaped bits, which rows of the matrix 832 include unshaped bits, or may specify a combination of the two.
[0123] The third example 860 shown by Fig. 8C is an example of a row sequence to a matrix 862 that may be used for segments of bits that are selected by a transmitter for retransmission using an RV3 index (e.g., the second subset of bits 614) . The segment of bits in the third example 860 includes shaped bits (shown with a sense dotted pattern) and unshaped bits (shown with a light dotted pattern) . The shaped bits may be systematic bits, other bits that are not systematic bits, or a combination of the two. The unshaped bits may be unshaped systematic bits, unshaped parity bits, other bits that are not systematic bits or parity bits, or any combination thereof.
[0124] In a similar manner as described with regard to Fig. 8B, the SBPM inter-leaver may write bits into the matrix 862 based at least in part on a shaped order and an unshaped order that is associated with the transmission. For example, for a modulation order of Qm = 5 and shaping to 2 bit levels of the symbols, the SBPM inter-leaver may use a shaped bits row sequence of [2, 3] for shaped bits, and may use an unshaped row sequence of [1, 4, 5] for unshaped bits.
[0125] Based at least in part on the transmitter selecting the segment of bits using an RV index of RV3 (e.g., the second subset of bits 712 described with regard to Fig. 7A) , the segment of bits may be based at least in part on a wraparound at a circular buffer, as described with regard to Fig. 6. For example, a start of the segment of bits selected by the transmitter may include parity bits and, based at least in part on the wraparound, shaped bits that are positioned at a first bit level of the circular buffer based at least in part on a reorder operation. Accordingly, to write the segment of bits to the matrix 862, the SBPM inter-leaver may begin at Step 1 and use a write execution order that is based at least in part on the unshaped bits row sequence. That is, based at least in part on the segment of bits beginning with unshaped bits, the SBPM inter-leaver may begin writing to the matrix 862 using the unshaped bits row sequence. To illustrate, the unshaped row sequence begins with row 1, followed by row 4. Accordingly, in Step 1, the SBPM inter-leaver may begin writing to the matrix 862 by using a write execution order that starts at row 1, followed by writing to row 4.
[0126] As shown by reference number 864, the SBPM inter-leaver may detect a wraparound event and trigger recording a current inter-leaver index that is associated with the wraparound event. A wraparound event may be based at least in part on the SBPM inter-lever detecting that the bits being written into the matrix 862 via the segment of bits have transitioned from an end of the circular buffer (e.g., parity bits) to a start of the circular buffer. Based at least in part on the segments of bits being based at least in part on a reorder operation, the transition may also include transitioning from unshaped bits (e.g., parity bits) to shaped bits (e.g., shaped systematic bits) . Accordingly, the SBPM inter-leaver may record an inter-leaver index of a position in a current unshaped bits row being written to, where the inter-leaver index may be a last write position of an unshaped parity bit or a first write position of an empty position after the last write position. As shown by reference number 866, the SBPM inter-leaver may proceed to Step 2 and switch from writing bits into the matrix 862 using the unshaped bits row sequence, to writing into the matrix 862 using a write execution order that is based at least in part on the shaped bits row sequence. That is, the SBPM inter-leaver may switch from writing into a row of the matrix 862 that is associated with unshaped bits (e.g., an unshaped bits row) to writing to a row of the matrix 862 that is associated with shaped bits (e.g., a shaped bits row) . To illustrate, based at least in part on the shaped row sequence, the SBPM inter-leaver may use a write execution order that begins at row 2, followed by row 3, as shown by Fig. 8C. Based at least in part on completing the writing of the shaped bits to the shaped bits rows, the SBPM inter-leaver may transition to Step 3 as shown by reference number 868 and resume writing to the unshaped bits rows by returning to an empty position in the matrix 862 as indicated by the inter-leaver index, and writing a remainder of the segment of bits to the matrix 862 based at least in part on the unshaped bits row sequence (e.g., completing row four, followed by row 5) .
[0127] In a similar manner as described with regard to Fig. 8B, a transmitter may transmit an indication of the row sequence used to write into the matrix 862, such as by signaling a preconfigured row sequence. The row sequence indicated by the transmitter may specify which rows of the matrix 862 include shaped bits, which rows of the matrix 832 include unshaped bits, or may specify a combination of the two.
[0128] In some scenarios that are associated with the transmitter selecting a segment of bits for retransmission using an RV3 index, a transmitted bit length of E may not include an entirety of shaped bits. For such a scenario, a shaped order and an unshaped order of the transmission may be computed based at least in part on the following formula: where Ncb is a circular buffer length, and k0 is a starting position defined for each RV. To illustrate, a shaped order may be computed as: and an unshaped order may be computed as: In some aspects, the computations for the shaped order and the unshaped order may be conditional on satisfying: and
[0129] As indicated above, Figs. 8A, 8B, and 8C are provided as examples. Other examples may differ from what is described with regard to Figs. 8A, 8B, and 8C.
[0130] Figs. 9A and 9B are diagrams illustrating a first example 900 and a second example 950, respectively, of receiver-side processing for reordered bits.
[0131] As at least part of a HARQ process, a receiver may receive a retransmission that includes a segment of bits selected by a transmitter from a circular buffer (e.g., at the transmitter) using an RV index as described herein. The bits may be based at least in part on PAS and a reorder operation at the transmitter as described with regard to Figs. 7A-7C, an SBPM inter-leave process that is based at least in part on a row sequence as described with regard to Figs. 8A and 8B, or a combination of the two. To recover the transmitted information, a receiver may perform reverse operations relative to the transmitter.
[0132] The first example 900 shown by Fig. 9A includes at least a portion of a receiver processing path that includes a reverse reorder operation that is performed by the receiver after FEC decoding. In some cases, the first example 900 may perform one or more reverse operations that are described with regard to Fig. 7B. The first example 900 includes a de-mapping block 902 that estimates a received symbol and de-maps the symbol to bits. In some aspects, the de-mapping block 902 may generate log-likelihood ratios (LLRs) instead of bits. The bits (or LLRs) are then input to a rate recovery block 904 that recovers a codeword (e.g., represented by bits or LLRs) by performing any combination of SBPM de-inter-leaving, inserting placeholders for punctured bits, or removing repetition (e.g., by combining or discarding) . The SBPM de-inter-leaving may be based at least in part on the receiver obtaining an indication of a row sequence used by an SBPM inter-leaver at a transmitter. An output of the rate recovery block 904 may then be input to an FEC decoder block 906 that may combine the output of the rate recovery block 904 with information received in a prior transmission. The FEC decoder block 906 may decode the combined information to recover bits that do not include encoding.
[0133] The receiver processing path shown by the first example 900 includes a reorder operation 908 that is positioned after the FEC decoder block 906. The reorder operation 908 may reposition bits to original positions as shown by reference number 910. To illustrate, the repositioning of bits may reposition some bits from a first bit level position to another bit level position, or from another bit level position to the first bit level position.
[0134] The second example 950 shown by Fig. 9B includes at least a portion of a receiver processing path that includes a reverse reorder operation that is performed by the receiver prior FEC decoding. In some cases, the second example 950 may perform one or more reverse operations relative to those described with regard to Fig. 7C. The second example 950 includes the de-mapping block 902, the rate recovery block 904, and the FEC decoder block 906 described with regard to Fig. 9A. However, in the second example 950, the output of the rate recovery block 904 is fed into a reorder operation 952 that is positioned before the FEC decoder block 906. The reorder operation 952 may reposition bits to original positions in a similar manner as described with regard to Fig. 9A such that the FEC decoder block 906 outputs bits in the order shown by reference number 910.
[0135] As indicated above, Figs. 9A and 9B are provided as examples. Other examples may differ from what is described with regard to Figs. 9A and 9B.
[0136] Fig. 10 is a diagram illustrating an example 1000 of a wireless communication process between a transmitter 1002 (e.g., a network node 110 or a UE 120) and a receiver 1004 (e.g., a UE 120 or a network node 110) , in accordance with the present disclosure. The transmitter 1002 may transmit and / or receive communications with the receiver 1004, and the receiver 1004 may transmit and / or receive communications with the transmitter 1002. In the example 1000, the transmitter 1002 is a first wireless communication device that performs shaped bits and unshaped bits reordering as described with regard to Figs. 7A-7C, inter-leaver matrix writing based at least in part on a row sequence as described with regard to Figs. 8A-8C, or a combination of the two. In the example 1000, the receiver is a second wireless communication device that performs reverse reordering of the shaped bits and unshaped bits relative to the transmitter 1002, reverse inter-leaver matrix operations relative to the transmitter 1002, or a combination of the two, as described with regard to Figs. 9A and 9B. However, the transmitter 1002 may also include reverse reordering functionality, reverse inter-leaver matrix operations, or a combination of the two, as described with regard to the transmitter 1002. Alternatively, or additionally, the receiver 1004 may include shaped bits and unshaped bits reordering functionality, inter-leaver matrix writing based at least in part on a row sequence, or a combination of the two, as described with regarding to the transmitter 1002.
[0137] As shown by reference number 1010, a transmitter 1002 and a receiver 1004 may establish a connection. To illustrate, in a first example, the transmitter 1002 may be a network node 110 and the receiver 1004 may be a UE 120. In a second example, the transmitter 1002 may be a UE 120 and the receiver 1004 may be a network node 110. In both the first example and the second example, the UE 120 may power up in a cell coverage area provided by the network node 110, and the UE 120 and the network node 110 may perform one or more procedures (e.g., a random access channel (RACH) procedure and / or an RRC procedure) to establish a wireless connection. As another example, the UE 120 may move into the cell coverage area provided by the network node 110 and may perform a handover from a source network node (e.g., another network node 110) to the network node 110. Alternatively, or additionally, the network node 110 and the UE 120 may communicate via the connection based at least in part on any combination of Layer 1 signaling (e.g., DCI and / or UCI) , Layer 2 signaling (e.g., a MAC CE) , and / or Layer 3 signaling (e.g., RRC signaling) . To illustrate, the network node 110 may request, via RRC signaling, UE capability information and / or the UE 120 may transmit, via RRC signaling, the UE capability information. As part of communicating via the connection, the network node 110 may transmit configuration information via Layer 3 signaling (e.g., RRC signaling) , and activate and / or deactivate a particular configuration via Layer 2 signaling (e.g., a MAC CE) and / or Layer 1 signaling (e.g., DCI) . To illustrate, the network node 110 may transmit the configuration information via Layer 3 signaling at a first point in time associated with the UE 120 being tolerant of communication delays, and the network node 110 may transmit an activation of the configuration via Layer 2 signaling and / or Layer 1 signaling at a second point in time associated with the UE being less tolerant of communication delays.
[0138] As shown by reference number 1015, the receiver 1004 may transmit, and the transmitter 1002 may receive, an indication of a reordering capability. For instance, the receiver 1004 may be a UE 120 that indicates support for reordering shaped bits and unshaped bits based at least in part on a circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections as described with regard to Fig. 6-7C. Alternatively, or additionally, the receiver 1004 may indicate support for inter-leaver matrix mapping (e.g., SBPM inter-leaver matrix mapping) that is based at least in part on one or more row sequences as described with regard to Figs. 8A and 8B. In some cases, the receiver 1004 may indicate support for reordering shaped bits and unshaped bits in a receiver processing chain as described with regard to Figs. 9A and 9B. While the example 1000 includes the receiver 1004 indicating a reordering capability to the transmitter 1002, other examples may include the transmitter 1002 indicating a reordering capability to the receiver 1004, such as in the second example described above in which the transmitter is a UE 120 and the receiver 1004 is a network node 110.
[0139] For clarity, Fig. 10 illustrates the receiver 1004 transmitting the indication of the reordering capability in a separate transaction than establishing a connection with the transmitter 1002. However, in some aspects, the receiver 1004 may transmit the indication of the reordering capability as part of establishing a connection with the transmitter 1002.
[0140] As shown by reference number 1020, the transmitter 1002 may generate a transmission based at least in part on bit reordering. To illustrate, as described with regard to Figs. 3A and 3B, the transmitter 1002 may generate encoded bits based at least in part on a PAS-based architecture such that the encoded bits include shaped bits and unshaped bits. The transmitter 1002 may initially generate the encoded bits as a group of bits that use a first order as described with regard to Fig. 6. The first order may include positioning a first portion of the unshaped bits closest to a front of the bit group relative to the shaped bits and a second portion of the unshaped bits. The first portion may be followed by the shaped bits, and the shaped bits may be followed by the second portion. Based at least in part on the encoded bits including shaped bits and unshaped bis, the transmitter 1002 may reorder the bits into a second order as described with regard to Figs. 7A-7C. As one example, the second order may be based at least in part on a storing format for a circular buffer, where the storing format maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection (e.g., an RV0 index selection) and a second subset of bits that are associated with a second RV index selection (e.g., an RV3 index selection) . The second order, the storing format, or both may include positioning the shaped bits closest to the front of the bit group relative to the first portion of unshaped bits and the second portion of unshaped bits. The first portion of unshaped bits may follow the shaped bits in an adjacent position to the shaped bits, and the second portion of unshaped bits may follow the first portion of unshaped bits in an adjacent position to the first portion of unshaped bits. With regard to the storage format for the circular buffer, the shaped bits may be positioned at a first bit level position in the circular buffer. In some aspects, prior to storing the reordered bits in the circular buffer, the shaped bits and unshaped bits may be included in a bit group that includes one or more punctate bits, where the punctate bit(s) are positioned at a start of the bit group (e.g., for the first order, the second order, or both) . The punctate bits may not be stored in the circular buffer and may be removed from the bit group.
[0141] In some aspects, the transmitter 1002 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits, such as in a manner as described with regard to Fig. 7B. In other aspects, the transmitter 1002 may reorder the shaped bits and the unshaped bits (e.g., from the first order to the second order) after encoding the shaped bits and the unshaped bits. The encoding process performed by the transmitter 1002 may result in the transmitter 1002 generating one or more parity bits, and the transmitter 1002 may store the parity bit (s) in the circular buffer as at least part of the encoded bits.
[0142] Alternatively, or additionally, the transmitter 1002 may write the encoded bits for the transmission to one or more rows of an inter-leaver matrix, such as an SBPM inter-leaver matrix. In writing the encoded bits to the inter-leaver matrix, the transmitter may use a write execution order that is based at least in part on a row sequence in a similar manner as described with regard to Figs. 8A-8C. Writing the encoded bits to the inter-leaver matrix may include writing shaped bits to shaped bits rows of the inter-leaver matrix (e.g., based at least in part on one or more associated bit levels for the shaped bits, a shaped order, or a combination of the two) and writing unshaped bits to unshaped bits rows of the inter-leaver matrix (e.g., based at least in part on one or more associated bit levels for the unshaped bits, an unshaped order, or a combination of the two) . Writing the unshaped bits to the unshaped bits rows may also include the transmitter 1002 writing the parity bit (s) to at least one unshaped bits row of the inter-leaver matrix.
[0143] As shown by reference number 1025, the transmitter 1002 may transmit, and the receiver 1004 may receive, an indication of one or more row sequences. For example, the transmitter 1002 may transmit an indication of a row sequence for shaped bits rows, a row sequence for unshaped bits rows, or a row sequence for both shaped bits rows and unshaped bits rows) that is used to write bits into the inter-leaver matrix. As an example, the transmitter 1002 may indicate selection of a preconfigured row sequence in a table or specified by a communication standard.
[0144] As shown by reference number 1030, the transmitter 1002 may transmit, and the receiver 1004 may receive, the transmission. The transmission may include bits that are based at least in part on PAS and, consequently, may include shaped bits and the unshaped bits. An ordering of the shaped bits and the unshaped bits may be based at least in part on reordering, on one or more row sequences used for inter-leaving, or a combination of the two.
[0145] As shown by reference number 1035, the receiver 1004 may transmit, and the transmitter 1002 may receive, a retransmission request. As one example, the transmission may be associated with a HARQ process, and the receiver 1004 may transmit a NACK for a retransmission based at least in part on failing to successfully decode the transmission.
[0146] As shown by reference number 1040, the transmitter 1002 may obtain a segment of bits from the circular buffer using an RV index, where the segment of bits is a subset of bits that are stored in the circular buffer. Example RV indices include RV0 and RV3. In some aspects, the circular buffer may store encoded bits from the transmission described with regard to reference number 1030, where the circular buffer uses a storage format for the encoded bits that maximizes a quantity of shaped bits for multiple RV index selections as described above.
[0147] The transmitter 1002 may write the segment of bits to an inter-leaver matrix using a row sequence as described with regard to Figs. 8A and 8B. In some cases, the segment of bits may include one or more parity bits, and the transmitter 1002 may write the parity bits to one or more unshaped bits rows of the inter-leaver matrix. Alternatively, or additionally, the parity bits may form an end of the circular buffer such that the transmitter 1002 detects a wraparound event in which the bits within the segment of bits transition from an end of the circular buffer (e.g., unshaped parity bits) to a beginning of the circular buffer (e.g., shaped bits) . Based at least in part on detecting the wraparound event, the transmitter 1002 may record an inter-leaver index that is associated with the wraparound event, and may switch from writing to an unshaped bits row of the inter-leaver matrix to writing to a shaped bits row of the inter-leaver matrix. Based at least in part on completing writing the shaped bits to the shaped bits row (s) of the inter-leaver matrix, the transmitter 1002 may resume writing to the unshaped bits row (s) and, more particularly, may resume writing at an empty position in an unshaped bits row that is indicated by the inter-leaver index.
[0148] As shown by reference number 1045, the transmitter 1002 may transmit, and the receiver 1004 may receive, an indication of one or more row sequences. For example, the transmitter 1002 may transmit the indication in a similar manner as described with regard to reference number 1025.
[0149] As shown by reference number 1050, the transmitter 1002 may transmit, and the receiver may receive, a retransmission. In some aspects, the retransmission may include, as encoded bits, a subset of bits, and not an entirety of bits, that were transmitted in the transmission described with regard to reference number 1030. The encoded bits (e.g., the subset of bits) included in the retransmission may include shaped bits and the unshaped bits, and an ordering of the shaped bits and the unshaped bits may be based at least in part on reordering, on one or more row sequences used for inter-leaving, or a combination of the two as described with regard to Figs. 7A-7C and 8A-8C.
[0150] As shown by reference number 1055, the receiver 1004 may recover information from the transmission based at least in part on bit reordering. As one example, the receiver 1004 may perform a reverse inter-leaver matrix operation relative to the transmitter 1002. To illustrate, the receiver 1004 may write the encoded bits of the retransmission to one or more columns of an inter-leaver matrix, and may read the encoded bits from one or more rows of the inter-leaver matrix based at least in part on one or more row sequences that are indicated by the transmitter 1002. For example, the receiver 1004 may use a read execution order that is based at least in part on the row sequence (s) and a reversal of a write execution order used by the transmitter 1002. In some aspects, the encoded bits of the retransmission may include one or more parity bits that are written to one or more unshaped bits rows of the inter-leaver matrix. Alternatively, or additionally, in reading from the inter-leaver matrix, the receiver 1004 may detect a wraparound event. In a similar manner as the transmitter 1002, the receiver 1004 may record an inter-leaver index of a current unshaped bits row and the wraparound event, and the receiver 1004 may switch from reading from the unshaped bits row to reading from the shaped bits row (s) . Based at least in part on completing reading from the shaped bits rows of the inter-leaver matrix, the receiver 1004 may resume reading from the unshaped bits row using a location that is indicated by the inter-leaver index.
[0151] The receiver 1004 may reorder the shaped bits and the unshaped bits from a second order that positions the shaped bits at one or more locations that maximize a quantity of shaped bits for multiple RV index selections as described above, to a first order as described with regard to Fig. 6. In a first example, the receiver 1004 may reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits as described with regard to Fig. 9A. In a second example, the receiver 1004 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits as described with regard to Fig. 9B.
[0152] Using a circular buffer storage format that maximizes a quantity of shaped bits in multiple subsets of bits that are based at least in part on respective RV indices may enable a transmitter to generate a transmission that includes more shaping bits and, consequently, generate a transmission that increases power efficiency, increases spectral efficiency, or a combination of both. Including more shaped bits may reduce an average transmit power level for a transmission, may enable the use of a higher MCS for the transmission, or a combination of the two, resulting in increased power efficiency, increased spectral efficiency, or a combination of the two. Increased power efficiency may extend a battery life for some devices, and increased spectral efficiency may result in increased data throughput, reduced data transfer latencies, or a combination of the two.
[0153] As indicated above, Fig. 10 is provided as an example. Other examples may differ from what is described with regard to Fig. 10.
[0154] Fig. 11 is a diagram illustrating an example process 1100 performed, for example, at a transmitter or an apparatus of a transmitter. Example process 1100 is an example where the apparatus or the transmitter (e.g., a network node 110, a UE 120, an apparatus 1300, or an apparatus 1400) performs operations associated with circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections.
[0155] As shown in Fig. 11, in some aspects, process 1100 may include generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping (block 1110) . For example, the transmitter (e.g., using communication manager 1306, depicted in Fig. 13 for a network node, and using communication manager 1406, depicted in Fig. 14 for a UE) may generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping, as described above.
[0156] As further shown in Fig. 11, in some aspects, process 1100 may include storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits (block 1120) . For example, the transmitter (e.g., using communication manager 1306, depicted in Fig. 13 for a network node, and using communication manager 1406, depicted in Fig. 14 for a UE) may store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits, as described above.
[0157] Process 1100 may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes described elsewhere herein.
[0158] In a first aspect, the storing format includes the shaped bits being positioned at a first bit level of the circular buffer.
[0159] In a second aspect, the first order includes a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits, the first portion being followed by the shaped bits, and the shaped bits being followed by the second portion, and the second order includes the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, and the first portion and the second portion following the bits.
[0160] In a third aspect, the bit group includes one or more punctate bits that are positioned at a start of the bit group for the first order and the second order.
[0161] In a fourth aspect, the one or more punctate bits are not stored in the circular buffer.
[0162] In a fifth aspect, process 1100 includes reordering the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits.
[0163] In a sixth aspect, process 1100 includes generating one or more parity bits after encoding the shaped bits and the unshaped bits, and storing the one or more parity bits in the circular buffer as at least part of the encoded bits.
[0164] In a seventh aspect, process 1100 includes reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0165] In an eighth aspect, the first RV index selection is based at least in part on RV0, and the second RV index selection is based at least in part on RV3.
[0166] In a ninth aspect, process 1100 includes obtaining a segment of bits from the circular buffer, the segment of bits including the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits, and writing the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows including at least one of one or more shaped bits rows, and one or more unshaped bits rows.
[0167] In a tenth aspect, the segment of bits includes one or more parity bits, and writing the segment of bits to the one or more rows of the inter-leaver matrix includes writing the one or more parity bits to at least one unshaped bits row of the one or more unshaped bits rows.
[0168] In an eleventh aspect, process 1100 includes detecting, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event, recording, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event, and switching from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows.
[0169] In a twelfth aspect, process 1100 includes completing the writing to the one or more shaped bits rows, and resuming the writing to the at least one unshaped bits row based at least in part on the inter-leaver index.
[0170] In a thirteenth aspect, process 1100 includes transmitting an indication of the row sequence.
[0171] Although Fig. 11 shows example blocks of process 1100, in some aspects, process 1100 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in Fig. 11. Additionally, or alternatively, two or more of the blocks of process 1100 may be performed in parallel.
[0172] Fig. 12 is a diagram illustrating an example process 1200 performed, for example, at a receiver or an apparatus of a receiver. Example process 1200 is an example where the apparatus or the receiver (e.g., a network node 110, a UE 120, an apparatus 1300, or an apparatus 1400) performs operations associated with circular buffer storage format that maximizes a quantity of shaped bits for multiple RV index selections.
[0173] As shown in Fig. 12, in some aspects, process 1200 may include receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping (block 1210) . For example, the receiver (e.g., using reception component 1302 or communication manager 1306, depicted in Fig. 13 for a network node, and using reception component 1402 or communication manager 1406, depicted in Fig. 14 for a UE) may receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping, as described above.
[0174] As further shown in Fig. 12, in some aspects, process 1200 may include reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission (block 1220) . For example, the receiver (e.g., using communication manager 1306, depicted in Fig. 13 for a network node, and using communication manager 1406, depicted in Fig. 14 for a UE) may reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission, as described above.
[0175] Process 1200 may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes described elsewhere herein.
[0176] In a first aspect, the first order includes a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits, the first portion being followed by the shaped bits, and the shaped bits being followed by the second portion, and the second order includes the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, and the first portion and the second portion following the shaped bits.
[0177] In a second aspect, process 1200 includes reordering the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits.
[0178] In a third aspect, process 1200 includes reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0179] In a fourth aspect, the RV index includes an RV0, or an RV3.
[0180] In a fifth aspect, process 1200 includes receiving an indication of a row sequence that is associated with an inter-leaver matrix, writing the encoded bits to one or more columns of the inter-leaver matrix, and reading the encoded bits from one or more rows of the inter-leaver matrix based at least in part on the row sequence, the row sequence including at least one of one or more shaped bits rows, or one or more unshaped bits rows.
[0181] In a sixth aspect, the encoded bits include one or more parity bits, and reading the encoded bits from the one or more rows of the inter-leaver matrix includes reading the one or more parity bits from at least one unshaped bits row of the one or more unshaped bits rows.
[0182] In a seventh aspect, process 1200 includes detecting, based at least in part on reading the one or more parity bits from the at least one unshaped bits row, a wraparound event, recording, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event, and switching from reading from the at least one unshaped bits row to reading from the one or more shaped bits rows.
[0183] In an eighth aspect, process 1200 includes completing the reading from the one or more shaped bits rows, and resuming the reading from the at least one unshaped bits row based at least in part on the inter-leaver index.
[0184] Although Fig. 12 shows example blocks of process 1200, in some aspects, process 1200 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in Fig. 12. Additionally, or alternatively, two or more of the blocks of process 1200 may be performed in parallel.
[0185] Fig. 13 is a diagram of an example apparatus 1300 for wireless communication. The apparatus 1300 may be a network node (e.g., a network node 110) , or a network node 110 may include the apparatus 1300. In some aspects, the apparatus 1300 includes a reception component 1302, a transmission component 1304, or a communication manager 1306, which may be in communication with one another (for example, via one or more buses or one or more other components) . In some aspects, the communication manager 1306 is the communication manager 155 described in connection with Fig. 1. As shown, the apparatus 1300 may communicate with another apparatus 1308, such as a UE or a network node (such as a CU, a DU, an RU, or a base station) , using the reception component 1302 and the transmission component 1304. The communication manager 1306 may be included in, or implemented via, a processing system (for example, the processing system 145 described in connection with Fig. 1) of the transmitter.
[0186] In some aspects, the apparatus 1300 may be configured to perform one or more operations described herein in connection with Figs. 6-10. Additionally, or alternatively, the apparatus 1300 may be configured to perform one or more processes described herein, such as process 1100 of Fig. 11, process 1200 of Fig. 12, or a combination thereof. In some aspects, the apparatus 1300 or one or more components shown in Fig. 13 may include one or more components of the transmitter described in connection with Fig. 1. Additionally, or alternatively, one or more components shown in Fig. 13 may be implemented within one or more components described in connection with Fig. 1. Additionally, or alternatively, one or more components of the set of components may be implemented at least in part as software stored in one or more memories. For example, a component (or a portion of a component) may be implemented as instructions or code stored in a non-transitory computer-readable medium and executable by one or more controllers or one or more processors to perform the functions or operations of the component.
[0187] The reception component 1302 may receive communications, such as reference signals, control information, data communications, or a combination thereof, from the apparatus 1308. The reception component 1302 may provide received communications to one or more other components of the apparatus 1300. In some aspects, the reception component 1302 may perform signal processing on the received communications, and may provide the processed signals to the one or more other components of the apparatus 1300. In some aspects, the reception component 1302 may include one or more components of the transmitter described above in connection with Fig. 1, such as a radio, one or more RF chains, one or more transceivers, or one or more modems, each of which may in turn be coupled with one or more antennas of the transmitter.
[0188] The transmission component 1304 may transmit communications, such as reference signals, control information, data communications, or a combination thereof, to the apparatus 1308. In some aspects, one or more other components of the apparatus 1300 may generate communications and may provide the generated communications to the transmission component 1304 for transmission to the apparatus 1308. In some aspects, the transmission component 1304 may perform signal processing on the generated communications, and may transmit the processed signals to the apparatus 1308. In some aspects, the transmission component 1304 may include one or more components of the transmitter described above in connection with Fig. 1, such as a radio, one or more RF chains, one or more transceivers, or one or more modems, each of which may in turn be coupled with one or more antennas of the transmitter described in connection with Fig. 1. In some aspects, the transmission component 1304 may be co-located with the reception component 1302.
[0189] The communication manager 1306 may support operations of the reception component 1302 or the transmission component 1304. For example, the communication manager 1306 may receive information associated with configuring reception of communications by the reception component 1302 or transmission of communications by the transmission component 1304. Additionally, or alternatively, the communication manager 1306 may generate or provide control information to the reception component 1302 or the transmission component 1304 to control reception or transmission of communications.
[0190] Based at least in part on the apparatus 1300 being a network node (or being in a network node) that is a transmitter, the communication manager 1306 may generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The communication manager 1306 may store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0191] The communication manager 1306 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits. Alternatively, the communication manager 1306 may generate one or more parity bits after encoding the shaped bits and the unshaped bits.
[0192] The communication manager 1306 may store the one or more parity bits in the circular buffer as at least part of the encoded bits. In some aspects, the communication manager 1306 may reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0193] The communication manager 1306 may obtain a segment of bits from the circular buffer, the segment of bits including the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits. In some aspects, the communication manager 1306 may write the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows including at least one of one or more shaped bits rows, and one or more unshaped bits rows.
[0194] The communication manager 1306 may detect, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event. Based at least in part on detecting the wraparound event, the communication manager 1306 may record an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event. The communication manager 1306 may switch from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows. Alternatively, or additionally, the communication manager 1306 may complete the writing to the one or more shaped bits rows, and the communication manager 1306 may resume the writing to the at least one unshaped bits row based at least in part on the inter-leaver index. The transmission component 1304 may transmit an indication of the row sequence.
[0195] Alternatively, or additionally, based at least in part on the apparatus 1300 being a network node (or being in a network node) that is a receiver, the reception component 1302 may receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on PAS. The communication manager 1306 may reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0196] The communication manager 1306 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits. Alternatively, the communication manager 1306 may reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0197] In some aspects, the reception component 1302 may receive an indication of a row sequence that is associated with an inter-leaver matrix. The communication manager 1306 may write the encoded bits to one or more columns of the inter-leaver matrix. Alternatively, or additionally, the communication manager 1306 may read the encoded bits from one or more rows of the inter-leaver matrix based at least in part on the row sequence, the row sequence including at least one of one or more shaped bits rows, or one or more unshaped bits rows.
[0198] The communication manager 1306 may detect, based at least in part on reading the one or more parity bits from the at least one unshaped bits row, a wraparound event. In some aspects, the communication manager 1306 may record, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event. The communication manager 1306 may switch from reading from the at least one unshaped bits row to reading from the one or more shaped bits rows. The communication manager 1306 may complete the reading from the one or more shaped bits rows, and the communication manager 1306 may resume the reading from the at least one unshaped bits row based at least in part on the inter-leaver index.
[0199] The number and arrangement of components shown in Fig. 13 are provided as an example. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in Fig. 13. Furthermore, two or more components shown in Fig. 13 may be implemented within a single component, or a single component shown in Fig. 13 may be implemented as multiple, distributed components. Additionally, or alternatively, a set of (one or more) components shown in Fig. 13 may perform one or more functions described as being performed by another set of components shown in Fig. 13.
[0200] Fig. 14 is a diagram of an example apparatus 1400 for wireless communication. The apparatus 1400 may be a UE (e.g., a UE 120) , or a UE (e.g., a UE 120) may include the apparatus 1400. In some aspects, the apparatus 1400 includes a reception component 1402, a transmission component 1404, or a communication manager 1406, which may be in communication with one another (for example, via one or more buses or one or more other components) . In some aspects, the communication manager 1406 is the communication manager 150 described in connection with Fig. 1. As shown, the apparatus 1400 may communicate with another apparatus 1408, such as a UE or a network node (such as a CU, a DU, an RU, or a base station) , using the reception component 1402 and the transmission component 1404. The communication manager 1406 may be included in, or implemented via, a processing system (for example, the processing system 140 described in connection with Fig. 1) of the receiver.
[0201] In some aspects, the apparatus 1400 may be configured to perform one or more operations described herein in connection with Figs. 6-10. Additionally, or alternatively, the apparatus 1400 may be configured to perform one or more processes described herein, such as process 1100 of Fig. 11, process 1200 of Fig. 12, or a combination thereof. In some aspects, the apparatus 1400 or one or more components shown in Fig. 14 may include one or more components of the receiver described in connection with Fig. 1. Additionally, or alternatively, one or more components shown in Fig. 14 may be implemented within one or more components described in connection with Fig. 1. Additionally, or alternatively, one or more components of the set of components may be implemented at least in part as software stored in one or more memories. For example, a component (or a portion of a component) may be implemented as instructions or code stored in a non-transitory computer-readable medium and executable by one or more controllers or one or more processors to perform the functions or operations of the component.
[0202] The reception component 1402 may receive communications, such as reference signals, control information, data communications, or a combination thereof, from the apparatus 1408. The reception component 1402 may provide received communications to one or more other components of the apparatus 1400. In some aspects, the reception component 1402 may perform signal processing on the received communications, and may provide the processed signals to the one or more other components of the apparatus 1400. In some aspects, the reception component 1402 may include one or more components of the receiver described above in connection with Fig. 1, such as a radio, one or more RF chains, one or more transceivers, or one or more modems, each of which may in turn be coupled with one or more antennas of the receiver.
[0203] The transmission component 1404 may transmit communications, such as reference signals, control information, data communications, or a combination thereof, to the apparatus 1408. In some aspects, one or more other components of the apparatus 1400 may generate communications and may provide the generated communications to the transmission component 1404 for transmission to the apparatus 1408. In some aspects, the transmission component 1404 may perform signal processing on the generated communications, and may transmit the processed signals to the apparatus 1408. In some aspects, the transmission component 1404 may include one or more components of the receiver described above in connection with Fig. 1, such as a radio, one or more RF chains, one or more transceivers, or one or more modems, each of which may in turn be coupled with one or more antennas of the receiver described in connection with Fig. 1. In some aspects, the transmission component 1404 may be co-located with the reception component 1402.
[0204] The communication manager 1406 may support operations of the reception component 1402 or the transmission component 1404. For example, the communication manager 1406 may receive information associated with configuring reception of communications by the reception component 1402 or transmission of communications by the transmission component 1404. Additionally, or alternatively, the communication manager 1406 may generate or provide control information to the reception component 1402 or the transmission component 1404 to control reception or transmission of communications.
[0205] Based at least in part on the apparatus 1400 being a UE (or being in a UE) that is a receiver, the reception component 1402 may receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on PAS. The communication manager 1406 may reorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on an RV index that is associated with the retransmission.
[0206] The communication manager 1406 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits. Alternatively, the communication manager 1406 may reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0207] In some aspects, the reception component 1402 may receive an indication of a row sequence that is associated with an inter-leaver matrix. The communication manager 1406 may write the encoded bits to one or more columns of the inter-leaver matrix. Alternatively, or additionally, the communication manager 1406 may read the encoded bits from one or more rows of the inter-leaver matrix based at least in part on the row sequence, the row sequence including at least one of one or more shaped bits rows, or one or more unshaped bits rows.
[0208] The communication manager 1406 may detect, based at least in part on reading the one or more parity bits from the at least one unshaped bits row, a wraparound event. In some aspects, the communication manager 1406 may record, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event. The communication manager 1406 may switch from reading from the at least one unshaped bits row to reading from the one or more shaped bits rows. The communication manager 1406 may complete the reading from the one or more shaped bits rows, and the communication manager 1406 may resume the reading from the at least one unshaped bits row based at least in part on the inter-leaver index.
[0209] Alternatively, or additionally, based at least in part on the apparatus 1400 being a UE (or being in a UE) that is a transmitter, the communication manager 1406 may generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping. The communication manager 1406 may store the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first RV index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0210] The communication manager 1406 may reorder the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits. Alternatively, the communication manager 1406 may generate one or more parity bits after encoding the shaped bits and the unshaped bits.
[0211] The communication manager 1406 may store the one or more parity bits in the circular buffer as at least part of the encoded bits. In some aspects, the communication manager 1406 may reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0212] The communication manager 1406 may obtain a segment of bits from the circular buffer, the segment of bits including the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits. In some aspects, the communication manager 1406 may write the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows including at least one of one or more shaped bits rows, and one or more unshaped bits rows.
[0213] The communication manager 1406 may detect, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event. Based at least in part on detecting the wraparound event, the communication manager 1406 may record an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event. The communication manager 1406 may switch from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows. Alternatively, or additionally, the communication manager 1406 may complete the writing to the one or more shaped bits rows, and the communication manager 1406 may resume the writing to the at least one unshaped bits row based at least in part on the inter-leaver index. The transmission component 1404 may transmit an indication of the row sequence.
[0214] The number and arrangement of components shown in Fig. 14 are provided as an example. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in Fig. 14. Furthermore, two or more components shown in Fig. 14 may be implemented within a single component, or a single component shown in Fig. 14 may be implemented as multiple, distributed components. Additionally, or alternatively, a set of (one or more) components shown in Fig. 14 may perform one or more functions described as being performed by another set of components shown in Fig. 14.
[0215] The following provides an overview of some Aspects of the present disclosure:
[0216] Aspect 1: A method of wireless communication performed by a transmitter, comprising: generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and storing the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first redundancy version (RV) index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.
[0217] Aspect 2: The method of Aspect 1, wherein the storing format comprises the shaped bits being positioned at a first bit level of the circular buffer.
[0218] Aspect 3: The method of any of Aspects 1-2, wherein the first order comprises: a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits, the first portion being followed by the shaped bits, and the shaped bits being followed by the second portion, and wherein the second order comprises: the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, and the first portion and the second portion following the bits.
[0219] Aspect 4: The method of Aspect 3, wherein the bit group includes one or more punctate bits that are positioned at a start of the bit group for the first order and the second order.
[0220] Aspect 5: The method of Aspect 4, wherein the one or more punctate bits are not stored in the circular buffer.
[0221] Aspect 6: The method of any of Aspects 1-5, further comprising: reordering the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits.
[0222] Aspect 7: The method of Aspect 6, further comprising: generating one or more parity bits after encoding the shaped bits and the unshaped bits; and storing the one or more parity bits in the circular buffer as at least part of the encoded bits.
[0223] Aspect 8: The method of any of Aspects 1-7, further comprising: reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0224] Aspect 9: The method of any of Aspects 1-8, wherein the first RV index selection is based at least in part on RV index 0 (RV0) , and wherein the second RV index selection is based at least in part on RV index 3 (RV3) .
[0225] Aspect 10: The method of any of Aspects 1-9, further comprising: obtaining a segment of bits from the circular buffer, the segment of bits comprising the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits; and writing the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows comprising at least one of: one or more shaped bits rows, and one or more unshaped bits rows.
[0226] Aspect 11: The method of Aspect 10, wherein the segment of bits includes one or more parity bits, and wherein writing the segment of bits to the one or more rows of the inter-leaver matrix comprises: writing the one or more parity bits to at least one unshaped bits row of the one or more unshaped bits rows.
[0227] Aspect 12: The method of Aspect 11, further comprising: detecting, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event; recording, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event; and switching from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows.
[0228] Aspect 13: The method of Aspect 12, further comprising: completing the writing to the one or more shaped bits rows; and resuming the writing to the at least one unshaped bits row based at least in part on the inter-leaver index.
[0229] Aspect 14: The method of Aspect 10, further comprising transmitting an indication of the row sequence.
[0230] Aspect 15: A method of wireless communication performed by a receiver, comprising: receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; and reordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on a redundancy version (RV) index that is associated with the retransmission.
[0231] Aspect 16: The method of Aspect 15, wherein the first order comprises: a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits, the first portion being followed by the shaped bits, and the shaped bits being followed by the second portion, and wherein the second order comprises: the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, and the first portion and the second portion following the shaped bits.
[0232] Aspect 17: The method of any of Aspects 15-16, further comprising: reordering the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits.
[0233] Aspect 18: The method of any of Aspects 15-17, further comprising: reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.
[0234] Aspect 19: The method of any of Aspects 15-18, wherein the RV index comprises: an RV index 0 (RV0) , or an RV index 3 (RV3) .
[0235] Aspect 20: The method of any of Aspects 15-19, further comprising: receiving an indication of a row sequence that is associated with an inter-leaver matrix; writing the encoded bits to one or more columns of the inter-leaver matrix; and reading the encoded bits from one or more rows of the inter-leaver matrix based at least in part on the row sequence, the row sequence comprising at least one of: one or more shaped bits rows, or one or more unshaped bits rows.
[0236] Aspect 21: The method of Aspect 20, wherein the encoded bits include one or more parity bits, and wherein reading the encoded bits from the one or more rows of the inter-leaver matrix comprises: reading the one or more parity bits from at least one unshaped bits row of the one or more unshaped bits rows.
[0237] Aspect 22: The method of Aspect 21, further comprising: detecting, based at least in part on reading the one or more parity bits from the at least one unshaped bits row, a wraparound event; recording, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event; and switching from reading from the at least one unshaped bits row to reading from the one or more shaped bits rows.
[0238] Aspect 23: The method of Aspect 22, further comprising: completing the reading from the one or more shaped bits rows; and resuming the reading from the at least one unshaped bits row based at least in part on the inter-leaver index.
[0239] Aspect 24: An apparatus for wireless communication at a device, the apparatus comprising one or more processors; one or more memories coupled with the one or more processors; and instructions stored in the one or more memories and executable by the one or more processors to cause the apparatus to perform the method of one or more of Aspects 1-14.
[0240] Aspect 25: An apparatus for wireless communication at a device, the apparatus comprising one or more memories and one or more processors coupled to the one or more memories, the one or more processors configured to cause the device to perform the method of one or more of Aspects 1-14.
[0241] Aspect 26: An apparatus for wireless communication, the apparatus comprising at least one means for performing the method of one or more of Aspects 1-14.
[0242] Aspect 27: A non-transitory computer-readable medium storing code for wireless communication, the code comprising instructions executable by one or more processors to perform the method of one or more of Aspects 1-14.
[0243] Aspect 28: A non-transitory computer-readable medium storing a set of instructions for wireless communication, the set of instructions comprising one or more instructions that, when executed by one or more processors of a device, cause the device to perform the method of one or more of Aspects 1-14.
[0244] Aspect 29: A device for wireless communication, the device comprising a processing system that includes one or more processors and one or more memories coupled with the one or more processors, the processing system configured to cause the device to perform the method of one or more of Aspects 1-14.
[0245] Aspect 30: An apparatus for wireless communication at a device, the apparatus comprising one or more memories and one or more processors coupled to the one or more memories, the one or more processors individually or collectively configured to cause the device to perform the method of one or more of Aspects 1-14.
[0246] Aspect 31: A device comprising a processing system that includes one or more processors and one or more code-storing memories coupled with the one or more processors, the processing system configured to cause the device to perform the method of one or more of Aspects 1-14.
[0247] Aspect 32: A device comprising a processing system that includes processor circuitry and code-storing memory circuitry, the processing system configured to cause the device to perform the method of one or more of Aspects 1-14.
[0248] Aspect 33: An apparatus for wireless communication at a device, the apparatus comprising one or more processors; one or more memories coupled with the one or more processors; and instructions stored in the one or more memories and executable by the one or more processors to cause the apparatus to perform the method of one or more of Aspects 15-23.
[0249] Aspect 34: An apparatus for wireless communication at a device, the apparatus comprising one or more memories and one or more processors coupled to the one or more memories, the one or more processors configured to cause the device to perform the method of one or more of Aspects 15-23.
[0250] Aspect 35: An apparatus for wireless communication, the apparatus comprising at least one means for performing the method of one or more of Aspects 15-23.
[0251] Aspect 36: A non-transitory computer-readable medium storing code for wireless communication, the code comprising instructions executable by one or more processors to perform the method of one or more of Aspects 15-23.
[0252] Aspect 37: A non-transitory computer-readable medium storing a set of instructions for wireless communication, the set of instructions comprising one or more instructions that, when executed by one or more processors of a device, cause the device to perform the method of one or more of Aspects 15-23.
[0253] Aspect 38: A device for wireless communication, the device comprising a processing system that includes one or more processors and one or more memories coupled with the one or more processors, the processing system configured to cause the device to perform the method of one or more of Aspects 15-23.
[0254] Aspect 39: An apparatus for wireless communication at a device, the apparatus comprising one or more memories and one or more processors coupled to the one or more memories, the one or more processors individually or collectively configured to cause the device to perform the method of one or more of Aspects 15-23.
[0255] Aspect 40: A device comprising a processing system that includes one or more processors and one or more code-storing memories coupled with the one or more processors, the processing system configured to cause the device to perform the method of one or more of Aspects 15-23.
[0256] Aspect 41: A device comprising a processing system that includes processor circuitry and code-storing memory circuitry, the processing system configured to cause the device to perform the method of one or more of Aspects 15-23.
[0257] It will be apparent that systems or methods described herein may be implemented in different forms of hardware or a combination of hardware and software. A component being configured to perform a function means that the component has a capability to perform the function, and does not require the function to be actually performed by the component, unless noted otherwise.
[0258] As used herein, the term “determine” or “determining” can encompass one or more of a wide variety of actions. For example, “determining” can include one or more of calculating, computing, processing, deriving, detecting, estimating, investigating, looking up, inferring, ascertaining, measuring, resolving, selecting, choosing, obtaining, identifying, interpreting, demodulating, decoding, reading, establishing, forming or generating, among other examples. In some such examples, determining can involve a processor performing some type of calculating, computing, deriving, estimating, inferring, ascertaining, resolving, predicting or other processing to obtain one or more numerical values, sets, elements or other information or results. In some other such examples, determining can involve a processor identifying, looking up, investigating or otherwise obtaining some type of value, set, element or other information or result from a table, a data structure, a database or other memory device or location. In some other such examples, determining can involve a processor identifying, interpreting, demodulating, decoding, detecting, reading or otherwise obtaining some type of value, set, element or other information or result signaled in, for example, a received wireless packet. In some other such examples, determining can involve a processor selecting or choosing one or more values, sets, elements or other information or results from a larger set of values, sets elements or other information or results. In some other such examples, determining can involve a processor performing a measurement, such as on a received signal.
[0259] As used herein, the articles “a” and “an” are intended to refer to one or more items and may be used interchangeably with “one or more” or “at least one. ” As used herein, a phrase referring to “at least one of” or “one or more of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c. Additionally, as used herein, a phrase referring to “a” or “an” element refers to one or more of such elements acting individually or collectively to perform the recited function (s) . Additionally, as used herein, a “set” can refer to one or more items, and a “subset” can refer to a whole set or less than the whole set, but not an empty set. “Set, ” “group, ” and similar terms are intended to include one or more items and may be used interchangeably with “one or more. ” Furthermore, as used herein, the term “or” is intended to be interpreted in the inclusive sense (such as when referring to a series) and may be used interchangeably with “and / or, ” unless otherwise explicitly indicated (for example, if used in conjunction with “either” or “only one of” ) . For example, “A or B” may include A only, B only, or a combination of A and B. Also, as used herein, the terms “has, ” “have, ” “having, ” “comprise, ” “comprising, ” “include” and “including, ” and derivatives thereof or similar terms are intended to be open-ended terms that do not limit an element that they modify (for example, an element “having” A also may have B) .
[0260] As used herein, the phrase “associated with” is intended to be interpreted in the inclusive sense, unless otherwise explicitly indicated. For example, the phrase “associated with” is not to be construed as a reference to a closed set of conditions, factors, criteria, elements, components, or actions, among other examples. Specifically, unless a phrase refers to “associated with only ‘a, ’ ” or the equivalent in context, whatever it is that is “associated with ‘a, ’ ” may be associated with “a” alone or associated with a combination of “a” and one or more other conditions, factors, criteria, elements, components, or actions, among other examples. In various examples, the phrase “associated with” may be interpreted to mean “in association with, ” “in accordance with, ” “based on, ” “based at least in part on, ” “as a function of, ” “in response to, ” “responsive to, ” or “using” as appropriate in the relevant context unless otherwise explicitly indicated. Furthermore, what follows the phrase “associated with, ” “in association with, ” “in accordance with, ” “based on, ” “based at least in part on, ” “as a function of, ” “in response to, ” “responsive to, ” or “using” is not necessarily the focal point or primary factor associated with the limitation preceding the phrase.
[0261] As used herein, “satisfying a threshold” may, depending on the context, refer to a value being greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, or not equal to the threshold, among other examples.
[0262] Even though particular combinations of features are recited in the claims or disclosed in the specification, these combinations are not intended to limit the scope of all aspects described herein. Many of these features may be combined in ways not specifically recited in the claims or disclosed in the specification. The disclosure of various aspects includes each dependent claim in combination with every other claim in the claim set.
Claims
A transmitter, comprising:a processing system that includes one or more processors and one or more code-storing memories coupled with the one or more processors, the processing system configured to cause the transmitter to:generate encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; andstore the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first redundancy version (RV) index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.The transmitter of claim 1, wherein the storing format comprises the shaped bits being positioned at a first bit level of the circular buffer.The transmitter of claim 1, wherein the first order comprises:a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits,the first portion being followed by the shaped bits, andthe shaped bits being followed by the second portion, andwherein the second order comprises:the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, andthe first portion and the second portion following the bits.The transmitter of claim 1, wherein the processing system is configured to cause the transmitter to:reorder the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits.The transmitter of claim 1, wherein the processing system is configured to cause the transmitter to:reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.The transmitter of claim 1, wherein the processing system is configured to cause the transmitter to:obtain a segment of bits from the circular buffer, the segment of bits comprising the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits; andwrite the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows comprising at least one of:one or more shaped bits rows, andone or more unshaped bits rows.The transmitter of claim 6, wherein the segment of bits includes one or more parity bits, andwherein the processing system, to cause the transmitter to write the segment of bits to the one or more rows of the inter-leaver matrix, is configured to cause the transmitter to:write the one or more parity bits to at least one unshaped bits row of the one or more unshaped bits rows.The transmitter of claim 7, wherein the processing system is configured to cause the transmitter to:detect, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event;record, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event; andswitch from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows.The transmitter of claim 8, wherein the processing system is configured to cause the transmitter to:complete the writing to the one or more shaped bits rows; andresume the writing to the at least one unshaped bits row based at least in part on the inter-leaver index.The transmitter of claim 6, wherein the processing system is configured to cause the transmitter totransmit an indication of the row sequence.A receiver, comprising:a processing system that includes one or more processors and one or more code-storing memories coupled with the one or more processors, the processing system configured to cause the receiver to:receive encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; andreorder, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on a redundancy version (RV) index that is associated with the retransmission.The receiver of claim 11, wherein the first order comprises:a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits,the first portion being followed by the shaped bits, andthe shaped bits being followed by the second portion, andwherein the second order comprises:the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, andthe first portion and the second portion following the shaped bits.The receiver of claim 11, wherein the processing system is configured to cause the receiver to:reorder the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits.The receiver of claim 11, wherein the processing system is configured to cause the receiver to:reorder the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.The receiver of claim 11, wherein the processing system is configured to cause the receiver to:receive an indication of a row sequence that is associated with an inter-leaver matrix;write the encoded bits to one or more columns of the inter-leaver matrix; andread the encoded bits from one or more rows of the inter-leaver matrix based at least in part on the row sequence, the row sequence comprising at least one of:one or more shaped bits rows, orone or more unshaped bits rows.The receiver of claim 15, wherein the encoded bits include one or more parity bits, andwherein the processing system, to cause the receiver to read the encoded bits from the one or more rows of the inter-leaver matrix, is configured to cause the receiver to:read the one or more parity bits from at least one unshaped bits row of the one or more unshaped bits rows.The receiver of claim 16, wherein the processing system is configured to cause the receiver to:detect, based at least in part on reading the one or more parity bits from the at least one unshaped bits row, a wraparound event;record, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event; andswitch from reading from the at least one unshaped bits row to reading from the one or more shaped bits rows.The receiver of claim 17, wherein the processing system is configured to cause the receiver to:complete the reading from the one or more shaped bits rows; andresume the reading from the at least one unshaped bits row based at least in part on the inter-leaver index.A method of wireless communication performed by a transmitter, comprising:generating encoded bits that include shaped bits and unshaped bits in a first order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; andstoring the encoded bits in a circular buffer using a storing format that maximizes a quantity of the shaped bits that are included in a first subset of bits that are associated with a first redundancy version (RV) index selection and a second subset of bits that are associated with a second RV index selection, the storing format being based at least in part on a second order of the shaped bits and the unshaped bits.The method of claim 19, wherein the storing format comprises the shaped bits being positioned at a first bit level of the circular buffer.The method of claim 19, wherein the first order comprises:a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits,the first portion being followed by the shaped bits, andthe shaped bits being followed by the second portion, andwherein the second order comprises:the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, andthe first portion and the second portion following the bits.The method of claim 19, further comprising:reordering the shaped bits and the unshaped bits from the first order to the second order prior to encoding the shaped bits and the unshaped bits.The method of claim 19, further comprising:reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.The method of claim 19, further comprising:obtaining a segment of bits from the circular buffer, the segment of bits comprising the first subset of bits or the second subset of bits, the segment of bits including one or more of the shaped bits and one or more of the unshaped bits; andwriting the segment of bits to one or more rows of an inter-leaver matrix using a row sequence that is based at least in part on a shaped order and an unshaped order, the one or more rows comprising at least one of:one or more shaped bits rows, andone or more unshaped bits rows.The method of claim 24, wherein the segment of bits includes one or more parity bits, andwherein writing the segment of bits to the one or more rows of the inter-leaver matrix comprises:writing the one or more parity bits to at least one unshaped bits row of the one or more unshaped bits rows.The method of claim 25, further comprising:detecting, based at least in part on writing the one or more parity bits to the at least one unshaped bits row, a wraparound event;recording, based at least in part on detecting the wraparound event, an inter-leaver index of the at least one unshaped bits row that is associated with the wraparound event;switching from writing to the at least one unshaped bits row to writing to the one or more shaped bits rows;completing the writing to the one or more shaped bits rows; andresuming the writing to the at least one unshaped bits row based at least in part on the inter-leaver index.A method of wireless communication performed by a receiver, comprising:receiving encoded bits in a retransmission, the encoded bits including shaped bits and unshaped bits in a second order, the shaped bits and the unshaped bits being based at least in part on probabilistic amplitude shaping; andreordering, based at least in part on receiving the encoded bits in the retransmission, the shaped bits and the unshaped bits using a first order and based at least in part on a redundancy version (RV) index that is associated with the retransmission.The method of claim 27, wherein the first order comprises:a first portion of the unshaped bits being positioned closest to a front of a bit group relative to the shaped bits and a second portion of the unshaped bits,the first portion being followed by the shaped bits, andthe shaped bits being followed by the second portion, andwherein the second order comprises:the shaped bits being positioned closest to the front of the bit group relative to the first portion and the second portion, andthe first portion and the second portion following the shaped bits.The method of claim 27, further comprising:reordering the shaped bits and the unshaped bits from the first order to the second order prior to decoding the shaped bits and the unshaped bits.The method of claim 27, further comprising:reordering the shaped bits and the unshaped bits from the first order to the second order after encoding the shaped bits and the unshaped bits.