Display substrate and display apparatus

Abstract

A display substrate and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer, the driving structure layer comprises a plurality of circuit units, each circuit unit comprises a pixel driver circuit, a first initialization signal line (71), and a first power supply line (81), the light-emitting structure layer comprises a plurality of light-emitting units, each light-emitting unit comprises a light-emitting device, and the light-emitting device of the light-emitting unit is connected to the pixel driver circuit in the circuit unit; the first initialization signal line (71) is configured to provide a first initialization signal to the pixel driver circuit, and the first power supply line (81) is configured to provide a first power supply signal to the pixel driver circuit; and the driving structure layer further comprises at least one first connection line (91), the first connection line (91) is connected to the first initialization signal line (71), and the first connection line (91) is provided between the first power supply lines (81) of adjacent circuit units.

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate, including a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the driving structure layer away from the substrate; the driving structure layer includes a plurality of circuit units, at least one circuit unit including a pixel driving circuit, at least one first initial trace extending along a first direction, and at least one constant voltage signal trace extending along a second direction, the first direction and the second direction intersecting; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit including a light-emitting device, the light-emitting device of the at least one light-emitting unit being connected to the pixel driving circuit in the at least one circuit unit; the first initial trace is configured to provide a first initial signal to the pixel driving circuit, and the constant voltage signal trace is configured to provide a constant voltage signal to the pixel driving circuit or the light-emitting device; the driving structure layer further includes at least one first connecting trace extending along the second direction, the first connecting trace being connected to the first initial trace; in the first direction, the first connecting trace is disposed between the constant voltage signal traces of adjacent circuit units.

[0005] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit periodically arranged in the first direction. The plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a third light-emitting unit emitting a second color light, and a second light-emitting unit emitting a third color light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit, the pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit, and the pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The constant voltage signal trace includes at least a first power line and a second power line. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the light-emitting device. The first power line is respectively disposed in the first circuit unit and the second circuit unit, and the second power line is respectively disposed in the first circuit unit and the third circuit unit. In the first direction, the first connection trace is disposed between the first power line in the first circuit unit and the first power line in the second circuit unit.

[0006] In an exemplary embodiment, the pixel driving circuit in the first circuit unit and the pixel driving circuit in the second circuit unit are mirror-symmetrical with respect to the column center line, which is a straight line located between two adjacent circuit units in the first direction and extending along the second direction.

[0007] In an exemplary embodiment, the first initial trace includes a first initial signal line, the first connection trace includes a first connection line, and the first connection line is connected to the first initial signal line; the first initial signal line is configured to provide the same first initial signal to the pixel driving circuits in the first circuit unit, the second circuit unit, and the third circuit unit.

[0008] In an exemplary embodiment, the first initial trace includes a first type of first initial line and a second type of first initial line, and the first connection trace includes a first type of first connection line and a second type of first connection line. The first type of first connection line is connected to the first type of first initial line, and the second type of first connection line is connected to the second type of first initial line. The first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit, and the second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of first initial signal is different from the voltage of the second type of first initial signal.

[0009] In an exemplary embodiment, in the first direction, the first type of first connection line is disposed between constant voltage signal traces of an adjacent circuit unit, and the second type of first connection line is disposed between constant voltage signal traces of another adjacent circuit unit.

[0010] In an exemplary embodiment, in the first direction, the first type of first connection line and the second type of first connection line are together disposed between the constant voltage signal traces of adjacent circuit units.

[0011] In an exemplary embodiment, the first initial trace includes a first type of first initial line, a second type of first initial line, and a third type of first initial line; the first connection trace includes a first type of first connection line, a second type of first connection line, and a third type of first connection line; the first type of first connection line is connected to the first type of first initial line; the second type of first connection line is connected to the second type of first initial line; and the third type of first connection line is connected to the third type of first initial line. The first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit; the second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit; and the third type of first initial line is configured to provide a third type of first initial signal to the pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of first initial signal, the voltage of the second type of first initial signal, and the voltage of the third type of first initial signal are different.

[0012] In an exemplary embodiment, in the first direction, the first type of first connection line is disposed between constant voltage signal traces of an adjacent circuit unit, the second type of first connection line is disposed between constant voltage signal traces of another adjacent circuit unit, and the third type of first connection line is disposed between constant voltage signal traces of yet another adjacent circuit unit.

[0013] In an exemplary embodiment, in the first direction, the first type of first connection line, the second type of first connection line, and the third type of first connection line are arranged together between the constant voltage signal traces of adjacent circuit units.

[0014] In an exemplary embodiment, at least one circuit unit further includes a first type of second initial line and a second type of second initial line extending along the first direction. The first type of second initial line is configured to provide a first type of second initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit. The second type of second initial line is configured to provide a second type of second initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal.

[0015] In an exemplary embodiment, the driving structure layer further includes a first type of second connecting line and a second type of second connecting line extending along the second direction, wherein the first type of second connecting line is connected to the first type of second initial line and the second type of second connecting line is connected to the second type of second initial line; the first type of second connecting line is disposed in the second circuit unit and the second type of second connecting line is disposed in the third circuit unit.

[0016] In an exemplary embodiment, at least one circuit unit further includes a first type of second initial line, a second type of second initial line, and a third type of second initial line extending along the first direction. The first type of second initial line is configured to provide a first type of second initial signal to a pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit. The second type of second initial line is configured to provide a second type of second initial signal to a pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit. The third type of second initial line is configured to provide a third type of second initial signal to a pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of second initial signal, the voltage of the second type of second initial signal, and the voltage of the third type of second initial signal are different.

[0017] In an exemplary embodiment, the driving structure layer further includes a first type of second connecting line, a second type of second connecting line, and a third type of second connecting line extending along the second direction. The first type of second connecting line is connected to the first type of second initial line, the second type of second connecting line is connected to the second type of second initial line, and the third type of second connecting line is connected to the third type of second initial line.

[0018] In an exemplary embodiment, the pixel driving circuit includes at least a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first capacitor includes at least a first plate and a second plate, and the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first plate on the substrate. The second capacitor includes at least a third plate and a fourth plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate. The first electrode of the first transistor and the first electrode of the second transistor are connected to the first initial trace. The second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate, respectively. The second electrode of the third transistor is connected to the second plate and the fourth plate, respectively. The first electrode of the fourth transistor is connected to a data signal line extending along the second direction, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor and the third plate, respectively. A shielding electrode is disposed between at least one of the fourth plates and at least one of the data signal lines, and the shielding electrode is connected to the constant voltage signal trace.

[0019] In an exemplary embodiment, the driving structure layer includes multiple conductive layers in a direction perpendicular to the substrate, and the shielding electrode is disposed between the conductive layer where the fourth electrode plate is located and the conductive layer where the data signal line is located.

[0020] In an exemplary embodiment, the second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate via a first node electrode, respectively. The constant voltage signal trace includes at least a first power line, which is configured to provide a first power signal to the pixel driving circuit. In at least one circuit unit, an opening is provided on the first power line, and the orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the first node electrode on the substrate.

[0021] In an exemplary embodiment, the second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate via a first node electrode, respectively. The constant voltage signal trace includes at least a second power line, which is configured to provide a second power signal to the light-emitting device. In at least one circuit unit, the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the first node electrode on the substrate. The second power line includes at least a first region that overlaps with the first node electrode and a second region that does not overlap with the first node electrode. The width of the first region is smaller than the width of the second region, and the width is the dimension in the first direction.

[0022] In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the fourth transistor includes at least a fourth active layer, the constant voltage signal trace includes at least a second power line, the second power line being configured to provide a second power signal to the light-emitting device; in at least one circuit unit, the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the substrate.

[0023] In an exemplary embodiment, the fourth transistor includes at least a fourth gate electrode and a fourth active layer. The data signal line is connected to a data connection electrode, which is connected to a first region of the fourth active layer via a first active via. The third electrode is connected to a third node electrode, which is connected to a second region of the fourth active layer via a second active via. In the second direction, there is a first spacing between the first active via and the fourth gate electrode, and a second spacing between the second active via and the fourth gate electrode. The first spacing is 1.5 μm to 10 μm, and the second spacing is 1.5 μm to 10 μm. The first spacing is the minimum distance between the edge of the first active via near the fourth gate electrode and the edge of the fourth gate electrode near the first active via, and the second spacing is the minimum distance between the edge of the second active via near the fourth gate electrode and the edge of the fourth gate electrode near the second active via.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 is a schematic diagram of a display device;

[0028] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 is a schematic cross-sectional view of a display substrate;

[0030] Figure 4 is an equivalent circuit diagram of a pixel driving circuit;

[0031] Figure 5A is a schematic diagram of the arrangement of a circuit unit according to an exemplary embodiment of the present disclosure;

[0032] Figure 5B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0033] Figure 5C is a schematic diagram of the connection between a circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure;

[0034] Figure 6 is a schematic diagram of the arrangement of signal lines in a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 8 is a schematic diagram of a mesh connectivity structure according to an exemplary embodiment of the present disclosure;

[0037] Figure 9 is a schematic diagram of a display substrate after the formation of a first semiconductor layer pattern according to the present disclosure;

[0038] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure.

[0039] Figures 11A and 11B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0040] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0041] Figures 13A and 13B are schematic diagrams of a display substrate after a second semiconductor layer pattern has been formed in this disclosure;

[0042] Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.

[0043] Figure 15 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to the present disclosure;

[0044] Figures 16A and 16B are schematic diagrams of a display substrate after the formation of the fifth conductive layer pattern according to the present disclosure.

[0045] Figure 17 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0046] Figures 18A and 18B are schematic diagrams of a display substrate after the formation of the sixth conductive layer pattern according to the present disclosure;

[0047] Figure 19 is a cross-sectional view along direction AA in Figure 18A;

[0048] Figure 20 is a schematic diagram of the arrangement of signal lines in another display substrate according to an exemplary embodiment of the present disclosure;

[0049] Figure 21 is a schematic diagram of the arrangement of signal lines in a display substrate according to another exemplary embodiment of the present disclosure;

[0050] Figure 22 is a schematic diagram of the arrangement of signal lines in another display substrate according to an exemplary embodiment of the present disclosure.

[0051] Explanation of reference numerals in the attached drawings: 10—First capacitor; 11—First electrode; 12—Second electrode; 13—Third electrode; 14—Fourth electrode; 15—Electrode connecting strip; 20—Second capacitor; 21—First active layer; 22—Second active layer; 23—Third active layer; 24—Fourth active layer; 25—Fifth active layer; 26—Sixth active layer; 27—Sixth active layer; 31—First gate electrode; 32—Second gate electrode; 33B—Third bottom gate electrode; 33T—Third top gate electrode; 34—Fourth gate electrode; 35—Fifth gate electrode; 36—Sixth gate electrode; 37—Seventh gate electrode; 41—First light-emitting signal line; 42—Second light-emitting signal line; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Sixth connecting electrode; 57—Seventh connecting electrode; 58—Initial connecting electrode; 61—First scan signal line; 62—Second scan signal line; 63—Third scan signal line; 64—Fourth scan signal line; 65—First power connection line; 66—Second power connection line; 67—Shielding electrode; 71—First initial signal line; 71-1—First type first initial line; 71-2—Second type first initial line; 71-3—Third type first initial line; 72-1—First type second initial line; 72-2—Second type second initial line; 73—Initial connecting block; 74—First connecting block; 75—Second connecting block; 76—Third connecting block; 81—First power line; 82—Second power line; 83—Data signal line; 84—Anode connecting electrode; 91—First connecting line; 91-1—Class 1, First Connecting Line; 91-2—Class 2, First Connecting Line; 91-3—Class 3, First Connecting Line; 92-1—Class 1, Second Connecting Line; 92-2—Class 2, Second Connecting Line;101—Substrate; 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer; 111—First insulating layer; 112—Second insulating layer; 113—Third insulating layer; 114—Fourth insulating layer; 115—Fifth insulating layer; 116—Sixth insulating layer; 117—First planarization layer. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0053] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0054] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0055] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0056] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0057] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0058] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0059] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0060] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0061] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0062] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0063] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple first light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the first light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. A light-emitting driver can generate transmit signals to be provided to the first light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the first light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0064] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0065] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner.

[0066] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0067] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0068] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0069] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, in an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, or 8T1C structure. As shown in Figure 4, the pixel driving circuit can adopt a 7T2C structure. Each pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0070] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1. The second node N2 is connected to the second electrode of the third transistor T3, the first electrode of the fifth transistor T5, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the fourth transistor T4, and the first terminal of the second capacitor C2. The fourth node N4 is connected to the second electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6.

[0071] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second node N2. The first terminal of the second capacitor C2 is connected to the third node N3, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0072] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0073] In an exemplary embodiment, the second transistor T2 can be referred to as the second reset transistor. The gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode of the second transistor T2 is connected to the first initial signal line INIT1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0074] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first terminal of the third transistor T3 is connected to the second terminal of the seventh transistor T7, and the second terminal of the third transistor T3 is connected to the second node N2.

[0075] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0076] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0077] In an exemplary embodiment, the sixth transistor T6 can be referred to as the third reset transistor. The gate electrode of the sixth transistor T6 is connected to the second scan signal line S2, the first electrode of the sixth transistor T6 is connected to the second initial signal line INIT2, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0078] In an exemplary embodiment, the seventh transistor T7 can be referred to as the second light-emitting control transistor. The gate electrode of the seventh transistor T7 is connected to the second light-emitting signal line EM2, and the first electrode of the seventh transistor T3 is connected to the first power supply line VDD.

[0079] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0080] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide constant voltage signals to the pixel driving circuit; this disclosure does not limit the scope of the application.

[0081] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0082] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of both. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor. LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and oxide transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0083] In an exemplary embodiment, in the pixel driving circuit shown in FIG4, the seventh transistor can be a low-temperature polysilicon transistor (P-type transistor), and the first transistor T1 to the sixth transistor T6 can be oxide transistors (N-type transistors).

[0084] Figure 5A is a schematic diagram of the arrangement of circuit units according to an exemplary embodiment of the present disclosure; Figure 5B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure; and Figure 5C is a schematic diagram of the connection between circuit units and light-emitting units according to an exemplary embodiment of the present disclosure. As shown in Figures 5A, 5B, and 5C, in a direction perpendicular to the display substrate, the display area may include a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units, each circuit unit may include at least a pixel driving circuit; the light-emitting structure layer may include multiple light-emitting units, each light-emitting unit may include at least a light-emitting device; at least one pixel driving circuit is connected to at least one light-emitting unit; and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0085] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may at least partially overlap, or the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may not overlap.

[0086] In an exemplary embodiment, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3, which may be periodically arranged in a first direction X. The plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, and a third light-emitting unit F3, where the second light-emitting unit F2 may be disposed on one side of the first light-emitting unit F1 in a second direction Y, and the third light-emitting unit F3 may be disposed on one side of the first light-emitting unit F1 and the second light-emitting unit F2 in a first direction X.

[0087] In an exemplary embodiment, the first light-emitting unit F1 may include at least a first light-emitting device, the second light-emitting unit F2 may include at least a second light-emitting device, and the third light-emitting unit F3 may include at least a third light-emitting device. The pixel driving circuit in the first circuit unit Q1 is connected to the first light-emitting device in the first light-emitting unit F1 to form a first sub-pixel; the pixel driving circuit in the second circuit unit Q2 is connected to the second light-emitting device in the second light-emitting unit F2 to form a second sub-pixel; and the pixel driving circuit in the third circuit unit Q3 is connected to the third light-emitting device in the third light-emitting unit F3 to form a third sub-pixel. In an exemplary embodiment, a sub-pixel is formed by a connected circuit unit and a light-emitting unit.

[0088] In an exemplary embodiment, the first light-emitting device may be a light-emitting device that emits red light, the second light-emitting device may be a light-emitting device that emits green light, and the third light-emitting device may be a light-emitting device that emits blue light. Thus, the first circuit unit Q1 is the circuit unit whose pixel driving circuit drives the red light-emitting device, the second circuit unit Q2 is the circuit unit whose pixel driving circuit drives the green light-emitting device, and the third circuit unit Q3 is the circuit unit whose pixel driving circuit drives the blue light-emitting device.

[0089] In an exemplary embodiment, the shape of the circuit unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon, and the shape of the light-emitting unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon.

[0090] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the driving structure layer on a side away from the substrate; the driving structure layer includes a plurality of circuit units, at least one circuit unit including a pixel driving circuit, at least one first initial trace extending along a first direction, and at least one constant voltage signal trace extending along a second direction, the first direction and the second direction intersecting; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit including a light-emitting device, the light-emitting device of the at least one light-emitting unit being connected to the pixel driving circuit in the at least one circuit unit; the first initial trace is configured to provide a first initial signal to the pixel driving circuit, and the constant voltage signal trace is configured to provide a constant voltage signal to the pixel driving circuit or the light-emitting device; the driving structure layer further includes at least one first connecting trace extending along the second direction, the first connecting trace being connected to the first initial trace; in the first direction, the first connecting trace is disposed between the constant voltage signal traces of adjacent circuit units.

[0091] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit periodically arranged in the first direction. The plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a third light-emitting unit emitting a second color light, and a second light-emitting unit emitting a third color light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit, the pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit, and the pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The constant voltage signal trace includes at least a first power line and a second power line. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the light-emitting device. The first power line is respectively disposed in the first circuit unit and the second circuit unit, and the second power line is respectively disposed in the first circuit unit and the third circuit unit. In the first direction, the first connection trace is disposed between the first power line in the first circuit unit and the first power line in the second circuit unit.

[0092] In an exemplary embodiment, the first initial trace includes a first initial signal line, the first connection trace includes a first connection line, and the first connection line is connected to the first initial signal line; the first initial signal line is configured to provide the same first initial signal to the pixel driving circuits in the first circuit unit, the second circuit unit, and the third circuit unit.

[0093] In an exemplary embodiment, the first initial trace includes a first type of first initial line and a second type of first initial line, and the first connection trace includes a first type of first connection line and a second type of first connection line. The first type of first connection line is connected to the first type of first initial line, and the second type of first connection line is connected to the second type of first initial line. The first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit, and the second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of first initial signal is different from the voltage of the second type of first initial signal.

[0094] In an exemplary embodiment, the first initial trace includes a first type of first initial line, a second type of first initial line, and a third type of first initial line; the first connection trace includes a first type of first connection line, a second type of first connection line, and a third type of first connection line; the first type of first connection line is connected to the first type of first initial line; the second type of first connection line is connected to the second type of first initial line; and the third type of first connection line is connected to the third type of first initial line. The first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit; the second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit; and the third type of first initial line is configured to provide a third type of first initial signal to the pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of first initial signal, the voltage of the second type of first initial signal, and the voltage of the third type of first initial signal are different.

[0095] In an exemplary embodiment, at least one circuit unit further includes a first type of second initial line and a second type of second initial line extending along the first direction. The first type of second initial line is configured to provide a first type of second initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit. The second type of second initial line is configured to provide a second type of second initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal.

[0096] In an exemplary embodiment, at least one circuit unit further includes a first type of second initial line, a second type of second initial line, and a third type of second initial line extending along the first direction. The first type of second initial line is configured to provide a first type of second initial signal to a pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit. The second type of second initial line is configured to provide a second type of second initial signal to a pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit. The third type of second initial line is configured to provide a third type of second initial signal to a pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of second initial signal, the voltage of the second type of second initial signal, and the voltage of the third type of second initial signal are different.

[0097] The following examples illustrate the display substrate of this embodiment.

[0098] Figure 6 is a schematic diagram of the signal line arrangement in a display substrate according to an exemplary embodiment of the present disclosure. In a direction perpendicular to the display substrate, the display area may include a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units, each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer may include multiple light-emitting units, each light-emitting unit may include at least a light-emitting device. At least one pixel driving circuit is connected to at least one light-emitting device, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light. As shown in Figure 6, the multiple circuit units may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3, which may be periodically arranged in a first direction X. In this embodiment, the first circuit unit Q1 is the circuit unit whose pixel driving circuit drives a red light-emitting device, the second circuit unit Q2 is the circuit unit whose pixel driving circuit drives a green light-emitting device, and the third circuit unit Q3 is the circuit unit whose pixel driving circuit drives a blue light-emitting device.

[0099] In an exemplary embodiment, the pixel driving circuits of some circuit units can adopt a mirror design. For example, the pixel driving circuits of the first circuit unit Q1 and the second circuit unit Q2 can be mirror-symmetrical with respect to the column center line. That is, the pixel driving circuit connecting the red light-emitting device and the pixel driving circuit connecting the green light-emitting device can be mirror-symmetrical structures, and the column center line can be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y.

[0100] In some possible implementations, the pixel driving circuits of the first circuit unit Q1 and the third circuit unit Q3 can be mirror-symmetrical with respect to the column center line, that is, the pixel driving circuit connected to the red light-emitting device and the pixel driving circuit connected to the blue light-emitting device can be mirror-symmetrical structures. Alternatively, the pixel driving circuits of the second circuit unit Q2 and the third circuit unit Q3 can be mirror-symmetrical with respect to the column center line, that is, the pixel driving circuit connected to the green light-emitting device and the pixel driving circuit connected to the blue light-emitting device can be mirror-symmetrical structures. This disclosure does not limit the scope of the implementation.

[0101] In an exemplary embodiment, the driving structure layer may further include multiple first initial traces for transmitting a first initial signal and multiple second initial traces for transmitting a second initial signal. The first initial traces may include a first initial signal line 71, and the second initial traces may include a first type of second initial line 72-1 and a second type of second initial line 72-2. The shapes of the first initial signal line 71, the first type of second initial line 72-1, and the second type of second initial line 72-2 may be straight lines or broken lines extending along the first direction X of the main body.

[0102] In an exemplary embodiment, a first initial signal line 71 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of circuit units in the cell row. The first initial signal line 71 is configured to provide a first initial signal with the same voltage to the pixel driving circuit in the first circuit unit Q1 to the third circuit unit Q3 in the cell row.

[0103] In an exemplary embodiment, a first type of second initial line 72-1 may be disposed in each cell row and connected to the pixel driving circuits in a plurality of first circuit units Q1 and a plurality of second circuit units Q2 in the cell row. The first type of second initial line 72-1 is configured to provide a first type of second initial signal to the pixel driving circuits in the first circuit units Q1 and the second circuit units Q2 in the cell row.

[0104] In an exemplary embodiment, a second type of second initial line 72-2 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of third circuit units Q3 in the cell row. The second type of second initial line 72-2 is configured to provide a second type of second initial signal to the pixel driving circuit in the third circuit unit Q3 in the cell row, wherein the voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal.

[0105] This embodiment of the present disclosure splits the second initial trace for transmitting the second initial signal into a first type of second initial line and a second type of second initial line. The first type of second initial line is configured to provide the first type of second initial signal to the pixel driving circuit in the first circuit unit and the second circuit unit, and the second type of second initial line is configured to provide the second type of second initial signal to the pixel driving circuit in the third circuit unit. This enables the provision of different reset voltages to light-emitting devices of different colors, which can effectively improve the low grayscale display quality, display quality and display effect.

[0106] In some possible implementations, a first type of second initial line may be configured to provide a first type of second initial signal to the pixel driving circuits in the first and third circuit units, and a second type of second initial line may be configured to provide a second type of second initial signal to the pixel driving circuits in the second circuit unit. Alternatively, a first type of second initial line may be configured to provide a first type of second initial signal to the pixel driving circuits in the second and third circuit units, and a second type of second initial line may be configured to provide a second type of second initial signal to the pixel driving circuits in the first circuit unit. This disclosure does not limit the scope of the implementation.

[0107] In some possible implementations, the second initial trace transmitting the second initial signal can be split into a first type of second initial line, a second type of second initial line, and a third type of second initial line. The first type of second initial line is configured to provide a first type of second initial signal to the pixel driving circuit of one of the first to third circuit units. The second type of second initial line is configured to provide a second type of second initial signal to the pixel driving circuit of another of the first to third circuit units. The third type of second initial line is configured to provide a third type of second initial signal to the pixel driving circuit of yet another of the first to third circuit units. The voltage of the first type of second initial signal, the voltage of the second type of second initial signal, and the voltage of the third type of second initial signal are different, and this disclosure does not limit them.

[0108] In an exemplary embodiment, the drive structure layer may further include multiple first power connection lines 65, multiple second power connection lines 66, multiple first power lines 81, multiple second power lines 82, and multiple data signal lines 83. The shapes of the first power connection lines 65 and second power connection lines 66 may be straight lines or broken lines extending along a first direction X, and the shapes of the first power lines 81, second power lines 82, and data signal lines 83 may be straight lines or broken lines extending along a second direction Y.

[0109] In an exemplary embodiment, the first power connection line 65 may be disposed in each cell row, and the first power line 81 may be disposed in the cell column where the first circuit cell Q1 and the second circuit cell Q2 are located. The first power connection line 65 is connected to the first power line 81. The first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. The first power line 81 is configured to provide the first power signal to the pixel driving circuits in the first circuit cell Q1 to the third circuit cell Q3.

[0110] In an exemplary embodiment, the second power connection line 66 can be disposed in each cell row, and the second power line 82 can be disposed in the cell column where the first circuit cell Q1 and the third circuit cell Q3 are located. The second power connection line 66 is connected to the second power line 82. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting the second power signal. The second power line 82 is configured to provide the second power signal to the light-emitting device.

[0111] In an exemplary embodiment, a data signal line 83 may be provided in each cell column, and the data signal line 83 is configured to provide data signals to the pixel driving circuits in the first circuit cell Q1 to the third circuit cell Q3.

[0112] In an exemplary embodiment, the driving structure layer may further include multiple first connection traces and multiple second connection traces. The first connection traces may include a first connection line 91, and the second connection traces may include a first type of second connection line 92-1 and a second type of second connection line 92-2. The shapes of the first connection line 91, the first type of second connection line 92-1, and the second type of second connection line 92-2 may be straight lines or broken lines extending along the second direction Y of the main body.

[0113] In an exemplary embodiment, the first connecting line 91 is connected to the first initial signal line 71, and the first initial signal line 71 and the first connecting line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0114] In an exemplary embodiment, the first connecting line 91 can be disposed between the first power line 81 in the first circuit unit Q1 and the first power line 81 in the second circuit unit Q2, so that the first connecting line 91 can be moved away from the data signal line 83, thereby reducing the parasitic capacitance between the data signal line 83 and the first connecting line 91.

[0115] As shown in Figure 6, the data signal line 83 in the second circuit unit Q2 is located on the side of this circuit unit closer to the third circuit unit Q3, and the data signal line 83 in the third circuit unit Q3 is located on the side of this circuit unit closer to the second circuit unit Q2. That is, the data signal lines 83 in the second circuit unit Q2 and the third circuit unit Q3 are adjacent to each other. If the first connecting line 91 is located between the second circuit unit Q2 and the third circuit unit Q3, the first connecting line 91 is close to the data signal lines 83 in both the second and third circuit units Q2, resulting in a large parasitic capacitance between the data signal lines 83 and the first connecting line 91. Similarly, the data signal line 83 in the first circuit unit Q1 is located on the side closer to the third circuit unit Q3. If the first connecting line 91 is located between the first circuit unit Q1 and the third circuit unit Q3, the first connecting line 91 is close to the data signal line 83 in the first circuit unit Q1, resulting in a large parasitic capacitance between the data signal lines 83 and the first connecting line 91. This disclosure, by placing the first connecting line 91 between the first circuit unit Q1 and the second circuit unit Q2, allows the first connecting line 91 to be located away from the data signal line 83, effectively reducing the parasitic capacitance between the data signal line 83 and the first connecting line 91. Furthermore, since the first connecting line 91 is located between the two first power lines 81 of two adjacent circuit units, it not only further reduces the parasitic capacitance between the data signal line 83 and the first connecting line 91, but also, the first power line 81 with a constant potential can effectively shield the influence of the voltage jumps of the data signal line 83 on the first initial signal in the first connecting line 91, improving the stability of the first initial signal. This effectively ensures the accuracy of the threshold voltage Vth compensation and the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reducing the variation in the output current of the pixel driving circuit, effectively reducing the variation in light emission brightness, and effectively improving display quality and display effect.

[0116] In an exemplary embodiment, the first power line 81 and the second power line 82 can serve as constant voltage signal traces of this disclosure, and the first connecting line 91 can be disposed between constant voltage signal traces of adjacent circuit units. For example, the first connecting line 91 can be disposed between two adjacent first power lines 81. Alternatively, the first connecting line 91 can be disposed between two adjacent second power lines 82. Furthermore, the first connecting line 91 can be disposed between the first power line 81 and an adjacent second power line 82, which can also improve the stability of the first initial signal.

[0117] In an exemplary embodiment, the first power line 81 and the first connection line 91 can be disposed on the same layer. For example, for a 2SD display substrate, the first power line 81 and the first connection line 91 can be disposed in the second source / drain metal layer. As another example, for a 3SD display substrate, the first power line 81 and the first connection line 91 can be disposed in the second source / drain metal layer or the third source / drain metal layer.

[0118] In some possible implementations, the first power line 81 and the first connecting line 91 can be disposed in different conductive layers. For example, the shielding first power line 81 can be disposed in the second source-drain metal layer, and the first connecting line 91 can be disposed in the third source-drain metal layer. Alternatively, the first connecting line 91 can be disposed in the second source-drain metal layer, and the shielding first power line 81 can be disposed in the third source-drain metal layer; this disclosure does not impose any limitations on these aspects.

[0119] In an exemplary embodiment, the first initial signal line 71 and the first connection line 91 can be disposed in different conductive layers. For example, the first initial signal line 71 can be disposed in a gate metal layer or a first source / drain metal layer, and the first connection line 91 can be disposed in a second source / drain metal layer.

[0120] In an exemplary embodiment, the width of the first connecting line 91 can be from 1 μm to 100 μm.

[0121] In an exemplary embodiment, the first type of second connection line 92-1 is connected to the first type of second initial line 72-1, and the first type of second initial line 72-1 and the first type of second connection line 92-1 form a mesh-like interconnected structure on the display substrate for transmitting the first type of second initial signal.

[0122] In an exemplary embodiment, the first type of second connection line 92-1 may be disposed in the cell column where the second circuit unit Q2 is located.

[0123] In an exemplary embodiment, the second type of second connection line 92-2 is connected to the second type of second initial line 72-2, and the second type of second initial line 72-2 and the second type of second connection line 92-2 form a mesh-like interconnected structure on the display substrate for transmitting the second type of second initial signal.

[0124] In an exemplary embodiment, the second type of second connection line 92-2 can be disposed in the cell column where the third circuit unit Q3 is located.

[0125] In an exemplary embodiment, each of the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may have three vertical signal lines. That is, in addition to the data signal line 83, the circuit unit may also have two vertical signal lines for transmitting DC signals. For example, the three vertical signal lines in the first circuit unit Q1 may be a first power line 81, a second power line 82, and a data signal line 83. Similarly, the three vertical signal lines in the second circuit unit Q2 may be a first power line 81, a data signal line 83, and a first-type second connection line 92-1. Furthermore, the three vertical signal lines in the third circuit unit Q3 may be a second power line 82, a data signal line 83, and a second-type second connection line 92-2.

[0126] In an exemplary embodiment, the vertical signal lines transmitting DC signals can be arranged periodically in a first direction. For example, the first power line 81 can be respectively disposed in the first circuit unit Q1 and the second circuit unit Q2, and the second power line 82 can be respectively disposed in the first circuit unit Q1 and the third circuit unit Q3. As another example, the first type of second connecting line 92-1 can be disposed in the second circuit unit Q2, and the second type of second connecting line 92-2 can be disposed in the third circuit unit Q3.

[0127] In some possible implementations, depending on actual needs, at least one of the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be provided with two or four vertical signal lines; this disclosure does not limit this to any particular implementation.

[0128] Figure 7 is a schematic diagram of a display substrate structure according to an exemplary embodiment of the present disclosure, illustrating the structure of six circuit units in a unit row and six unit columns. The circuit units in the Nth and N+3th unit columns are third circuit units, the circuit units in the N+1th and N+4th unit columns are first circuit units, and the circuit units in the N+2th and N+5th unit columns are second circuit units. On a plane parallel to the display substrate, the display substrate may include multiple circuit units forming multiple unit rows and multiple unit columns. At least one circuit unit may include a pixel driving circuit, and a first light-emitting signal line 41, a second light-emitting signal line 42, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 71, a first type of second initial line 72-1 (or a second type of second initial line 72-2), a first power line (not shown), and a data signal line (not shown) connected to the pixel driving circuit. At least one pixel driving circuit may include at least a first capacitor 10, a second capacitor 20, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a third reset transistor, and a seventh transistor T7 as a second light-emitting control transistor.

[0129] In an exemplary embodiment, the first light-emitting signal line 41 and the second light-emitting signal line 42 are configured to provide a first light-emitting control signal and a second light-emitting control signal to the pixel driving circuit, respectively; the first scan signal line 61 to the fourth scan signal line 64 are configured to provide a first scan signal to the pixel driving circuit, respectively; the first power line is configured to provide a first power signal to the pixel driving circuit; and the data signal line is configured to provide a data signal to the pixel driving circuit.

[0130] In an exemplary embodiment, a first initial signal line 71 is configured to provide the same first initial signal to the pixel driving circuits in the first to third circuit units, a first type of second initial line 72-1 is configured to provide a first type of second initial signal to the pixel driving circuits in the first and second circuit units, and a second type of second initial line 72-2 is configured to provide a second type of second initial signal to the pixel driving circuits in the third circuit unit. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal.

[0131] In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 can be oxide transistors, and the seventh transistor T7 can be a polysilicon transistor. The first capacitor 10 may include at least a stacked first plate and a second plate, and the second capacitor 20 may include at least a stacked third plate and a fourth plate.

[0132] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first terminal of the first transistor T1 is connected to the first initial signal line 71, and the second terminal of the first transistor T1 is connected to the gate electrode 33 of the third transistor T3 and the first plate of the first capacitor 10, respectively. The gate electrode of the second transistor T2 is connected to the third scan signal line 63, the first terminal of the second transistor T2 is connected to the first initial signal line 71, and the second terminal of the second transistor T2 is connected to the second terminal of the fourth transistor T4 and the third plate of the second capacitor 20, respectively. The first terminal of the third transistor T3 is connected to the second terminal of the seventh transistor T7, and the second terminal of the third transistor T3 is connected to the first terminal of the fifth transistor T5, the second plate of the first capacitor 10, and the fourth plate of the second capacitor 20, respectively. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first terminal of the fourth transistor T4 is connected to the data signal line. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 41, and the second terminal of the fifth transistor T5 is connected to the second terminal of the sixth transistor T6. The gate electrode of the sixth transistor T6 is connected to the second scan signal line 62, and the first electrode of the sixth transistor T6 is connected to the first type second initial line 72-1 (or the second type second initial line 72-2). The gate electrode of the seventh transistor T7 is connected to the second light emission signal line 42, and the first electrode of the seventh transistor T7 is connected to the first power supply line.

[0133] In an exemplary embodiment, the shapes of the first light-emitting signal line 41, the second light-emitting signal line 42, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first initial signal line 71, the first type of second initial line 72-1, and the second type of second initial line 72-2 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line and the data signal line can be straight lines or broken lines extending along the second direction Y of the main body.

[0134] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0135] In an exemplary embodiment, the second light-emitting signal line 42 may be located on the side opposite to the second direction Y of the gate electrode 33 (i.e., the third gate electrode) of the third transistor T3. The first scan signal line 61 may be located on the side of the gate electrode 33 of the third transistor T3 in the second direction Y. The first initial signal line 71 may be located on the side of the first scan signal line 61 away from the gate electrode 33 of the third transistor T3. The third scan signal line 63 may be located on the side of the first initial signal line 71 away from the gate electrode 33 of the third transistor T3. The fourth scan signal line 64 may be located on the side of the third scan signal line 63 away from the gate electrode 33 of the third transistor T3. The first light-emitting signal line 41 may be located on the side of the fourth scan signal line 64 away from the gate electrode 33 of the third transistor T3. The second scan signal line 62 and the second type of second initial line 72-2 may be located on the side of the first light-emitting signal line 41 away from the gate electrode 33 of the third transistor T3. The first type of second initial line 72-1 may be located on the side of the second type of second initial line 72-2 away from the gate electrode 33 of the third transistor T3.

[0136] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least: a first semiconductor layer disposed on a substrate, a first insulating layer disposed on the side of the first semiconductor layer away from the substrate, a first conductive layer (first gate metal layer) disposed on the side of the first insulating layer away from the substrate, a second insulating layer disposed on the side of the first conductive layer away from the substrate, a second conductive layer (second gate metal layer) disposed on the side of the second insulating layer away from the substrate, a third insulating layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer (third gate metal layer) disposed on the side of the third insulating layer away from the substrate, a fourth insulating layer disposed on the side of the third conductive layer away from the substrate, a second semiconductor layer disposed on the side of the fourth insulating layer away from the substrate, a fifth insulating layer disposed on the side of the second semiconductor layer away from the substrate, a fourth conductive layer (fourth gate metal layer) disposed on the side of the fifth insulating layer away from the substrate, a sixth insulating layer disposed on the side of the fourth conductive layer away from the substrate, a fifth conductive layer (first source / drain metal layer) disposed on the side of the sixth insulating layer away from the substrate, a first planarization layer disposed on the side of the fifth conductive layer away from the substrate, and a sixth conductive layer (second source / drain metal layer) disposed on the side of the first planarization layer away from the substrate.

[0137] In an exemplary embodiment, a first electrode plate can be disposed in a first conductive layer and serve as the first terminal of a first capacitor 10, having the potential of a first node N1 in the pixel driving circuit. The first electrode plate can be connected to the second terminal of a first transistor T1 and the gate electrode 33 of a third transistor T3 via a first connecting electrode 51. A second electrode plate can be disposed in a second conductive layer and serve as the second terminal of the first capacitor 10, having the potential of a second node N2 in the pixel driving circuit. The second electrode plate can be connected to the second terminal of a third transistor T3 via a second connecting electrode 52. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode plate having the potential of the first node and the second electrode plate having the potential of the second node form the first capacitor 10 of the pixel driving circuit.

[0138] In an exemplary embodiment, the third electrode plate can be disposed in the first conductive layer and can serve as the first terminal of the second capacitor 10, having the potential of the third node N3 in the pixel driving circuit. The third electrode plate can be connected to the second terminal of the second transistor T2 and the second terminal of the fourth transistor T4 via the third connecting electrode 53. The fourth electrode plate can be disposed in the second conductive layer and can serve as the second terminal of the second capacitor 20, having the potential of the second node N2 in the pixel driving circuit. The fourth electrode plate can be connected to the first terminal of the fifth transistor T5 via the fourth connecting electrode 54. The orthographic projection of the fourth electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The third electrode plate 13 having the potential of the third node and the fourth electrode plate having the potential of the second node form the second capacitor 20 of the pixel driving circuit.

[0139] In an exemplary embodiment, the second type of second initial line 72-2 can be disposed in the first conductive layer, the first light-emitting signal line 41, the second scanning signal line 62 and the third scanning signal line 63 can be disposed in the fourth conductive layer, and the second light-emitting signal line 42, the first scanning signal line 61, the fourth scanning signal line 64, the first initial signal line 71 and the first type of second initial line 72-1 can be disposed in the fifth conductive layer.

[0140] In an exemplary embodiment, the pixel driving circuits in some adjacent cell columns may be substantially identical. For example, the pixel driving circuits in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the pixel driving circuits in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. And again, the pixel driving circuits in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0141] In an exemplary embodiment, the pixel driving circuits in some adjacent cell columns can be mirror-symmetrical with respect to the column center line. For example, the pixel driving circuits in the (N+1)th cell column and the (N+2)th cell column can be mirror-symmetrical with respect to the column center line. Similarly, the pixel driving circuits in the (N+4)th cell column and the (N+5)th cell column can be mirror-symmetrical with respect to the column center line.

[0142] Figure 8 is a schematic diagram of a mesh-like interconnected structure according to an exemplary embodiment of the present disclosure. As shown in Figure 8, the display substrate may further include a first power connection line 65, a second power connection line 66, and a second power line 82. The shapes of the first power connection line 65 and the second power connection line 66 may be straight lines or broken lines extending along the first direction X, and the shapes of the first power line 81 and the second power line 82 may be straight lines or broken lines extending along the second direction Y. The first power connection line 65 may be located on the side opposite to the second direction Y of the gate electrode 33 of the third transistor T3, and the second power connection line 66 may be located on the side of the second direction Y of the gate electrode 33 of the third transistor T3.

[0143] In an exemplary embodiment, a first power connection line 65 extending along a first direction X is connected to a first power line 81 extending along a second direction Y, and the first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting a first power signal.

[0144] In an exemplary embodiment, the first power connection line 65 may be provided in each cell row, and the first power line 81 may be provided in some cell columns (such as the N+1 cell column, the N+2 cell column, the N+4 cell column and the N+5 cell column). The first power line 81 may be connected to the first power connection line 65 through a via.

[0145] In an exemplary embodiment, a second power connection line 66 extending along a first direction X is connected to a second power line 82 extending along a second direction Y. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting a second power signal.

[0146] In an exemplary embodiment, the second power connection line 66 may be provided in each cell row, and the second power line 82 may be provided in some cell columns (such as the Nth cell column, the N+1th cell column, the N+3rd cell column, and the N+4th cell column). The second power line 82 may be connected to the second power connection line 66 through a via.

[0147] In an exemplary embodiment, the display substrate may further include a first connecting line 91, a first type of second connecting line 92-1, and a second type of second connecting line 92-2. The shapes of the first connecting line 91, the first type of second connecting line 92-1, and the second type of second connecting line 92-2 may be straight lines or broken lines extending along the second direction Y of the main body portion.

[0148] In an exemplary embodiment, a first initial signal line 71 extending along a first direction X is connected to a first connecting line 91 extending along a second direction Y, and the first initial signal line 71 and the first connecting line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0149] In an exemplary embodiment, the first initial signal line 71 may be disposed in each cell row, and the first connecting line 91 may be disposed in some cell columns (such as between the N+1th cell column and the N+2th cell column, or between the N+4th cell column and the N+5th cell column). The first connecting line 91 may be connected to the first initial signal line 71 through a via.

[0150] In an exemplary embodiment, a first type of second initial line 72-1 extending along the first direction X is connected to a first type of second connecting line 92-1 extending along the second direction Y. The first type of second initial line 72-1 and the first type of second connecting line 92-1 form a mesh-like interconnected structure on the display substrate for transmitting the first type of second initial signal.

[0151] In an exemplary embodiment, the first type of second initial line 72-1 can be provided in each cell row, and the first type of second connecting line 92-1 can be provided in some cell columns (such as the N+2 cell column and the N+5 cell column). The first type of second connecting line 92-1 can be connected to the first type of second initial line 72-1 through a via.

[0152] In an exemplary embodiment, a second type of second initial line 72-2 extending along the first direction X is connected to a second type of second connection line 92-2 extending along the second direction Y. The second type of second initial line 72-2 and the second type of second connection line 92-2 form a mesh-like interconnected structure on the display substrate for transmitting the second type of second initial signal.

[0153] In an exemplary embodiment, the second type of second initial line 72-2 can be provided in each cell row, and the second type of second connecting line 92-2 can be provided in some cell columns (such as the Nth cell column and the N+3th cell column). The second type of second connecting line 92-2 can be connected to the second type of second initial line 72-2 through vias.

[0154] In an exemplary embodiment, the first power connection line 65 and the second power connection line 66 may be disposed in the fifth conductive layer, and the first power line 81, the second power line 82, the first connection line 91, the first type of second connection line 92-1 and the second type of second connection line 92-2 may be disposed in the sixth conductive layer.

[0155] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0156] In an exemplary embodiment, taking six circuit units with one cell row and six cell columns (cell N to cell N+5) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0157] (11) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, patterning the first semiconductor thin film by a patterning process, and forming a first semiconductor layer pattern on the substrate, as shown in FIG9.

[0158] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit in the display substrate may include at least the seventh active layer 27 of the seventh transistor T7.

[0159] In an exemplary embodiment, the seventh active layer 27 can be L-shaped. The seventh active layer 27 may include a first region 27-1, a second region 27-2, and a channel region. The first region 27-1 and the second region 27-2 can be configured separately.

[0160] In an exemplary embodiment, in at least one cell row, the first region 27-1 of the seventh active layer in some adjacent circuit cells can be interconnected, and the seventh active layers 27 of two adjacent circuit cells can be an integral structure interconnected. For example, the seventh active layers 27 in the (N-1)th cell column and the seventh active layers 27 in the Nth cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 27-1 of the seventh active layer. Similarly, the seventh active layers 27 in the N+2th cell column and the seventh active layers 27 in the N+3th cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 27-1 of the seventh active layer. Furthermore, the seventh active layers 27 in the N+5th cell column and the seventh active layers 27 in the N+6th cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 27-1 of the seventh active layer. This disclosure effectively reduces the lateral wiring space, the number of vias, and the area occupied by the pixel driving circuit by setting some adjacent circuit units to share the first region of the seventh active layer (i.e., the first pole of the seventh transistor T7), which is beneficial to achieving high resolution.

[0161] In an exemplary embodiment, the first region 27-1 of the seventh active layer can serve as the first electrode of the seventh transistor T7, and the second region 27-2 of the seventh active layer can serve as the second electrode of the seventh transistor T7.

[0162] In exemplary embodiments, the first semiconductor layers in some adjacent cell columns may be substantially identical. For example, the shape and position of the seventh active layer 27 in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the shape and position of the seventh active layer 27 in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. Furthermore, the shape and position of the seventh active layer 27 in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0163] In an exemplary embodiment, the first semiconductor layer in some adjacent cell columns may be mirror-symmetric with respect to the column center line. For example, the seventh active layer 27 in the (N+1)th and (N+2)th cell columns may be mirror-symmetric with respect to the column center line. Similarly, the seventh active layer 27 in the (N+4)th and (N+5)th cell columns may be mirror-symmetric with respect to the column center line.

[0164] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), i.e., the seventh transistor T7 is an LTPS transistor. In an exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0165] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer covering the first semiconductor layer; and a first conductive layer pattern disposed on the first insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the first conductive layer in Figure 10A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0166] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least the first electrode 11 of the first capacitor, the third electrode 13 of the second capacitor, the seventh gate electrode 37, and the second type of second initial line 72-2.

[0167] In an exemplary embodiment, the shape of the first plate 11 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The first plate 11 is configured as a capacitor plate of the first capacitor (the first end of the first capacitor C1).

[0168] In an exemplary embodiment, a first electrode plate connecting block 11-1 may be provided on the first electrode plate 11. The shape of the first electrode plate connecting block 11-1 may be block-shaped (such as rectangular) and connected to the first electrode plate 11. The first electrode plate connecting block 11-1 is configured to be connected to the first connecting electrode subsequently formed.

[0169] In an exemplary embodiment, in at least one circuit unit, the first electrode plate 11 and the first electrode plate connecting block 11-1 can be an integral structure that is interconnected.

[0170] In an exemplary embodiment, the third plate 13 of the second capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, the edges of the block shape can be straight lines or broken lines, and it can be located on one side of the first plate 11 in the second direction Y. The third plate 13 is configured as a capacitor plate of the second capacitor (the first end of the second capacitor C2).

[0171] In an exemplary embodiment, a second electrode plate connecting block 13-1 may be provided on the third electrode plate 13. The shape of the second electrode plate connecting block 13-1 may be block-shaped (such as rectangular) and connected to the third electrode plate 13. The second electrode plate connecting block 13-1 is configured to be connected to the third connecting electrode subsequently formed.

[0172] In an exemplary embodiment, in at least one circuit unit, the third electrode plate 13 and the second electrode plate connecting block 13-1 can be an integral structure that is interconnected.

[0173] In an exemplary embodiment, the seventh gate electrode 37 may be block-shaped (e.g., rectangular), and the orthographic projection of the seventh gate electrode 37 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate. The seventh gate electrode 37 may serve as the gate electrode of the seventh transistor T7.

[0174] In an exemplary embodiment, in at least one cell row, the seventh gate electrodes 37 in some adjacent circuit cells can be interconnected, and the seventh gate electrodes 37 of two circuit cells can be an integrally connected structure. For example, the seventh gate electrodes 37 in the (N-1)th cell column and the seventh gate electrodes 37 in the Nth cell column can be an integrally connected structure. Similarly, the seventh gate electrodes 37 in the N+2th cell column and the seventh gate electrodes 37 in the N+3th cell column can be an integrally connected structure. Furthermore, the seventh gate electrodes 37 in the N+5th cell column and the seventh gate electrodes 37 in the N+6th cell column can be an integrally connected structure. By setting the seventh gate electrodes 37 in some adjacent circuit cells to an integrally connected structure, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0175] In an exemplary embodiment, the shape of the second type of second initial line 72-2 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The second type of second initial line 72-2 can be arranged on the side of the third electrode 13 away from the first electrode 11. The second type of second initial line 72-2 is configured to provide a second type of second initial signal to the sixth transistor T6 of the circuit cell in the Nth cell column and the N+3th cell column.

[0176] In an exemplary embodiment, an initial connection block 73 may be provided on the second type of second initial line 72-2. The initial connection block 73 may be block-shaped (e.g., rectangular), may be located on the side away from the third electrode plate 13, and may be connected to the second type of second initial line 72-2. The initial connection block 73 is configured to be connected to the subsequently formed initial connection electrode.

[0177] In an exemplary embodiment, the initial connecting block 73 may be disposed between the (N-1)th and N+1th unit columns, between the N+2th and N+3th unit columns, and between the N+5th and N+6th unit columns. In at least one unit row, the second type of second initial line 72-2 and the plurality of initial connecting blocks 73 may be an integral structure interconnected with each other.

[0178] In an exemplary embodiment, the first conductive layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the first electrode 11 and the third electrode 13 in the Nth, N+1th, N+3th, and N+4th cell columns may be substantially identical. Similarly, the shapes and positions of the first electrode 11 and the third electrode 13 in the N+2th and N+5th cell columns may be substantially identical.

[0179] In an exemplary embodiment, the first conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the first electrode 11 and the third electrode 13 in the (N+1)th and (N+2)th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the first electrode 11 and the third electrode 13 in the (N+2)th and (N+3)th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the first conductive layer in the (N+4)th and (N+5)th cell columns may be mirror-symmetrical with respect to the column center line.

[0180] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer pattern; and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the second conductive layer in Figure 11A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0181] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second electrode 12 of the first capacitor, a fourth electrode 14 of the second capacitor, and an electrode connecting strip 15.

[0182] In an exemplary embodiment, the shape of the second electrode plate 12 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured as another capacitor electrode plate of the first capacitor (the second end of the first capacitor C1). The stacked first electrode plate 11 and the second electrode plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0183] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor can be block-shaped (such as rectangular), with rounded corners at the corners and straight or broken edges. It can be located on one side of the second electrode plate 12 in the second direction Y. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 is configured as another capacitor electrode of the second capacitor (the second end of the second capacitor C2). The stacked third electrode plate 13 and the fourth electrode plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0184] In an exemplary embodiment, the shape of the electrode connecting strip 15 can be an extension along the second direction Y into a strip shape, and it can be disposed between the second electrode 12 and the fourth electrode 14. One end of the electrode connecting strip 15 is connected to the second electrode 12, and the other end of the electrode connecting strip 15 is connected to the fourth electrode 14.

[0185] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 12, the fourth electrode plate 14, and the electrode plate connecting strip 15 can be an integral structure that is interconnected.

[0186] In an exemplary embodiment, the second conductive layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the second electrode 12 and the fourth electrode 14 in the Nth, N+1th, N+3th, and N+4th cell columns may be substantially identical. Similarly, the shapes and positions of the second electrode 12 and the fourth electrode 14 in the N+2th and N+5th cell columns may be substantially identical.

[0187] In an exemplary embodiment, the second conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the second electrode 12 and the fourth electrode 14 in the N+1 and N+2 cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the second conductive layer in the N+4 and N+5 cell columns may be mirror-symmetrical with respect to the column center line.

[0188] (14) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third insulating layer covering the second conductive layer; and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the third conductive layer in Figure 12A. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0189] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include a third bottom gate electrode 33B and a bottom gate connection block 33-1.

[0190] In an exemplary embodiment, the third bottom gate electrode 33B can be block-shaped (such as rectangular), and the orthogonal projection of the third bottom gate electrode 33B on the substrate is within the range of the orthogonal projection of the second electrode plate 12 on the substrate. The third bottom gate electrode 33B can serve as the bottom gate electrode of the third transistor T3.

[0191] In an exemplary embodiment, the bottom gate connection block 33-1 can be L-shaped. The first end of the bottom gate connection block 33-1 is connected to the third bottom gate electrode 33B, and the second end of the bottom gate connection block 33-1 extends toward the fourth electrode plate 14. The second end of the bottom gate connection block 33-1 is configured to be connected to the second connection electrode formed subsequently.

[0192] In an exemplary embodiment, in at least one circuit unit, the third bottom gate electrode 33B and the bottom gate connection block 33-1 can be an integral structure that is interconnected.

[0193] (15) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the second semiconductor film by a patterning process to form a fourth insulating layer covering a third conductive layer, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in Figures 13A and 13B, where Figure 13B is a planar schematic diagram of the second semiconductor layer in Figure 13A.

[0194] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit in the display substrate may include the first active layer 21 of the first transistor T1 to the sixth active layer 26 of the sixth transistor T6, and the first active layer 21, the second active layer 22 and the fourth active layer 24 may be an integral structure interconnected with each other, and the fifth active layer 25 and the sixth active layer 26 may be an integral structure interconnected with each other.

[0195] In an exemplary embodiment, the first active layer 21, the second active layer 22, the fourth active layer 24, and the fifth active layer 25 to the sixth active layer 26 can be located on the same side of the third active layer 23 in the first direction X. The first active layer 21, the second active layer 22, the fourth active layer 24, and the fifth active layer 25 to the sixth active layer 26 can be located on one side of the third active layer 23 in the second direction Y, and the seventh active layer 27 can be located on the opposite side of the third active layer 23 in the second direction Y. The second active layer 22 can be located on one side of the first active layer 21 in the second direction Y, and the fourth active layer 24 can be located on one side of the second active layer 22 in the second direction Y, that is, the first active layer 21 and the fourth active layer 24 can be located on opposite sides of the second active layer 22 in the second direction Y. The fifth active layer 25 can be located on one side of the third active layer 23 in the second direction Y, and the sixth active layer 26 can be located on one side of the fifth active layer 25 in the second direction Y.

[0196] In an exemplary embodiment, the first active layer 21 to the fifth active layer 25 can be a strip shape extending along the second direction Y, and the sixth active layer 26 can be a "U" shape.

[0197] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer may be interconnected, and the first region 21-1 of the first active layer may serve as the first region 22-1 of the second active layer. The second region 22-2 of the second active layer and the second region 24-2 of the fourth active layer may be interconnected, and the second region 22-2 of the second active layer may serve as the second region 24-2 of the fourth active layer. The second region 25-2 of the fifth active layer and the second region 26-2 of the sixth active layer may be interconnected, and the second region 25-2 of the fifth active layer may serve as the second region 26-2 of the sixth active layer. The second regions 21-2 of the first active layer, 23-1 and 23-2 of the third active layer, 24-1 of the fourth active layer, 25-1 of the fifth active layer, and 26-1 of the sixth active layer may be individually configured.

[0198] In an exemplary embodiment, the orthographic projections of the second region 25-2 of the fifth active layer and the second region 26-2 of the sixth active layer onto the substrate at least partially overlap with the orthographic projection of the second initial line 72-2 of the second class onto the substrate.

[0199] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode 33B on the substrate.

[0200] In an exemplary embodiment, the first region 21-1 of the first active layer can serve as the first electrode of the first transistor T1, the second region 21-2 of the first active layer can serve as the second electrode of the first transistor T1, the first region 22-1 of the second active layer can serve as the first electrode of the second transistor T2, the second region 22-2 of the second active layer can serve as the second electrode of the second transistor T2, the first region 23-1 of the third active layer can serve as the first electrode of the third transistor T3, the second region 23-2 of the third active layer can serve as the second electrode of the third transistor T3, the first region 24-1 of the fourth active layer can serve as the first electrode of the fourth transistor T4, the second region 24-2 of the fourth active layer can serve as the second electrode of the fourth transistor T4, the first region 25-1 of the fifth active layer can serve as the first electrode of the fifth transistor T5, the second region 25-2 of the fifth active layer can serve as the second electrode of the fifth transistor T5, the first region 26-1 of the sixth active layer can serve as the first electrode of the sixth transistor T6, and the second region 26-2 of the sixth active layer can serve as the second electrode of the sixth transistor T6.

[0201] In an exemplary embodiment, since the second terminal of the third transistor T3 in the pixel driving circuit is connected to the first terminal of the fifth transistor T5, the second region 23-2 of the third active layer and the first region 25-1 of the fifth active layer can be directly connected. Because the distance between the second region 23-2 of the third active layer and the first region 25-1 of the fifth active layer is relatively large, the active connection line connecting them is not only relatively long, but also overlaps with the fourth electrode plate 14. Therefore, this disclosure adopts a scheme where the second region 23-2 of the third active layer and the first region 25-1 of the fifth active layer are set separately, avoiding redundant traces in the oxide active layer and reducing the impact of redundant traces on the stability of the pixel driving circuit.

[0202] In exemplary embodiments, the second semiconductor layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the Nth and N+3th cell columns may be substantially identical. Similarly, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the N+1th and N+4th cell columns may be substantially identical. Furthermore, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the N+2th and N+5th cell columns may be substantially identical.

[0203] In an exemplary embodiment, the second semiconductor layer in some adjacent cell columns may be mirror-symmetric with respect to the column center line. For example, the first active layer 21 to the sixth active layer 26 in the N+1 and N+2 cell columns may be mirror-symmetric with respect to the column center line. Similarly, the second semiconductor layer in the N+4 and N+5 cell columns may be mirror-symmetric with respect to the column center line.

[0204] In an exemplary embodiment, the second semiconductor layer can be an oxide layer, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. In an exemplary embodiment, the oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). For example, the second semiconductor layer can be indium gallium zinc oxide (IGZO).

[0205] (16) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: sequentially depositing a fifth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer pattern; and a fourth conductive layer pattern disposed on the fifth insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth gate metal (GATE4) layer.

[0206] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 31, a second gate electrode 32, a third top gate electrode 33T, a fourth gate electrode 34, a fifth gate electrode 35, a sixth gate electrode 36, a first light-emitting signal line 41, a second scan signal line 62, and a third scan signal line 63.

[0207] In an exemplary embodiment, the first gate electrode 31 may be block-shaped (such as rectangular), and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first gate electrode 31 may serve as the gate electrode of the first transistor T1.

[0208] In an exemplary embodiment, in at least one cell row, the first gate electrodes 31 in some adjacent circuit cells can be interconnected, and the first gate electrodes 31 of two circuit cells can be an integrally connected structure. For example, the first gate electrodes 31 in the (N-1)th cell column and the first gate electrodes 31 in the Nth cell column can be an integrally connected structure. Similarly, the first gate electrodes 31 in the N+2th cell column and the first gate electrodes 31 in the N+3th cell column can be an integrally connected structure. Furthermore, the first gate electrodes 31 in the N+5th cell column and the first gate electrodes 31 in the N+6th cell column can be an integrally connected structure. By setting the first gate electrodes 31 in some adjacent circuit cells to an integrally connected structure, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0209] In an exemplary embodiment, the second gate electrode 32 may be block-shaped (such as rectangular) and may be disposed on one side of the first gate electrode 31 in the second direction Y. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second gate electrode 32 may serve as the gate electrode of the second transistor T2.

[0210] In an exemplary embodiment, the third top gate electrode 33T can be block-shaped (such as rectangular), and the orthographic projection of the third top gate electrode 33T on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The third top gate electrode 33T can serve as the top gate electrode of the third transistor T3.

[0211] In an exemplary embodiment, the fourth gate electrode 34 may be block-shaped (e.g., rectangular) and may be disposed on one side of the second gate electrode 32 in the second direction Y. The orthographic projection of the fourth gate electrode 34 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth gate electrode 34 may serve as the gate electrode of the fourth transistor T4.

[0212] In an exemplary embodiment, the fifth gate electrode 35 may be block-shaped (e.g., rectangular) and may be disposed on one side of the fourth gate electrode 34 in the second direction Y. The orthographic projection of the fifth gate electrode 35 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer on the substrate. The fifth gate electrode 35 may serve as the gate electrode of the fifth transistor T5.

[0213] In an exemplary embodiment, the sixth gate electrode 36 may be block-shaped (e.g., rectangular) and may be disposed on one side of the fifth gate electrode 35 in the second direction Y. The orthographic projection of the sixth gate electrode 36 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The sixth gate electrode 36 may serve as the gate electrode of the sixth transistor T6.

[0214] In an exemplary embodiment, the shape of the first light-emitting signal line 41 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. The first light-emitting signal line 41 can be arranged on one side of the fourth gate electrode 34 in the second direction Y, and connected to multiple fifth gate electrodes 35 in a unit row, thus realizing that the first light-emitting signal line 41 can control the conduction or disconnection of the fifth transistor T5.

[0215] In an exemplary embodiment, in at least one cell row, the first light-emitting signal line 41 and the plurality of fifth gate electrodes 35 can be an integral structure that is interconnected.

[0216] In an exemplary embodiment, the shape of the second scan signal line 62 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The second scan signal line 62 can be arranged on one side of the first light-emitting signal line 41 in the second direction Y, and connected to a plurality of sixth gate electrodes 36 in a unit row, thus enabling the second scan signal line 62 to control the conduction or disconnection of the sixth transistor T6.

[0217] In an exemplary embodiment, in at least one cell row, the second scan signal line 62 and the plurality of sixth gate electrodes 36 can be an integral structure interconnected with each other.

[0218] In an exemplary embodiment, the third scan signal line 63 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The third scan signal line 63 can be disposed between the first gate electrode 31 and the fourth gate electrode 34, and connected to multiple second gate electrodes 32 in a cell row, thus enabling the third scan signal line 63 to control the conduction or disconnection of the second transistor T2.

[0219] In an exemplary embodiment, the fourth conductive layer in some adjacent cell columns may be substantially identical. For example, the shape and position of the fourth conductive layer in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the shape and position of the fourth conductive layer in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. Furthermore, the shape and position of the fourth conductive layer in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0220] In an exemplary embodiment, the fourth conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the fourth conductive layers in the (N-1)th and N+1th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the fourth conductive layers in the N+2th and N+3th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the fourth conductive layers in the N+5th and N+6th cell columns may be mirror-symmetrical with respect to the column center line.

[0221] (17) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, as shown in FIG15.

[0222] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a first via V1 to a twentieth via V20.

[0223] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer (which is also the first region of the second active layer) onto the substrate. The sixth and fifth insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to allow a subsequently formed first type of first initial line to be connected to the first region of the first active layer (which is also the first region of the second active layer) through the via.

[0224] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The sixth and fifth insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer through the via.

[0225] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the second region of the second active layer (which is also the second region of the fourth active layer) onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the second region of the second active layer (which is also the second region of the fourth active layer). The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the second region of the second active layer (which is also the second region of the fourth active layer) through the via.

[0226] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the first region of the third active layer onto the substrate. The sixth and fifth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the third active layer. The fourth via V4 is configured to allow a subsequently formed seventh connection electrode to be connected to the first region of the third active layer through the via.

[0227] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the second region of the third active layer onto the substrate. The sixth insulating layer and the fifth insulating layer within the fifth via V5 are etched away, exposing the surface of the second region of the third active layer. The fifth via V5 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the third active layer through the via.

[0228] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The sixth and fifth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the fourth active layer. The sixth via V6 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the fourth active layer through the via.

[0229] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The sixth and fifth insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the fifth active layer. The seventh via V7 is configured to allow the subsequently formed fourth connection electrode to be connected to the first region of the fifth active layer through the via.

[0230] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is located within the range of the orthographic projection of the second region of the fifth active layer (which is also the second region of the sixth active layer) onto the substrate. The sixth insulating layer and the fifth insulating layer within the eighth via V8 are etched away, exposing the surface of the second region of the fifth active layer (which is also the second region of the sixth active layer). The eighth via V8 is configured to allow the subsequently formed sixth connection electrode to be connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the via.

[0231] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the orthographic projection of the first region of the sixth active layer onto the substrate. The sixth and fifth insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the sixth active layer. The ninth via V9 in the Nth and N+3th cell columns are configured to allow subsequently formed initial connection electrodes to connect to the first region of the sixth active layer through the via. The ninth via V9 in the N+1th, N+2th, N+4th, and N+5th cell columns are configured to allow subsequently formed first-type second initial lines to connect to the first region of the sixth active layer through the via.

[0232] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the first region of the seventh active layer onto the substrate. The sixth, fifth, fourth, third, second, and first insulating layers within the tenth via V10 are etched away, exposing the surface of the first region of the seventh active layer. The tenth via V10 is configured to allow a subsequently formed first power connection line to connect to the first region of the seventh active layer through this via. Since two partially adjacent circuit units share the same first region of the seventh active layer, they can share the same tenth via V10, effectively reducing the number of vias and decreasing the footprint of the pixel driving circuit, which is beneficial for achieving high resolution.

[0233] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second region of the seventh active layer onto the substrate. The sixth, fifth, fourth, third, second, and first insulating layers within the eleventh via V11 are etched away, exposing the surface of the second region of the seventh active layer. The eleventh via V11 is configured to allow the subsequently formed seventh connection electrode to be connected to the second region of the seventh active layer through the via.

[0234] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the third top gate electrode 33T on the substrate. The sixth insulating layer in the twelfth via V12 is etched away, exposing the surface of the third top gate electrode 33T. The twelfth via V12 is configured to allow the subsequently formed first connection electrode to be connected to the third top gate electrode 33T through the via.

[0235] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the fourth gate electrode 34 on the substrate. The sixth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the fourth gate electrode 34. The thirteenth via V13 is configured to allow the subsequently formed fourth scan signal line to be connected to the fourth gate electrode 34 through the via.

[0236] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the range of the orthographic projection of the first gate electrode 31 onto the substrate. The sixth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the first gate electrode 31. The fourteenth via V14 is configured to allow the subsequently formed first scan signal line to connect to the first gate electrode 31 through this via. Since the first gate electrodes 31 in two partially adjacent circuit units are interconnected as a single structure, the two partially adjacent circuit units can share the fourteenth via V14, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0237] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate lies within the orthogonal projection of the seventh gate electrode 37 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fifteenth via V15 are etched away, exposing the surface of the seventh gate electrode 37. The fifteenth via V15 is configured to allow the subsequently formed second light-emitting signal line to connect to the seventh gate electrode 37 through this via. Since the seventh gate electrodes 37 in two partially adjacent circuit units are interconnected as a single structure, the two partially adjacent circuit units can share the fifteenth via V15, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0238] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the first electrode plate connecting block 11-1 on the substrate. The sixth, fifth, fourth, third, and second insulating layers within the sixteenth via V16 are etched away, exposing the surface of the first electrode plate connecting block 11-1. The sixteenth via V16 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate connecting block 11-1 through the via.

[0239] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the second electrode plate 12 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the seventeenth via V17 are etched away, exposing the surface of the second electrode plate 12. The seventeenth via V17 is configured to allow a subsequently formed second connection electrode to be connected to the second electrode plate 12 through the via.

[0240] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the second electrode connecting block 13-1 of the third electrode 13 on the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighteenth via V18 are etched away, exposing the surface of the second electrode connecting block 13-1. The eighteenth via V18 is configured to allow the subsequently formed third connecting electrode to be connected to the second electrode connecting block 13-1 through the via.

[0241] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the fourth electrode plate 14 on the substrate. The sixth, fifth, fourth and third insulating layers within the nineteenth via V19 are etched away, exposing the surface of the fourth electrode plate 14. The nineteenth via V19 is configured to allow the subsequently formed fourth connection electrode to be connected to the fourth electrode plate 14 through the via.

[0242] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the bottom gate connector 33-1 onto the substrate. The sixth, fifth, and fourth insulating layers within the twentieth via V20 are etched away, exposing the surface of the bottom gate connector 33-1. The twentieth via V20 is configured to allow a subsequently formed second connection electrode to be connected to the bottom gate connector 33-1 through the via.

[0243] In an exemplary embodiment, the display substrate may further include a twenty-first via V21. The orthographic projection of the twenty-first via V21 onto the substrate lies within the orthographic projection range of the initial connection block 73 of the second type of second initial line 72-2 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the twenty-first via V21 are etched away, exposing the surface of the initial connection block 73. The twenty-first via V21 is configured to allow subsequently formed initial connection electrodes to connect to the initial connection block 73 through this via. In an exemplary embodiment, the twenty-first via V21 may be disposed between the (N-1)th and Nth unit columns, and between the N+2th and N+3th unit columns.

[0244] In an exemplary embodiment, a first spacing 'a' may be present between the third via V3 and the fourth gate electrode 34. This first spacing 'a' can be approximately 1.5 μm to 10 μm, and can be the minimum distance between the edge of the third via V3 near the fourth gate electrode 34 and the edge of the fourth gate electrode 34 near the third via V3. A second spacing 'b' may be present between the sixth via V6 and the fourth gate electrode 34. This second spacing 'b' can be approximately 1.5 μm to 10 μm, and can be the minimum distance between the edge of the sixth via V6 near the fourth gate electrode 34 and the edge of the fourth gate electrode 34 near the sixth via V6. The third via V3 can serve as the first active via of this disclosure, and the sixth via V6 can serve as the second active via of this disclosure. By setting the distance between the active vias and the gate electrode, this disclosure can not only reduce redundant traces in the oxide active layer but also ensure the stability of the oxide fourth transistor T4.

[0245] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the sixth insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the fifth conductive layer in Figure 16A. In an exemplary embodiment, the fifth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0246] In an exemplary embodiment, the fifth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51 to a seventh connection electrode 57, a second light-emitting signal line 42, a first scan signal line 61, a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a first type of second initial line 72-1.

[0247] In an exemplary embodiment, the first connecting electrode 51 can be L-shaped. The first end of the first connecting electrode 51 is connected to the third top gate electrode 33T through the twelfth via V12, and the second end is connected to the second region of the first active layer through the second via V2. The portion between the first and second ends is connected to the first electrode plate connecting block 11-1 through the sixteenth via V16. Since the first electrode plate connecting block 11-1 is connected to the first electrode plate 11, the first connecting electrode 51 achieves the connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end (first electrode plate 11) of the first capacitor C1, forming the first node N1 of the pixel driving circuit. That is, the first electrode plate 11, the gate electrode of the third transistor T3, and the first connecting electrode 51 have the potential of the first node. In an exemplary embodiment, the first connecting electrode 51 can serve as the first node electrode of this disclosure.

[0248] In an exemplary embodiment, the second connecting electrode 52 can be a strip extending along the first direction X. The first end of the second connecting electrode 52 is connected to the second electrode plate 12 through the seventeenth via V17, and the second end of the second connecting electrode 52 is connected to the bottom gate connecting block 33-1 through the twentieth via V20. The first end and the second end are connected to the second region of the third active layer through the fifth via V5. Since the bottom gate connecting block 33-1 is connected to the third bottom gate electrode 33B, the second connecting electrode 52 realizes the connection between the bottom gate electrode of the third transistor T3, the second electrode of the third transistor T3, and the second end (second electrode plate 12) of the first capacitor C1, forming a partial second node N2 of the pixel driving circuit, that is, the second connecting electrode 52 and the second electrode plate 12 have the potential of the second node.

[0249] In an exemplary embodiment, the third connecting electrode 53 can be a strip extending along the first direction X. The first end of the third connecting electrode 53 is connected to the second region of the second active layer (which is also the second region of the fourth active layer) through a third via V3, and the second end of the third connecting electrode 53 is connected to the second electrode plate connecting block 13-1 through an eighteenth via V18. Since the second electrode plate connecting block 13-1 is connected to the third electrode plate 13, the third connecting electrode 53 achieves the interconnection between the second electrode of the second transistor T2, the second electrode of the fourth transistor T4, and the first end of the second capacitor C2 (the third electrode plate 13), forming the third node N3 of the pixel driving circuit. That is, the third connecting electrode 53 and the third electrode plate 13 have the potential of the third node. In an exemplary embodiment, the third connecting electrode 53 can serve as the third node electrode of this disclosure.

[0250] In an exemplary embodiment, the fourth connecting electrode 54 can be a strip shape extending along the first direction X. The first end of the fourth connecting electrode 54 is connected to the first region of the fifth active layer through the seventh via V7, and the second end of the fourth connecting electrode 54 is connected to the fourth electrode plate 14 through the nineteenth via V19. The fourth connecting electrode 54 realizes the connection between the first electrode of the fifth transistor T5 and the second end of the second capacitor C2 (the fourth electrode plate 14), forming a partial second node N2 of the pixel driving circuit, that is, the fourth connecting electrode 54 and the fourth electrode plate 14 have the potential of the second node.

[0251] In an exemplary embodiment, the second connecting electrode 52 and the fourth connecting electrode 54 together form the second node N2 of the pixel driving circuit, and the second electrode 12, the fourth electrode 14, the second connecting electrode 52 and the fourth connecting electrode 54 have the potential of the second node.

[0252] In an exemplary embodiment, since the first electrode plate 11 has a potential of a first node and the second electrode plate 12 has a potential of a second node, the first electrode plate 11 having a potential of a first node and the second electrode plate 12 having a potential of a second node form the first capacitor C1 of the pixel driving circuit.

[0253] In an exemplary embodiment, since the third electrode plate 13 has a potential of the third node and the fourth electrode plate 14 has a potential of the second node, the third electrode plate 13 having a potential of the third node and the fourth electrode plate 14 having a potential of the second node form the second capacitor C2 of the pixel driving circuit.

[0254] In an exemplary embodiment, the fifth connection electrode 55 may be block-shaped. The fifth connection electrode 55 is connected to the first region of the fourth active layer via a sixth via V6, and is configured to connect to a subsequently formed data signal line. In an exemplary embodiment, the fifth connection electrode 55 may serve as a data connection electrode of this disclosure.

[0255] In an exemplary embodiment, the sixth connection electrode 56 may be block-shaped. The sixth connection electrode 56 is connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the eighth via V8. The sixth connection electrode 56 is configured to be connected to the subsequently formed anode connection electrode.

[0256] In an exemplary embodiment, the seventh connecting electrode 57 may be a strip shape extending along the first direction X. The first end of the seventh connecting electrode 57 is connected to the first region of the third active layer through the fourth via V4, and the second end of the seventh connecting electrode 57 is connected to the second region of the seventh active layer through the eleventh via V11.

[0257] In an exemplary embodiment, the fifth conductive layer may further include an initial connection electrode 58. The initial connection electrode 58 may be a strip shape extending along the first direction X. The first end of the initial connection electrode 58 is connected to the first region of the sixth active layer through a ninth via V9, and the second end of the initial connection electrode 58 is connected to the initial connection block 73 through a twenty-first via V21.

[0258] In an exemplary embodiment, the initial connection electrode 58 can be disposed in the circuit cells of the Nth and N+3rd cell columns. Since the initial connection block 73 is connected to the second type of second initial line 72-2, the second type of second initial line 72-2 can write the second type of second initial signal into the first electrode of the sixth transistor T6 of the circuit cells in the Nth and N+3rd cell columns.

[0259] In an exemplary embodiment, a third connection block 76 may be provided on the initial connection electrode 58. The third connection block 76 may be block-shaped (e.g., rectangular) and connected to the initial connection electrode 58. The third connection block 76 is configured to connect to a second type of second connection line subsequently formed.

[0260] In an exemplary embodiment, the shape of the second light-emitting signal line 42 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. The orthographic projection of the second light-emitting signal line 42 on the substrate at least partially overlaps with the orthographic projection of the seventh gate electrode 37 on the substrate, and is connected to the seventh gate electrode 37 through the fifteenth via V15, thus enabling the second light-emitting signal line 42 to control the conduction or disconnection of the seventh transistor T7.

[0261] In an exemplary embodiment, the shape of the first scan signal line 61 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first gate electrode 31 on the substrate, and is connected to the first gate electrode 31 in each circuit unit through the fourteenth via V14, thereby realizing the connection between the first scan signal line 61 and the gate electrode of the first transistor T1 in each circuit unit. The first scan signal line 61 can control the conduction or disconnection of the first transistor T1.

[0262] In an exemplary embodiment, the fourth scan signal line 64 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. The orthographic projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthographic projection of the fourth gate electrode 34 on the substrate, and is connected to the fourth gate electrode 34 in each circuit unit through the thirteenth via V13, thereby realizing the connection between the fourth scan signal line 64 and the gate electrode of the fourth transistor T4 in each circuit unit. The fourth scan signal line 64 can control the conduction or disconnection of the fourth transistor T4.

[0263] This embodiment of the present disclosure, by placing the second light-emitting signal line 42, the first scan signal line 61, and the fourth scan signal line 64 in the fifth conductive layer, can effectively reduce the resistance of the light-emitting signal line and the scan signal line, reduce the voltage drop of the light-emitting signal line and the scan signal, and improve the driving quality, display quality, and display quality.

[0264] In an exemplary embodiment, the shape of the first power connection line 65 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The first power connection line 65 is connected to the first region of the seventh active layer in each circuit cell through the tenth via V10. The first power connection line 65 is configured to connect to the subsequently formed first power line, thereby enabling the first power line to write the first power signal into the first terminal of the seventh transistor T7 in each circuit cell.

[0265] In an exemplary embodiment, a first power connection block 65-1 may be provided on the first power connection line 65. The first power connection block 65-1 may be block-shaped (e.g., rectangular) and connected to the first power connection line 65. The first power connection block 65-1 is configured to connect to a subsequently formed first power line. In an exemplary embodiment, the first power connection block 65-1 may be disposed in the circuit units of the N+1th, N+2th, N+4th, and N+5th unit columns.

[0266] In an exemplary embodiment, the second power connection line 66 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. A second power connection block 66-1 can be provided on the second power connection line 66. The second power connection block 66-1 can be block-shaped (e.g., rectangular) and connected to the second power connection line 66. The second power connection block 66-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 66-1 can be disposed in the circuit units of the Nth, N+1th, N+3th, and N+4th unit columns.

[0267] In an exemplary embodiment, at least one circuit unit may further include a shielding electrode 67 on the second power connection line 66. The shielding electrode 67 may be shaped as a strip extending along the second direction Y, and may be disposed on the side of the second power connection line 66 near the fourth scan signal line 64. The first end of the shielding electrode 67 is connected to the second power connection line 66, and the second end of the shielding electrode 67 extends toward the direction near the fourth scan signal line 64.

[0268] In an exemplary embodiment, the shielding electrode 67 may be disposed in the circuit cells of the N+1 and N+3 cell columns. The orthographic projection of the shielding electrode 67 on the substrate at least partially overlaps with the orthographic projection of the edge of the fourth electrode plate 14 on the first direction X side in the N+1 and N+3 cell columns on the substrate. The shielding electrode 67 is configured to reduce the parasitic capacitance between the data signal line and the fourth electrode plate.

[0269] In an exemplary embodiment, in at least one unit row, the second power connection line 66, the plurality of second power connection blocks 66-1, and the plurality of shielding electrodes 67 can be an integral structure that is interconnected.

[0270] In an exemplary embodiment, the shape of the first initial signal line 71 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a cell row. The first initial signal line 71 is connected to the first region of the first active layer (which is also the first region of the second active layer) in each circuit cell through the first via V1. The first initial signal line 71 enables the simultaneous writing of the first initial signal to the first terminal of the first transistor T1 and the first terminal of the second transistor T2 in each circuit cell.

[0271] In an exemplary embodiment, a first connecting block 74 may be provided on the first initial signal line 71. The first connecting block 74 may be block-shaped (such as rectangular), and may be provided on the side of the first initial signal line 71 near the first scan signal line 61 and connected to the first initial signal line 71. The first connecting block 74 is configured to connect to the subsequently formed first initial connecting line.

[0272] In an exemplary embodiment, the first connecting block 74 may be disposed between the N+1th and N+2th cell columns, and between the N+4th and N+5th cell columns. In at least one cell row, the first initial signal line 71 and the plurality of first connecting blocks 74 may be an integral structure interconnected with each other.

[0273] In an exemplary embodiment, the shape of the first type of second initial line 72-1 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The first type of second initial line 72-1 is connected to the first region of the sixth active layer of the circuit cells in the N+1, N+2, N+4 and N+5 cell columns through the eighth via V8, thereby enabling the first type of second initial signal to be written into the first terminal of the sixth transistor T6 of the circuit cells in the N+1, N+2, N+4 and N+5 cell columns.

[0274] In an exemplary embodiment, a second connecting block 75 may be provided on the first type of second initial line 72-1. The second connecting block 75 may be block-shaped (such as rectangular) and connected to the first type of second initial line 72-1. The second connecting block 75 is configured to connect to the subsequently formed first type of second connecting line.

[0275] In an exemplary embodiment, the second connecting block 75 may be disposed in the circuit cells of the N+2th and N+5th cell columns. In at least one cell row, the first type of second initial line 72-1 and the plurality of second connecting blocks 75 may be an integral structure interconnected with each other.

[0276] In an exemplary embodiment, in at least one circuit unit, the second light-emitting signal line 42 and the first power supply connection line 65 may be located on the side opposite to the second direction Y of the third top gate electrode 33T, and the first light-emitting signal line 41, the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the second power supply connection line 66, the first initial signal line 71, the first type of second initial line 72-1 and the second type of second initial line 72-2 may be located on the side of the second direction Y of the third top gate electrode 33T.

[0277] In an exemplary embodiment, in at least one circuit unit, the second light-emitting signal line 42 may be located on the side opposite to the second direction Y of the third top gate electrode 33T, and the first power supply connection line 65 may be located on the side of the second light-emitting signal line 42 away from the third top gate electrode 33T. The first scan signal line 61 can be located on one side of the third top gate electrode 33T in the second direction Y. The first initial signal line 71 can be located on the side of the first scan signal line 61 away from the third top gate electrode 33T. The third scan signal line 63 can be located on the side of the first initial signal line 71 away from the third top gate electrode 33T. The second power connection line 66 can be located on the side of the third scan signal line 63 away from the third top gate electrode 33T. The fourth scan signal line 64 can be located on the side of the second power connection line 66 away from the third top gate electrode 33T. The first light emission signal line 41 can be located on the side of the fourth scan signal line 64 away from the third top gate electrode 33T. The second scan signal line 62 can be located on the side of the first light emission signal line 41 away from the third top gate electrode 33T. The second type of second initial line 72-2 can be located on the side of the second scan signal line 62 away from the third top gate electrode 33T. The first type of second initial line 72-1 can be located on the side of the second type of second initial line 72-2 away from the third top gate electrode 33T.

[0278] In an exemplary embodiment, the fifth conductive layer in some adjacent cell columns may be substantially identical. For example, the shape and position of the fifth conductive layer in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the shape and position of the fifth conductive layer in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. Furthermore, the shape and position of the fifth conductive layer in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0279] In an exemplary embodiment, the fifth conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the fifth conductive layers in the (N+1)th and (N+2)th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the fifth conductive layers in the (N+2)th and (N+3)th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the fifth conductive layers in the (N+4)th and (N+5)th cell columns may be mirror-symmetrical with respect to the column center line.

[0280] (19) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the first planarization layer, as shown in FIG17.

[0281] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a thirty-first via V31 and a thirty-second via V32.

[0282] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate. The first planarization layer within the 31st via V31 is removed, exposing the surface of the fifth connecting electrode 55. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the fifth connecting electrode 55 through the via.

[0283] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the 6th connecting electrode 56 on the substrate. The first planarization layer within the 32nd via V32 is removed, exposing the surface of the 6th connecting electrode 56. The 32nd via V32 is configured to allow a subsequently formed anode connecting electrode to be connected to the 6th connecting electrode 56 through the via.

[0284] In an exemplary embodiment, at least one circuit unit may further include a thirty-third via V33. The orthographic projection of the thirty-third via V33 onto the substrate lies within the range of the orthographic projection of the first power connection block 65-1 on the first power connection line 65 onto the substrate. The first planarization layer within the thirty-third via V33 is removed, exposing the surface of the first power connection block 65-1. The thirty-third via V33 is configured to allow a subsequently formed first power line to connect to the first power connection block 65-1 through the via. In an exemplary embodiment, the thirty-third via V33 may be disposed in the circuit units of the N+1th, N+2nd, N+4th, and N+5th unit columns.

[0285] In an exemplary embodiment, at least one circuit unit may further include a thirty-fourth via V34. The orthographic projection of the thirty-fourth via V34 onto the substrate lies within the orthographic projection of the second power connection block 66-1 onto the substrate. A first planarization layer within the thirty-fourth via V34 is removed, exposing the surface of the second power connection block 66-1. The thirty-fourth via V34 is configured to allow a subsequently formed second power line to connect to the second power connection block 66-1 through this via. In an exemplary embodiment, the thirty-fourth via V34 may be disposed in circuit units in the Nth, N+1th, N+3th, and N+4th unit columns.

[0286] In an exemplary embodiment, at least one circuit unit may further include a thirty-fifth via V35. The orthographic projection of the thirty-fifth via V35 onto the substrate lies within the orthographic projection of the first connecting block 74 onto the substrate. A first planarization layer within the thirty-fifth via V35 is removed, exposing the surface of the first connecting block 74. The thirty-fifth via V35 is configured to allow subsequently formed first initial connection lines to connect to the first connecting block 74 through this via. In an exemplary embodiment, the thirty-fifth via V35 may be disposed between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns.

[0287] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate lies within the orthographic projection of the second connecting block 75 of the first type second initial line 72-1 onto the substrate. A first planarization layer within the thirty-sixth via V36 is removed, exposing the surface of the second connecting block 75. The thirty-sixth via V36 is configured to allow subsequently formed first type second connecting lines to connect to the second connecting block 75 through this via. In an exemplary embodiment, the thirty-sixth via V36 may be located in the N+2nd and N+5th unit columns.

[0288] In an exemplary embodiment, at least one circuit unit may further include a thirty-seventh via V37. The orthographic projection of the thirty-seventh via V37 onto the substrate lies within the orthographic projection of the third connecting block 76 of the initial connecting electrode 58 onto the substrate. A first planarization layer within the thirty-seventh via V37 is removed, exposing the surface of the third connecting block 76. A thirty-sixth via V36 is configured to allow subsequently formed second-type second connecting lines to connect to the third connecting block 76 through this via. In an exemplary embodiment, the thirty-seventh via V37 may be disposed in the Nth and N+3rd unit columns.

[0289] (20) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film using a patterning process to form a sixth conductive layer disposed on the first planarization layer, as shown in Figures 18A and 18B, where Figure 18B is a planar schematic diagram of the sixth conductive layer in Figure 18A. In an exemplary embodiment, the sixth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0290] In an exemplary embodiment, the sixth conductive layer of each circuit unit includes at least a data signal line 83 and an anode connection electrode 84.

[0291] In an exemplary embodiment, the data signal line 83 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 83 is connected to the fifth connection electrode 55 through the thirty-first via V31. Since the fifth connection electrode 55 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write data signals to the first electrode of the fourth transistor T4.

[0292] In an exemplary embodiment, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projections of the first electrode plate 11 to the fourth electrode plate 14 and the first connecting electrode 51 to the sixth connecting electrode 56 on the substrate. This can avoid signal crosstalk caused by data voltage jumps in the data signal line, avoid the impact of data voltage jumps on transistors, improve the working stability of the pixel driving circuit, and improve the display effect.

[0293] In an exemplary embodiment, the anode connection electrode 84 can be a strip shape extending along the second direction Y. The anode connection electrode 84 is connected to the sixth connection electrode 56 through the thirty-second via V32, and the anode connection electrode 84 is configured to be connected to the subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the via, the pixel driving circuit can output driving current to the light-emitting device.

[0294] In an exemplary embodiment, the data signal line 83 in the (N+1)th unit column (the unit column where the first circuit unit is located) is disposed on the side of the unit column close to the Nth unit column (the unit column where the third circuit unit is located), and the data signal line 83 in the (N+1)th unit column is relatively close to the fourth electrode plate 14 in the Nth unit column. The data signal line 83 in the (N+4)th unit column (the unit column where the first circuit unit is located) is disposed on the side of the unit column close to the (N+3)th unit column (the unit column where the third circuit unit is located), and the data signal line 83 in the (N+4)th unit column is relatively close to the fourth electrode plate 14 in the N+3th unit column. Studies have shown that a large parasitic capacitance between the data signal line 83 and the second node N2 (the fourth electrode plate 14) can cause fluctuations in the gate-source voltage Vgs of the third transistor, resulting in fluctuations in the output current of the pixel driving circuit, and thus causing uneven display. This disclosure can effectively reduce the parasitic capacitance between the data signal line 83 and the second node N2 by providing a shielding electrode.

[0295] Figure 19 is a cross-sectional view along direction AA in Figure 18A. As shown in Figure 19, the display substrate may include a first insulating layer 111 disposed on a substrate 101, a third electrode plate 13 disposed on the first insulating layer 111, a second insulating layer 112 disposed on the third electrode plate 13, a fourth electrode plate 14 disposed on the second insulating layer 112, a third insulating layer 113 disposed on the fourth electrode plate 14, a fourth insulating layer 114 disposed on the third insulating layer 113, a fifth insulating layer 115 disposed on the fourth insulating layer 114, a sixth insulating layer 116 disposed on the fifth insulating layer 115, a shielding electrode 67 disposed on the sixth insulating layer 116, a first planarization layer 117 disposed on the shielding electrode 67, and a data signal line 83 and an anode connection electrode 84 disposed on the first planarization layer 117.

[0296] In an exemplary embodiment, the shielding electrode 67 located in the fifth conductive layer (SD1) is disposed between the second conductive layer (GATE2) where the fourth electrode 14 is located and the sixth conductive layer (SD2) where the data signal line 83 is located. The parasitic capacitance between the fourth electrode 14 and the data signal line 83 is separated by the shielding electrode 67, thereby effectively reducing the parasitic capacitance between the data signal line 83 and the second node N2. This effectively ensures the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reduces the change in the output current of the pixel driving circuit, effectively reduces the change in light emission brightness, and effectively improves the display quality and display effect. Since the shielding electrode 67 is connected to the second power connection line 66, and the second power connection line 66 is connected to the second power line 82, the shielding electrode 67, which has a constant potential, can effectively shield the influence of the jump voltage of the data signal line 83 on the second node N2, effectively ensuring the accuracy of the threshold voltage Vth compensation, and further improving the display quality and display effect.

[0297] In some possible implementations, the shielding electrode 67 can be connected to other DC signal lines, such as the first power connection line, the first initial signal line, the first type of second initial line, or the second type of second initial line. Alternatively, similar shielding electrodes can be provided on the first power connection line, the first initial signal line, the first type of second initial line, or the second type of second initial line. Or, similar shielding electrodes can be provided on the first scan signal line or the fourth scan signal line. This disclosure does not limit the scope of the invention.

[0298] In some possible implementations, the shielding electrode 67 may be disposed in other film layers, such as the third conductive layer (GATE3), the second semiconductor layer, or the fourth conductive layer (GATE4), which is not limited herein.

[0299] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may further include a first power line 81. The shape of the first power line 81 may be a straight line or a broken line extending along the second direction Y of the main body. The first power line 81 is connected to the first power connection block 65-1 through the thirty-third via V33. Since the first power connection block 65-1 is connected to the first power connection line 65, the interconnection between the first power connection line 65 extending along the first direction X of the main body and the first power line 81 extending along the second direction Y of the main body is realized. The first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0300] In an exemplary embodiment, the first power connection line 65 can be disposed in each cell row, and the first power line 81 can be disposed in the N+1 cell column, the N+2 cell column, the N+4 cell column and the N+5 cell column respectively, that is, the first power line 81 can be disposed in the cell column where the first circuit unit and the second circuit unit are located.

[0301] In an exemplary embodiment, at least one circuit unit may have an opening 81-1 on the first power line 81. The orthographic projection of the opening 81-1 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 on the substrate, so as to reduce the overlap capacitance between the first connecting electrode 51 and the first power line 81, which can effectively reduce the parasitic capacitance of the first node N1.

[0302] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may further include a second power line 82. The shape of the second power line 82 may be a straight line or a broken line extending along the second direction Y of the main body. The second power line 82 is connected to the second power connection block 66-1 through the thirty-fourth via V34. Since the second power connection block 66-1 is connected to the second power connection line 66, the interconnection between the second power connection line 66 extending along the first direction X of the main body and the second power line 82 extending along the second direction Y of the main body is realized. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity, display quality, and display performance. In addition, by setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen ratio, and facilitate the realization of full-screen display.

[0303] In an exemplary embodiment, the second power connection line 66 can be disposed in each cell row, and the second power line 82 can be disposed in the circuit cells of the Nth cell column, the N+1th cell column, the N+3th cell column and the N+4th cell column respectively, that is, the second power line 82 can be disposed in the cell columns where the first circuit cell and the third circuit cell are located.

[0304] In an exemplary embodiment, the second power line 82 can be a variable width structure. The second power line 82 may include a first region that overlaps with the first connecting electrode 51 and a second region that does not overlap with the first connecting electrode 51. The width of the second power line is the dimension in the first direction X. The width of the first region may be smaller than the width of the second region to reduce the overlap capacitance between the first connecting electrode 51 and the second power line 82, which can effectively reduce the parasitic capacitance of the first node N1.

[0305] In an exemplary embodiment, the orthographic projection of the second power line 82 of a portion of the circuit units onto the substrate at least partially overlaps with the orthographic projection of the first active layer 21, the second active layer 22, or the fourth active layer 24 onto the substrate. This allows the first active layer 21, the second active layer 22, or the fourth active layer 24 to be enveloped by the second power line 82, reducing the impact of illumination on the characteristics of the oxide first transistor T1, the oxide second transistor T2, or the oxide fourth transistor T4. For example, the second power line 82 in the N+1th and N+4th unit columns at least partially overlaps with the orthographic projection of the first active layer 21, the second active layer 22, or the fourth active layer 24 onto the substrate.

[0306] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may further include a first connecting line 91. The shape of the first connecting line 91 may be a straight line or a broken line extending along the second direction Y of the main body portion. The first connecting line 91 is connected to the first connecting block 74 through the thirty-fifth via V35. Since the first connecting block 74 is connected to the first initial signal line 71, the interconnection between the first initial signal line 71 extending along the first direction X of the main body portion and the first connecting line 91 extending along the second direction Y of the main body portion is realized. The first initial signal line 71 and the first connecting line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial connecting line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0307] In an exemplary embodiment, the first connection line 91 may be disposed between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns, so that the first connection line 91 can be moved away from the data signal line 83, thereby reducing the parasitic capacitance between the data signal line 83 and the first connection line 91.

[0308] In an exemplary embodiment, the data signal line 83 in the (N+2)th unit column is disposed on the side of the circuit column closest to the (N+3)th unit column, and the data signal line 83 in the (N+3)th unit column is disposed on the side of the circuit column closest to the (N+2)th unit column. That is, the data signal lines 83 in the (N+2)th and (N+3)th unit columns are adjacent to each other, therefore the first connecting line 91 cannot be disposed between the (N+2)th and (N+3)th unit columns. The data signal line 83 in the (N+1)th unit column is disposed on the side of the circuit column closest to the (N)th unit column, and the data signal line 83 in the (N+4)th unit column is disposed on the side of the circuit column closest to the (N+3)th unit column. Therefore, the first connecting line 91 cannot be disposed between the (N)th and (N+1)th unit columns, nor between the (N+3)th and (N+4)th unit columns. This disclosure, by placing the first connection line 91 between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns, allows the first connection line 91 to be located away from the data signal line 83, reducing the parasitic capacitance between the data signal line 83 and the first connection line 91. Furthermore, since the first connection line 91 is located between two adjacent first power lines 81, not only can the parasitic capacitance between the data signal line 83 and the first connection line 91 be further reduced, but the first power line 81, with its constant potential, can effectively shield the impact of the voltage jumps of the data signal line 83 on the first connection line 91, improving the stability of the first initial signal, effectively ensuring the accuracy of the threshold voltage Vth compensation and the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reducing the variation in the output current of the pixel driving circuit, effectively reducing the variation in light emission brightness, and effectively improving display quality and display effect.

[0309] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may further include a first type of second connection line 92-1. The shape of the first type of second connection line 92-1 may be a straight line or a broken line extending along the second direction Y of the main body portion. The first type of second connection line 92-1 is connected to the second connection block 75 through the thirty-sixth via V36. Since the second connection block 75 is connected to the first type of second initial line 72-1, the interconnection of the first type of second initial line 72-1 extending along the first direction X of the main body portion and the first type of second connection line 92-1 extending along the second direction Y of the main body portion is realized. The first type of second initial line 72-1 and the first type of second connection line 92-1 form a mesh-like interconnection structure on the display substrate for transmitting the first type of second initial signal. This not only effectively reduces the resistance of the first type of second connection line and reduces the voltage drop of the first type of second initial signal, but also effectively improves the uniformity of the first type of second initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0310] In an exemplary embodiment, the first type of second connection line 92-1 can be set in the N+2th and N+5th unit columns, that is, the first type of second connection line 92-1 can be set in the unit column where the second circuit unit is located.

[0311] In an exemplary embodiment, the orthographic projection of the first type of second connection line 92-1 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21, the second active layer 22, or the fourth active layer 24 on the substrate, so that the first active layer 21, the second active layer 22, or the fourth active layer 24 can be wrapped by the first type of second connection line 92-1, reducing the influence of light on the characteristics of the oxide first transistor T1, the oxide second transistor T2, or the oxide fourth transistor T4, and improving the driving performance of the pixel driving circuit.

[0312] In an exemplary embodiment, the sixth conductive layer of at least one circuit unit may further include a second type of second connecting line 92-2. The shape of the second type of second connecting line 92-2 may be a straight line or a broken line extending along the second direction Y in its main body. The second type of second connecting line 92-2 is connected to the third connecting block 76 through a thirty-seventh via V37. Since the third connecting block 76 is connected to the initial connecting electrode 58, and the initial connecting electrode 58 is connected to the second type of second initial line 72-2...

[0313] Therefore, the second type of second initial line 72-2 extending along the first direction X of the main body is interconnected with the second type of second connecting line 92-2 extending along the second direction Y of the main body. The second type of second initial line 72-2 and the second type of second connecting line 92-2 form a mesh-like interconnection structure on the display substrate for transmitting the second type of second initial signal. This not only effectively reduces the resistance of the second type of second connecting line and reduces the voltage drop of the second type of second initial signal, but also effectively improves the uniformity of the second type of second initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0314] In an exemplary embodiment, the second type of second connection line 92-2 can be set in the Nth unit column and the N+3th unit column, that is, the second type of second connection line 92-2 can be set in the unit column where the third circuit unit is located.

[0315] In an exemplary embodiment, the orthographic projection of the second type of second connection line 92-2 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21, the second active layer 22, or the fourth active layer 24 on the substrate, so that the first active layer 21, the second active layer 22, or the fourth active layer 24 can be wrapped by the second type of second connection line 92-2, thereby reducing the influence of light on the characteristics of the oxide first transistor T1, the oxide second transistor T2, or the oxide fourth transistor T4.

[0316] Subsequent fabrication processes may include forming a second planarization layer having an anode via exposed on the surface of the anode connection electrode 84, the anode via being configured to allow the subsequent formation of an anode to be connected to the anode connection electrode through the via.

[0317] Thus, the driving structure layer of this embodiment is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a first type of second initial line (or a second type of second initial line), a first power line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer (GATE1), a second insulating layer, a second conductive layer (GATE2), a third insulating layer, a third conductive layer (GATE3), a fourth insulating layer, a semiconductor layer, a fifth insulating layer, a fourth conductive layer (GATE4), a sixth insulating layer, a fifth conductive layer (SD1), a first planarization layer, a sixth conductive layer (SD2), and a second planarization layer, sequentially disposed on the substrate. The first semiconductor layer may include at least the active layer of the seventh transistor T7; the first conductive layer may include at least the first electrode of the first capacitor, the third electrode of the second capacitor, the gate electrode of the seventh transistor T7, and the second type of second initial line; the second conductive layer may include at least the second electrode of the first capacitor and the fourth electrode of the second capacitor; the third conductive layer may include at least the third bottom gate electrode; the second semiconductor layer may include at least the active layers of the first transistor T1 to the sixth transistor T6; the fourth conductive layer may include at least the first light-emitting signal line, the second scan signal line, the third scan signal line, and the gate electrodes of multiple transistors; the fifth conductive layer may include at least the second light-emitting signal line, the first scan signal line, the fourth scan signal line, the first initial signal line, the first type of second initial line, and multiple sixth connection electrodes; the sixth conductive layer may include at least the first power line, the second power line, the data signal line, the first connection line, the first type of second connection line, and the second type of second connection line.

[0318] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0319] In an exemplary embodiment, the first, second, third, fourth, fifth, and sixth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0320] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0321] An exemplary embodiment of this disclosure provides a display substrate. By placing a first connection line for transmitting a first initial signal between a first power supply line of a first circuit unit and a first power supply line of a second circuit unit, the first connection line can be moved away from the data signal line, effectively reducing the parasitic capacitance between the data signal line and the first connection line. Furthermore, the first power supply line with a constant potential can effectively shield the impact of the data signal line's voltage jump on the first connection line, improving the stability of the first initial signal. This effectively ensures the accuracy of threshold voltage Vth compensation and the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reducing the variation in the output current of the pixel driving circuit, effectively reducing the variation in light emission brightness, and effectively improving display quality and display effect.

[0322] This disclosed display substrate splits the second initial trace for transmitting the second initial signal into a first type of second initial line and a second type of second initial line. The first type of second initial line is configured to provide the first type of second initial signal to the pixel driving circuit of a portion of the circuit units from the first to the third circuit units, and the second type of second initial line is configured to provide the second type of second initial signal to the pixel driving circuit of another portion of the circuit units from the first to the third circuit units. This enables the provision of different reset voltages to light-emitting devices of different colors, which can effectively improve the low grayscale display quality, display quality, and display effect.

[0323] This disclosure shows that by reducing redundant traces in the oxide active layer and setting the distance between the active via and the gate electrode, the stability of the oxide transistor can be guaranteed.

[0324] This disclosed display substrate, by setting a shielding electrode between the data signal line and the fourth plate with the potential of the second node, effectively reduces the parasitic capacitance between the data signal line and the second node, effectively ensuring the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reducing the variation in the output current of the pixel driving circuit, effectively reducing the variation in light emission brightness, and effectively improving display quality and effect. By connecting the shielding electrode to the second power line, the shielding electrode with a constant potential can effectively shield the impact of the data signal line's voltage jumps on the second node, effectively ensuring the accuracy of threshold voltage Vth compensation, and further improving display quality and effect.

[0325] This disclosure shows that by providing a signal line with a constant potential to wrap the first active layer, the second active layer, or the fourth active layer, the influence of light on the characteristics of oxide transistors can be reduced, and the driving performance of the pixel driving circuit can be improved.

[0326] This disclosure simplifies the pixel driving circuit structure by setting a first electrode and a third electrode in a first conductive layer, and a second electrode and a fourth electrode in a second conductive layer. The first and second electrodes form a first capacitor, and the third and fourth electrodes form a second capacitor. This simplifies the design requirements, makes the pixel driving circuit more compact, reduces the area occupied by the pixel driving circuit, effectively improves the layout space utilization, and makes the structural layout more reasonable. This is conducive to achieving high resolution (PPI) display. The signal line connection structure is simple and has no complex overlap, which can effectively improve product yield and reduce production costs.

[0327] This disclosure improves the uniformity and symmetry of the pixel driving circuit by setting a mirrored arrangement of the pixel driving circuits in some adjacent unit columns. This not only enables the design of uniform process and coupling capacitors, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0328] This disclosure sets the seventh active layer of some adjacent cell columns into an interconnected integrated structure, and the first gate electrode of some adjacent cell columns into an interconnected integrated structure. On the one hand, this can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is conducive to achieving high resolution. On the other hand, it can effectively increase the size of the capacitor plate and effectively increase the capacitance value of the capacitor, thereby maximizing the stability of the pixel driving circuit.

[0329] This embodiment of the present disclosure provides a first power connection line and a first power line, which form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.

[0330] This embodiment of the disclosure, by setting a second power connection line and a second power line, and forming a mesh-like interconnected structure on the display substrate to transmit the second power signal, can not only effectively reduce the resistance of the second power line and the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance. By setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen-to-body ratio, and facilitate the realization of full-screen display.

[0331] This embodiment of the disclosure, by setting a first connecting line, a first type of second connecting line, and a second type of second connecting line, forms a mesh-like interconnected structure on the display substrate to transmit a first initial signal. The first type of second initial line and the first type of second connecting line form a mesh-like interconnected structure on the display substrate to transmit a first type of second initial signal. The second type of second initial line and the second type of second connecting line form a mesh-like interconnected structure on the display substrate to transmit a second type of second initial signal. This not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial signal, but also effectively improves the uniformity of the initial signal in the display substrate, effectively improving display uniformity, and enhancing display quality.

[0332] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0333] Figure 20 is a schematic diagram of the signal line arrangement in another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 20, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 6. The difference is that the first initial trace for transmitting the first initial signal in this embodiment includes a first type of first initial line 71-1 and a second type of first initial line 71-2, and the first connection trace includes a first type of first connection line 91-1 and a second type of first connection line 91-2. The shape of the first type of first initial line 71-1 and the second type of first initial line 71-2 can be a straight line or a broken line extending along the first direction X of the main body. The shape of the first type of first connection line 91-1 and the second type of first connection line 91-2 can be a straight line or a broken line extending along the second direction Y of the main body.

[0334] In an exemplary embodiment, a first type of first initial line 71-1 may be disposed in each cell row and connected to the pixel driving circuits in a plurality of first circuit units Q1 and a plurality of second circuit units Q2 in the cell row. The first type of first initial line 71-1 is configured to provide a first type of first initial signal to the pixel driving circuits in the first circuit units Q1 and the second circuit units Q2 in the cell row.

[0335] In an exemplary embodiment, a second type of first initial line 71-2 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of third circuit units Q3 in the cell row. The second type of first initial line 71-2 is configured to provide a second type of first initial signal to the pixel driving circuit in the third circuit unit Q3 in the cell row. The voltage of the first type of first initial signal is different from the voltage of the second type of first initial signal.

[0336] In an exemplary embodiment, the first type of first initial line 71-1 and the second type of first initial line 71-2 can be disposed in the same conductive layer, or the first type of first initial line 71-1 and the second type of first initial line 71-2 can be disposed in different conductive layers to save wiring space.

[0337] In an exemplary embodiment, a first type of first connection line 91-1 is connected to a first type of first initial line 71-1, and the first type of first initial line 71-1 and the first type of first connection line 91-1 form a mesh-like interconnected structure on the display substrate for transmitting a first type of first initial signal. A second type of first connection line 91-2 is connected to a second type of first initial line 71-2, and the second type of first initial line 71-2 and the second type of first connection line 91-2 form a mesh-like interconnected structure on the display substrate for transmitting a second type of first initial signal.

[0338] In an exemplary embodiment, the first type of first connecting line 91-1 and the second type of first connecting line 91-2 can be alternately arranged in the first direction X. For example, a minimum cycle of 6 circuit units can be used, with one first type of first connecting line 91-1 in 3 circuit units and one second type of first connecting line 91-2 in the other 3 circuit units. Both the first type of first connecting line 91-1 and the second type of first connecting line 91-2 are arranged between the first power line 81 in the first circuit unit Q1 and the first power line 81 in the second circuit unit Q2.

[0339] Studies have shown that for the same initial signal voltage, in the dark state (0 nits), the data signal voltages corresponding to red, green, and blue light-emitting devices differ by approximately 0.5V, while in the bright state (1500 nits), the difference is approximately 0.75V. In other words, the initial signal voltages corresponding to red, green, and blue light-emitting devices are different in their bright states. This embodiment splits the first initial trace transmitting the first initial signal into a first type of first initial line and a second type of first initial line. The first type of first initial line is configured to provide the first type of first initial signal to the pixel driving circuits in the first and second circuit units, and the second type of first initial line is configured to provide the second type of first initial signal to the pixel driving circuit in the third circuit unit. By adjusting the voltage of the first initial signal, the data signal voltages of different circuit units are adjusted, achieving high brightness and low power consumption. For example, when there is only one first initial trace transmitting the first initial signal and the voltage of the first initial signal is 5V, the data signal voltage range is approximately 0.45V to 6.39V. When there are two initial traces transmitting the first initial signal, the voltage of the first type of first initial signal is 4.5V, and the voltage of the second type of first initial signal is 5V, the range of the data signal voltage is approximately 0.45V to 5.87V. The data signal voltage can be reduced by 0.52V, which not only achieves high brightness but also effectively reduces power consumption.

[0340] In some possible implementations, a first type of first initial line may be configured to provide a first type of first initial signal to the pixel driving circuits in the first and third circuit units, and a second type of first initial line may be configured to provide a second type of first initial signal to the pixel driving circuits in the second circuit unit. Alternatively, a first type of first initial line may be configured to provide a first type of first initial signal to the pixel driving circuits in the second and third circuit units, and a second type of first initial line may be configured to provide a second type of first initial signal to the pixel driving circuits in the first circuit unit. This disclosure does not limit the scope of the implementation.

[0341] Figure 21 is a schematic diagram of the arrangement of signal lines in another exemplary embodiment of the present disclosure. As shown in Figure 21, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 20, except that the first type of first connecting line 91-1 and the second type of first connecting line 91-2 are adjacent to each other.

[0342] In an exemplary embodiment, the first type of first connecting line 91-1 and the second type of first connecting line 91-2 can be arranged adjacent to each other in the first direction X, and the two connecting lines are arranged together between the first power line 81 in the first circuit unit Q1 and the first power line 81 in the second circuit unit Q2.

[0343] In an exemplary embodiment, three circuit units can be used as the minimum cycle. In each of the three circuit units, one first type first connection line 91-1 and one second type first connection line 91-2 are respectively provided. The first type first initial line 71-1 and the first type first connection line 91-1 form a mesh-connected structure on the display substrate for transmitting the first type first initial signal. The second type first initial line 71-2 and the second type first connection line 91-2 form a mesh-connected structure on the display substrate for transmitting the second type first initial signal.

[0344] In some possible implementations, a signal line for transmitting DC signals may also be provided between the first type of first connecting line 91-1 and the second type of first connecting line 91-2, which is not limited herein.

[0345] Figure 22 is a schematic diagram of the arrangement of signal lines in a display substrate according to another exemplary embodiment of the present disclosure. As shown in Figure 22, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 6. The difference is that the first initial trace for transmitting the first initial signal in this embodiment includes a first type of first initial line 71-1, a second type of first initial line 71-2, and a third type of first initial line 71-3. The first connection trace includes a first type of first connection line 91-1, a second type of first connection line 91-2, and a third type of first connection line 91-3. The shapes of the first type of first initial line 71-1, the second type of first initial line 71-2, and the third type of first initial line 71-3 can be straight lines or broken lines extending along the first direction X of the main body. The shapes of the first type of first connection line 91-1, the second type of first connection line 91-2, and the third type of first connection line 91-3 can be straight lines or broken lines extending along the second direction Y of the main body.

[0346] In an exemplary embodiment, a first type of first initial line 71-1 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of first circuit units Q1 in the cell row. The first type of first initial line 71-1 is configured to provide a first type of first initial signal to the pixel driving circuit in the first circuit unit Q1 in the cell row.

[0347] In an exemplary embodiment, the second type of first initial line 71-2 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of third circuit units Q3 in the cell row. The second type of first initial line 71-2 is configured to provide a second type of first initial signal to the pixel driving circuit in the third circuit unit Q3 in the cell row.

[0348] In an exemplary embodiment, a third type of first initial line 71-3 may be disposed in each cell row and connected to the pixel driving circuit in a plurality of second circuit units Q2 in the cell row. The third type of first initial line 71-3 is configured to provide a third type of first initial signal to the pixel driving circuit in the second circuit unit Q2 in the cell row. The voltage of the first type of first initial signal, the voltage of the second type of first initial signal and the voltage of the third type of first initial signal are different.

[0349] In an exemplary embodiment, the first type of first initial line 71-1, the second type of first initial line 71-2, and the third type of first initial line 71-3 can be disposed in the same conductive layer, or the first type of first initial line 71-1, the second type of first initial line 71-2, and the third type of first initial line 71-3 can be disposed in different conductive layers to save wiring space.

[0350] In an exemplary embodiment, a first type of first connection line 91-1 is connected to a first type of first initial line 71-1, and the first type of first initial line 71-1 and the first type of first connection line 91-1 form a mesh-like interconnected structure on the display substrate for transmitting a first type of first initial signal. A second type of first connection line 91-2 is connected to a second type of first initial line 71-2, and the second type of first initial line 71-2 and the second type of first connection line 91-2 form a mesh-like interconnected structure on the display substrate for transmitting a second type of first initial signal. A third type of first connection line 91-3 is connected to a third type of first initial line 71-3, and the third type of first initial line 71-3 and the third type of first connection line 91-3 form a mesh-like interconnected structure on the display substrate for transmitting a third type of first initial signal.

[0351] In an exemplary embodiment, the first type of first connecting line 91-1, the third type of first connecting line 91-3, and the second type of first connecting line 91-2 can be alternately arranged in the first direction X. For example, a minimum cycle of 9 circuit units can be used, with one first type of first connecting line 91-1 in 3 circuit units, one third type of first connecting line 91-3 in another 3 circuit units, and one second type of first connecting line 91-2 in the remaining 3 circuit units. The first type of first connecting line 91-1, the second type of first connecting line 91-2, and the third type of first connecting line 91-3 are all arranged between the first power line 81 in the first circuit unit Q1 and the first power line 81 in the second circuit unit Q2.

[0352] In some possible implementations, the first type of first connecting line 91-1, the second type of first connecting line 91-2, and the third type of first connecting line 91-3 can be arranged adjacently in the first direction X, and the three connecting lines are arranged together between the first power line 81 in the same first circuit unit Q1 and the first power line 81 in the second circuit unit Q2. In other possible implementations, two of the first type of first connecting line, the second type of first connecting line, and the third type of first connecting line can be arranged adjacently and together between two first power lines 81, while the other connecting line is arranged separately between two first power lines 81. This disclosure does not limit the scope of the implementation.

[0353] This embodiment divides the first initial trace transmitting the first initial signal into a first type of first initial line, a second type of first initial line, and a third type of first initial line. The first type of first initial line is configured to provide the first type of first initial signal to the pixel driving circuit of one of the circuit units from the first to the third circuit units. The second type of first initial line is configured to provide the second type of first initial signal to the pixel driving circuit of another circuit unit from the first to the third circuit units. The third type of first initial line is configured to provide the third type of first initial signal to the pixel driving circuit of yet another circuit unit from the first to the third circuit units. By changing the voltage of the first initial signal, the data signal voltage of different circuit units can be adjusted more flexibly, achieving high brightness and low power consumption.

[0354] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. For example, the solutions described above can be applied not only to mirror-image solutions but also to non-mirror-image solutions, and this disclosure does not limit them.

[0355] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0356] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0357] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

A display substrate includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the driving structure layer on a side away from the substrate; the driving structure layer includes a plurality of circuit units, at least one circuit unit including a pixel driving circuit, at least one first initial trace extending along a first direction, and at least one constant voltage signal trace extending along a second direction, the first direction and the second direction intersecting; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit including a light-emitting device, the light-emitting device of the at least one light-emitting unit being connected to the pixel driving circuit in the at least one circuit unit; the first initial trace is configured to provide a first initial signal to the pixel driving circuit, and the constant voltage signal trace is configured to provide a constant voltage signal to the pixel driving circuit or the light-emitting device; the driving structure layer further includes at least one first connecting trace extending along the second direction, the first connecting trace being connected to the first initial trace; in the first direction, the first connecting trace is disposed between the constant voltage signal traces of adjacent circuit units. The display substrate according to claim 1, wherein, The plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit periodically arranged in the first direction. The plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a third light-emitting unit emitting a second color light, and a second light-emitting unit emitting a third color light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit, the pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit, and the pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The constant voltage signal trace includes at least a first power line and a second power line. The first power line is configured to provide a first power signal to the pixel driving circuit, and the second power line is configured to provide a second power signal to the light-emitting device. The first power line is respectively disposed in the first circuit unit and the second circuit unit, and the second power line is respectively disposed in the first circuit unit and the third circuit unit. In the first direction, the first connection trace is disposed between the first power line in the first circuit unit and the first power line in the second circuit unit. The display substrate according to claim 2, wherein, The pixel driving circuit in the first circuit unit and the pixel driving circuit in the second circuit unit are mirror-symmetrical with respect to the column center line, which is a straight line located between two adjacent circuit units in the first direction and extending along the second direction. The display substrate according to claim 2, wherein, The first initial trace includes a first initial signal line, and the first connection trace includes a first connection line connected to the first initial signal line; the first initial signal line is configured to provide the same first initial signal to the pixel driving circuits in the first circuit unit, the second circuit unit, and the third circuit unit. The display substrate according to claim 2, wherein, The first initial trace includes a first type of first initial line and a second type of first initial line; the first connection trace includes a first type of first connection line and a second type of first connection line; the first type of first connection line is connected to the first type of first initial line, and the second type of first connection line is connected to the second type of first initial line; the first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit; the second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit; the voltage of the first type of first initial signal is different from the voltage of the second type of first initial signal. According to claim 5, the display substrate, wherein, In the first direction, the first type of first connection line is disposed between the constant voltage signal traces of an adjacent circuit unit, and the second type of first connection line is disposed between the constant voltage signal traces of another adjacent circuit unit. According to claim 5, the display substrate, wherein, In the first direction, the first type of first connection line and the second type of first connection line are arranged together between the constant voltage signal traces of adjacent circuit units. The display substrate according to claim 2, wherein, The first initial trace includes a first type of first initial line, a second type of first initial line, and a third type of first initial line. The first connection trace includes a first type of first connection line, a second type of first connection line, and a third type of first connection line. The first type of first connection line is connected to the first type of first initial line, the second type of first connection line is connected to the second type of first initial line, and the third type of first connection line is connected to the third type of first initial line. The first type of first initial line is configured to provide a first type of first initial signal to the pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit. The second type of first initial line is configured to provide a second type of first initial signal to the pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit. The third type of first initial line is configured to provide a third type of first initial signal to the pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of first initial signal, the voltage of the second type of first initial signal, and the voltage of the third type of first initial signal are different. The display substrate according to claim 8, wherein, In the first direction, the first type of first connection line is disposed between the constant voltage signal traces of an adjacent circuit unit, the second type of first connection line is disposed between the constant voltage signal traces of another adjacent circuit unit, and the third type of first connection line is disposed between the constant voltage signal traces of yet another adjacent circuit unit. The display substrate according to claim 8, wherein, In the first direction, the first type of first connection line, the second type of first connection line, and the third type of first connection line are arranged together between the constant voltage signal traces of adjacent circuit units. The display substrate according to claim 2, wherein, At least one circuit unit further includes a first type of second initial line and a second type of second initial line extending along the first direction, the first type of second initial line being configured to provide a first type of second initial signal to the pixel driving circuits of two circuit units from the first circuit unit to the third circuit unit, and the second type of second initial line being configured to provide a second type of second initial signal to the pixel driving circuit of the other circuit unit from the first circuit unit to the third circuit unit, wherein the voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal. The display substrate according to claim 11, wherein, The driving structure layer further includes a first type of second connecting line and a second type of second connecting line extending along the second direction. The first type of second connecting line is connected to the first type of second initial line, and the second type of second connecting line is connected to the second type of second initial line. The first type of second connecting line is disposed in the second circuit unit, and the second type of second connecting line is disposed in the third circuit unit. The display substrate according to claim 2, wherein, At least one circuit unit further includes a first type of second initial line, a second type of second initial line, and a third type of second initial line extending along the first direction. The first type of second initial line is configured to provide a first type of second initial signal to a pixel driving circuit of one of the circuit units from the first circuit unit to the third circuit unit. The second type of second initial line is configured to provide a second type of second initial signal to a pixel driving circuit of another circuit unit from the first circuit unit to the third circuit unit. The third type of second initial line is configured to provide a third type of second initial signal to a pixel driving circuit of yet another circuit unit from the first circuit unit to the third circuit unit. The voltage of the first type of second initial signal, the voltage of the second type of second initial signal, and the voltage of the third type of second initial signal are different. The display substrate according to claim 13, wherein, The driving structure layer further includes a first type of second connecting line, a second type of second connecting line, and a third type of second connecting line extending along the second direction. The first type of second connecting line is connected to the first type of second initial line, the second type of second connecting line is connected to the second type of second initial line, and the third type of second connecting line is connected to the third type of second initial line. The display substrate according to any one of claims 1 to 14, wherein, The pixel driving circuit includes at least a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first capacitor includes at least a first plate and a second plate, and the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first plate on the substrate. The second capacitor includes at least a third plate and a fourth plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate. The first electrode of the first transistor and the first electrode of the second transistor are connected to the first initial trace. The second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate, respectively. The second electrode of the third transistor is connected to the second plate and the fourth plate, respectively. The first electrode of the fourth transistor is connected to a data signal line extending along the second direction, and the second electrode of the fourth transistor is connected to the second electrode of the second transistor and the third plate, respectively. A shielding electrode is provided between at least one fourth plate and at least one data signal line, and the shielding electrode is connected to the constant voltage signal trace. The display substrate according to claim 15, wherein, In a direction perpendicular to the substrate, the driving structure layer includes multiple conductive layers, and the shielding electrode is disposed between the conductive layer where the fourth electrode plate is located and the conductive layer where the data signal line is located. The display substrate according to claim 15, wherein, The second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate through the first node electrode, respectively. The constant voltage signal trace includes at least a first power line, which is configured to provide a first power signal to the pixel driving circuit. In at least one circuit unit, an opening is provided on the first power line, and the orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the first node electrode on the substrate. The display substrate according to claim 15, wherein, The second electrode of the first transistor is connected to the gate electrode of the third transistor and the first plate through the first node electrode, respectively. The constant voltage signal trace includes at least a second power line, which is configured to provide a second power signal to the light-emitting device. In at least one circuit unit, the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the first node electrode on the substrate. The second power line includes at least a first region that overlaps with the first node electrode and a second region that does not overlap with the first node electrode. The width of the first region is smaller than the width of the second region, and the width is the dimension in the first direction. The display substrate according to claim 15, wherein, The first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the fourth transistor includes at least a fourth active layer, and the constant voltage signal trace includes at least a second power line, which is configured to provide a second power signal to the light-emitting device. In at least one circuit unit, the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the substrate. The display substrate according to claim 15, wherein, The fourth transistor includes at least a fourth gate electrode and a fourth active layer. The data signal line is connected to a data connection electrode. The data connection electrode is connected to a first region of the fourth active layer through a first active via. The third electrode is connected to a third node electrode. The third node electrode is connected to a second region of the fourth active layer through a second active via. In the second direction, the first active via and the fourth gate electrode have a first spacing, and the second active via and the fourth gate electrode have a second spacing. The first spacing is 1.5 μm to 10 μm, and the second spacing is 1.5 μm to 10 μm. The first spacing is the minimum distance between the edge of the first active via near the fourth gate electrode and the edge of the fourth gate electrode near the first active via, and the second spacing is the minimum distance between the edge of the second active via near the fourth gate electrode and the edge of the fourth gate electrode near the second active via. A display device comprising a display substrate as described in any one of claims 1 to 20.

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