Display substrate, manufacturing method, and display apparatus

Abstract

Provided are a display substrate, a manufacturing method, and a display apparatus. The display substrate comprises a base and a driving module disposed on the base. The driving module comprises a multi-stage driving circuit. The driving circuit comprises a first node control circuit (11), a carry output circuit (12), a second node control circuit (13), and a driving output circuit (14). The display substrate further comprises a first first voltage line (V11), a first second voltage line (V12), a third voltage line (V3), and a fourth voltage line (V4) that are disposed on the base. The second node control circuit (13) is electrically connected to a carry output terminal (NX), the first first voltage line (V11), the first second voltage line (V12), and a second control node (PD2) separately. The driving output circuit (14) is electrically connected to the second control node (PD2), the third voltage line (V3), the fourth voltage line (V4), and a driving output terminal (NT) separately. The width of the third voltage line (V3) is greater than the width of the first first voltage line (V11), and / or the width of the fourth voltage line (V4) is greater than the width of the first second voltage line (V12). The falling edge of the provided driving signal has no step, leading to strong driving capability.

Description

Display substrate, manufacturing method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a manufacturing method and a display device. BACKGROUND

[0002] The related display substrate includes a driving circuit with weak driving capability, and the falling edge of the driving signal output by the driving circuit has a step. SUMMARY

[0003] In one aspect, the display substrate provided by the embodiments of the present disclosure includes a substrate, and a driving module disposed on the substrate, the driving module including a multi-stage driving circuit; the driving circuit includes a first node control circuit, a carry output circuit, a second node control circuit and a driving output circuit; the display substrate further includes a first voltage line, a second voltage line, a third voltage line and a fourth voltage line disposed on the substrate.

[0004] The first node control circuit is electrically connected with a first control node, and is configured to control the potential of the first control node.

[0005] The carry output circuit is electrically connected with the first control node and a carry output end respectively, and is configured to provide a carry signal through the carry output end under the control of the potential of the first control node.

[0006] The second node control circuit is electrically connected with the carry output end, the first voltage line, the second voltage line and a second control node respectively, and is configured to control the second control node to be connected or disconnected with the first voltage line and to be connected or disconnected with the second voltage line under the control of the carry signal.

[0007] The driving output circuit is electrically connected with the second control node, the third voltage line, the fourth voltage line and a driving output end respectively, and is configured to control the driving output end to be connected or disconnected with the third voltage line and to be connected or disconnected with the fourth voltage line under the control of the potential of the second control node.

[0008] The line width of the third voltage line is greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is greater than the line width of the second voltage line.

[0009] Optionally, the first node control circuit includes a first control circuit, a second control circuit and a third control circuit.

[0010] The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal;

[0011] The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal.

[0012] The third control circuit is electrically connected to the second clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the second clock signal terminal.

[0013] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate;

[0014] At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate; the gate of the first transistor and the gate of the second transistor are electrically connected.

[0015] At least a portion of the gate of the third transistor is disposed between the first clock signal line and the second clock signal line;

[0016] In the odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a first via, and the gate of the third transistor is electrically connected to the second clock signal line through a second via.

[0017] In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through a third via, and the gate of the third transistor is electrically connected to the first clock signal line through a fourth via.

[0018] Optionally, the orthographic projection of the first via on the substrate is disposed on a first side of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the second via on the substrate is disposed on a second side of the orthographic projection of the gate of the third transistor on the substrate.

[0019] The orthogonal projection of the third via on the substrate is disposed on the second side of the orthogonal projection of the gate of the first transistor on the substrate, and the orthogonal projection of the fourth via on the substrate is disposed on the first side of the orthogonal projection of the gate of the third transistor on the substrate.

[0020] The first side and the second side are opposite sides.

[0021] Optionally, the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the second node.

[0022] The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node.

[0023] The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node.

[0024] Optionally, the first transistor and the second transistor are p-type transistors, and the third transistor is an n-type transistor; or,

[0025] The first transistor and the second transistor are n-type transistors, and the third transistor is a p-type transistor.

[0026] Optionally, the first node control circuit includes a first control circuit, a second control circuit, and a third control circuit;

[0027] The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal;

[0028] The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal.

[0029] The third control circuit is electrically connected to the first clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the first clock signal terminal.

[0030] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate;

[0031] At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate.

[0032] The orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate;

[0033] The gates of the first transistor, the second transistor, and the third transistor are electrically connected.

[0034] Optionally, in the odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a fifth via;

[0035] In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through the sixth via.

[0036] The orthographic projection of the fifth via on the substrate is disposed on the first side of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the sixth via on the substrate is disposed on the second side of the orthographic projection of the gate of the third transistor on the substrate.

[0037] The first side and the second side are opposite sides.

[0038] Optionally, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate;

[0039] At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate.

[0040] The orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate;

[0041] The gates of the first transistor, the second transistor, and the third transistor are integrally formed.

[0042] Optionally, the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the second node.

[0043] The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node.

[0044] The gate of the third transistor is electrically connected to the first clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node;

[0045] The first transistor, the second transistor, and the third transistor are all p-type transistors; or, the first transistor, the second transistor, and the third transistor are all n-type transistors.

[0046] Optionally, the driving circuit further includes an input circuit and an energy storage circuit; the display substrate further includes a second first voltage line and a second second voltage line disposed on the substrate;

[0047] The input circuit is electrically connected to the input terminal, the second first voltage line, the second second voltage line, the first node, the second node, the third node, the first control node, and the first first voltage line, respectively. It is used to control the connection or disconnection between the first node and the second second voltage line, the connection or disconnection between the first node and the second first voltage line, the connection or disconnection between the second node and the first control node, and the connection or disconnection between the third node and the second second voltage line, respectively, under the control of the input signal provided by the input terminal.

[0048] The first end of the energy storage circuit is electrically connected to the first voltage line, and the second end of the energy storage circuit is electrically connected to the first control node.

[0049] Optionally, the line width of the first voltage line is greater than the line width of the second voltage line, and the line width of the first voltage line is greater than the line width of the second voltage line.

[0050] Optionally, the carry output circuit is also electrically connected to the second first voltage line and the first second voltage line respectively, and is used to control the connection or disconnection between the carry output terminal and the second first voltage line, and the connection or disconnection between the carry output terminal and the first second voltage line, under the control of the potential of the first control node.

[0051] Optionally, the driving circuit further includes a power-on setting circuit; the display substrate further includes a power-on setting control line disposed on the substrate;

[0052] The power-on set circuit is electrically connected to the power-on set control line, the first control node, and the second first voltage line, respectively, and is used to control the connection or disconnection between the first control node and the second first voltage line under the control of the power-on set control signal provided by the power-on set control line.

[0053] Optionally, the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate;

[0054] The fourth voltage line, the third voltage line, the first second voltage line, the first first voltage line, the second clock signal line, the first clock signal line, the second second voltage line, the power-on set control line, and the second first voltage line are arranged sequentially in the direction away from the display area.

[0055] Optionally, the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the power-on set circuit includes an eighth transistor and a ninth transistor; and the energy storage circuit includes a first capacitor.

[0056] The gate of the fourth transistor is electrically connected to the input terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second voltage line.

[0057] The gate of the fifth transistor is electrically connected to the input terminal, the first terminal of the fifth transistor is electrically connected to the second first voltage line, and the second terminal of the fifth transistor is electrically connected to the first node.

[0058] The gate of the sixth transistor is electrically connected to the input terminal, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the first control node.

[0059] The gate of the seventh transistor is electrically connected to the input terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the second voltage line.

[0060] The first plate of the first capacitor is electrically connected to the first voltage line, and the second plate of the first capacitor is electrically connected to the first control node.

[0061] The gate of the eighth transistor is electrically connected to the power-on set control line, the first terminal of the eighth transistor is electrically connected to the first control node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor.

[0062] The gate of the ninth transistor is electrically connected to the power-on set control line, and the second terminal of the ninth transistor is electrically connected to the second first voltage line.

[0063] The carry-out circuit includes a tenth transistor and an eleventh transistor;

[0064] The gate of the tenth transistor is electrically connected to the first control node, the first terminal of the tenth transistor is electrically connected to the second first voltage line, and the second terminal of the tenth transistor is electrically connected to the carry output terminal.

[0065] The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the carry output terminal, and the second terminal of the eleventh transistor is electrically connected to the first second voltage line.

[0066] The second node control circuit includes a twelfth transistor and a thirteenth transistor;

[0067] The gate of the twelfth transistor is electrically connected to the carry output terminal, the first terminal of the twelfth transistor is electrically connected to the first voltage line, and the second terminal of the twelfth transistor is electrically connected to the second control node.

[0068] The gate of the thirteenth transistor is electrically connected to the carry output terminal, the first terminal of the thirteenth transistor is electrically connected to the second control node, and the second terminal of the thirteenth transistor is electrically connected to the first second voltage line.

[0069] The drive output circuit includes a fourteenth transistor and a fifteenth transistor;

[0070] The gate of the fourteenth transistor is electrically connected to the second control node, the first terminal of the fourteenth transistor is electrically connected to the third voltage line, and the second terminal of the fourteenth transistor is electrically connected to the drive output terminal.

[0071] The gate of the fifteenth transistor is electrically connected to the second control node, the first terminal of the fifteenth transistor is electrically connected to the drive output terminal, and the second terminal of the fifteenth transistor is electrically connected to the fourth voltage line.

[0072] Optionally, the fourth transistor, the seventh transistor, the eleventh transistor, the thirteenth transistor, and the fifteenth transistor are all n-type transistors, and the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the fourteenth transistor are all p-type transistors.

[0073] In a second aspect, embodiments of this disclosure provide a manufacturing method for manufacturing the aforementioned display substrate, the manufacturing method comprising:

[0074] A drive module, a first voltage line, a first second voltage line, a third voltage line, and a fourth voltage line are disposed on the substrate;

[0075] The line width of the third voltage line is set to be greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is set to be greater than the line width of the first second voltage line.

[0076] In a third aspect, embodiments of this disclosure provide a display device including the display substrate described above. Attached Figure Description

[0077] Figure 1 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0078] Figure 2 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0079] Figure 3 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0080] Figure 4 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0081] Figure 5 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 4;

[0082] Figure 6 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0083] Figures 7, 8A, and 8B are layout diagrams of at least one embodiment of the driving circuit shown in Figure 4;

[0084] Figure 9 is a layout diagram of the first gate metal layer in Figure 7;

[0085] Figure 10 is a layout diagram of the second gate metal layer in Figure 7;

[0086] Figure 11 is a layout diagram of the third gate metal layer in Figure 7;

[0087] Figure 12 is a layout diagram of the first semiconductor layer in Figure 7;

[0088] Figure 13 is a layout diagram of the second semiconductor layer in Figure 7;

[0089] Figure 14 is a layout diagram of the first source / drain metal layer in Figure 7;

[0090] Figure 15A is a layout diagram of the second source / drain metal layer in Figure 7;

[0091] Figure 15B is a stack-up diagram of the first gate metal layer and the first semiconductor layer in Figure 7;

[0092] Figure 15C is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 7;

[0093] Figure 15D is a layout diagram of the second gate metal layer and the third gate metal layer in Figure 7;

[0094] Figure 15E is a layout diagram of the first source / drain metal layer, the first semiconductor layer, and the second semiconductor layer;

[0095] Figures 16 and 17 are layout diagrams of at least one embodiment of the driving circuit shown in Figure 4;

[0096] Figures 18 and 19 are layout diagrams of at least one embodiment shown in Figure 6;

[0097] Figure 20 is a layout diagram of the first gate metal layer in Figure 18;

[0098] Figure 21 is a layout diagram of the second gate metal layer in Figure 18;

[0099] Figure 22 is a layout diagram of the third gate metal layer in Figure 18;

[0100] Figure 23 is a layout diagram of the first semiconductor layer in Figure 18;

[0101] Figure 24 is a layout diagram of the second semiconductor layer in Figure 18;

[0102] Figure 25 is a layout diagram of the first source / drain metal layer in Figure 18;

[0103] Figure 26A is a layout diagram of the second source / drain metal layer in Figure 18;

[0104] Figure 26B is a stack-up diagram of the first gate metal layer and the first semiconductor layer in Figure 18;

[0105] Figure 26C is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 18;

[0106] Figure 26D is a layout diagram of the second gate metal layer and the third gate metal layer in Figure 18;

[0107] Figure 26E is a layout diagram of the first source / drain metal layer, the first semiconductor layer, and the second semiconductor layer;

[0108] Figures 27, 28 and 29 are layout diagrams of at least one embodiment shown in Figure 6. Detailed Implementation

[0109] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0110] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0111] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0112] The display substrate described in this embodiment includes a substrate and a driving module disposed on the substrate. The driving module includes a multi-stage driving circuit. The driving circuit includes a first node control circuit, a carry output circuit, a second node control circuit, and a driving output circuit. The display substrate also includes a first voltage line, a first second voltage line, a third voltage line, and a fourth voltage line disposed on the substrate.

[0113] The first node control circuit is electrically connected to the first control node and is used to control the potential of the first node;

[0114] The carry output circuit is electrically connected to the first control node and the carry output terminal respectively, and is used to provide a carry signal through the carry output terminal under the control of the potential of the first control node;

[0115] The second node control circuit is electrically connected to the carry output terminal, the first first voltage line, the first second voltage line, and the second control node, respectively, and is used to control the connection or disconnection between the second control node and the first first voltage line under the control of the carry signal.

[0116] The drive output circuit is electrically connected to the second control node, the third voltage line, the fourth voltage line and the drive output terminal respectively, and is used to control the connection or disconnection between the drive output terminal and the third voltage line, and the connection or disconnection between the drive output terminal and the fourth voltage line under the control of the potential of the second control node;

[0117] The line width of the third voltage line is greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is greater than the line width of the first second voltage line.

[0118] Optionally, the first voltage line can be a first high voltage line, the first second voltage line can be a first low voltage line, the third voltage line can be a second high voltage line, and the fourth voltage line can be a second low voltage line.

[0119] In specific implementation, since the channel width and length of the transistors included in the drive output circuit are relatively large, the line width of the second high voltage line and / or the line width of the second low voltage line are set to be relatively large, the line width of the second high voltage line is set to be greater than the line width of the first high voltage line, and / or the line width of the second low voltage line is set to be greater than the line width of the first low voltage line.

[0120] As shown in Figure 1, at least one embodiment of the driving circuit includes a first node control circuit 11, a carry output circuit 12, a second node control circuit 13, and a drive output circuit 14.

[0121] The first node control circuit 11 is electrically connected to the first control node PD and is used to control the potential of the first control node PD.

[0122] The carry output circuit 12 is electrically connected to the first control node PD and the carry output terminal NX, respectively, and is used to provide a carry signal through the carry output terminal NX under the control of the potential of the first control node PD.

[0123] The second node control circuit 13 is electrically connected to the carry output terminal NX, the first first voltage line V11, the first second voltage line V12, and the second control node PD2, respectively. It is used to control the second control node PD2 to connect or disconnect with the first first voltage line V11 and the second control node PD2 to connect or disconnect with the first second voltage line V12 under the control of the carry signal.

[0124] The drive output circuit 14 is electrically connected to the second control node PD2, the third voltage line V3, the fourth voltage line V4 and the drive output terminal NT, respectively. It is used to control the connection or disconnection between the drive output terminal NT and the third voltage line V3, and the connection or disconnection between the drive output terminal NT and the fourth voltage line V4, under the control of the potential of the second control node PD2.

[0125] In at least one embodiment of this disclosure, the first node control circuit includes a first control circuit, a second control circuit, and a third control circuit;

[0126] The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal;

[0127] The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal.

[0128] The third control circuit is electrically connected to the second clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the second clock signal terminal.

[0129] In a specific implementation, the first node control circuit may include a first control circuit, a second control circuit, and a third control circuit; the first control circuit controls the connection or disconnection between the second node and the first voltage line under the control of the potential of the first clock signal terminal; the second control circuit controls the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal; and the third control circuit controls the connection or disconnection between the first control node and the third node under the control of the potential of the second clock signal terminal.

[0130] In at least one embodiment of this disclosure, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate.

[0131] At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate; the gate of the first transistor and the gate of the second transistor are electrically connected.

[0132] At least a portion of the gate of the third transistor is disposed between the first clock signal line and the second clock signal line;

[0133] In the odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a first via, and the gate of the third transistor is electrically connected to the second clock signal line through a second via.

[0134] In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through a third via, and the gate of the third transistor is electrically connected to the first clock signal line through a fourth via.

[0135] Optionally, the gate of the first transistor and the gate of the second transistor can be integrally formed.

[0136] In at least one embodiment of this disclosure, the orthogonal projection of the first via on the substrate is disposed on a first side of the orthogonal projection of the gate of the first transistor on the substrate, and the orthogonal projection of the second via on the substrate is disposed on a second side of the orthogonal projection of the gate of the third transistor on the substrate.

[0137] The orthogonal projection of the third via on the substrate is disposed on the second side of the orthogonal projection of the gate of the first transistor on the substrate, and the orthogonal projection of the fourth via on the substrate is disposed on the first side of the orthogonal projection of the gate of the third transistor on the substrate.

[0138] The first side and the second side are opposite sides.

[0139] Optionally, the first side can be the left side and the second side can be the right side; or, the first side can be the right side and the second side can be the left side.

[0140] In a specific implementation, the first control circuit may include a first transistor, the second control circuit may include a second transistor, and the third control circuit may include a third transistor; the gates of the first transistor and the second transistor are both electrically connected to the first clock signal terminal, and the gate of the third transistor is electrically connected to the second clock signal terminal.

[0141] In the odd-numbered stage driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through the first via, and the gate of the third transistor is electrically connected to the second clock signal line through the second via; in the even-numbered stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through the third via, and the gate of the third transistor is electrically connected to the first clock signal line through the fourth via.

[0142] The orthographic projection of the first via on the substrate is located to the left of the orthographic projection of the gate of the first transistor on the substrate; the orthographic projection of the second via on the substrate is located to the right of the orthographic projection of the gate of the third transistor on the substrate; the orthographic projection of the third via on the substrate is located to the right of the orthographic projection of the gate of the first transistor on the substrate; and the orthographic projection of the fourth via on the substrate is located to the left of the orthographic projection of the gate of the third transistor on the substrate; or,

[0143] The orthographic projection of the first via on the substrate is located to the right of the orthographic projection of the gate of the first transistor on the substrate; the orthographic projection of the second via on the substrate is located to the left of the orthographic projection of the gate of the third transistor on the substrate; the orthographic projection of the third via on the substrate is located to the left of the orthographic projection of the gate of the first transistor on the substrate; and the orthographic projection of the fourth via on the substrate is located to the right of the orthographic projection of the gate of the third transistor on the substrate.

[0144] In adjacent stage drive circuits, the clock signal is connected by alternating holes on the left and right sides to enable the access of odd and even row drive signals, so as to reduce the difference between odd and even row drive.

[0145] Optionally, the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the second node.

[0146] The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node.

[0147] The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node.

[0148] In at least one embodiment of this disclosure, the first transistor and the second transistor are p-type transistors, and the third transistor is an n-type transistor; or,

[0149] The first transistor and the second transistor are n-type transistors, and the third transistor is a p-type transistor.

[0150] In at least one embodiment of this disclosure, the first node control circuit includes a first control circuit, a second control circuit, and a third control circuit;

[0151] The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal;

[0152] The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal.

[0153] The third control circuit is electrically connected to the first clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the first clock signal terminal.

[0154] In at least one embodiment of this disclosure, the first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate.

[0155] At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate.

[0156] The orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate;

[0157] The gates of the first transistor, the second transistor, and the third transistor are electrically connected.

[0158] In a specific implementation, when the gates of the first transistor, the second transistor, and the third transistor are all electrically connected to the first clock signal line, the orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate, so as to save lateral space and facilitate the realization of a narrow bezel.

[0159] Optionally, the gates of the first transistor, the second transistor, and the third transistor can be integrally formed.

[0160] In at least one embodiment of this disclosure, in an odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a fifth via.

[0161] In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through the sixth via.

[0162] The orthographic projection of the fifth via on the substrate is disposed on the first side of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the sixth via on the substrate is disposed on the second side of the orthographic projection of the gate of the third transistor on the substrate.

[0163] The first side and the second side are opposite sides.

[0164] In a specific implementation, in an odd-numbered driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a fifth via; in an even-numbered driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through a sixth via.

[0165] The orthographic projection of the fifth via on the substrate is located to the left of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the sixth via on the substrate is located to the right of the orthographic projection of the gate of the third transistor on the substrate; or,

[0166] The orthographic projection of the fifth via on the substrate is located to the right of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the sixth via on the substrate is located to the left of the orthographic projection of the gate of the third transistor on the substrate.

[0167] In adjacent stage drive circuits, the clock signal is connected by alternating holes on the left and right sides to enable the access of odd and even row drive signals, so as to reduce the difference between odd and even row drive.

[0168] Optionally, the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the second node.

[0169] The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node.

[0170] The gate of the third transistor is electrically connected to the first clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node;

[0171] The first transistor, the second transistor, and the third transistor are all p-type transistors; or, the first transistor, the second transistor, and the third transistor are all n-type transistors.

[0172] In at least one embodiment of this disclosure, the driving circuit further includes an input circuit and an energy storage circuit; the display substrate further includes a second first voltage line and a second second voltage line disposed on the substrate;

[0173] The input circuit is electrically connected to the input terminal, the second first voltage line, the second second voltage line, the first node, the second node, the third node, the first control node, and the first first voltage line, respectively. It is used to control the connection or disconnection between the first node and the second second voltage line, the connection or disconnection between the first node and the second first voltage line, the connection or disconnection between the second node and the first control node, and the connection or disconnection between the third node and the second second voltage line, respectively, under the control of the input signal provided by the input terminal.

[0174] The first end of the energy storage circuit is electrically connected to the first voltage line, and the second end of the energy storage circuit is electrically connected to the first control node.

[0175] In a specific implementation, the driving circuit may further include an input circuit and an energy storage circuit; the input circuit, under the control of the input signal, controls the connection or disconnection between the first node and the second second voltage line, controls the connection or disconnection between the first node and the second first voltage line, controls the connection or disconnection between the second node and the first control node, and controls the connection or disconnection between the third node and the second second voltage line; the energy storage circuit is used to maintain the potential of the first control node.

[0176] Optionally, the second first voltage line can be a second first high voltage line, and the second second voltage line can be a second first low voltage line;

[0177] The first high-voltage line and the second high-voltage line can be used to provide a first high-voltage signal, and the first low-voltage line and the second low-voltage line can be used to provide a first low-voltage signal.

[0178] In at least one embodiment of this disclosure, the linewidth of the first voltage line is greater than the linewidth of the second voltage line, and the linewidth of the first voltage line is greater than the linewidth of the second voltage line.

[0179] In at least one embodiment of this disclosure, the carry output circuit is further electrically connected to the second first voltage line and the first second voltage line, respectively, for controlling the connection or disconnection between the carry output terminal and the second first voltage line, and controlling the connection or disconnection between the carry output terminal and the first second voltage line, under the control of the potential of the first control node.

[0180] In specific implementation, the carry output circuit can control the connection or disconnection between the carry output terminal and the second first voltage line under the control of the potential of the first control node, and control the connection or disconnection between the carry output terminal and the first second voltage line.

[0181] In at least one embodiment of this disclosure, the driving circuit further includes a power-on setting circuit; the display substrate further includes a power-on setting control line disposed on the substrate;

[0182] The power-on set circuit is electrically connected to the power-on set control line, the first control node, and the second first voltage line, respectively, and is used to control the connection or disconnection between the first control node and the second first voltage line under the control of the power-on set control signal provided by the power-on set control line.

[0183] In a specific implementation, the driving circuit may further include a power-on set circuit. Under the control of a power-on set control signal, the power-on set circuit controls the connection or disconnection between the first control node and the second first voltage line. When the driving circuit is powered on, the power-on set control line provides a valid power-on set control signal. The power-on set circuit controls the connection between the first control node and the second first voltage line to control the carry signal output terminal to output a low voltage signal and control the driving signal output terminal to output a low electrical signal, thus preventing abnormal output from the driving circuit during power-on.

[0184] Optionally, the fourth voltage line, the third voltage line, the first second voltage line, the first first voltage line, the second second voltage line, and the second first voltage line are arranged sequentially in a direction away from the display area.

[0185] Optionally, the fourth voltage line, the third voltage line, the first second voltage line, the first first voltage line, the second second voltage line, and the second first voltage line are arranged on the same layer.

[0186] In at least one embodiment of this disclosure, the display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate;

[0187] The fourth voltage line, the third voltage line, the first second voltage line, the first first voltage line, the second clock signal line, the first clock signal line, the second second voltage line, the power-on set control line, and the second first voltage line are arranged sequentially in the direction away from the display area.

[0188] As shown in Figure 2, based on at least one embodiment of the driving circuit shown in Figure 1,

[0189] The first node control circuit includes a first control circuit 21, a second control circuit 22, and a third control circuit 23;

[0190] The first control circuit 21 is electrically connected to the first clock signal terminal CK, the first first voltage line V11, and the second node N2, respectively, and is used to control the connection or disconnection between the second node N2 and the first first voltage line V11 under the control of the potential of the first clock signal terminal CK.

[0191] The second control circuit 22 is electrically connected to the first clock signal terminal CK, the first node N1 and the first control node PD respectively, and is used to control the connection or disconnection between the first node N1 and the first control node PD under the control of the potential of the first clock signal terminal CK.

[0192] The third control circuit 23 is electrically connected to the second clock signal terminal CKN, the first control node PD, and the third node N3 respectively, and is used to control the connection or disconnection between the first control node PD and the third node N3 under the control of the potential of the second clock signal terminal CKN.

[0193] The driving circuit also includes an input circuit 41, an energy storage circuit 42, and a power-on set circuit 43;

[0194] The input circuit 41 is electrically connected to the input terminal NI, the second first voltage line V21, the second second voltage line V22, the first node N1, the second node N2, the third node N3, the first control node PD, and the first first voltage line V11, respectively. Under the control of the input signal provided by the input terminal NI, it controls the connection or disconnection between the first node N1 and the second second voltage line V22, controls the connection or disconnection between the first node N1 and the second first voltage line V21, controls the connection or disconnection between the second node N2 and the first control node PD, and controls the connection or disconnection between the third node N3 and the second second voltage line V22.

[0195] The first end of the energy storage circuit 42 is electrically connected to the first voltage line V11, and the second end of the energy storage circuit 42 is electrically connected to the first control node PD.

[0196] The power-on set circuit 43 is electrically connected to the power-on set control line CX, the first control node PD, and the second first voltage line V21, respectively, and is used to control the connection or disconnection between the first control node PD and the second first voltage line V21 under the control of the power-on set control signal provided by the power-on set control line CX.

[0197] The carry output circuit 12 is also electrically connected to the second first voltage line V21 and the first second voltage line V12, respectively, and is used to control the connection or disconnection between the carry output terminal NX and the second first voltage line V21, and the connection or disconnection between the carry output terminal NX and the first second voltage line V12, under the control of the potential of the first control node PD.

[0198] As shown in Figure 3, based on at least one embodiment of the driving circuit shown in Figure 1,

[0199] The first node control circuit includes a first control circuit 21, a second control circuit 22, and a third control circuit 23;

[0200] The first control circuit 21 is electrically connected to the first clock signal terminal CK, the first first voltage line V11, and the second node N2, respectively, and is used to control the connection or disconnection between the second node N2 and the first first voltage line V11 under the control of the potential of the first clock signal terminal CK.

[0201] The second control circuit 22 is electrically connected to the first clock signal terminal CK, the first node N1 and the first control node PD respectively, and is used to control the connection or disconnection between the first node N1 and the first control node PD under the control of the potential of the first clock signal terminal CK.

[0202] The third control circuit 23 is electrically connected to the first clock signal terminal CK, the first control node PD, and the third node N3, respectively, and is used to control the connection or disconnection between the first control node PD and the third node N3 under the control of the potential of the first clock signal terminal CK.

[0203] The driving circuit also includes an input circuit 41, an energy storage circuit 42, and a power-on set circuit 43;

[0204] The input circuit 41 is electrically connected to the input terminal NI, the second first voltage line V21, the second second voltage line V22, the first node N1, the second node N2, the third node N3, the first control node PD, and the first first voltage line V11, respectively. Under the control of the input signal provided by the input terminal NI, it controls the connection or disconnection between the first node N1 and the second second voltage line V22, controls the connection or disconnection between the first node N1 and the second first voltage line V21, controls the connection or disconnection between the second node N2 and the first control node PD, and controls the connection or disconnection between the third node N3 and the second second voltage line V22.

[0205] The first end of the energy storage circuit 42 is electrically connected to the first voltage line V11, and the second end of the energy storage circuit 42 is electrically connected to the first control node PD.

[0206] The power-on set circuit 43 is electrically connected to the power-on set control line CX, the first control node PD, and the second first voltage line V21, respectively, and is used to control the connection or disconnection between the first control node PD and the second first voltage line V21 under the control of the power-on set control signal provided by the power-on set control line CX.

[0207] The carry output circuit 12 is also electrically connected to the second first voltage line V21 and the first second voltage line V12, respectively, and is used to control the connection or disconnection between the carry output terminal NX and the second first voltage line V21, and the connection or disconnection between the carry output terminal NX and the first second voltage line V12, under the control of the potential of the first control node PD.

[0208] In at least one embodiment of this disclosure, in an odd-numbered stage driving circuit, the first clock signal terminal can be electrically connected to a first clock signal line, and the second clock signal terminal can be electrically connected to a second clock signal line; in an even-numbered stage driving circuit, the first clock signal terminal can be electrically connected to a second clock signal line, and the second clock signal terminal can be electrically connected to a first clock signal line; or...

[0209] In odd-level driving circuits, the first clock signal terminal can be electrically connected to the second clock signal line, and the second clock signal terminal can be electrically connected to the first clock signal line; in even-level driving circuits, the first clock signal terminal can be electrically connected to the first clock signal line, and the second clock signal terminal can be electrically connected to the second clock signal line.

[0210] Optionally, the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the power-on set circuit includes an eighth transistor and a ninth transistor; and the energy storage circuit includes a first capacitor.

[0211] The gate of the fourth transistor is electrically connected to the input terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second voltage line.

[0212] The gate of the fifth transistor is electrically connected to the input terminal, the first terminal of the fifth transistor is electrically connected to the second first voltage line, and the second terminal of the fifth transistor is electrically connected to the first node.

[0213] The gate of the sixth transistor is electrically connected to the input terminal, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the first control node.

[0214] The gate of the seventh transistor is electrically connected to the input terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the second voltage line.

[0215] The first plate of the first capacitor is electrically connected to the first voltage line, and the second plate of the first capacitor is electrically connected to the first control node.

[0216] The gate of the eighth transistor is electrically connected to the power-on set control line, the first terminal of the eighth transistor is electrically connected to the first control node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor.

[0217] The gate of the ninth transistor is electrically connected to the power-on set control line, and the second terminal of the ninth transistor is electrically connected to the second first voltage line.

[0218] The carry-out circuit includes a tenth transistor and an eleventh transistor;

[0219] The gate of the tenth transistor is electrically connected to the first control node, the first terminal of the tenth transistor is electrically connected to the second first voltage line, and the second terminal of the tenth transistor is electrically connected to the carry output terminal.

[0220] The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the carry output terminal, and the second terminal of the eleventh transistor is electrically connected to the first second voltage line.

[0221] The second node control circuit includes a twelfth transistor and a thirteenth transistor;

[0222] The gate of the twelfth transistor is electrically connected to the carry output terminal, the first terminal of the twelfth transistor is electrically connected to the first voltage line, and the second terminal of the twelfth transistor is electrically connected to the second control node.

[0223] The gate of the thirteenth transistor is electrically connected to the carry output terminal, the first terminal of the thirteenth transistor is electrically connected to the second control node, and the second terminal of the thirteenth transistor is electrically connected to the first second voltage line.

[0224] The drive output circuit includes a fourteenth transistor and a fifteenth transistor;

[0225] The gate of the fourteenth transistor is electrically connected to the second control node, the first terminal of the fourteenth transistor is electrically connected to the third voltage line, and the second terminal of the fourteenth transistor is electrically connected to the drive output terminal.

[0226] The gate of the fifteenth transistor is electrically connected to the second control node, the first terminal of the fifteenth transistor is electrically connected to the drive output terminal, and the second terminal of the fifteenth transistor is electrically connected to the fourth voltage line.

[0227] In at least one embodiment of this disclosure, the fourth transistor, the seventh transistor, the eleventh transistor, the thirteenth transistor, and the fifteenth transistor are all n-type transistors, and the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the twelfth transistor, and the fourteenth transistor are all p-type transistors.

[0228] As shown in Figure 4, based on at least one embodiment of the driving circuit shown in Figure 2, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the third control circuit includes a third transistor T3.

[0229] The gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, the source of the first transistor T1 is electrically connected to the first high voltage line VGH11, and the drain of the first transistor T1 is electrically connected to the second node N2.

[0230] The gate of the second transistor T2 is electrically connected to the first clock signal terminal CK, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the first control node PD.

[0231] The gate of the third transistor T3 is electrically connected to the second clock signal terminal CKN, the source of the third transistor T3 is electrically connected to the drain of the second transistor T2, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0232] The input circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; the power-on set circuit includes an eighth transistor T8 and a ninth transistor T9; the energy storage circuit includes a first capacitor C1.

[0233] The gate of the fourth transistor T4 is electrically connected to the input terminal NI, the source of the fourth transistor T4 is electrically connected to the first node N1, and the drain of the fourth transistor T4 is electrically connected to the second first low voltage line VGL21.

[0234] The gate of the fifth transistor T5 is electrically connected to the input terminal NI, the source of the fifth transistor T5 is electrically connected to the second first high voltage line VGH21, and the drain of the fifth transistor T5 is electrically connected to the first node N1.

[0235] The gate of the sixth transistor T6 is electrically connected to the input terminal NI, the first terminal of the sixth transistor T6 is electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the first control node PD.

[0236] The gate of the seventh transistor T7 is electrically connected to the input terminal NI, the first terminal of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the second first low voltage line VGL21.

[0237] The first plate of the first capacitor C1 is electrically connected to the first high voltage line VGH11, and the second plate of the first capacitor C1 is electrically connected to the first control node PD.

[0238] The gate of the eighth transistor T8 is electrically connected to the power-on set control line CX, the source of the eighth transistor T8 is electrically connected to the first control node PD, and the drain of the eighth transistor T8 is electrically connected to the source of the ninth transistor T9.

[0239] The gate of the ninth transistor T9 is electrically connected to the power-on set control line CX, and the drain of the ninth transistor T9 is electrically connected to the second first high voltage line VGH21.

[0240] The carry-out circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0241] The gate of the tenth transistor T10 is electrically connected to the first control node PD, the source of the tenth transistor T10 is electrically connected to the second first high voltage line VGH21, and the drain of the tenth transistor T10 is electrically connected to the carry output terminal NX.

[0242] The gate of the eleventh transistor T11 is electrically connected to the first control node PD, the first terminal of the eleventh transistor T11 is electrically connected to the carry output terminal NX, and the drain of the eleventh transistor T11 is electrically connected to the first low voltage line VGL11.

[0243] The second node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13;

[0244] The gate of the twelfth transistor T12 is electrically connected to the carry output terminal NX, the source of the twelfth transistor T12 is electrically connected to the first high voltage line VGH11, and the drain of the twelfth transistor T12 is electrically connected to the second control node PD2.

[0245] The gate of the thirteenth transistor T13 is electrically connected to the carry output terminal NX, the source of the thirteenth transistor T13 is electrically connected to the second control node PD2, and the second terminal of the thirteenth transistor T13 is electrically connected to the first low voltage line VGL11.

[0246] The drive output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0247] The gate of the fourteenth transistor T14 is electrically connected to the second control node PD2, the source of the fourteenth transistor T14 is electrically connected to the second high voltage line VGH2, and the drain of the fourteenth transistor T14 is electrically connected to the drive output terminal NT.

[0248] The gate of the fifteenth transistor T15 is electrically connected to the second control node PD2, the first terminal of the fifteenth transistor T15 is electrically connected to the drive output terminal NT, and the second terminal of the fifteenth transistor T15 is electrically connected to the second low voltage line VGL2.

[0249] In at least one embodiment of the driving circuit shown in Figure 4, T1, T2, T5, T6, T8, T9, T10, T12 and T14 are all p-type transistors, and T3, T4, T7, T11, T13 and T15 are all n-type transistors.

[0250] At least one embodiment of this disclosure provides a novel 15T1C driving circuit that adopts a hybrid CMOS circuit architecture to realize the shift output of the driving signal. The circuit architecture is simple and can use fewer TFTs (thin-film transistors) to achieve the corresponding functions, which is beneficial for achieving a narrow bezel.

[0251] In at least one embodiment of the drive circuit shown in Figure 4, the channel width-to-length ratio of T14 is greater than that of T12, and the channel width-to-length ratio of T15 is greater than that of T13. Since the current flowing through T14 and the current flowing through T15 are relatively large, the line width of the second high-voltage line VGH2 can be set to be greater than that of the first high-voltage line VGH11, and the line width of the second low-voltage line VGL2 can be set to be greater than that of the first low-voltage line VGL11, so as to reduce the IR drop of VGH2 and the IR drop of VGL2.

[0252] The channel width-to-length ratio of T12 is greater than that of T10. Since the current flowing through T12 is larger, the line width of the first high-voltage line VGH11 can be set to be greater than that of the second high-voltage line VGH21 to reduce the IR drop of VGH11.

[0253] The channel width-to-length ratio of T13 is greater than that of T4, and the channel width-to-length ratio of T13 is greater than that of T1. Since the current flowing through T13 is larger, the line width of the first low voltage line VGL11 can be set to be greater than that of the second low voltage line VGL21 to reduce the IR drop of VGL11.

[0254] In at least one embodiment shown in FIG4, VGH11 and VGH21 can both provide a first high voltage signal, VGL11 and VGL21 can both provide a first low voltage signal, VGH2 can provide a second high voltage signal, and VGL2 can provide a second low voltage signal.

[0255] The voltage value of the first low voltage signal is less than the voltage value of the second low voltage signal, so that when PD2 is connected to the first low voltage signal, T15 can be completely turned off, so that the falling edge of the drive signal provided by the drive output terminal NT of the drive circuit is stepless and the drive capability is strong.

[0256] As shown in Figure 5, when at least one embodiment of the driving circuit shown in Figure 4 is in operation, the driving cycle may include a first stage P1, a second stage P2, a third stage P3 and a fourth stage P4 set sequentially.

[0257] In the first stage P1, NI provides a high voltage signal, T5 and T6 are turned off, and T4 and T7 are turned on. At this time, the first low voltage signal is provided to N1 and N3, CK controls T1 and T2 to turn off, and the potential of PD is maintained at high voltage.

[0258] In the second stage P2, when CKN provides a high voltage signal and CK provides a low voltage signal, T3 is turned on and T2 is turned on. The first low voltage signal is continuously written to PD. The potential of PD is pulled down to the first low voltage value. T10 is turned on and NX outputs the first high voltage signal. T13 is turned on and PD2 is connected to the first low voltage signal. T14 is turned on and NT provides the second high voltage signal.

[0259] In the third stage P3, NI provides a low voltage signal, T4 and T7 are off, T5 and T6 are on, pulling the potential of N1 high. CK provides a low voltage signal, CKN provides a high voltage signal, controlling T1 and T2 to be off and T3 to be on. The potentials of PD and N3 are maintained at the first low voltage value within one line scan time of 1H. T10 is on, NT outputs the first high voltage signal, T13 is on, PD2 is connected to the first low voltage signal, T14 is on, and NT provides the second high voltage signal.

[0260] In the fourth stage P4, when CK provides a low voltage signal, T1 and T2 are turned on, NI provides a low voltage signal, T6 is turned on, PD is connected to the first high voltage signal, T11 is turned on, NX provides the first low voltage signal, T12 is turned on, PD2 is connected to the first high voltage signal, T15 is turned on, and NT provides the second low voltage signal.

[0261] At least one embodiment of the driving circuit shown in Figure 4 of this disclosure can achieve partial refresh by controlling VGH2 to provide an AC voltage signal during operation. When no display refresh is performed, VGH2 provides a low voltage signal, and when display refresh is performed, VGH2 provides a second high voltage signal.

[0262] As shown in Figure 6, based on at least one embodiment of the driving circuit shown in Figure 3, the first control circuit includes a first transistor T1, the second control circuit includes a second transistor T2, and the third control circuit includes a third transistor T3.

[0263] The gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, the source of the first transistor T1 is electrically connected to the first high voltage line VGH11, and the drain of the first transistor T1 is electrically connected to the second node N2.

[0264] The gate of the second transistor T2 is electrically connected to the first clock signal terminal CK, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the first control node PD.

[0265] The gate of the third transistor T3 is electrically connected to the first clock signal terminal CK, the source of the third transistor T3 is electrically connected to the drain of the second transistor T2, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0266] The input circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; the power-on set circuit includes an eighth transistor T8 and a ninth transistor T9; the energy storage circuit includes a first capacitor C1.

[0267] The gate of the fourth transistor T4 is electrically connected to the input terminal NI, the source of the fourth transistor T4 is electrically connected to the first node N1, and the drain of the fourth transistor T4 is electrically connected to the second first low voltage line VGL21.

[0268] The gate of the fifth transistor T5 is electrically connected to the input terminal NI, the source of the fifth transistor T5 is electrically connected to the second first high voltage line VGH21, and the drain of the fifth transistor T5 is electrically connected to the first node N1.

[0269] The gate of the sixth transistor T6 is electrically connected to the input terminal NI, the first terminal of the sixth transistor T6 is electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the first control node PD.

[0270] The gate of the seventh transistor T7 is electrically connected to the input terminal NI, the first terminal of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the second first low voltage line VGL21.

[0271] The first plate of the first capacitor C1 is electrically connected to the first high voltage line VGH11, and the second plate of the first capacitor C1 is electrically connected to the first control node PD.

[0272] The gate of the eighth transistor T8 is electrically connected to the power-on set control line CX, the source of the eighth transistor T8 is electrically connected to the first control node PD, and the drain of the eighth transistor T8 is electrically connected to the source of the ninth transistor T9.

[0273] The gate of the ninth transistor T9 is electrically connected to the power-on set control line CX, and the drain of the ninth transistor T9 is electrically connected to the second first high voltage line VGH21.

[0274] The carry-out circuit includes a tenth transistor T10 and an eleventh transistor T11;

[0275] The gate of the tenth transistor T10 is electrically connected to the first control node PD, the source of the tenth transistor T10 is electrically connected to the second first high voltage line VGH21, and the drain of the tenth transistor T10 is electrically connected to the carry output terminal NX.

[0276] The gate of the eleventh transistor T11 is electrically connected to the first control node PD, the first terminal of the eleventh transistor T11 is electrically connected to the carry output terminal NX, and the drain of the eleventh transistor T11 is electrically connected to the first low voltage line VGL11.

[0277] The second node control circuit includes a twelfth transistor T12 and a thirteenth transistor T13;

[0278] The gate of the twelfth transistor T12 is electrically connected to the carry output terminal NX, the source of the twelfth transistor T12 is electrically connected to the first high voltage line VGH11, and the drain of the twelfth transistor T12 is electrically connected to the second control node PD2.

[0279] The gate of the thirteenth transistor T13 is electrically connected to the carry output terminal NX, the source of the thirteenth transistor T13 is electrically connected to the second control node PD2, and the second terminal of the thirteenth transistor T13 is electrically connected to the first low voltage line VGL11.

[0280] The drive output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;

[0281] The gate of the fourteenth transistor T14 is electrically connected to the second control node PD2, the source of the fourteenth transistor T14 is electrically connected to the second high voltage line VGH2, and the drain of the fourteenth transistor T14 is electrically connected to the drive output terminal NT.

[0282] The gate of the fifteenth transistor T15 is electrically connected to the second control node PD2, the first terminal of the fifteenth transistor T15 is electrically connected to the drive output terminal NT, and the second terminal of the fifteenth transistor T15 is electrically connected to the second low voltage line VGL2.

[0283] In at least one embodiment of the driving circuit shown in Figure 6, T1, T2, T3, T5, T6, T8, T9, T10, T12 and T14 are all p-type transistors, and T4, T7, T11, T13 and T15 are all n-type transistors.

[0284] In at least one embodiment of this disclosure, the power-on set circuit may include only the eighth transistor;

[0285] The gate of the eighth transistor is electrically connected to the power-on set control line CX, the source of the eighth transistor is electrically connected to the first control node PD, and the drain of the eighth transistor is electrically connected to the second first high voltage line VGH21.

[0286] Figures 7 and 8A are layout diagrams of at least one embodiment of the driving circuit shown in Figure 4. The driving circuit shown in Figure 7 can be an odd-level driving circuit, with the first clock signal terminal electrically connected to the first clock signal line NCK and the second clock signal terminal electrically connected to the second clock signal line NCB.

[0287] Figure 9 is a layout diagram of the first gate metal layer in Figure 7, Figure 10 is a layout diagram of the second gate metal layer in Figure 7, Figure 11 is a layout diagram of the third gate metal layer in Figure 7, Figure 12 is a layout diagram of the first semiconductor layer in Figure 7, Figure 13 is a layout diagram of the second semiconductor layer in Figure 7, Figure 14 is a layout diagram of the first source / drain metal layer in Figure 7, and Figure 15A is a layout diagram of the second source / drain metal layer in Figure 7.

[0288] Figure 15B is a stack-up diagram of the first gate metal layer and the first semiconductor layer in Figure 7. Figure 15C is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 7. Figure 15D is a layout diagram of the second gate metal layer and the third gate metal layer in Figure 7. Figure 15E is a layout diagram of the first source / drain metal layer, the first semiconductor layer, and the second semiconductor layer.

[0289] The first semiconductor layer can be a polysilicon layer, and the second semiconductor layer can be an IGZO (indium gallium zinc oxide) semiconductor layer.

[0290] As shown in Figure 9, the gate labeled G1 is the gate of T1, and the gate labeled G2 is the gate of T2.

[0291] In Figure 10, the first gate portion of T3 is labeled G31, and in Figure 11, the second gate portion of T3 is labeled G32; the gate of T3 includes the first gate portion G31 and the second gate portion G32 of T3.

[0292] In Figure 12, the active pattern labeled A1 is T1, and the active pattern labeled A2 is T2.

[0293] In Figure 13, the active graphic of T3 is labeled A3;

[0294] In Figure 14, the pole labeled S14 is the first pole of T14, the pole labeled D14 is the second pole of T15, the pole labeled S15 is the first pole of T15, and the pole labeled S15 is the second pole of T15.

[0295] As shown in Figures 7-15E, the gate G1 of T1 is electrically connected to the first clock signal line NCK through a via H1, G31 is electrically connected to G32, and G32 is electrically connected to the second clock signal line NCB through a second via H2.

[0296] G1 and G2 are integrally molded;

[0297] The orthographic projections of G1 and G2 on the substrate are positioned between the orthographic projections of NCK and NCB on the substrate.

[0298] The orthographic projections of G31 and G32 on the substrate are positioned between the orthographic projections of NCK and NCB on the substrate.

[0299] The orthographic projection of the first via H1 on the substrate is located to the left of the orthographic projection of G1 on the substrate. The orthographic projection of the second via H2 on the substrate is located to the right of the orthographic projection of G31 on the substrate. The orthographic projection of the second via H2 on the substrate is located to the right of the orthographic projection of G32 on the substrate.

[0300] As shown in Figures 7-15E, VGL2, VGH2, VGL11, VGH11, NCB, NCK, VGL21, CX, and VGH21 are arranged sequentially along the direction away from the display area;

[0301] T5, T4, T7, T8 and T9 can be arranged sequentially along the first direction, which can be the vertical direction;

[0302] T1, T2, T3, T10, and T11 can be arranged sequentially along the first direction;

[0303] C1, T12, and T13 can be arranged sequentially along the first direction;

[0304] T14 and T15 can be arranged sequentially along the first direction;

[0305] T5, T1, and T14 can be arranged sequentially along the second direction. The first direction can intersect with the second direction. For example, the first direction can be a horizontal direction.

[0306] In at least one embodiment of Figures 7-15E, the channel width-to-length ratio of T14 is greater than that of T12, the channel width and length of T15 are greater than that of T13, the linewidth of the second high-voltage line VGH2 is greater than that of the first high-voltage line VGH11, and the linewidth of the second low-voltage line VGL2 is greater than that of the first low-voltage line VGL11.

[0307] The channel width-to-length ratio of T12 is greater than that of T10, and the line width of the first high-voltage line VGH11 is greater than that of the second high-voltage line VGH21.

[0308] The channel width-to-length ratio of T13 is greater than that of T4, the channel width-to-length ratio of T13 is greater than that of T1, and the line width of the first low voltage line VGL11 is greater than that of the second low voltage line VGL21.

[0309] As shown in Figure 8B, the orthographic projection of VGH2 on the substrate partially overlaps with the orthographic projection of T14 on the substrate, and the orthographic projection of VGH2 on the substrate partially overlaps with the orthographic projection of T15 on the substrate.

[0310] The orthographic projection of VGL2 on the substrate partially overlaps with the orthographic projection of T14 on the substrate, and the orthographic projection of VGL2 on the substrate partially overlaps with the orthographic projection of T15 on the substrate.

[0311] The orthographic projection of VGH11 onto the substrate partially overlaps with the orthographic projection of C1 onto the substrate;

[0312] The orthographic projection of VGH11 on the substrate partially overlaps with the orthographic projection of T12 on the substrate, and the orthographic projection of VGH11 on the substrate partially overlaps with the orthographic projection of T13 on the substrate.

[0313] The orthographic projection of VGH21 onto the substrate partially overlaps with the orthographic projection of T7 onto the substrate;

[0314] The orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T5 on the substrate, the orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T4 on the substrate, the orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T7 on the substrate, the orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T8 on the substrate, and the orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T9 on the substrate.

[0315] The orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T5 on the substrate; the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T4 on the substrate; the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T7 on the substrate; the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T8 on the substrate; and the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T9 on the substrate.

[0316] The orthographic projection of NCK on the substrate partially overlaps with the orthographic projection of T1 on the substrate; the orthographic projection of NCK on the substrate partially overlaps with the orthographic projection of T2 on the substrate; the orthographic projection of NCK on the substrate partially overlaps with the orthographic projection of T3 on the substrate; and the orthographic projection of NCK on the substrate partially overlaps with the orthographic projection of T11 on the substrate.

[0317] The orthographic projection of NCB on the substrate partially overlaps with the orthographic projection of T1 on the substrate; the orthographic projection of NCB on the substrate partially overlaps with the orthographic projection of T2 on the substrate; the orthographic projection of NCB on the substrate partially overlaps with the orthographic projection of T6 on the substrate; and the orthographic projection of NCB on the substrate partially overlaps with the orthographic projection of T3 on the substrate.

[0318] T10 is at least partially disposed on the substrate between the orthographic projection of NCK on the substrate and the orthographic projection of NCB on the substrate;

[0319] T11 is at least partially disposed on the substrate between the orthographic projection of NCK on the substrate and the orthographic projection of NCB on the substrate.

[0320] Figures 16 and 17 are layout diagrams of at least one embodiment of the driving circuit shown in Figure 6. The driving circuit shown in Figure 16 can be an even-stage driving circuit, with the first clock signal terminal electrically connected to the second clock signal line NCB and the second clock signal terminal electrically connected to the first clock signal line NCK.

[0321] As shown in Figures 16 and 17, the gate G1 of T1 is electrically connected to the second clock signal line NCB through three vias H3, G31 is electrically connected to G32, and G32 is electrically connected to the first clock signal line NCK through the fourth via H4.

[0322] The orthographic projection of the third via H3 on the substrate is set to the right side of the orthographic projection of G1 on the substrate, the orthographic projection of the fourth via H4 on the substrate is set to the left side of the orthographic projection of G31 on the substrate, and the orthographic projection of the fourth via H4 on the substrate is set to the left side of the orthographic projection of G32 on the substrate.

[0323] The layout of the first gate metal layer in Figure 16 is shown in Figure 9, the layout of the second gate metal layer in Figure 16 is shown in Figure 10, and the layout of the third gate metal layer in Figure 16 is shown in Figure 11.

[0324] In at least one embodiment of this disclosure, in adjacent stage driving circuits, the clock signal is connected by alternating holes on the left and right sides to realize the access of the odd and even row driving signals, so as to reduce the difference between odd and even row driving.

[0325] In at least one embodiment shown in Figures 7, 8A, 16 and 17, T3, T4, T7, T11, T13 and T15 can be dual-gate transistors to reduce leakage current of oxide transistors.

[0326] Figures 18 and 19 are layout diagrams of at least one embodiment shown in Figure 6. The driving circuit shown in Figure 18 can be an odd-level driving circuit, with the first clock signal terminal electrically connected to the first clock signal line NCK and the second clock signal terminal electrically connected to the second clock signal line NCB.

[0327] Figure 20 is a layout diagram of the first gate metal layer in Figure 18, Figure 21 is a layout diagram of the second gate metal layer in Figure 18, Figure 22 is a layout diagram of the third gate metal layer in Figure 18, Figure 23 is a layout diagram of the first semiconductor layer in Figure 18, Figure 24 is a layout diagram of the second semiconductor layer in Figure 18, Figure 25 is a layout diagram of the first source / drain metal layer in Figure 18, and Figure 26A is a layout diagram of the second source / drain metal layer in Figure 18.

[0328] Figure 26B is a stacked diagram of the first gate metal layer and the first semiconductor layer in Figure 18. Figure 26C is a layout diagram of the second gate metal layer and the second semiconductor layer in Figure 18. Figure 26D is a layout diagram of the second gate metal layer and the third gate metal layer in Figure 18. Figure 26E is a layout diagram of the first source / drain metal layer, the first semiconductor layer, and the second semiconductor layer.

[0329] As shown in Figures 18-26E, the gate G1 of T1, the gate G2 of T2, and the gate G3 of T3 are integrally formed. The gate of T1 is electrically connected to CK through the fifth via H5. The orthogonal projection of H5 on the substrate is located to the left of the orthogonal projection of the gate G1 of T1 on the substrate.

[0330] In Figure 20, the gate labeled G1 is the gate of T1, the gate labeled G2 is the gate of T2, and the gate labeled G3 is the gate of T3.

[0331] In Figure 21, G41 is the first gate portion of T4, G71 is the first gate portion of T7, G111 is the first gate portion of T11, G131 is the first gate portion of T13, and G151 is the first gate portion of T15.

[0332] In Figure 22, the part labeled G42 is the second gate portion of T4, the part labeled G72 is the second gate portion of T7, the part labeled G112 is the second gate portion of T11, the part labeled G132 is the second gate portion of T13, and the part labeled G152 is the second gate portion of T15.

[0333] In Figure 23, the active pattern labeled A1 is T1, the active pattern labeled A2 is T2, and the active pattern labeled A3 is T3.

[0334] In Figure 24, the active pattern labeled A4 is T4, the active pattern labeled A7 is T7, the active pattern labeled A11 is T11, the active pattern labeled A13 is T13, and the active pattern labeled A15 is T15.

[0335] In Figure 25, the pole labeled S14 is the first pole of T14, the pole labeled D14 is the second pole of T15, the pole labeled S15 is the first pole of T15, and the pole labeled S15 is the second pole of T15.

[0336] As shown in Figures 18-26E, ESTV, VGL2, VGH2, VGL11, VGH11, NCB, NCK, VGL21, CX, and VGH21 are arranged sequentially along the direction away from the display area;

[0337] ESTV is the starting voltage line;

[0338] T5, T4, T7, T9 and T8 are arranged along the first direction, which can be vertical; T1 and T2 are arranged along the first direction; T10 and T11 are arranged along the first direction; C1, T12 and T13 are arranged along the first direction; T6 and T3 are arranged along the first direction; T14 and T15 are arranged along the first direction.

[0339] In at least one embodiment of Figures 18-26E, the channel width-to-length ratio of T14 is greater than that of T12, the channel width and length of T15 are greater than that of T13, the linewidth of the second high-voltage line VGH2 is greater than that of the first high-voltage line VGH11, and the linewidth of the second low-voltage line VGL2 is greater than that of the first low-voltage line VGL11.

[0340] The channel width-to-length ratio of T12 is greater than that of T10, and the line width of the first high-voltage line VGH11 is greater than that of the second high-voltage line VGH21.

[0341] The channel width-to-length ratio of T13 is greater than that of T4, the channel width-to-length ratio of T13 is greater than that of T1, and the line width of the first low voltage line VGL11 is greater than that of the second low voltage line VGL21.

[0342] Figures 27, 28 and 30 are layout diagrams of at least one embodiment of the driving circuit shown in Figure 6. The driving circuit shown in Figure 27 can be an even-stage driving circuit, with the first clock signal terminal electrically connected to the second clock signal line NCB.

[0343] As shown in Figures 27, 28 and 30, the gate G1 of T1 is electrically connected to the second clock signal line NCB through the sixth via H6;

[0344] The orthographic projection of the sixth via H6 on the substrate is set to the right side of the orthographic projection of G1 on the substrate.

[0345] The layout of the first gate metal layer in Figure 27 is shown in Figure 20.

[0346] In at least one embodiment of this disclosure, in adjacent stage driving circuits, the clock signal is connected by alternating holes on the left and right sides to realize the access of the odd and even row driving signals, so as to reduce the difference between odd and even row driving.

[0347] As shown in Figure 29, the orthographic projection of VGH2 on the substrate partially overlaps with the orthographic projection of T14 on the substrate, and the orthographic projection of VGH2 on the substrate partially overlaps with the orthographic projection of T15 on the substrate.

[0348] The orthographic projection of VGL2 on the substrate partially overlaps with the orthographic projection of T14 on the substrate, and the orthographic projection of VGL2 on the substrate partially overlaps with the orthographic projection of T15 on the substrate.

[0349] The orthographic projection of VGH11 onto the substrate partially overlaps with the orthographic projection of C1 onto the substrate; the orthographic projection of VGL11 onto the substrate partially overlaps with the orthographic projection of C1 onto the substrate.

[0350] The orthographic projection of VGH11 on the substrate partially overlaps with the orthographic projection of T12 on the substrate, and the orthographic projection of VGH11 on the substrate partially overlaps with the orthographic projection of T13 on the substrate.

[0351] The orthographic projection of VGH21 on the substrate partially overlaps with the orthographic projection of T5 on the substrate, the orthographic projection of VGH21 on the substrate partially overlaps with the orthographic projection of T8 on the substrate, and the orthographic projection of VGH21 on the substrate partially overlaps with the orthographic projection of T9 on the substrate.

[0352] The orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T4 on the substrate, and the orthographic projection of CX on the substrate partially overlaps with the orthographic projection of T7 on the substrate.

[0353] The orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T4 on the substrate, the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T7 on the substrate, the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T8 on the substrate, and the orthographic projection of VGL21 on the substrate partially overlaps with the orthographic projection of T9 on the substrate.

[0354] The orthographic projection of NCK onto the substrate partially overlaps with the orthographic projection of T3 onto the substrate.

[0355] The manufacturing method described in this disclosure is used to manufacture the above-mentioned display substrate, and the manufacturing method includes:

[0356] A drive module, a first voltage line, a first second voltage line, a third voltage line, and a fourth voltage line are disposed on the substrate;

[0357] The line width of the third voltage line is set to be greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is set to be greater than the line width of the first second voltage line.

[0358] The display device described in this disclosure includes the display substrate described above.

[0359] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising a substrate and a driving module disposed on the substrate, the driving module comprising a multi-stage driving circuit; the driving circuit comprising a first node control circuit, a carry output circuit, a second node control circuit and a driving output circuit; the display substrate further comprising a first voltage line, a first second voltage line, a third voltage line and a fourth voltage line disposed on the substrate; The first node control circuit is electrically connected to the first control node and is used to control the potential of the first control node; The carry output circuit is electrically connected to the first control node and the carry output terminal respectively, and is used to provide a carry signal through the carry output terminal under the control of the potential of the first control node; The second node control circuit is electrically connected to the carry output terminal, the first first voltage line, the first second voltage line, and the second control node, respectively, and is used to control the connection or disconnection between the second control node and the first first voltage line under the control of the carry signal. The drive output circuit is electrically connected to the second control node, the third voltage line, the fourth voltage line and the drive output terminal respectively, and is used to control the connection or disconnection between the drive output terminal and the third voltage line, and the connection or disconnection between the drive output terminal and the fourth voltage line under the control of the potential of the second control node; The line width of the third voltage line is greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is greater than the line width of the first second voltage line.

2. The display substrate as claimed in claim 1, wherein, The first node control circuit includes a first control circuit, a second control circuit, and a third control circuit; The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal; The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal. The third control circuit is electrically connected to the second clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the second clock signal terminal.

3. The display substrate as described in claim 2, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate also includes a first clock signal line and a second clock signal line disposed on the substrate. At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate; the gate of the first transistor and the gate of the second transistor are electrically connected. At least a portion of the gate of the third transistor is disposed between the first clock signal line and the second clock signal line; In the odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through a first via, and the gate of the third transistor is electrically connected to the second clock signal line through a second via. In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through a third via, and the gate of the third transistor is electrically connected to the first clock signal line through a fourth via.

4. The display substrate as described in claim 3, wherein, The orthographic projection of the first via on the substrate is disposed on the first side of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the second via on the substrate is disposed on the second side of the orthographic projection of the gate of the third transistor on the substrate. The orthogonal projection of the third via on the substrate is disposed on the second side of the orthogonal projection of the gate of the first transistor on the substrate, and the orthogonal projection of the fourth via on the substrate is disposed on the first side of the orthogonal projection of the gate of the third transistor on the substrate. The first side and the second side are opposite sides.

5. The display substrate as claimed in claim 3, wherein, The gate of the first transistor is electrically connected to the first clock signal terminal, the first terminal of the first transistor is electrically connected to the first voltage line, and the second terminal of the first transistor is electrically connected to the second node. The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node. The gate of the third transistor is electrically connected to the second clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node.

6. The display substrate as claimed in claim 5, wherein, The first transistor and the second transistor are p-type transistors, and the third transistor is an n-type transistor; or, The first transistor and the second transistor are n-type transistors, and the third transistor is a p-type transistor.

7. The display substrate as claimed in claim 1, wherein, The first node control circuit includes a first control circuit, a second control circuit, and a third control circuit; The first control circuit is electrically connected to the first clock signal terminal, the first first voltage line, and the second node, respectively, and is used to control the connection or disconnection between the second node and the first first voltage line under the control of the potential of the first clock signal terminal; The second control circuit is electrically connected to the first clock signal terminal, the first node, and the first control node, respectively, and is used to control the connection or disconnection between the first node and the first control node under the control of the potential of the first clock signal terminal. The third control circuit is electrically connected to the first clock signal terminal, the first control node, and the third node, respectively, and is used to control the connection or disconnection between the first control node and the third node under the control of the potential of the first clock signal terminal.

8. The display substrate as claimed in claim 7, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate also includes a first clock signal line and a second clock signal line disposed on the substrate. At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate. The orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate; The gates of the first transistor, the second transistor, and the third transistor are electrically connected.

9. The display substrate as claimed in claim 8, wherein, In the odd-level driving circuit, the gate of the first transistor is electrically connected to the first clock signal line through the fifth via. In the even-stage driving circuit, the gate of the first transistor is electrically connected to the second clock signal line through the sixth via. The orthographic projection of the fifth via on the substrate is disposed on the first side of the orthographic projection of the gate of the first transistor on the substrate, and the orthographic projection of the sixth via on the substrate is disposed on the second side of the orthographic projection of the gate of the third transistor on the substrate. The first side and the second side are opposite sides.

10. The display substrate as claimed in claim 7, wherein, The first control circuit includes a first transistor, the second control circuit includes a second transistor, and the third control circuit includes a third transistor; the display substrate also includes a first clock signal line and a second clock signal line disposed on the substrate. At least a portion of the orthographic projection of the gate of the first transistor onto the substrate and at least a portion of the orthographic projection of the gate of the second transistor onto the substrate are disposed between the orthographic projection of the first clock signal line onto the substrate and the orthographic projection of the second clock signal line onto the substrate. The orthographic projection of the gate of the third transistor on the substrate at least partially overlaps with the orthographic projection of the first clock signal line on the substrate; The gates of the first transistor, the second transistor, and the third transistor are integrally formed.

11. The display substrate as claimed in claim 10, wherein, The gate of the first transistor is electrically connected to the first clock signal terminal, the first terminal of the first transistor is electrically connected to the first voltage line, and the second terminal of the first transistor is electrically connected to the second node. The gate of the second transistor is electrically connected to the first clock signal terminal, the first terminal of the second transistor is electrically connected to the first node, and the second terminal of the second transistor is electrically connected to the first control node. The gate of the third transistor is electrically connected to the first clock signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the third transistor is electrically connected to the third node; The first transistor, the second transistor, and the third transistor are all p-type transistors; or, the first transistor, the second transistor, and the third transistor are all n-type transistors.

12. The display substrate according to any one of claims 2 to 11, wherein, The driving circuit further includes an input circuit and an energy storage circuit; the display substrate further includes a second first voltage line and a second second voltage line disposed on the substrate; The input circuit is electrically connected to the input terminal, the second first voltage line, the second second voltage line, the first node, the second node, the third node, the first control node, and the first first voltage line, respectively. It is used to control the connection or disconnection between the first node and the second second voltage line, the connection or disconnection between the first node and the second first voltage line, the connection or disconnection between the second node and the first control node, and the connection or disconnection between the third node and the second second voltage line, respectively, under the control of the input signal provided by the input terminal. The first end of the energy storage circuit is electrically connected to the first voltage line, and the second end of the energy storage circuit is electrically connected to the first control node.

13. The display substrate as claimed in claim 12, wherein, The line width of the first voltage line is greater than the line width of the second voltage line, and the line width of the first voltage line is greater than the line width of the second voltage line.

14. The display substrate as claimed in claim 13, wherein, The carry-out output circuit is also electrically connected to the second first voltage line and the first second voltage line respectively, and is used to control the connection or disconnection between the carry-out output terminal and the second first voltage line, and the connection or disconnection between the carry-out output terminal and the first second voltage line, under the control of the potential of the first control node.

15. The display substrate as claimed in claim 12, wherein, The driving circuit further includes a power-on setting circuit; the display substrate further includes a power-on setting control line disposed on the substrate; The power-on set circuit is electrically connected to the power-on set control line, the first control node, and the second first voltage line, respectively, and is used to control the connection or disconnection between the first control node and the second first voltage line under the control of the power-on set control signal provided by the power-on set control line.

16. The display substrate as claimed in claim 15, wherein, The display substrate further includes a first clock signal line and a second clock signal line disposed on the substrate; The fourth voltage line, the third voltage line, the first second voltage line, the first first voltage line, the second clock signal line, the first clock signal line, the second second voltage line, the power-on set control line, and the second first voltage line are arranged sequentially in the direction away from the display area.

17. The display substrate as claimed in claim 15, wherein, The input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the power-on set circuit includes an eighth transistor and a ninth transistor; the energy storage circuit includes a first capacitor; The gate of the fourth transistor is electrically connected to the input terminal, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the second voltage line. The gate of the fifth transistor is electrically connected to the input terminal, the first terminal of the fifth transistor is electrically connected to the second first voltage line, and the second terminal of the fifth transistor is electrically connected to the first node. The gate of the sixth transistor is electrically connected to the input terminal, the first terminal of the sixth transistor is electrically connected to the second node, and the second terminal of the sixth transistor is electrically connected to the first control node. The gate of the seventh transistor is electrically connected to the input terminal, the first terminal of the seventh transistor is electrically connected to the third node, and the second terminal of the seventh transistor is electrically connected to the second voltage line. The first plate of the first capacitor is electrically connected to the first voltage line, and the second plate of the first capacitor is electrically connected to the first control node. The gate of the eighth transistor is electrically connected to the power-on set control line, the first terminal of the eighth transistor is electrically connected to the first control node, and the second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor. The gate of the ninth transistor is electrically connected to the power-on set control line, and the second terminal of the ninth transistor is electrically connected to the second first voltage line. The carry-out circuit includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is electrically connected to the first control node, the first terminal of the tenth transistor is electrically connected to the second first voltage line, and the second terminal of the tenth transistor is electrically connected to the carry output terminal. The gate of the eleventh transistor is electrically connected to the first control node, the first terminal of the eleventh transistor is electrically connected to the carry output terminal, and the second terminal of the eleventh transistor is electrically connected to the first second voltage line. The second node control circuit includes a twelfth transistor and a thirteenth transistor; The gate of the twelfth transistor is electrically connected to the carry output terminal, the first terminal of the twelfth transistor is electrically connected to the first voltage line, and the second terminal of the twelfth transistor is electrically connected to the second control node. The gate of the thirteenth transistor is electrically connected to the carry output terminal, the first terminal of the thirteenth transistor is electrically connected to the second control node, and the second terminal of the thirteenth transistor is electrically connected to the first second voltage line. The drive output circuit includes a fourteenth transistor and a fifteenth transistor; The gate of the fourteenth transistor is electrically connected to the second control node, the first terminal of the fourteenth transistor is electrically connected to the third voltage line, and the second terminal of the fourteenth transistor is electrically connected to the drive output terminal. The gate of the fifteenth transistor is electrically connected to the second control node, the first terminal of the fifteenth transistor is electrically connected to the drive output terminal, and the second terminal of the fifteenth transistor is electrically connected to the fourth voltage line.

18. The display substrate as claimed in claim 17, wherein, The fourth, seventh, eleventh, thirteenth, and fifteenth transistors are all n-type transistors, while the fifth, sixth, eighth, ninth, tenth, twelfth, and fourteenth transistors are all p-type transistors.

19. A method of manufacturing a display substrate as described in any one of claims 1 to 18, the method comprising: A drive module, a first voltage line, a first second voltage line, a third voltage line, and a fourth voltage line are disposed on the substrate; The line width of the third voltage line is set to be greater than the line width of the first voltage line, and / or the line width of the fourth voltage line is set to be greater than the line width of the first second voltage line.

20. A display device comprising a display substrate as claimed in any one of claims 1 to 18.

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