Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate (10) comprises a display area, a frame area located at the periphery of the display area, and a binding area located in the frame area away from a first side of the display area; the array substrate (10) comprises a base (1), an adapter electrode (2), and a plurality of compensation resistors (4); the adapter electrode (2) is disposed on the base (1) and located in the frame area; a compensation signal line (3) extends from the binding area to the frame area, and is arranged around the periphery of the adapter electrode (2); the plurality of compensation resistors (4) are arranged at intervals in the frame area; one end of each of the plurality of compensation resistors (4) is electrically connected to the compensation signal line (3), and the other end is electrically connected to the adapter electrode (2); and the resistance values of at least two of the compensation resistors (4) are different.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the rapid development of the display industry, users have increasingly higher demands for viewing experience. Liquid crystal display (LCD) technology has been successfully applied to display products such as laptops, monitors, and televisions. As LCD products become more widely used, people are also placing higher demands on their display quality. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate has a display area, a border area located around the display area, and a bonding area located on a first side of the border area away from the display area; wherein, the array substrate includes: a substrate, a transfer electrode, and a plurality of compensation resistors; the transfer electrode is disposed on the substrate and located in the border area; the compensation signal line extends from the bonding area to the border area and is disposed circumferentially along the transfer electrode; the plurality of compensation resistors are spaced apart in the border area, and one end of each compensation resistor is electrically connected to the compensation signal line, and the other end is electrically connected to the transfer electrode; wherein, at least two of the compensation resistors have different resistance values.

[0004] In some embodiments, the compensation signal line includes a first compensation signal line, the first compensation signal line extending to one end of the frame area and electrically connected to the adapter electrode.

[0005] In some embodiments, the display area includes a second side opposite to the first side and a third side located between the first side and the second side; the plurality of compensation resistors are a plurality of voltage divider lines, the plurality of voltage divider lines include a plurality of first-type voltage divider lines, the plurality of first-type voltage divider lines are located on the second side and / or the third side.

[0006] In some embodiments, the plurality of first-type voltage divider lines are located on the second side, and the resistance of the first-type voltage divider lines closer to the third side is greater than the resistance of the first-type voltage divider lines farther from the third side.

[0007] In some embodiments, the plurality of first-type voltage divider lines are located on the third side, and the resistance value of the first-type voltage divider line closer to the bonding area is greater than the resistance value of the first-type voltage divider line farther from the bonding area.

[0008] In some embodiments, the first type of voltage dividing lines are located at the second side and the third side, and the resistance of the first type of voltage dividing lines located at the second side is smaller than the resistance of the first type of voltage dividing lines located at the third side.

[0009] In some embodiments, the first compensation signal line is electrically connected with a plurality of the first type of voltage dividing lines, and the resistance of the first type of voltage dividing lines decreases with the increase of the extension length of the first compensation signal line.

[0010] In some embodiments, the array substrate comprises a plurality of the first compensation signal lines, and each of the opposite sides of the frame region is provided with at least one of the first compensation signal lines. Each of the first compensation signal lines is connected with at least one of the first type of voltage dividing lines, and the first compensation signal lines located at the opposite sides of the frame region receive voltage signals with the same amplification factor.

[0011] In some embodiments, a symmetry axis is further included, the symmetry axis extends along a first direction, the first direction is parallel to the array substrate and perpendicular to the extension direction of the binding region; and the connection points of the first type of voltage dividing lines located at the opposite sides of the frame region and the transfer electrodes are symmetrically arranged about the symmetry axis.

[0012] In some embodiments, the resistances of the first type of voltage dividing lines symmetrically arranged about the symmetry axis are the same.

[0013] In some embodiments, the compensation signal line comprises a second compensation signal line, the second compensation signal line extends from one side of the binding region along the extension direction thereof to the frame region, and is connected to the other side of the binding region along the extension direction thereof.

[0014] In some embodiments, the display region comprises a second side opposite to the first side, and a third side between the first side and the second side; and the compensation resistances are a plurality of voltage dividing lines, the plurality of voltage dividing lines comprise a plurality of second type of voltage dividing lines, the plurality of second type of voltage dividing lines are located at the second side and / or the third side.

[0015] In some embodiments, the plurality of second type of voltage dividing lines are located at the second side, and the resistance of the second type of voltage dividing lines close to the third side is smaller than the resistance of the second type of voltage dividing lines away from the third side.

[0016] In some embodiments, the plurality of second type of voltage dividing lines are located at the third side, and the resistance of the second type of voltage dividing lines close to one side of the binding region is greater than the resistance of the second type of voltage dividing lines away from one side of the binding region.

[0017] In some embodiments, the plurality of second-type voltage divider lines are located on the second side and the third side, and the resistance of the second-type voltage divider line located on the third side is greater than the resistance of the second-type voltage divider line located on the second side.

[0018] In some embodiments, the first compensation signal line and the second compensation signal line are made of the same material and are disposed in the same layer.

[0019] In some embodiments, the array substrate includes: a gate conductive layer, a source / drain conductive layer, and a transparent conductive layer. The gate conductive layer is disposed on the substrate and includes a compensation signal line. The source / drain conductive layer is disposed on the side of the gate conductive layer away from the substrate. The transparent conductive layer is disposed on the side of the source / drain conductive layer away from the substrate, and the transfer electrode is located on the transparent conductive layer. The compensation resistor is disposed in at least one of the gate conductive layer, the source / drain conductive layer, or the transparent conductive layer.

[0020] In some embodiments, the compensation signal line and the compensation resistor are located on the same layer, and the compensation signal line is connected to the compensation resistor.

[0021] In some embodiments, the compensation resistor is a voltage divider line, and the voltage divider line is arranged in an arc shape.

[0022] In some embodiments, the transparent conductive layer further includes a common electrode, which is electrically connected to the transition electrode.

[0023] On the other hand, a display panel is provided, including an array substrate as described in any of the above embodiments, and a counter substrate disposed opposite to the array substrate; and a liquid crystal layer located between the array substrate and the counter substrate.

[0024] In another aspect, a display panel is provided, including an array substrate as described in any of the above embodiments, a counter substrate disposed opposite to the array substrate, and a sealing adhesive connected between the array substrate and the counter substrate, the sealing adhesive being located in the border area; wherein, a common electrode layer is disposed on the side of the counter substrate near the array substrate, the common electrode layer including a common electrode, the common electrode being electrically connected to the transfer electrode through conductive particles.

[0025] In another aspect, a display device is provided. The display device includes: a display panel as described in the above embodiments and a common voltage generation circuit, the common voltage generation circuit being coupled to the bonding area, and the common voltage generation circuit being configured to provide a common voltage for the compensation signal line.

[0026] In some embodiments, the display device further includes: a plurality of flip-chip films bonded to a bonding region of an array substrate, the bonding region including a plurality of bonding sub-regions, each of the flip-chip films being bonded to one of the bonding sub-regions and coupled to the compensation signal line; the common voltage generation circuit being electrically connected to the display panel through the plurality of flip-chip films.

[0027] In some embodiments, where the compensation signal line includes a first compensation signal line, the display device further includes an operational amplifier coupled to the common voltage generation circuit and the first compensation signal line, the operational amplifier being configured to amplify the common voltage signal from the common voltage generation circuit and transmit it to the first compensation signal line. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be considered as schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of this disclosure.

[0029] Figure 1A is a top view of a display device according to some embodiments of the present disclosure;

[0030] Figure 1B is a top view of another display device according to some embodiments of the present disclosure;

[0031] Figure 2 is a top view of another embodiment of a display device according to the present disclosure.

[0032] Figure 3A is a top view of an array substrate according to some embodiments of the present disclosure;

[0033] Figure 3B is a top view of another array substrate according to some embodiments of the present disclosure;

[0034] Figure 3C is a top view of another array substrate according to some embodiments of the present disclosure;

[0035] Figure 3D is a top view of another array substrate according to some embodiments of the present disclosure;

[0036] Figure 4A is a top view of an array substrate according to some embodiments of the present disclosure;

[0037] Figure 4B is a top view of another array substrate according to some embodiments of the present disclosure;

[0038] Figure 5 is a top view of an array substrate according to some embodiments of the related art;

[0039] Figure 6A is a cross-sectional structural diagram of an array substrate according to some embodiments of the present disclosure;

[0040] Figure 6B is another cross-sectional view of an array substrate according to some embodiments of the present disclosure;

[0041] Figure 6C is another cross-sectional view of an array substrate according to some embodiments of the present disclosure;

[0042] Figure 7A is a connection structure diagram of the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure;

[0043] Figure 7B is a diagram showing another connection structure between the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 7C is a diagram showing another connection structure of the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure;

[0045] Figure 7D is a diagram showing another connection structure between the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure.

[0046] Figure 7E is a diagram showing another connection structure between the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure.

[0047] Figure 7F is a diagram showing another connection structure of the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure.

[0048] Figure 7G is a diagram showing another connection structure between the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure.

[0049] Figure 7H is a diagram showing another connection structure of the compensation resistor and the transfer electrode of the array substrate according to some embodiments of the present disclosure.

[0050] Figure 7I is a connection structure diagram of the compensation resistor and the transfer electrode of an array substrate according to some embodiments of the present disclosure;

[0051] Figure 8 is a structural diagram of a compensation resistor for an array substrate according to some embodiments of the present disclosure;

[0052] Figure 9 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0053] Figure 10 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0054] Figure 11 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0055] Figure 12 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0056] Figure 13 is another structural diagram of a display device according to some embodiments of the present disclosure. Detailed Implementation

[0057] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0058] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0059] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0060] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0061] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and includes the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0062] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0063] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when…” or “in the event of…” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrase “if determination…” or “if detection [the stated condition or event]” may optionally be interpreted as meaning “in the event of determination…” or “in response to determination…” or “in response to detection [the stated condition or event]” or “in response to detection [the stated condition or event].”

[0064] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0065] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0067] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0068] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0069] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0070] The transistors used in the circuits provided in the embodiments of this application can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors), or other switching devices with the same characteristics. The embodiments of this application all use thin-film transistors as examples for illustration. Preferably, the thin-film transistors used in the embodiments of this disclosure can be amorphous silicon semiconductor transistors, oxide semiconductor transistors, or low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0071] With the continuous advancement of display technology, liquid crystal display products are being used more and more widely, such as in display devices like laptops, monitors, and televisions. Among them, liquid crystal display devices (LCDs) have advantages such as small size, low power consumption, thinness, and no radiation. However, with the widespread use of liquid crystal display devices, people have also put forward higher requirements for the display quality of liquid crystal display devices.

[0072] In some embodiments, large-size, narrow-bezel liquid crystal display devices, such as high aperture ratio advanced super-dimensional switching (HADS) display devices, have narrow bezels (e.g., bezel width of 3.5mm). This results in a smaller width of the signal lines located within the bezel area, leading to increased resistance and weakened recovery capability of the signal lines. Furthermore, the high resolution of the liquid crystal display device results in larger internal coupling capacitances (e.g., the coupling capacitance formed between the data lines and the common electrode), causing signal distortion and potential drift during signal transmission. As the refresh rate increases, this potential is difficult to recover to its initial state within one frame, causing lateral crosstalk. This affects the normal charging and discharging of pixels, resulting in line retention during the display phase of the liquid crystal display device, which is difficult to eliminate. Line retention, also known as image persistence, refers to a static image remaining on the screen for an extended period. This phenomenon changes over time and with changes in the image, eventually disappearing. For example, in a liquid crystal display device, the pixel electrodes may accumulate charge due to coupling capacitance and other reasons. When the charge accumulates to a certain extent over a long period of time, it will cause a potential difference and electric field to form between the pixel electrode and the common electrode. As these charges slowly disappear, they will cause image retention in the liquid crystal display device, affecting the display effect.

[0073] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel, and a display device that can improve the stability of signal transmission and enhance the anti-interference capability of the display device, thereby improving the display quality.

[0074] For ease of description below, an XYZ coordinate system is established. The third direction Z is perpendicular to the substrate, i.e., the thickness direction in this application. The XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0075] It should be noted that, for example, 32 / 3 in the accompanying drawings of some embodiments of this disclosure indicates that component 32 belongs to component 3, and other similar reference numerals in the drawings also follow the above description.

[0076] The array substrate, display panel and display device provided in this disclosure are described below.

[0077] Some embodiments of this disclosure provide an array substrate 10, as shown in FIG1A and FIG2. The array substrate 10 has a display area AA, a border area BB located around the display area AA, and a bonding area CC located on the first side A1 of the border area BB away from the display area AA. The bonding area CC is used to bond circuit boards (e.g., flexible circuit boards) and / or data driver chips, etc.

[0078] It is understood that, referring to Figures 1A and 2, the border area BB is located outside the display area AA, that is, the border area BB of the array substrate 10 is set around the display area AA of the array substrate 10.

[0079] The following description assumes that the array substrate 10 has a rectangular structure. However, the embodiments disclosed herein include, but are not limited to, this. The shape of the array substrate 10 may also be any other shape.

[0080] For example, the binding area CC is located on the side of the border area BB that is far away from the first side A1 of the display area AA. For example, if the display area AA has a rectangular structure, then the display area AA includes four boundaries. Here, the first side A1 can be any one of the four boundaries of the display area AA, and the first side A1 is close to the binding area CC.

[0081] The array substrate 10 includes a substrate 1, a transfer electrode 2, a compensation signal line 3, and compensation resistors 4. The transfer electrode 2 is disposed on the substrate 1 and located in the border area BB. The compensation signal line 3 extends from the bonding area CC to the border area BB and is disposed circumferentially along the transfer electrode 2. A plurality of compensation resistors 4 are disposed at intervals in the border area BB, and one end of each compensation resistor 4 is electrically connected to the compensation signal line 3, and the other end is electrically connected to the transfer electrode 2. At least two of the compensation resistors 4 have different resistance values.

[0082] For example, referring to Figures 1A, 1B, and 2, the compensation signal line 3 in Figures 1A, 1B, and 2 all extends from the bonding area CC to the side of the border area BB away from the bonding area CC. The compensation signal line 3 is arranged circumferentially along the adapter electrode 4. The adapter electrode 2 can be arranged around the display area as shown in Figures 1A and 2, for example, in a ring shape, or it can partially surround the display area. For example, as shown in Figure 1B, the adapter electrode 2 is partially disconnected in the border area BB opposite the bonding area CC. It can be understood that since the adapter electrode 2 is located in the border area BB... The portion of the compensation signal line 3 extending into the frame area BB is located around the partial transfer electrode 4. It should be noted that the transfer electrodes here can all be set to the same layer, such as any layer including the display area pixel electrode layer, common electrode layer, gate line layer, data line layer, etc. The transfer electrodes can also be set in at least two layers, or a structure with two or more layers electrically connected. For example, electrical connection can be achieved by setting vias on the insulating layer. The at least two film layers can be any two or more layers including the display area pixel electrode layer, common electrode layer, gate line layer, data line layer, etc., and are not limited here.

[0083] One end of the aforementioned compensation resistor 4 is electrically connected to the compensation signal line 3, and the other end is electrically connected to the transfer electrode 2. That is, the compensation resistor 4 is electrically connected between the compensation signal line 3 and the transfer electrode 2. It can be understood that the voltage signal transmitted by the compensation signal line 3 will pass through the compensation resistor 4 before being transmitted to the transfer electrode 2. This setting allows the compensation resistor 4 and the transfer electrode 2 to be connected in series, meaning that the compensation resistor 4 can play the role of voltage divider.

[0084] By setting at least two compensation resistors 4 with different resistance values, the signal transmitted by the compensation signal line 3 can be divided before being transmitted to the adapter electrode 2. This ensures that the voltage signal received by the adapter electrode 2 at different locations is consistent or tends to be consistent. Since the adapter electrode 2 is used to connect to the common electrode, it means that under the action of the compensation signal line 3 and the compensation resistors 4, the voltage signal received by the common electrode in different areas can be consistent or tends to be consistent, thereby improving the problem of lateral crosstalk affecting the display effect caused by the excessive coupling capacitance.

[0085] There are multiple ways to set up the compensation signal line. The following is a schematic illustration of different ways to set up the compensation signal line with reference to the attached drawings, but it is not limited to the examples in this article.

[0086] In some embodiments, referring to FIG1A, the compensation signal line 3 includes a first compensation signal line 31, the first compensation signal line 31 extending to one end of the frame area BB and electrically connected to the adapter electrode 2.

[0087] For example, referring to FIG1A, one end of the first compensation signal line 31 extending to the frame area BB is located on the side of the frame area BB away from the bonding area CC and is electrically connected to the adapter electrode 2. That is, the frame area BB on the opposite side of the first compensation signal line 31 extending to the bonding area CC is electrically connected to the adapter electrode 2, which can ensure signal transmission between the first compensation signal line 31 and the adapter electrode 2.

[0088] It should be noted that the end of the first compensation signal line 31 extending into the frame area BB is directly electrically connected to the adapter electrode 2, without a compensation resistor 4 between them. This is because the voltage signal transmitted by the first compensation signal line 31 will suffer some loss during transmission. Specifically, the voltage signal at the end of the first compensation signal line 31 extending into the frame area BB away from the bonding area CC is smaller than the voltage signal at the end of the first compensation signal line 31 extending into the frame area BB closer to the bonding area CC. Therefore, in order to ensure that the voltage of the adapter electrode 2 is consistent at all positions, that is, the voltage received by the adapter electrode 2 at a certain position does not need to be divided by the compensation resistor 4 to achieve the same voltage as that received by the adapter electrode 4 at other positions, it is necessary to ensure that the signal transmitted to the common electrode remains consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0089] In some embodiments, referring to Figures 3A, 3B, 3C and 1A, the display area AA includes a second side A2 opposite to the first side A1, and a third side A3 located between the first side A1 and the second side A2; the plurality of compensation resistors 4 are a plurality of voltage divider lines 41, the plurality of voltage divider lines 41 including a plurality of first-type voltage divider lines 410, the plurality of first-type voltage divider lines 410 being located on the second side A2 and / or the third side A3.

[0090] For example, referring to Figure 3A, multiple first-type voltage divider lines 410 are all located on the second side A2; referring to Figure 3B, multiple first-type voltage divider lines 410 are all located on the third side A3; referring to Figures 3C and 1A, multiple first-type voltage divider lines 410 are located on the second side A2 and the third side A3, respectively. The positions of the first-type voltage divider lines 410 can be set according to actual needs and are not specifically limited here.

[0091] It should be noted that, taking a rectangular shape for the display area AA as an example, the second side A2 is the side opposite to the first side A1, meaning the second side A2 is farther away from the binding area CC relative to the first side A1. The third side A3 is located between the first side A1 and the second side A2. For example, the third side A3 can be two opposite sides extending between the first side A1 and the second side A2, and the third side A3 is closer to the binding area CC relative to the second side A2. The above is only one example. Specifically, the shape of the display area AA is not limited. When the shape of the display area AA is other than other shapes, the second side A2 is still the side opposite to the first side A1, and the third side A3 is located between the first side A1 and the second side A2.

[0092] The reason for setting multiple first-type voltage divider lines 410 is that the voltage signal transmitted by the first compensation signal line 31 will suffer certain losses during transmission. That is, the attenuation of the voltage signal of the first compensation signal line 31 is different at different positions. Therefore, in order to ensure that the voltage received by the transfer electrode 2 at each position is consistent or tends to be consistent, that is, the voltage received by the transfer electrode 2 at different positions needs to be divided by multiple first-type voltage divider lines 410. This will ensure that the voltage received by the transfer electrode 4 at different positions is consistent, so as to ensure that the signal transmitted to the common electrode can be consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0093] In some embodiments, referring to FIG3A, a plurality of first-type voltage divider lines 410 are located on the second side A2, and the resistance R2 of the first-type voltage divider line 410 closer to the third side A3 is greater than the resistance R1 of the first-type voltage divider line 410 farther from the third side A3.

[0094] For example, referring to FIG3A, the resistance value of the first type voltage divider line 410 away from the third side A3 is R1, and the resistance value of the first type voltage divider line 410 near the third side A3 is R2. Since the first compensation signal line 31 extends from the bonding area CC through the third side A3 to the second side A2 during its extension, the first compensation signal line 31 is first electrically connected to the first type voltage divider line 410 near the third side A3, and then electrically connected to the first type voltage divider line 410 away from the third side A3. During the transmission of the first compensation signal line 31, there will be signal attenuation, that is, the voltage transmitted to the transfer electrode 2 away from the third side A3 will be less than the voltage transmitted to the transfer electrode 2 near the third side A3. Therefore, setting the resistance value relationship of R1 being less than R2 can ensure that the voltage transmitted to the transfer electrode 2 away from the third side A3 is consistent with the voltage transmitted to the transfer electrode 2 near the third side A3, so as to ensure that the signal transmitted to the common electrode is consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by the large coupling capacitance affecting the display effect.

[0095] In some embodiments, referring to FIG3B, a plurality of first-type voltage divider lines 410 are located on the third side A3, and the resistance R4 of the first-type voltage divider line 410 on the side closer to the bonding area CC is greater than the resistance R3 of the first-type voltage divider line 410 on the side farther from the bonding area CC.

[0096] For example, referring to FIG3B, the resistance of the first type voltage divider line 410 on the side closer to the bonding area CC is R4, and the resistance of the first type voltage divider line 410 on the side farther from the bonding area CC is R3. Since the first compensation signal line 31 extends from the bonding area CC through the third side A3 to the second side A2 during the extension process, the first compensation signal line 31 is first electrically connected to the first type voltage divider line 410 on the side closer to the bonding area CC, and then electrically connected to the first type voltage divider line 410 on the side farther from the bonding area CC. During transmission, the first compensation signal line 31 will experience signal attenuation. That is, the voltage transmitted to the transfer electrode 2 on the side away from the bonding area CC will be less than the voltage transmitted to the transfer electrode 2 on the side close to the bonding area CC. Therefore, by setting the resistance value of R3 to be less than that of R4, it can be ensured that the voltage transmitted to the transfer electrode 2 on the side away from the bonding area CC is consistent with the voltage transmitted to the transfer electrode 2 on the side close to the bonding area CC. This ensures that the voltage signal transmitted to the common electrode on the side close to the bonding area CC is consistent with the voltage signal transmitted to the common electrode on the side away from the bonding area CC, thereby avoiding the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0097] In some embodiments, referring to Figures 3C and 1A, multiple first-type voltage divider lines 410 are located on the second side A2 and the third side A3, respectively, and the resistance of the first-type voltage divider line 410 located on the second side A2 is less than the resistance of the first-type voltage divider line 410 located on the third side A3.

[0098] For example, referring to Figures 3C and 1A, as described above, the first compensation signal line 31 extends from the bonding area CC through the third side A3 to the second side A2 during its extension. Therefore, the first compensation signal line 31 is first electrically connected to the first type voltage divider line 410 located on the third side A3, and then electrically connected to the first type voltage divider line 410 located on the second side A2. During the transmission of the first compensation signal line 31, there will be signal attenuation, that is, the voltage transmitted to the adapter electrode 2 on the third side A3 will be greater than the voltage transmitted to the adapter electrode 2 on the second side A2. Therefore, by setting the above resistance relationship, it can be ensured that the voltage of the adapter electrode 2 finally transmitted to the third side A3 is consistent with the voltage of the adapter electrode 2 transmitted to the second side A2, so as to ensure that the voltage signal transmitted to the common electrode on the third side A3 is consistent with the voltage signal transmitted to the common electrode on the second side A2, thereby avoiding the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0099] It should be noted that, referring to Figures 3C and 1A, the number of first-type voltage divider lines 410 located on the second side A2 is different in Figures 3C and 1A, and the number of first-type voltage divider lines 410 located on the third side A3 is also different. Here, the number of first-type voltage divider lines 410 on the second side A2 or the third side A3 is not limited, and the specific number depends on the actual needs.

[0100] In some embodiments, referring to Figures 3C and 1A, the first compensation signal line 31 is electrically connected to a plurality of first-type voltage divider lines 410, and the resistance of the first-type voltage divider lines 410 decreases as the extension length of the first compensation signal line 31 increases.

[0101] For example, referring to FIG1A, as described in the foregoing section, the first compensation signal line 31 experiences signal attenuation during transmission; that is, the longer the extension length of the first compensation signal line 31, the greater the attenuation. Correspondingly, the resistance of the first type of voltage divider line 410 connected to the first compensation signal line 31 changes based on the position of the first compensation signal line 31 transmitted to the adapter electrode 2. That is, the longer the extension length of the first compensation signal line 31, the smaller the voltage transmitted to the adapter electrode 2. To ensure that the voltage transmitted from the first compensation signal line 31 to the adapter electrode 2 remains consistent at different positions, the resistance of the first type of voltage divider line 410 is set to decrease as the extension length of the first compensation signal line 31 increases, for example, R4 > R3 > R2 > R1, to ensure that the voltage signal of the transmitted common electrode remains consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by excessive coupling capacitance affecting the display effect.

[0102] In some embodiments, referring to FIG3C, the array substrate 10 includes a plurality of first compensation signal lines 31. At least one first compensation signal line 31 is provided on each of the opposite sides of the frame region BB. Each first compensation signal line 31 is connected to at least one first type voltage divider line 410, and the voltage signals received by the first compensation signal lines 31 located on opposite sides of the frame region BB have the same amplification factor.

[0103] It should be noted that the voltage signal received by the first compensation signal line 31 comes from the operational amplifier, and the amplification factor refers to the factor by which the operational amplifier amplifies the voltage signal it receives. The above are set to the same amplification factor, that is, the number of operational amplifiers can be only one, which can save costs while ensuring the transmission efficiency of the voltage signal.

[0104] For example, referring to FIG3C, when the array substrate 10 includes multiple first compensation signal lines 31, the first compensation signal lines 31 can be arranged in the same manner on each of the opposite sides of the frame region BB. With this configuration, the transfer electrode 2 can receive bilateral compensation from the first compensation signal lines 31, and the common electrode electrically connected to the transfer electrode 2 can be quickly compensated, thereby improving the compensation efficiency.

[0105] It should be noted that the voltage signals received by the multiple first compensation signal lines 31 here are amplified by operational amplifiers, and the amplification factor of the voltage signals received by the multiple first compensation signal lines 31 is the same. However, in some embodiments of related technologies, the amplification factor of the signals received by the multiple compensation lines is different, requiring multiple operational amplifiers to amplify the voltage signals and multiple signal lines connected to the operational amplifiers to be arranged. Compared with related technologies, this application can simplify the circuit, reduce the cost of operational amplifiers and signal lines, and also help to reduce the width of the border area BB.

[0106] In some embodiments, referring to FIG3D, the array substrate 10 may also include only one first compensation signal line 31, and the first compensation signal line 31 is disposed on either side of the opposite sides of the frame region BB.

[0107] In some embodiments, referring to FIG3C, the array substrate 10 has a symmetry axis L, which extends along a first direction X. The first direction X is parallel to the array substrate 10 and perpendicular to the extension direction of the bonding region CC. The connection points of the first type of voltage divider line 410 located on both sides of the frame region BB and the transfer electrode 2 are symmetrically arranged about the symmetry axis L.

[0108] For example, referring to FIG3C, the connection points of the first type of voltage divider line 410 located on both sides of the bezel area BB and the adapter electrode 2 are symmetrically arranged about the axis of symmetry L. That is, multiple first type of voltage divider lines 410 are symmetrically arranged about the axis of symmetry L, that is, the compensation positions are symmetrical. The above symmetrical arrangement can improve the voltage division efficiency of the first type of voltage divider line 410, thereby improving the compensation efficiency of the common electrode at different positions, so as to avoid the problem of lateral crosstalk caused by the large coupling capacitance affecting the display effect.

[0109] In some embodiments, referring to FIG3C, the resistance values ​​of the first type of voltage divider lines 410 arranged symmetrically about the axis of symmetry L are the same.

[0110] It should be noted that, since the magnitude of the voltage signal transmitted by the first compensation signal line 31 is related to its extension length, the signals received by the first compensation signal line 31 by the symmetrically arranged transfer electrodes 2 about the axis of symmetry are usually consistent, and the required compensation voltage is consistent. Therefore, the resistance values ​​of the first type of voltage divider lines 410 symmetrically arranged about the axis of symmetry L are the same. The first type of voltage divider lines 410 can effectively play a precise compensation role, thereby improving the consistency of the voltage signals received by the common electrode at different positions, so as to avoid the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0111] It should also be noted that the above-mentioned symmetrical arrangement refers to the arrangement position of the first type of voltage divider line 410 about the axis of symmetry L, and is not a limitation on the shape of the first type of voltage divider line 410. Of course, in some embodiments, the shape of the first type of voltage divider line 410 can also be symmetrically arranged about the axis of symmetry L.

[0112] In some embodiments, referring to FIG2, the compensation signal line 3 includes a second compensation signal line 32, which extends from one side of the binding area CC along its extension direction to the border area BB and is connected to the other side of the binding area CC along its extension direction.

[0113] For example, referring to FIG2, the second compensation signal line 32 can be a common voltage signal line. The second compensation signal line 32 is arranged circumferentially along the adapter electrode 2, and the second compensation signal line 32 extends from one side of the bonding area CC to the side of the frame area BB away from the bonding area CC, and then connects to the other side of the bonding area CC along its extension direction. The extension direction of the bonding area CC is perpendicular to the first direction X.

[0114] It should be noted that the second compensation signal line 32 multiplexes the common voltage signal line, while the initial common voltage signal line COM is coupled between the first side A1 of the display area AA and the bonding area CC. Setting the second compensation signal line 32 can improve the transmission efficiency of the common voltage signal. The common voltage signal can be transmitted not only on the first side A1 of the display area AA, but also on the second side A2 of the display area AA. In addition, the second compensation signal line 32 has a compensation function, which can avoid the problem of inconsistent signals received by the common electrode at different positions.

[0115] In some embodiments, referring to FIG2, FIG4A and FIG4B, the display area AA includes a second side A2 opposite to the first side A1, and a third side A3 located between the first side A1 and the second side A2; the plurality of compensation resistors 4 are a plurality of voltage divider lines 41, the plurality of voltage divider lines 41 including a plurality of second type voltage divider lines 420, the plurality of second type voltage divider lines 420 being located on the second side A2, and / or, being located on the third side A3.

[0116] For example, referring to Figure 2, multiple second-type voltage divider lines 420 are all located on the second side A2; referring to Figure 4A, multiple second-type voltage divider lines 420 are all located on the third side A3; referring to Figure 4B, multiple second-type voltage divider lines 420 are located on the second side A2 and the third side A3 respectively. The location of the second-type voltage divider lines 420 can be set according to actual needs and is not specifically limited here.

[0117] It should be noted that for the specific descriptions of the second side A2 and the third side A3, please refer to the descriptions in the preceding sections, which will not be repeated here.

[0118] In some embodiments, referring to FIG4A, a plurality of second-type voltage divider lines 420 are located on the second side A2, and the resistance R6 of the second-type voltage divider line 420 closer to the third side A3 is less than the resistance R5 of the second-type voltage divider line 420 farther from the third side A3.

[0119] For example, referring to FIG4A, the resistance of the second type voltage divider line 420 away from the third side A3 is R5, and the resistance of the second type voltage divider line 420 near the third side A3 is R6. The second compensation signal line 32 multiplexes the common voltage signal line. According to the inventor's test, the common voltage in the display area AA is not completely consistent at different positions. The optimal distribution curve is shown in FIG5. The common voltage at the center of the display area AA is higher than the common voltage at the edge, for example, Vcom1 > Vcom2 > Vcom3. Therefore, using the voltage divider principle of the compensation resistor 4, the larger the resistance of the compensation resistor 4, the smaller the voltage ultimately transmitted to the transfer electrode 2. By setting the above-mentioned resistance relationship of R6 being less than R5, it can be ensured that the voltage ultimately transmitted to the transfer electrode 2 away from the third side A3 is consistent with the voltage transmitted to the transfer electrode 2 near the third side A3. This ensures that the signal transmitted to the common electrode remains consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by the excessive coupling capacitance affecting the display effect.

[0120] In some embodiments, referring to FIG4B, a plurality of second-type voltage divider lines 420 are located on the third side A3, and the resistance R8 of the second-type voltage divider line 420 on the side closer to the bonding area CC is greater than the resistance R7 of the second-type voltage divider line 420 on the side farther from the bonding area CC.

[0121] For example, referring to FIG4B, the resistance of the second type voltage divider line 420 on the side away from the bonding area CC is R7, and the resistance of the second type voltage divider line 420 on the side closer to the bonding area CC is R8. The second compensation signal line 31 multiplexes the common voltage signal line. According to the inventor's test, the common voltage in the display area AA is not completely consistent at different positions. The common voltage at the center of the display area AA is higher than the common voltage at the edge, and the common voltage on the side closer to the bonding area CC is higher than the common voltage on the side away from the bonding area CC. Therefore, by setting the resistance value relationship of R7 less than R8, it is possible to ensure that the voltage transmitted to the transfer electrode 2 away from the third side A3 is consistent with the voltage transmitted to the transfer electrode 2 close to the third side A3, so as to ensure that the voltage signal transmitted to the common electrode is consistent at different positions, thereby avoiding the problem of lateral crosstalk caused by the large coupling capacitance affecting the display effect.

[0122] In some embodiments, referring to FIG2, a plurality of second-type voltage divider lines 420 are located on the second side A2 and the third side A3, and the resistance of the second-type voltage divider line 420 located on the third side A3 is greater than the resistance of the second-type voltage divider line 420 located on the second side A2.

[0123] For example, referring to FIG2, as described above, the common voltage at the center of the display area AA is higher than the common voltage at the edge, and the common voltage on the side closer to the bonding area CC is higher than the common voltage on the side farther from the bonding area CC. Combining the two embodiments described above, by setting the above resistance relationship, it is possible to ensure that the voltage of the transfer electrode 2 finally transmitted to the third side A3 is consistent with the voltage of the transfer electrode 2 transmitted to the second side A2, so as to ensure that the voltage signal transmitted to the common electrode of the third side A3 and the voltage signal transmitted to the common electrode of the second side A2 are consistent, thereby avoiding the problem of lateral crosstalk caused by the excessively large coupling capacitance affecting the display effect.

[0124] It should be noted that, referring to Figure 2, the number of second-type voltage divider lines 420 located on the second side A2 and the number of second-type voltage divider lines 420 located on the third side A3 in Figure 2 are not limited, and the specific number depends on the actual needs.

[0125] In some embodiments, referring to Figures 1A and 2, the first compensation signal line 31 and the second compensation signal line 32 are made of the same material and are disposed in the same layer.

[0126] For example, when the first compensation signal line 31 and the second compensation signal line 32 exist simultaneously, since the first compensation signal line 31 and the second compensation signal line 32 have the same function and are both electrically connected to the voltage divider line 41, the same layer and the same material can simplify the structure and the manufacturing process.

[0127] The following describes the film structure in the array substrate.

[0128] In some embodiments, as shown in Figures 6A, 6B, and 6C, the array substrate 10 includes a gate conductive layer 102, a source / drain conductive layer 103, and a transparent conductive layer 104. The gate conductive layer 102 is disposed on the substrate 1 and includes a compensation signal line 3. The source / drain conductive layer 103 is disposed on the side of the gate conductive layer 102 away from the substrate 1. The transparent conductive layer 104 is disposed on the side of the source / drain conductive layer 103 away from the substrate 1, and the transfer electrode 2 is located on the transparent conductive layer 104. The compensation resistor 4 is disposed on at least one of the gate conductive layer 102, the source / drain conductive layer 103, or the transparent conductive layer 104.

[0129] It should be noted that the gate conductive layer 102, the source / drain conductive layer 103, or the transparent conductive layer 104 are all conductive layers. Therefore, the compensation resistor 4 is disposed in at least one of the gate conductive layer 102, the source / drain conductive layer 103, or the transparent conductive layer 104, which can improve the space utilization of the array substrate 10 and the transmission efficiency of the compensation resistor 4.

[0130] The aforementioned conductive layers can be used to form multiple thin-film transistors, and the thin-film transistors may include a gate located in the gate conductive layer 102 and a source and drain located in the source and drain conductive layers 103.

[0131] For example, the substrate 1 has a supporting and protective function and can be a rigid substrate, such as a glass substrate or a silicon substrate; it can also be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a PI (Polyimide) substrate, etc., which is not limited here.

[0132] For example, referring to FIG6B, the array substrate 10 further includes a first insulating layer 105 disposed between the gate conductive layer 102 and the source / drain conductive layer 103, and a second insulating layer 106 disposed between the source / drain conductive layer 103 and the transparent conductive layer 104.

[0133] For example, the materials of the first insulating layer 105 and the second insulating layer 106 can be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. The first insulating layer 105 and the second insulating layer 106 can be single-layer, double-layer or multi-layer structures to achieve the effect of blocking water and oxygen and blocking alkaline ions.

[0134] For example, the transparent conductive layer 104 can be made of indium tin oxide (ITO).

[0135] In some embodiments, as shown in FIG6A, the compensation signal line 3 and the compensation resistor 4 are located on the same layer and are connected to each other.

[0136] For example, when the compensation resistor 4 is disposed on the gate conductive layer 102, the compensation signal line 3 and the compensation resistor 4 are located on the same layer and are connected. The connection can be that the compensation signal line 3 and the compensation resistor 4 are in contact with each other. The compensation resistor 4 passes through the first insulating layer 105 and the second insulating layer 106 and is electrically connected to the transfer electrode 2 located on the transparent conductive layer 104.

[0137] The fact that the compensation signal line 3 and the compensation resistor 4 are located in the same layer simplifies the fabrication process, and the compensation signal line 3 and the compensation resistor 4 can be fabricated simultaneously using a sampling patterning process.

[0138] In some embodiments, the compensation signal line 3 and the compensation resistor 4 are located on different layers. For example, referring to FIG6B, the compensation resistor 4 is located on the source-drain conductive layer 103. In this case, the compensation resistor 4 passes through the first insulating layer 105 and is electrically connected to the compensation signal line 3, while the transfer electrode 2 passes through the second insulating layer 106 and is electrically connected to the compensation resistor 4. As another example, referring to FIG6C, the compensation resistor 4 is located on the transparent conductive layer 104. In this case, the compensation resistor 4 passes through the first insulating layer 105 and the second insulating layer 106 and is electrically connected to the compensation signal line 3, while the compensation resistor 4 and the transfer electrode 2 are connected on the transparent conductive layer 104.

[0139] In some embodiments, as shown in Figures 7A, 7B, 7C and 7D, the compensation resistor 4 is a voltage divider line 41, which is arranged in an arc shape.

[0140] For example, referring to Figures 7A, 7B, 7C and 7D, the compensation resistor 4 and the compensation signal line 3 shown in Figures 7A, 7B, 7C and 7D are located on the same layer, for example, both are disposed in the gate conductive layer 102. When the compensation resistor 4 is a voltage divider line 41, the voltage divider line 41 includes a plurality of array units 411 connected in sequence and arranged in an array. Each array unit includes a first part 41a and a second part 41b that are parallel to each other and arranged opposite to each other, and a third part 41c connected between the first part 41a and the second part 41b. The first direction X and the second direction Y are perpendicular to each other.

[0141] It should be noted that the above sequential connection refers to the array unit 411 that overlaps with the transfer electrode 2 being the first type of array unit 411a, and the first type of array units being sequentially connected. The array unit 411 that does not overlap with the transfer electrode 2 is the second type of array unit 411b, and the second type of array units are sequentially connected. The first array unit of the second type of array unit is connected to the compensation signal line 3, and the last array unit in the second type of array unit is sequentially connected to the first type of array unit.

[0142] Referring to Figure 7A, the array unit 411 in Figure 7A includes a first array unit, which includes a first part 41a and a second part 41b extending along a first direction X, and a third part 41c extending along a second direction Y. The first array units are arranged in five rows, and each row has a plurality of first array units 411. The first array units 411 in adjacent rows are arranged in a mirror symmetrical manner. At least a portion of the first array units 411 in each row overlaps with the adapter electrode 2 to form an electrical connection with the adapter electrode 2. The dimension of each first array unit in the first direction X is D1.

[0143] It should be noted that, as shown in Figure 7A, both the first type of array unit 411a and the second type of array unit 411b are provided with a connecting portion 41d. The connecting portion 41d connects to two adjacent rows of the first type of array unit 411a, and also connects to two adjacent rows of the second type of array unit 411b. For example, referring to Figure 7A, the connecting portion 41d is located between the end position of the second type of array unit 411a in the previous row and the start position of the first type of array unit 411b in the next row, and extends along the first direction X to connect two adjacent rows of the first type of array unit 411b, thereby realizing signal transmission within the compensation resistor 4.

[0144] Referring again to Figure 7A, when the compensation resistor 4 is a voltage divider line 41, the line width of the voltage divider line 41 can be the same as the line width L1 of the compensation signal line 3, or it can be smaller than the line width L2 of the compensation signal line 3. This setting can save wiring space, increase the compensation effect of the compensation resistor 4, and also facilitate a narrow bezel. This line width design can be applied to other embodiments in this disclosure.

[0145] Referring to Figure 7B, the array unit 411 in Figure 7B is a second array unit, including a first part 41a and a second part 41b extending along the first direction X, and a third part 41c extending along the second direction Y. The second array units are arranged in a row, and the dimension D2 of the second array unit 411 shown in Figure 7B in the first direction X is greater than the dimension D1 of the first array unit shown in Figure 7A in the first direction X.

[0146] It should be noted that, as shown in Figure 7B, the compensation signal line 3 in Figure 7B includes multiple rows of compensation units 301 arranged along the first direction X. The compensation unit 301 includes a first compensation unit 301a and a second compensation unit 301b. The second compensation unit 301b is connected between two first compensation units 301a, and the size of the first compensation unit 301a in the second direction Y is larger than the size of the second compensation unit 301b in the second direction Y. As shown in Figure 7B, in order to save wiring space, the compensation resistor 4 is set between the first compensation unit 301a and the second compensation unit 301b, and the compensation resistor 4 is electrically connected to the second compensation unit 301b. According to Figure 7B, two adjacent rows of second compensation units 301 are connected in the first direction X, and the size D2' of two adjacent rows of compensation units 301 in the first direction X is smaller than the size D2 of the second array unit 411 in the first direction X shown in Figure 7B. This setting can increase the wiring range of the compensation resistor 4.

[0147] Referring to Figure 7A, the size D1' of each row of the second compensation unit 301b in the first direction X is such that the ratio of the size D1 of the first array unit in the first direction X to the size D1' of the second compensation unit 301b in the first direction X ranges from 0.8 to 1.3. This setting can make the wiring more neat and reduce the manufacturing difficulty.

[0148] Referring to Figure 7C, the array unit 411 in Figure 7C is a third array unit, including a first part 41a and a second part 41b extending along the second direction Y, and a third part 41c extending along the first direction X. The third array units are arranged in three columns, and each column is provided with multiple third array units, wherein adjacent columns of third array units are arranged in a mirror symmetrical manner. The dimension of each column of third array units in the second direction Y is D3. The third array unit 411 located on the far right in Figure 7C is the third column of third array units 411. The third column of third array units 411 overlaps with the transfer electrode 2 to form an electrical connection with the transfer electrode 2.

[0149] Referring to Figure 7D, the array unit 411 in Figure 7D is the fourth array unit, including a first part 41a and a second part 41b extending along the second direction Y, and a third part 41c extending along the first direction X. The fourth array units are arranged in two columns. The array units 411 shown in Figure 7D, from left to right, are the first column array unit and the second column array unit, wherein the second column of fourth array units 411 overlaps with the transition electrode 2. Exemplarily, the dimension D4 of the second column of fourth array units 411 in the second direction Y is the same as the dimension D3 of the third column of third array units 411 in the second direction Y.

[0150] As shown in Figures 7E, 7F, 7G, and 7H, these figures illustrate the wiring structure diagrams of the compensation resistor 4 in Figure 1A connected at different locations. Specifically, the compensation resistor 4 shown in Figure 7E corresponds to the resistance value R4 in Figure 1A; the compensation resistor 4 shown in Figure 7F corresponds to the resistance value R3 in Figure 1A; the compensation resistor 4 shown in Figure 7G corresponds to the resistance value R2 in Figure 1A; and the compensation resistor 4 shown in Figure 7H corresponds to the resistance value R1 in Figure 1A. Based on the aforementioned description, the resistance value relationship is R4 > R3 > R2 > R1. Referring to Figures 7E, 7F, 7G, and 7H... In Figures 7F, 7G, and 7H, the number of corresponding second compensation units 301b connected to the compensation signal line 3 connected to the corresponding compensation resistor 4 varies to ensure sufficient wiring space. As can be seen from the figures, the larger the resistance value of the compensation resistor 4, the more second compensation units 301b are required. Specifically, the number of second compensation units 301b in Figure 7E is greater than that in Figure 7F, greater than that in Figure 7G, and greater than that in Figure 7H. For example, there are nine second compensation units 301b in Figure 7E, eight in Figure 7F, seven in Figure 7G, and five in Figure 7H. This is only one example; the specific number of second compensation units 301b is determined based on the resistance value of the compensation resistor 4 and the required winding space.

[0151] It should be noted that the compensation resistor 4 shown in Figures 7E, 7F, 7G and 7H is located on the same layer as the compensation signal line 3, for example, they are all set in the gate conductive layer. When the compensation resistor 4 is a voltage divider line 41, the transfer electrode 2 achieves electrical connection with the compensation resistor 4 located in the gate conductive layer through the transfer via K.

[0152] Referring to Figure 7I, which is a connection structure diagram of the compensation resistor 4 and the transfer electrode 2, a connecting block 1021 is provided in the gate conductive layer where the compensation resistor 4 is located. The connecting block 1021 overlaps with the array unit 411. The connecting block 1021 corresponds to the position of the via K, and the orthographic projection of the via K onto the substrate is located within the orthographic projection of the connecting block 1021 onto the substrate. The connecting block 1021 is used to increase the contact area between the transfer electrode 2 and the compensation resistor 4, ensuring that they can achieve sufficient electrical connection to improve signal transmission efficiency. It should be noted that the connecting block 1021 can be fabricated simultaneously with the compensation resistor 4, thus improving signal transmission efficiency without requiring additional processes and saving costs. The setting of the connecting block 1021 here can be applied to other embodiments of this disclosure.

[0153] In some embodiments, as shown in Figures 8 and 11, the array substrate 10 further includes a semiconductor layer 107 disposed between the first insulating layer 105 and the source / drain conductive layer 103. This semiconductor layer 107 is used to form the active layer of a transistor. Therefore, a compensation resistor 4 can be formed simultaneously during the fabrication of this semiconductor layer. In other words, the structure of the compensation resistor 4 can be reused from the semiconductor layer, eliminating the need for an additional compensation resistor 4, thus reducing costs. Furthermore, the size of the compensation resistor 4 can be adjusted by controlling the width-to-length ratio of the semiconductor pattern. Referring to Figure 8, the semiconductor layer and the source / drain conductive layer connecting both ends of the semiconductor layer serve as the compensation resistor. To prevent the influence of light on the semiconductor layer, a gate conductive layer 102 is used as a light-shielding layer to cover the semiconductor layer.

[0154] As shown in FIG9, some embodiments of this disclosure also provide a display panel 100, which includes an array substrate 10 provided in any of the above embodiments and a counter substrate 20 disposed opposite to the array substrate 10; and a liquid crystal layer 30 located between the array substrate 10 and the counter substrate 20. Therefore, the display panel 100 provided by the present invention has all the beneficial effects of the array substrate 10 provided in any of the above embodiments, which will not be elaborated here.

[0155] In some embodiments, referring to FIG9, the transparent conductive layer 104 of the display panel 100 further includes a common electrode 1041, which is electrically connected to the adapter electrode 2.

[0156] It is understood that, since the transfer electrode 2 is located on the transparent conductive layer 104, and the transparent conductive layer 104 includes the common electrode 1041 of the display area, the transfer electrode 2 and the common electrode 1041 are disposed on the same layer. Optionally, the transfer electrode 2 and the common electrode 1041 can be directly contacted or indirectly electrically connected; or the transparent conductive layer 104 and the pixel electrode of the display area are disposed on the same layer. A pixel capacitor can be formed between the pixel electrode and the common electrode 1041, and both the pixel electrode and the common electrode are located on the array substrate 10 of the display panel 100.

[0157] For example, the liquid crystal layer 30 contains multiple liquid crystal molecules. Since the display panel 100 itself cannot emit light, a backlight is needed to pass through the liquid crystal layer in the display panel. Because liquid crystal molecules have optical rotation characteristics for polarized light, a specific molecular arrangement direction can change the polarization direction of the polarized light. When the arrangement direction of the liquid crystal molecules is rotated under the control of the electric field generated between the pixel electrode and the common electrode, the polarization direction of the light passing through the liquid crystal molecules also changes. This allows the light to be controlled to pass through the liquid crystal layer and then emitted. In other words, by deflecting multiple liquid crystal molecules, the light is emitted from the display panel, which enables the display panel 100 to display the image to be displayed. The image to be displayed is the image that the display panel 100 needs to present, such as a black, white, gray, or color image.

[0158] As shown in FIG10, some embodiments of this disclosure also provide another display panel 100, the display panel 100 including the array substrate 10 provided in any of the above embodiments and the opposing substrate 20 disposed opposite to the array substrate 10; and the sealing adhesive 40 connected between the array substrate 10 and the opposing substrate 20, the sealing adhesive 40 being located in the border area BB.

[0159] For example, the array substrate 10 and the opposing substrate 20 also include a liquid crystal layer 30, which includes liquid crystal material located in the display area AA, and the sealant 40 of the display panel 100 surrounds the liquid crystal material.

[0160] For example, the display panel 100 also includes spacers, which can be disposed on the opposing substrate 20 or on the array substrate 10. A liquid crystal layer is disposed between the opposing substrate and the array substrate, and a black matrix layer 21 can be disposed on the opposing substrate 20.

[0161] For example, the material of the black matrix layer 21 includes, but is not limited to, one or more of BM (Black matrix) material, RGB Resin material, or BPS (4,4'-dihydroxydiphenyl sulfone) material. Among them, the material of BM can be Cr (chromium), CrOx (chromium oxide), or Black Resin.

[0162] For example, referring to FIG11, a common electrode layer 108 is provided on the side of the opposing substrate 20 near the array substrate 10. The common electrode layer 108 includes a common electrode 1041, which is electrically connected to the transfer electrode 2 through conductive particles Q, such as conductive particles in the sealant 40.

[0163] For example, a pixel capacitor can be formed between the pixel electrode and the common electrode 1041, and the pixel electrodes are all located on the array substrate 10 of the display panel 100, while the common electrode 1041 is located on the opposing substrate 20.

[0164] This invention applies to both planar electric field mode and vertical electric field mode. When used in planar electric field mode, the compensation resistor is electrically connected to the common electrode of the display panel's display area via a transfer electrode. When used in vertical electric field mode, the compensation resistor is electrically connected to the common electrode on the opposite side of the substrate via a transfer electrode and conductive particles. Additionally, when the display area has storage lines that also provide common signals, the compensation resistor and the storage lines in the display area can also be electrically connected via a transfer electrode.

[0165] For example, the material of the pixel electrode may include a transparent conductive material. For instance, the material of the pixel electrode may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0166] The material of the common electrode can also include transparent conductive materials. For example, the material of the common electrode can include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0167] The materials used for the aforementioned pixel electrodes and common electrodes are transparent conductive materials such as indium tin oxide (ITO), which can reduce the impact on light emission.

[0168] An electric field can be generated within the display panel 100, causing the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect under the influence of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 within the display panel 100, the degree of deflection of the liquid crystal molecules within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted in the area where the liquid crystal molecules are located within the liquid crystal layer 30, thus enabling the display panel 100 to display images.

[0169] For example, the electric field that drives the liquid crystal molecules in the liquid crystal layer 30 within the display panel 100 to deflect can be generated when a voltage is applied to the pixel electrode and the common electrode within the sub-pixel.

[0170] In some embodiments, the positional relationship between the pixel electrode and the common electrode included in the display panel 100 may be that the pixel electrode and the common electrode are located on the same layer, or that the pixel electrode and the common electrode are located on the array substrate 10 of the display panel at the same time, or that, as shown in FIG11, the pixel electrode is located on the array substrate 10 of the display panel 100 and the common electrode is located on the opposing substrate 20 of the display panel 100.

[0171] Some embodiments of this disclosure provide a display device 1000, as shown in FIG12, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0172] This disclosure does not impose any special restrictions on the specific form of the display device described above. The display device 1000 adopts the display panel 100 provided in the above embodiments. Therefore, the display device 1000 provided in this disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated here.

[0173] For example, as shown in FIG12, the display device 1000 is, for example, a rectangle or a rounded rectangle.

[0174] For example, the display device 1000 may be a thin film transistor liquid crystal display (TFT-LCD) device.

[0175] In some embodiments, as shown in FIG13, the display device 1000 includes a common voltage generation circuit 200 coupled to the bonding region CC, and the common voltage generation circuit 200 is configured to provide a common voltage for the compensation signal line 3.

[0176] For example, the common voltage generation circuit 200 can sample the common voltage at different locations through the sampling signal line 50, process the obtained sampling signal to generate the common voltage that needs to be compensated, so as to ensure the consistency of the common voltage received by the common electrode at different locations, thereby improving the picture quality of the display device 1000.

[0177] In some embodiments, referring to FIG13, the sampling signal line 50 is disposed in the frame area. One end of the sampling signal line 50 is coupled to the bonding area CC, and the other end is connected to the conductive particles Q of the sealing adhesive 40. As can be seen from the above, referring to FIG11, the conductive particles Q and the common electrode 1041 are electrically connected through the adapter electrode 2. That is to say, by sampling the conductive particles Q near the common electrode 1041, the voltage change of the common electrode 1041 can be detected.

[0178] In some embodiments, please continue to refer to FIG1A and FIG2. The display device 1000 includes a plurality of chip-on-film (COF) films 300. The plurality of COF films 300 are bonded to the bonding area CC of the array substrate 10. The bonding area includes a plurality of bonding sub-areas C1. Each COF film 300 is bonded to one bonding sub-area C1 and is coupled to the compensation signal line 3. The common voltage generation circuit 200 is electrically connected to the display panel 100 through the plurality of COF films 300.

[0179] For example, the flip-chip thin film 300 is coupled to the compensation signal line 3. The flip-chip thin film 300 is configured to receive the common voltage signal generated by the common voltage generation circuit 200, transmit it to the compensation signal line 3, and then perform compensation through the compensation signal line 3.

[0180] In some embodiments, referring to FIG1A, when the compensation signal line 3 includes the first compensation signal line 31, the display device 1000 further includes an operational amplifier 400, which is coupled to the common voltage generation circuit 200 and the first compensation signal line 31. The operational amplifier 400 is configured to amplify the common voltage signal from the common voltage generation circuit 200 and transmit it to the first compensation signal line 31.

[0181] It should be noted that the operational amplifier 400 is configured to receive a common voltage, and according to the actual compensation needs, combined with the signal loss problem transmitted by the first compensation signal line 31, an appropriate amplification factor is selected to meet the normal transmission of the signal, ensure the consistency of the common voltage received by the common electrode, and thus improve the picture quality of the display device 1000.

[0182] It should be noted that, referring to Figures 1A and 2, the signal received by the first compensation signal line 31 is a signal amplified by the operational amplifier 400. This signal is a pulse signal, therefore, there will be signal attenuation during the transmission of the first compensation signal line 31. Under the compensation effect of the compensation resistor, the uniformity of the voltage of the common electrode at different positions is ensured, thereby improving the display effect. The signal received by the second compensation signal line 32 is a common voltage signal, which has not undergone amplification. That is, the signal received by the second compensation signal line 32 is a constant voltage signal. Therefore, the loss of this signal during transmission is not considered in this application.

[0183] In some embodiments, referring to Figures 1A and 2, the display device 1000 includes a circuit board 500, in which a common voltage generation circuit 200 is disposed. As shown in Figure 2, the circuit board 500 is electrically connected to a flip-chip film 300, and the flip-chip film 300 is coupled to a compensation signal line 3. The common voltage generation circuit 200 transmits a common voltage signal to the flip-chip film 300 through the circuit board 500, and then transmits it to the compensation signal line 3 through the flip-chip film 300.

[0184] As shown in Figure 1A, when the compensation signal line 3 includes the first compensation signal line 31, the display device 1000 also includes an operational amplifier 400. The operational amplifier 400 is disposed on the circuit board 500 and is coupled to the common voltage generation circuit 200. The operational amplifier 400 amplifies the common voltage signal from the common voltage generation circuit 200 and transmits the common voltage signal to the flip-chip film 300 through the circuit board 500, and then transmits it to the first compensation signal line 31 through the flip-chip film 300.

[0185] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0186] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate having a display area, a border area surrounding the display area, and a bonding area located on a first side of the border area away from the display area; wherein, The array substrate includes: Substrate; A transfer electrode is disposed on the substrate and located in the border area; A compensation signal line extends from the bonding area to the frame area and is arranged circumferentially along the adapter electrode; Multiple compensation resistors are spaced apart in the frame area, and one end of each compensation resistor is electrically connected to the compensation signal line, and the other end is electrically connected to the adapter electrode. Among them, at least two of the compensation resistors have different resistance values.

2. The array substrate according to claim 1, wherein, The compensation signal line includes a first compensation signal line, which extends to one end of the frame area and is electrically connected to the adapter electrode.

3. The array substrate according to claim 2, wherein, The display area includes a second side opposite to the first side, and a third side located between the first side and the second side; The plurality of compensation resistors are multiple voltage divider lines, which include multiple first-type voltage divider lines located on the second side and / or the third side.

4. The array substrate according to claim 3, wherein, The plurality of first-type voltage divider lines are located on the second side, and the resistance of the first-type voltage divider lines closer to the third side is greater than the resistance of the first-type voltage divider lines farther away from the third side.

5. The array substrate according to claim 3, wherein, The plurality of first-type voltage divider lines are located on the third side, and the resistance of the first-type voltage divider line closer to the bonding area is greater than the resistance of the first-type voltage divider line farther away from the bonding area.

6. The array substrate according to claim 3, wherein, The plurality of first-type voltage divider lines are located on the second side and the third side, and the resistance of the first-type voltage divider line located on the second side is less than the resistance of the first-type voltage divider line located on the third side.

7. The array substrate according to any one of claims 3 to 6, wherein, The first compensation signal line is electrically connected to multiple first-type voltage divider lines, and the resistance of the first-type voltage divider lines decreases as the extension length of the first compensation signal line increases.

8. The array substrate according to claim 7, wherein, The array substrate includes multiple first compensation signal lines. At least one first compensation signal line is provided on each of the opposite sides of the frame area. Each first compensation signal line is connected to at least one first type voltage divider line, and the voltage signals received by the first compensation signal lines located on opposite sides of the frame area have the same amplification factor.

9. The array substrate according to claim 8, wherein, Also includes: A symmetry axis extends along a first direction, which is parallel to the array substrate and perpendicular to the extension direction of the bonding region; The connection points of the first type of voltage divider line located on both sides of the frame area and the adapter electrode are symmetrically arranged about the axis of symmetry.

10. The array substrate according to claim 9, wherein, The resistance values ​​of the first type of voltage divider lines, which are symmetrically arranged about the axis of symmetry, are the same.

11. The array substrate according to any one of claims 1 to 10, wherein, The compensation signal line includes a second compensation signal line, which extends from one side of the binding area along its extension direction to the border area and then connects to the other side of the binding area along its extension direction.

12. The array substrate according to claim 11, wherein, The display area includes a second side opposite to the first side, and a third side located between the first side and the second side; The plurality of compensation resistors are multiple voltage divider lines, including multiple second-type voltage divider lines, which are located on the second side and / or on the third side.

13. The array substrate according to claim 12, wherein, The plurality of second-type voltage divider lines are located on the second side, and the resistance of the second-type voltage divider lines closer to the third side is less than the resistance of the second-type voltage divider lines farther away from the third side.

14. The array substrate according to claim 12, wherein, The plurality of second-type voltage divider lines are located on the third side, and the resistance of the second-type voltage divider line closer to the bonding area is greater than the resistance of the second-type voltage divider line farther away from the bonding area.

15. The array substrate according to claim 12, wherein, The plurality of second-type voltage divider lines are located on the second side and the third side, and the resistance of the second-type voltage divider line located on the third side is greater than the resistance of the second-type voltage divider line located on the second side.

16. The array substrate according to any one of claims 11 to 15, wherein, The first compensation signal line and the second compensation signal line are made of the same material and are arranged in the same layer.

17. The array substrate according to any one of claims 1 to 16, wherein, include: A gate conductive layer is disposed on the substrate, and the gate conductive layer includes a compensation signal line; A source / drain conductive layer is disposed on the side of the gate conductive layer away from the substrate; A transparent conductive layer is disposed on the side of the source / drain conductive layer away from the substrate, and the transition electrode is located on the transparent conductive layer; The compensation resistor is disposed in at least one of the gate conductive layer, the source / drain conductive layer, or the transparent conductive layer.

18. The array substrate according to claim 17, wherein, The compensation signal line and the compensation resistor are located on the same layer, and the compensation signal line is connected to the compensation resistor.

19. The array substrate according to claim 18, wherein, The compensation resistor is a voltage divider line, and the voltage divider line is arranged in a bow shape.

20. The array substrate according to any one of claims 17 to 19, wherein, The transparent conductive layer also includes a common electrode, which is electrically connected to the transfer electrode.

21. A display panel, comprising: The array substrate as described in any one of claims 1 to 20; The opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the opposing substrate.

22. A display panel, comprising: The array substrate as described in any one of claims 1 to 19; The opposing substrate is disposed opposite to the array substrate; A sealing adhesive is used to connect the array substrate and the opposing substrate, and is located in the border area; The opposing substrate has a common electrode layer on the side closest to the array substrate; the common electrode layer includes a common electrode, which is electrically connected to the transfer electrode through conductive particles.

23. A display device, comprising: The display panel as claimed in claim 21, or the display panel as claimed in claim 22; and, A common voltage generation circuit, coupled to the bonding region, is configured to provide a common voltage for the compensation signal line.

24. The display device according to claim 23, wherein, Also includes: Multiple flip-chip films are bonded to a bonding area on an array substrate. The bonding area includes multiple bonding sub-regions. Each flip-chip film is bonded to one of the bonding sub-regions and is coupled to the compensation signal line. The common voltage generation circuit is electrically connected to the display panel through the multiple flip-chip films.

25. The display device according to claim 23 or 24, wherein, In the case where the compensation signal line includes a first compensation signal line, the display device further includes an operational amplifier coupled to the common voltage generation circuit and the first compensation signal line. The operational amplifier is configured to amplify the common voltage signal from the common voltage generation circuit and transmit it to the first compensation signal line.

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