Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a base substrate (001), and a plurality of sub-pixels (10) and a plurality of gate lines (130) located on the base substrate (001). The plurality of sub-pixels (10) are arranged in an array in a first direction (X) and a second direction (Y). Each sub-pixel (10) comprises a pixel electrode (110) and a common electrode (120). Each gate line (130) extends in the first direction (X), and two gate lines (130) are provided between two adjacent pixel electrodes (110) arranged in the second direction (Y). Each sub-pixel (10) further comprises a thin film transistor (140). The thin film transistor (140) comprises a first electrode (141), a gate (143), and a second electrode (142). The first electrode (141) is electrically connected to the pixel electrode (110) by means of a via (N). The common electrode (120) of each sub-pixel (10) comprises a recessed portion (150), and the recessed portion (150) is bent toward a direction away from the via (N) corresponding to the sub-pixel (10). The recessed portions (150) provide clearance for the vias, reducing the risk of poor contact of the common electrodes (120) at the vias (N), further enabling a more compact layout arrangement and thus helping to increase the pixel aperture ratio.

Description

Array substrate and display device Technical Field

[0001] At least one embodiment of this disclosure relates to an array substrate and a display device. Background Technology

[0002] In the fiercely competitive electronics market, low power consumption and high performance have become important trends in product differentiation. Continuously optimizing product structure to improve the performance of thin film transistor liquid crystal displays (TFT LCDs) has become one of the important means to enhance market competitiveness. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an array substrate, which includes a substrate, a plurality of sub-pixels and a plurality of gate lines located on the substrate. The plurality of sub-pixels are arranged in an array in a first direction and a second direction. Each sub-pixel includes a pixel electrode and a common electrode. The first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction. Each gate line extends along the first direction, and two gate lines are disposed between two adjacent pixel electrodes arranged along the second direction. Each sub-pixel also includes a thin-film transistor, each thin-film transistor including a first electrode, a gate, and a second electrode. The first electrode is electrically connected to the pixel electrode through a via. The common electrode of the sub-pixel includes a recessed portion, and the recessed portion is bent toward the via corresponding to the sub-pixel.

[0004] For example, according to at least one embodiment of the array substrate provided in this disclosure, the common electrode of the sub-pixel includes an edge adjacent to the thin-film transistor of the sub-pixel, the edge including a first portion and a second portion, and a junction connecting the first portion and the second portion, both the first portion and the second portion extending along the first direction, the second portion being further away from the via corresponding to the sub-pixel than the first portion.

[0005] For example, according to at least one embodiment of the array substrate provided in this disclosure, the common electrode of the sub-pixel includes a plurality of slits spaced apart along the first direction, each slit including a corner, and the plurality of corners of the common electrode of a plurality of sub-pixels in the same sub-pixel row are substantially located on the same straight line extending along the first direction.

[0006] For example, in an array substrate provided according to at least one embodiment of the present disclosure, each of the slits in the common electrode of the sub-pixel includes an end near a gate line electrically connected to a thin-film transistor of the sub-pixel, and in the first direction, the plurality of ends in the common electrode of the sub-pixel are not flush.

[0007] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the minimum distance between the ends of the plurality of slits of the common electrode of the sub-pixel and the edge is substantially the same.

[0008] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the plurality of slits of the common electrode of the sub-pixel includes a plurality of first slits and a plurality of second slits. In the second direction, the plurality of first slits are located on one side of the first portion, and the plurality of second slits are located on the same side of the second portion. The portions of each second slit located on both sides of the corner are of different sizes.

[0009] For example, according to at least one embodiment of the array substrate provided in this disclosure, the common electrode of the sub-pixel includes a connecting portion and a plurality of strip portions arranged in the first direction, with a slit between adjacent strip portions, the plurality of strip portions of the sub-pixel are connected to each other and connected to the plurality of strip portions of adjacent sub-pixels through the connecting portion, each strip portion includes a first protrusion, the connecting portion includes a second protrusion, the first protrusion and the second protrusion have the same protrusion direction, and the surface curvature of the first protrusion is smaller than the surface curvature of the second protrusion.

[0010] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of sub-pixels are arranged into a plurality of repeating units, each repeating unit including 2M sub-pixel rows arranged along the second direction and 2N sub-pixel columns arranged along the first direction, where M and N are both positive integers. The array substrate also includes a plurality of data lines arranged along the first direction. Sub-pixels in different sub-pixel columns are electrically connected to different data lines, sub-pixels in the same sub-pixel column are electrically connected to the same data line, and the data line electrically connected to the i-th sub-pixel in the same sub-pixel row is electrically connected to the data line electrically connected to the (N+i)-th sub-pixel, where i is a positive integer less than or equal to N.

[0011] For example, in the array substrate provided according to at least one embodiment of the present disclosure, in the same sub-pixel row, adjacent sub-pixels in the p-Nth sub-pixels are electrically connected to different gate lines, and adjacent sub-pixels in the j-2Nth sub-pixels are electrically connected to different gate lines, where p is a positive integer less than N and j is a positive integer greater than N and less than 2N.

[0012] For example, in an array substrate provided according to at least one embodiment of the present disclosure, in the same sub-pixel row, the odd-numbered sub-pixel of the p-N sub-pixels and the even-numbered sub-pixels of the j-2N sub-pixels are electrically connected to the same gate line, and the even-numbered sub-pixels of the p-N sub-pixels and the odd-numbered sub-pixels of the j-2N sub-pixels are electrically connected to another gate line.

[0013] For example, according to at least one embodiment of the array substrate provided in this disclosure, the plurality of gate lines include a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, and a plurality of fourth gate lines. Each of the sub-pixel rows includes a first side and a second side opposite to each other in the second direction. A first gate line is disposed on the first side of the k-th to M-th sub-pixel rows, and a second gate line is disposed on the second side of the k-th to M-th sub-pixel rows. In the k-th to M-th sub-pixel rows, the odd-numbered sub-pixel among the p-th to N-th sub-pixels and the even-numbered sub-pixels among the j-th to 2N-th sub-pixels are electrically connected to the first gate line. The even-numbered sub-pixels among the p-th to N-th sub-pixels are... The odd-numbered sub-pixel among the j-2N sub-pixels is electrically connected to the second gate line, where k is a positive integer less than M. A third gate line is provided on the first side of the s-2M sub-pixel rows, and a fourth gate line is provided on the second side of the s-2M sub-pixel rows. In the s-2M sub-pixel rows, the even-numbered sub-pixel among the p-N sub-pixels and the odd-numbered sub-pixel among the j-2N sub-pixels are electrically connected to the third gate line, and the odd-numbered sub-pixel among the p-N sub-pixels and the even-numbered sub-pixel among the j-2N sub-pixels are electrically connected to the fourth gate line, where s is a positive integer greater than M and less than 2M.

[0014] For example, according to at least one embodiment of the present disclosure, the array substrate provided includes multiple sub-pixels located in the same sub-pixel row, which include multiple sub-pixel groups. Each sub-pixel group includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along the first direction. The multiple sub-pixels located in the same sub-pixel column have the same emission color.

[0015] For example, according to at least one embodiment of the present disclosure, the array substrate further includes a plurality of support structures, the plurality of sub-pixels including a fourth sub-pixel, each of the support structures and the gate of the thin-film transistor of the fourth sub-pixel being disposed opposite to each other in the second direction, the plurality of gate lines including a plurality of fifth gate lines, the support structures being electrically connected to the fifth gate lines, and the fifth gate lines being electrically connected to the gate lines of the fourth sub-pixel being located on opposite sides of the pixel electrode of the fourth sub-pixel in the second direction.

[0016] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the gate of the thin-film transistor of the sub-pixel includes at least one first chamfer, and the support structure includes at least one second chamfer, wherein the first chamfer is not greater than the second chamfer.

[0017] For example, in an array substrate provided according to at least one embodiment of the present disclosure, the fourth sub-pixel is configured to emit blue light.

[0018] For example, according to at least one embodiment of the array substrate provided in this disclosure, the gate of the thin-film transistor of the sub-pixel is located on the same layer as the pixel electrode, and the minimum distance between the gate and the pixel electrode is D, where D satisfies: D≤(f1) 2 +d1 2 +f2 2 +d2 2 ) 0.5

[0019] In the formula, f1 represents the process fluctuation value of the gate, d1 represents the alignment deviation of the gate, f2 represents the process fluctuation value of the pixel electrode, and d2 represents the alignment deviation of the pixel electrode.

[0020] At least one embodiment of this disclosure also provides a display device, including an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments, wherein the counter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the array substrate and the counter substrate. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0023] Figure 2 is a partial structural schematic diagram of the gate line layer of the array substrate in Figure 1.

[0024] Figure 3 is a schematic diagram of the stacked gate line layer and pixel electrode layer of the array substrate in Figure 1.

[0025] Figure 4 is a partial structural schematic diagram of the gate lines of the array substrate in Figure 2.

[0026] Figure 5 is a schematic diagram of a display product when a display malfunction occurs.

[0027] Figure 6 is a partial connection diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0028] Figure 7 is a schematic diagram of the layout of the array substrate shown in Figure 6.

[0029] Figure 8 is a partial schematic diagram of the array substrate shown in Figure 7.

[0030] Figure 9 is a partial schematic diagram of the array substrate shown in Figure 8.

[0031] Figures 10 to 15 are process flow diagrams of the array substrate provided in at least one embodiment of the present disclosure.

[0032] Figure 16 is a schematic diagram of the structure of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0035] The features such as "perpendicular," "parallel," "identical," and "straight line" used in the embodiments of this disclosure include features such as "perpendicular," "parallel," "identical," and "straight line" in a strict sense, as well as those that include certain errors, such as "approximately perpendicular," "approximately parallel," "approximately identical," and "approximately straight line." Taking into account measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), these refer to the acceptable deviation range for a specific value as determined by a person skilled in the art. The "center" in the embodiments of this disclosure can include a strictly geometrically centered location and a location approximately centered within a small area surrounding the geometrically centered location.

[0036] At least one embodiment of this disclosure provides an array substrate, which includes a substrate, a plurality of sub-pixels and a plurality of gate lines located on the substrate. The plurality of sub-pixels are arranged in an array in a first direction and a second direction. Each sub-pixel includes a pixel electrode and a common electrode. The first direction and the second direction are both parallel to the substrate, and the first direction intersects the second direction. Each gate line extends along the first direction, and two gate lines are disposed between two adjacent pixel electrodes arranged along the second direction. Each sub-pixel also includes a thin-film transistor, each thin-film transistor including a first electrode, a gate and a second electrode. The first electrode is electrically connected to the pixel electrode through a via. The common electrode of the sub-pixel includes a recessed portion, and the recessed portion is bent toward the via corresponding to the sub-pixel.

[0037] In the array substrate provided by the embodiments of this disclosure, the common electrode of the sub-pixel includes a recessed portion, and the recessed portion is bent toward the via corresponding to the sub-pixel. This can reduce the risk of poor contact of the common electrode at the via, so as to enable the array substrate to have a good and stable display effect. At the same time, it can also make the layout more compact, which is beneficial to increase the pixel aperture ratio.

[0038] At least one embodiment of this disclosure also provides a display device, which includes an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments, wherein the counter substrate is disposed opposite to the array substrate, and the liquid crystal layer is located between the array substrate and the counter substrate.

[0039] The array substrate and display device provided in the embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings, so that the corresponding technical solutions can be clearer and easier to understand.

[0040] Figure 1 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0041] As shown in Figure 1, the array substrate includes a substrate 001 and a plurality of sub-pixels 10 located on the substrate 001. The plurality of sub-pixels 10 are arranged in an array in a first direction X and a second direction Y, and each sub-pixel 10 includes a pixel electrode 110 and a common electrode 120. For example, the common electrode 120 is configured to form an electric field with the pixel electrode 110. For example, a liquid crystal layer (not shown in the figure) may be disposed on one side of the array substrate, and the electric field formed between the common electrode 120 and the pixel electrode 110 can drive the liquid crystal molecules in the liquid crystal layer to deflect for display.

[0042] As shown in Figure 1, both the first direction X and the second direction Y are parallel to the substrate 001, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0043] As shown in Figure 1, the array substrate also includes multiple gate lines 130 located on the substrate 001, each gate line 130 extending along a first direction X. It should be noted that the extension direction of the gate line described here refers to the main direction of the gate line; that is, the gate line may also include local structures that do not extend along the first direction X, and the embodiments of this disclosure do not limit this. The multiple gate lines 130 are arranged along a second direction Y, and two gate lines 130 are disposed between two adjacent pixel electrodes 110 arranged along the second direction Y. For example, in the embodiments of this disclosure, a row of sub-pixels 10 arranged along the first direction X is used as a sub-pixel row, and two gate lines 130 are disposed between two adjacent sub-pixel rows. For example, the array substrate provided in the embodiments of this disclosure is a dual-gate-line array substrate, and display devices using dual-gate-line array substrates can reduce costs.

[0044] As shown in Figure 1, the sub-pixel 10 also includes a thin-film transistor 140, each of which includes a first electrode 141, a gate 143, and a second electrode 142. For example, one of the first electrode 141 and the second electrode 142 can be a source, and the other can be a drain. The first electrode 141 is electrically connected to the pixel electrode 110 through a via N. For example, the first electrode 141 of the thin-film transistor 140 is electrically connected to the pixel electrode 110 adjacent to the thin-film transistor 140 in the second direction Y. For example, the structure adjacent to the thin-film transistor 140 (e.g., the pixel electrode 110) refers to the structure that is adjacent to and closest to the thin-film transistor 140.

[0045] As shown in Figures 1 and 15, the common electrode 120 of sub-pixel 10 includes a recess 150, and the recess 150 bends away from the via N corresponding to sub-pixel 10. For example, the via corresponding to the sub-pixel refers to a via used to electrically connect the first electrode in the thin-film transistor of the sub-pixel to the pixel electrode. For example, the recess 150 bending away from the via N corresponding to sub-pixel 10 means that the recess 150 has an extending tendency away from the via N to increase the distance between it and the via N. For example, in the second direction Y, the common electrodes 120 of adjacent sub-pixels 10 are closely arranged, and the common electrode 120 of the sub-pixel can avoid the via N corresponding to sub-pixel 10 through its recess 150.

[0046] This allows for a compact layout, maximizing pixel aperture ratio while minimizing the risk of poor contact at vias in the common electrode, thus enabling the array substrate to achieve a good and stable display effect.

[0047] For example, as shown in FIG1, the common electrode 120 of sub-pixel 10 includes an edge 1500 adjacent to the thin-film transistor 140 of the sub-pixel 10. The edge 1500 includes a first portion 1510 and a second portion 1520, and a junction 1530 connecting the first portion 1510 and the second portion 1520. The first portion 1510 is located on one side of the second electrode 142 of the thin-film transistor 140 of the sub-pixel 10, and the second portion 1520 is located on one side of the via N corresponding to the sub-pixel 10. For example, both the first portion 1510 and the second portion 1520 extend along a first direction X, and in a second direction Y, the second portion 1520 is further away from the via N corresponding to the sub-pixel 10 than the first portion 1510. For example, the extension direction of the junction 1530 intersects the first direction X. For example, the second portion 1520 of the edge 1500 protrudes relative to the first portion 1510 in a direction away from the via N corresponding to the sub-pixel 10.

[0048] Therefore, the second part mentioned above can avoid the vias corresponding to the sub-pixels, thereby reducing the risk of poor contact of the common electrode at the via.

[0049] For example, as shown in FIG1, the common electrode 120 of sub-pixel 10 includes a plurality of slits 121 spaced apart along a first direction X, each slit 121 including a corner 1210. The plurality of corners 1210 of the common electrode 120 of a plurality of sub-pixels in the same sub-pixel row are substantially located on the same straight line extending along the first direction X.

[0050] This configuration allows the multiple slits in the common electrode of the sub-pixel to be arranged as parallel as possible, thus avoiding uneven distribution of the multiple slits in the common electrode of the sub-pixel, which would affect the pixel aperture ratio (for example, cause a decrease in the pixel aperture ratio).

[0051] For example, as shown in FIG1, each slit 121 in the common electrode 120 of the sub-pixel 10 includes an end 1220 near a gate line 130 electrically connected to the thin-film transistor 140 of the sub-pixel 10. In the first direction X, the plurality of ends 1220 in the common electrode 120 of the sub-pixel 10 are not flush.

[0052] For example, as shown in Figure 1, taking the rightmost sub-pixel 10 as an example, the thin-film transistor 140 of this sub-pixel 10 is electrically connected to the gate line 130 on the upper side of the sub-pixel 10, and the multiple ends 1220 of the common electrode 120 of this sub-pixel 10 near the gate line 130 are not flush. For example, a portion of the end 1220 of the common electrode 120 of the sub-pixel 10 is located on one side of the via N corresponding to the sub-pixel 10, and the distance between it and the straight line containing the corners 1210 of the multiple slits 121 in the common electrode 120 is M1. For example, another portion of the end 1220 of the common electrode 120 of the sub-pixel 10 is located on one side of the second electrode 142 of the thin-film transistor 140 of the sub-pixel 10, and the distance between it and the straight line containing the corners 1210 of the multiple slits 121 in the common electrode 120 is M2, and M1 is less than M2.

[0053] Therefore, the multiple ends of the common electrode of the sub-pixel that are close to the gate line electrically connected to the sub-pixel can be flexibly arranged according to the position of the edge of the common electrode, so as to minimize the impact on the pixel aperture ratio while avoiding the via corresponding to the sub-pixel.

[0054] For example, as shown in FIG1, the plurality of slits 121 of the common electrode 120 of the sub-pixel 10 include a plurality of first slits 1211 and a plurality of second slits 1212. In the second direction Y, the plurality of first slits 1211 are located on one side of a first portion 1510 of the edge 1500 of the common electrode 120, and the plurality of second slits 1212 are located on one side of a second portion 1520, and the portions of the second slits 1212 located on both sides of the corner 1210 are of different sizes.

[0055] For example, as shown in Figure 1, in the first direction X, a plurality of first slits 1211 are located on one side of a plurality of second slits 1212. For example, the size of the first slit 1211 in the second direction Y is larger than the size of the second slit 1212 in the second direction Y. For example, the size of the portion of the second slit 1212 located at the corner 1210 near the via N corresponding to the sub-pixel 10 is M1, and the size of the portion of the second slit 1212 located at the corner 1210 away from the via N corresponding to the sub-pixel 10 is M3, and M1 is smaller than M3. For example, the size of the portion of the first slit 1211 located at the corner 1210 near the via N corresponding to the sub-pixel 10 is M2, and the size of the portion of the first slit 1211 located at the corner 1210 away from the via N corresponding to the sub-pixel 10 is M3, and M2 and M3 are substantially equal.

[0056] This allows for flexible setting of the dimensions of multiple slits in the common electrode of the sub-pixel in the first direction, facilitating the avoidance of vias corresponding to the sub-pixel through the common electrode and making the layout more reasonable and orderly.

[0057] For example, as shown in FIG1, the minimum distance between the ends 1220 of the plurality of slits 121 in the common electrode 120 of the sub-pixel 10 and the edge 1500 is substantially the same. For example, in the second direction Y, the distance between the first slit 1211 in the common electrode 120 of the sub-pixel 10 and the first portion 1510 of the edge 1500 is L1, and the distance between the second slit 1212 in the common electrode 120 of the sub-pixel 10 and the second portion 1520 of the edge 1500 is L2, and L1 and L2 are substantially the same.

[0058] This design helps to maintain a uniform distance between the slit in the common electrode and the edge of the common electrode, thus better meeting process requirements.

[0059] For example, as shown in FIG1, the common electrode 120 of sub-pixel 10 includes a connecting portion 1230 and a plurality of strip portions 1240 arranged in a first direction X. A slit 121 is provided between adjacent strip portions 1240. The plurality of strip portions 1240 of sub-pixel 10 are connected to each other and connected to the plurality of strip portions 1240 of adjacent sub-pixels 10 via the connecting portion 1230. The connecting portion 1230 of the common electrode 120 is connected to the plurality of strip portions 1240 of the common electrode 120. For example, in the first direction X, the connecting portion 1230 of the common electrode 120 of sub-pixel 10 is located on one side of its plurality of strip portions 1240, and the size of the connecting portion 1230 is larger than the size of the strip portions 1240.

[0060] For example, as shown in FIG1, the connecting portion 1230 includes a first protrusion 1231, and the strip-shaped portion 1240 includes a second protrusion 1241. The first protrusion 1231 and the second protrusion 1241 protrude in the same direction, and the surface curvature of the first protrusion 1231 is smaller than that of the second protrusion 1241. For example, the edge of the first protrusion 1231 is gentler than the edge of the second protrusion 1241.

[0061] Since the first protrusion 1231 is closer to the edge of the sub-pixel 10 than the second protrusion 1241, reducing the surface curvature of the first protrusion 1231 can mitigate interference with the liquid crystal at that location. If the surface curvature of the first protrusion 1231 is too sharp, it is prone to charge accumulation, thereby disturbing the liquid crystal in that area. Since the second protrusion 1241 is located in the middle of the sub-pixel 10, its disturbance effect on the liquid crystal is smaller. To simplify the manufacturing process, its surface curvature can be greater than that of the first protrusion 1231.

[0062] Figure 2 is a partial structural schematic diagram of the gate line layer of the array substrate in Figure 1; Figure 3 is a schematic diagram of the stacked gate line layer and pixel electrode layer of the array substrate in Figure 1.

[0063] For example, as shown in Figures 1 and 2, the array substrate also includes a plurality of support structures 300, and a plurality of sub-pixels 10 including a fourth sub-pixel 14. The gates 143 of the thin-film transistors 140 of each support structure 300 and the fourth sub-pixel 14 are disposed opposite to each other in the second direction Y.

[0064] For example, as shown in Figures 1 and 2, the array substrate has multiple gate lines 130, including multiple fifth gate lines 135, and the support structure 300 is electrically connected to the fifth gate lines 135. The fifth gate lines 135 and the gate lines 130 electrically connected to the fourth sub-pixel 14 are respectively located on opposite sides of the pixel electrode 110 of the fourth sub-pixel 14 in the second direction Y.

[0065] For example, as shown in Figures 1 and 2, the multiple support structures 300 and multiple gate lines 130 in the array substrate are all located in the gate line layer. For example, the support structure 300 and the fifth gate line 135 are an integral structure, and they can be made of the same material and manufactured using the same process. For example, in the second direction Y, the thin film transistor 140 of the fourth sub-pixel 14 and the support structure 300 are located on opposite sides of the common electrode 120 of the fourth sub-pixel 14. For example, the array substrate may also include multiple spacers (see spacer 310 in Figure 9) and an opposing substrate, with the array substrate and the opposing substrate facing each other and spaced apart, a liquid crystal layer disposed between the array substrate and the opposing substrate, and the spacers located between the array substrate and the opposing substrate for support. For example, the spacers are located on the support structure 300, and the orthographic projection of the spacers on the substrate 001 falls into the orthographic projection of the support structure 300 on the substrate 001. In some cases, the opposing substrate includes an alignment film facing the array substrate. When the opposing substrate slides relative to the array substrate, it may scratch the alignment film and cause liquid crystal alignment disorder, resulting in light leakage. In this case, the support structure can play a role in blocking light.

[0066] For example, as shown in Figures 2 and 3, each sub-pixel 10 in the array substrate is configured to emit red, green, or blue light. For example, the fourth sub-pixel 14 is configured to emit blue light. Since blue light is closer to black than red and green light, this configuration can minimize the impact of the support structure on the transmittance of the array substrate.

[0067] Figure 4 is a partial structural schematic diagram of the gate lines of the array substrate in Figure 2.

[0068] For example, as shown in FIG4, the gate 143 of the thin-film transistor 140 of the sub-pixel 10 includes at least one first chamfer C1, and the support structure 300 includes at least one second chamfer C2, wherein the first chamfer C1 is not larger than the second chamfer C1. In some embodiments, at least one of the first chamfer C1 and the second chamfer C2 may be a rounded corner. For example, the orthographic projection area of ​​the gate 143 on the substrate 001 (see FIG1) is smaller than the orthographic projection area of ​​the support structure 300 on the substrate 001, thereby making the static electricity accumulation of the support structure 300 greater than that of the gate 143.

[0069] This design helps to prevent tip discharge of the support structure, thereby reducing the risk of electrostatic damage to the inside of the array substrate. At the same time, by making the first chamfer of the gate smaller, it is easier to wrap the channel region of the thin-film transistor through the gate, thereby reducing leakage current.

[0070] For example, as shown in Figure 3, the gate 143 of the thin-film transistor 140 of sub-pixel 10 is located on the same layer as the pixel electrode 110, and the minimum distance between the gate 143 and the pixel electrode 110 is D, which satisfies: D≥(f1 2 +d1 2 +f2 2 +d2 2 ) 0.5

[0071] In the formula, f1 represents the process fluctuation value of gate 143, d1 represents the alignment deviation of gate 143, f2 represents the process fluctuation value of pixel electrode 110, and d2 represents the alignment deviation of pixel electrode 110.

[0072] For example, as shown in Figure 3, the process variation value f1 of the gate 143 and the process variation value f2 of the pixel electrode 110 are both 0.5–5 micrometers. For example, the process variation value f1 of the gate 143 and the process variation value f2 of the pixel electrode 110 may be equal or different. For example, the process variation value f1 of the gate 143 may be 0.5–2.5 micrometers, 1.5–3.0 micrometers, 2.0–3.5 micrometers, 4.0–4.5 micrometers, or 4.5–5.0 micrometers. For example, the process variation value f2 of the pixel electrode 110 may be 0.5–2.5 micrometers, 1.5–3.0 micrometers, 2.0–3.5 micrometers, 4.0–4.5 micrometers, or 4.5–5.0 micrometers. For example, the alignment deviation d1 of the gate 143 and the alignment deviation d2 of the pixel electrode 110 may be equal or different. For example, the alignment deviation d1 of the gate 143 can be 1.0–1.5 μm, 2.0–2.5 μm, 3.0–3.5 μm, 2.0–3.5 μm, or 1.5–3.0 μm. For example, the alignment deviation d2 of the pixel electrode 110 can be 1.0–1.5 μm, 2.0–2.5 μm, 3.0–3.5 μm, 2.0–3.5 μm, or 1.5–3.0 μm. For example, D can be 1.7–2.6 μm, for example, 1.7–2.0 μm, 1.8–2.1 μm, 1.9–2.2 μm, or 2.0–2.4 μm.

[0073] By ensuring that D satisfies the above range, it is beneficial to reduce the risk of short circuits between the gate and the pixel electrode.

[0074] For example, as shown in Figure 3, the pixel electrode 110 has a block structure, and multiple pixel electrodes 110 are arranged at intervals. Due to the arrangement of multiple support structures 300, the projected area of ​​the pixel electrode 110 of the fourth sub-pixel 14 on the substrate 001 is small, while the projected area of ​​the pixel electrodes 110 of the remaining sub-pixels 10 on the substrate 001 is large. For example, the pixel electrode 110 includes a pixel corner 1110, and the pixel corners 1110 of the pixel electrodes 110 of multiple sub-pixels 10 in the same sub-pixel row are basically located on the same straight line, which is beneficial to increasing the pixel aperture ratio of the sub-pixel 10.

[0075] Figure 5 is a schematic diagram of a display product when a display malfunction occurs.

[0076] For example, some array substrates use adjacent sub-pixels sharing data lines to reduce costs by decreasing the number of data lines. However, as shown in Figure 5, this approach may reduce the charging time of sub-pixels and increase the difficulty of charging, resulting in display defects such as vertical lines in the product (e.g., for high-frequency display products).

[0077] Figure 6 is a partial connection diagram of an array substrate provided in at least one embodiment of the present disclosure; Figure 7 is a layout diagram of the array substrate shown in Figure 6.

[0078] For example, as shown in Figures 6 and 7, multiple sub-pixels 10 are arranged into multiple repeating units 100. Each repeating unit 100 includes 2M rows 110 of sub-pixels arranged along the second direction Y and 2N columns 120 of sub-pixels arranged along the first direction X, where M and N are both positive integers. Figure 6 illustrates a repeating unit 100, using M as 2 and N as 6 as an example, but is not limited thereto. For example, a repeating unit 100 may include 48 sub-pixels 10, arranged in 4 rows and 12 columns, but the embodiments of this disclosure are not limited thereto.

[0079] For example, as shown in Figures 6 and 7, the array substrate also includes multiple data lines 200, which are arranged along a first direction X. For example, each data line 200 may extend along the first direction X. Sub-pixels 10 in different sub-pixel columns 120 are electrically connected to different data lines 200, and sub-pixels 10 in the same sub-pixel column 120 are electrically connected to the same data line 200. Thus, the number of columns of the repeating unit 100 is equal to the number of data lines 200 electrically connected to it.

[0080] For example, as shown in Figure 6, the data line 200 electrically connected to the i-th sub-pixel 10 in the same sub-pixel row 110 is electrically connected to the data line 200 electrically connected to the (N+i)-th sub-pixel 10, where i is a positive integer less than or equal to N. For example, in the same sub-pixel row 110, the data line 200 electrically connected to the 1st sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 7th sub-pixel 10, and both are electrically connected to the same driving line D1. The data line 200 electrically connected to the 2nd sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 8th sub-pixel 10, and both are electrically connected to the same driving line D2. The data line 200 electrically connected to the 3rd sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 9th sub-pixel 10, and both are electrically connected to the same driving line D3. The data line 200 electrically connected to the 4th sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 10th sub-pixel 10, and both are electrically connected to the same driving line D4. The data line 200 electrically connected to the 5th sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 11th sub-pixel 10, and both are electrically connected to the same driving line D5. The data line 200 electrically connected to the 6th sub-pixel 10 is electrically connected to the data line 200 electrically connected to the 12th sub-pixel 10, and both are electrically connected to the same driving line D6.

[0081] Therefore, in this array substrate, each sub-pixel in the same sub-pixel row is connected to a separate data line, which helps to ensure that each sub-pixel has sufficient charging time, thereby reducing the charging difficulty of each sub-pixel. For example, for high-frequency products, this setting can reduce the risk of poor image quality (e.g., vertical lines) due to insufficient sub-pixel charging. In addition, since the data line electrically connected to the i-th sub-pixel is electrically connected to the data line electrically connected to the N+i-th sub-pixel, it can help to reduce costs.

[0082] For example, as shown in Figure 6, in the same sub-pixel row 110, adjacent sub-pixels 10 in the p-th to N-th sub-pixels 10 are electrically connected to different gate lines 130, and adjacent sub-pixels 10 in the j-th to 2N-th sub-pixels 10 are electrically connected to different gate lines 130, where p is a positive integer less than N and j is a positive integer greater than N and less than 2N. For example, at least one gate line 130 is provided on each side of the same sub-pixel row in the second direction Y. For example, adjacent sub-pixels 10 in the first N sub-pixels 10 are electrically connected to the gate lines 130 adjacent to both sides of their respective sub-pixel rows, and adjacent sub-pixels 10 in the N+1-2N-th sub-pixels 10 are electrically connected to the gate lines 130 adjacent to both sides of their respective sub-pixel rows.

[0083] This configuration allows the thin-film transistors of adjacent sub-pixels to be driven independently, thereby reducing the risk of signal interference.

[0084] For example, as shown in Figure 6, in the same sub-pixel row 110, the odd-numbered sub-pixel 10 among the p-Nth sub-pixels 10 and the even-numbered sub-pixels 10 among the j-2Nth sub-pixels 10 are electrically connected to the same gate line 130, and the even-numbered sub-pixels 10 among the p-Nth sub-pixels 10 and the odd-numbered sub-pixels 10 among the j-2Nth sub-pixels 10 are electrically connected to another gate line 130. It should be noted that the p-Nth sub-pixels 10 here include the p-th, p+1-th, p+2-th...Nth sub-pixels 10, and the odd-numbered sub-pixels 10 refer to the sub-pixels 10 corresponding to P, P+1, P+2... and N when N is odd. For example, if sub-pixels 2 through 6 include the 2nd, 3rd, 4th, 5th, and 6th sub-pixels 10, then the odd-numbered sub-pixels 10 among the 2nd through 6th sub-pixels 10 refer to the 3rd and 5th sub-pixels 10. Similarly, if sub-pixels j through 2N include the jth, j+1th, j+2th, ..., 2Nth sub-pixels 10, then the even-numbered sub-pixels 10 refer to the sub-pixels j, j+1, j+2th, ..., 2Nth sub-pixels 10 corresponding to j, j+1, j+2th, ..., and 2N being even numbers. For example, if sub-pixels 7 through 10 include the 7th, 8th, 9th, and 10th sub-pixels 10, then the even-numbered sub-pixels 10 among the 7th through 10th sub-pixels 10 refer to the 8th and 10th sub-pixels 10.

[0085] For example, as shown in Figure 6, taking sub-pixel 10 in the first row as an example, the 1st, 3rd and 5th sub-pixels 10 in the 1st to 6th sub-pixels 10 and the 8th, 10th and 12th sub-pixels 10 in the 7th to 12th sub-pixels 10 are all electrically connected to the same gate line 130, and the 2nd, 4th and 6th sub-pixels 10 in the 1st to 6th sub-pixels 10 and the 7th, 9th and 11th sub-pixels 10 in the 7th to 12th sub-pixels 10 are all electrically connected to another gate line 130.

[0086] This configuration allows the thin-film transistors of sub-pixels (e.g., the first sub-pixel and the seventh sub-pixel) that are electrically connected to each other (e.g., the data line electrically connected to the first sub-pixel and the data line electrically connected to the seventh sub-pixel) to be turned on by different gate lines, thereby enabling independent control of different sub-pixels.

[0087] For example, as shown in Figure 6, the multiple gate lines 130 include multiple first gate lines 131, multiple second gate lines 132, multiple third gate lines 133, and multiple fourth gate lines 134. For example, each sub-pixel row 110 includes a first side S1 and a second side S2 opposite each other in the second direction Y. The first side S1 of the k-th to M-th sub-pixel rows 110 is provided with a first gate line 131, and the second side S2 of the k-th to M-th sub-pixel rows 110 is provided with a second gate line 132, where k is a positive integer less than M. For example, taking a repeating unit 100 as an example, M can be 2, k can be 1, and the first side S1 of both the first and second sub-pixel rows 110 is provided with a first gate line 131, while the second side S2 of both the first and second sub-pixel rows 110 is provided with a second gate line 132.

[0088] For example, as shown in Figure 6, in the k-M sub-pixel rows 110, the odd-numbered sub-pixels 10 in the p-N sub-pixels 10 and the even-numbered sub-pixels 10 in the j-2N sub-pixels 10 are electrically connected to the first gate line 131, and the even-numbered sub-pixels 10 in the p-N sub-pixels 10 and the odd-numbered sub-pixels 10 in the j-2N sub-pixels 10 are electrically connected to the second gate line 132. For example, taking a repeating unit 100 as an example, N can be 6, and p can be one of 1 to 5. Then, in the first sub-pixel row 110 or the second sub-pixel row 110, the 1st, 3rd, and 5th sub-pixels 10 and the 8th, 10th, and 12th sub-pixels 10 are all electrically connected to the first gate line 131, and the 2nd, 4th, and 6th sub-pixels 10 and the 7th, 9th, and 11th sub-pixels 10 are all electrically connected to the second gate line 132.

[0089] For example, as shown in Figure 6, a third gate line 133 is provided on the first side S1 of the s-2Mth sub-pixel rows 110, and a fourth gate line 134 is provided on the second side S2 of the s-2Mth sub-pixel rows 110, where s is a positive integer greater than M and less than 2M. For example, taking a repeating unit 100 as an example, M can be 2, s can be 3, and a third gate line 133 is provided on the first side S1 of both the 3rd and 4th sub-pixel rows 110, and a fourth gate line 134 is provided on the second side S2 of both the 3rd and 4th sub-pixel rows 110.

[0090] For example, as shown in Figure 6, in the s to 2Mth sub-pixel rows 110, the even-numbered sub-pixel 10 in the p to Nth sub-pixels 10 and the odd-numbered sub-pixel 10 in the j to 2Nth sub-pixels 10 are electrically connected to the third gate line 133, and the odd-numbered sub-pixel 10 in the p to Nth sub-pixels 10 and the even-numbered sub-pixel 10 in the j to 2Nth sub-pixels 10 are electrically connected to the fourth gate line 134. For example, taking a repeating unit 100 as an example, N can be 6 and p can be one of 1 to 5. In the 3rd sub-pixel row 110 or the 4th sub-pixel row 110, the 2nd, 4th and 6th sub-pixels 10 and the 7th, 9th and 11th sub-pixels 10 are all electrically connected to the third gate line 133, and the 1st, 3rd and 5th sub-pixels 10 and the 8th, 10th and 12th sub-pixels 10 are all electrically connected to the fourth gate line 134.

[0091] This configuration allows multiple subpixels (e.g., subpixels 1-6 or 7-12) that are electrically connected to different data lines and are arranged consecutively in the same subpixel row to be alternately electrically connected to the gate lines located on both sides of the subpixel row. This allows for independent control of these subpixels, reducing the risk of signal interference between adjacent subpixels and ensuring the stability of signal transmission.

[0092] For example, as shown in Figure 6, multiple sub-pixels 10 located in the same sub-pixel row 110 include multiple sub-pixel groups 1010, each sub-pixel group 1010 including a first sub-pixel 11, a second sub-pixel 12, and a third sub-pixel 13 arranged along a first direction X. For example, multiple sub-pixels 10 located in the same sub-pixel column 120 have the same emission color. For example, taking a repeating unit 100 as an example, each sub-pixel row 110 includes four sub-pixel groups 1010. For example, multiple sub-pixels 10 in the same sub-pixel column 120 are configured to receive data signals of the same polarity.

[0093] For example, the application of the aforementioned positive and negative data signals can be controlled by a data driver connected to the data lines. For example, the data driver is configured to apply a positive data signal to odd-numbered data lines and a negative data signal to even-numbered data lines; or, to apply a negative data signal to odd-numbered data lines and a positive data signal to even-numbered data lines.

[0094] Figure 8 is a partial schematic diagram of the array substrate shown in Figure 7; Figure 9 is a partial schematic diagram of the array substrate shown in Figure 8. For example, Figure 8 is a partial schematic diagram of region A1 in Figure 7, and Figure 9 is a partial schematic diagram of region A2 in Figure 8.

[0095] For example, as shown in Figures 7 and 8, the array substrate also includes a light-shielding structure BM. The light-shielding structure BM can block the gate line 130, the data line 200 located in the adjacent sub-pixel row 110, and the thin film transistor 140 of the sub-pixel 10, etc., to reduce the influence of light on these structures, thereby helping to reduce leakage current and light leakage, and improve image quality.

[0096] For example, as shown in Figure 8, the light-shielding structure BM located between adjacent sub-pixel rows 110 has a first edge E1 and a second edge E2. The extension directions of the first edge E1 and the second edge E2 are not straight lines (for example, neither extends along the first direction X), but are flexibly set according to the position of each sub-pixel 10 in the sub-pixel row 110.

[0097] For example, as shown in FIG9, the minimum distance between the light-shielding structure BM and the support structure 300 (FIG. 9 also shows the spacer 310 disposed on the support structure 300) is the first distance; the minimum distance between the light-shielding structure BM and the gate 143 of the thin-film transistor 140 of the sub-pixel is the second distance; the minimum distance between the light-shielding structure BM and the via structure PN0 is the third distance; and the minimum distance between the light-shielding structure BM and the gate line 130 is the fourth distance. For example, the first, second, third, and fourth distances are all equal (denoted by d in FIG. 9). For example, d can be 7 micrometers, 6.5 micrometers, or 7.5 micrometers, but is not limited thereto, and the embodiments of this disclosure do not limit this.

[0098] This design ensures that the shading structure meets process requirements while maximizing its accuracy to better fulfill its shading function.

[0099] Figures 10 to 15 are process flow diagrams of the array substrate provided in at least one embodiment of the present disclosure.

[0100] For example, as shown in FIG10, a gate line layer is formed on a substrate 001. The gate line layer includes multiple gate lines 130, the gate of the thin film transistor of the sub-pixel 143, and a support structure 300. The gate lines 130 are electrically connected to the gate of the thin film transistor 143, and the support structure 300 is electrically connected to the gate of the thin film transistor 143.

[0101] For example, as shown in FIG11, a pixel electrode layer is formed after the gate line layer is formed. For example, the pixel electrode layer includes a plurality of pixel electrodes 110. For example, the pixel electrode layer is spaced apart from the gate line layer. In some embodiments, the gate line layer and the pixel electrode layer can be formed by a single mask, which is not limited to the embodiments of the present disclosure.

[0102] For example, as shown in FIG12, an active layer is provided on the pixel electrode layer. The active layer includes a plurality of active structures 144, and the orthographic projection of the active structures 144 on the substrate 001 overlaps with the orthographic projection of the gate 143 on the substrate 001.

[0103] For example, as shown in Figure 13, after the active layer is formed, a first metal layer is formed. For example, the first metal layer includes a data line 200, a first electrode 141 of a thin-film transistor, and a second electrode 142.

[0104] For example, as shown in Figure 14, an insulating layer can be formed on the active layer, and multiple vias N can be formed in the insulating layer.

[0105] For example, as shown in FIG15, after forming a plurality of vias N, a second metal layer may be formed. For example, the second metal layer includes a common electrode 110 for the sub-pixels and a bridging structure 111. For example, at least a portion of the bridging structure 111 is located in the vias N, and the pixel electrode 110 is electrically connected to the first electrode 141 of the thin-film transistor through the bridging structure 111.

[0106] Of course, the array substrate provided in the embodiments of this disclosure may also include other film layers, and there is no limitation thereto.

[0107] Figure 16 is a schematic diagram of the structure of a display device provided in at least one embodiment of the present disclosure.

[0108] As shown in Figure 16, at least one embodiment of this disclosure also provides a display device 1000, which includes the array substrate described in any of the above embodiments. Therefore, since the display device includes the array substrate, the technical effects of the array substrate can also be reflected in the display device, and will not be elaborated further here.

[0109] As shown in Figure 16, the display panel 1000 includes an array substrate 01, an opposing substrate 02, and a liquid crystal layer 03. The opposing substrate 02 and the array substrate 01 are disposed opposite each other to form a cell. The liquid crystal layer 03 is located between the array substrate 01 and the opposing substrate 02. The liquid crystal layer 03 includes a plurality of liquid crystal molecules 031, and the liquid crystal molecules 031 are deflected under the action of the array substrate 01 and the opposing substrate 02, thereby performing display. For example, the array substrate 01 can be the array substrate described in any of the above embodiments.

[0110] For example, as shown in Figure 16, a filter layer may also be provided on the side of the opposing substrate 02 facing the array substrate 01 to achieve color display. For example, the filter layer includes multiple filter units, each of which may correspond to a display electrode. For example, the multiple filter units may include multiple red filter units, multiple green filter units, and multiple blue filter units, but are not limited to these.

[0111] In embodiments of this disclosure, components located in the same layer may be fabricated from the same film layer using the same patterning process. For example, components located in the same layer may be located on the surface of the same component away from the substrate.

[0112] It should be noted that, for clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements present.

[0113] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0114] In the embodiments of this disclosure, components located in different layers are formed from different film layers through different patterning processes.

[0115] The following points need to be explained:

[0116] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0117] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0118] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended rights.

Claims

1. An array substrate, comprising: Substrate; Multiple sub-pixels are located on the substrate and are arranged in an array in a first direction and a second direction. Each sub-pixel includes a pixel electrode and a common electrode. The first direction and the second direction are both parallel to the substrate and intersect the second direction. Multiple gate lines are located on the substrate, each gate line extends along the first direction, and two gate lines are disposed between two adjacent pixel electrodes arranged along the second direction; The sub-pixel further includes a thin-film transistor, each of which includes a first electrode, a gate, and a second electrode. The first electrode is electrically connected to the pixel electrode through a via. The common electrode of the sub-pixel includes a recessed portion, and the recessed portion is bent toward the via corresponding to the sub-pixel.

2. The array substrate according to claim 1, wherein, The common electrode of the sub-pixel includes an edge adjacent to the thin-film transistor of the sub-pixel, the edge including a first portion and a second portion, and a junction connecting the first portion and the second portion. Both the first portion and the second portion extend along the first direction, with the second portion being further away from the via corresponding to the sub-pixel than the first portion.

3. The array substrate according to claim 2, wherein, The common electrode of the sub-pixel includes a plurality of slits spaced apart along the first direction, each slit including a corner, and the multiple corners of the common electrode of the plurality of sub-pixels in the same sub-pixel row are substantially located on the same straight line extending along the first direction.

4. The array substrate according to claim 3, wherein, Each of the slits in the common electrode of the sub-pixel includes an end near the gate line electrically connected to the thin-film transistor of the sub-pixel. In the first direction, multiple ends of the common electrode of the sub-pixel are not flush.

5. The array substrate according to claim 4, wherein, The minimum distance between the ends of the multiple slits of the common electrode of the sub-pixel and the edge is substantially the same.

6. The array substrate according to any one of claims 3-5, wherein, The plurality of slits of the common electrode of the sub-pixel includes a plurality of first slits and a plurality of second slits. In the second direction, the plurality of first slits are located on one side of the first portion, and the plurality of second slits are located on the same side of the second portion, wherein the portions of each second slit located on both sides of the corner are of different sizes.

7. The array substrate according to any one of claims 3-6, wherein, The common electrode of the sub-pixel includes a connecting portion and a plurality of strip-shaped portions arranged in the first direction, with a slit between adjacent strip-shaped portions. The plurality of strip-shaped portions of the sub-pixel are connected to each other and to the plurality of strip-shaped portions of adjacent sub-pixels through the connecting portion. Each of the strip-shaped portions includes a first protrusion, and the connecting portion includes a second protrusion. The first protrusion and the second protrusion have the same protrusion direction, and the surface curvature of the first protrusion is smaller than that of the second protrusion.

8. The array substrate according to any one of claims 1-7, wherein, The plurality of sub-pixels are arranged into a plurality of repeating units, each repeating unit comprising 2M sub-pixel rows arranged along the second direction and 2N sub-pixel columns arranged along the first direction, where M and N are both positive integers. The array substrate further includes multiple data lines, which are arranged along the first direction. Subpixels in different subpixel columns are electrically connected to different data lines, subpixels in the same subpixel column are electrically connected to the same data line, and the data line electrically connected to the i-th subpixel in the same subpixel row is electrically connected to the data line electrically connected to the (N+i)-th subpixel, where i is a positive integer less than or equal to N.

9. The array substrate according to claim 8, wherein, In the same sub-pixel row, adjacent sub-pixels in the p-th to N-th sub-pixels are electrically connected to different gate lines, and adjacent sub-pixels in the j-th to 2N-th sub-pixels are electrically connected to different gate lines, where p is a positive integer less than N and j is a positive integer greater than N and less than 2N.

10. The array substrate according to claim 9, wherein, In the same sub-pixel row, the odd-numbered sub-pixel of the p-N sub-pixels and the even-numbered sub-pixels of the j-2N sub-pixels are electrically connected to the same gate line, and the even-numbered sub-pixels of the p-N sub-pixels and the odd-numbered sub-pixels of the j-2N sub-pixels are electrically connected to another gate line.

11. The array substrate according to claim 10, wherein, The plurality of gate lines includes a plurality of first gate lines, a plurality of second gate lines, a plurality of third gate lines, and a plurality of fourth gate lines, and each of the sub-pixel rows includes a first side and a second side opposite to each other in the second direction. A first gate line is provided on the first side of the k-th to M-th sub-pixel rows, and a second gate line is provided on the second side of the k-th to M-th sub-pixel rows. In the k-th to M-th sub-pixel rows, the odd-numbered sub-pixels among the p-th to N-th sub-pixels and the even-numbered sub-pixels among the j-th to 2N-th sub-pixels are electrically connected to the first gate line, and the even-numbered sub-pixels among the p-th to N-th sub-pixels and the odd-numbered sub-pixels among the j-th to 2N-th sub-pixels are electrically connected to the second gate line. k is a positive integer less than M. A third gate line is provided on the first side of the s-2Mth sub-pixel rows, and a fourth gate line is provided on the second side of the s-2Mth sub-pixel rows. In the s-2Mth sub-pixel rows, the even-numbered sub-pixel of the p-Nth sub-pixels and the odd-numbered sub-pixels of the j-2Nth sub-pixels are electrically connected to the third gate line, and the odd-numbered sub-pixel of the p-Nth sub-pixels and the even-numbered sub-pixels of the j-2Nth sub-pixels are electrically connected to the fourth gate line, where s is a positive integer greater than M and less than 2M.

12. The array substrate according to any one of claims 8-11, wherein, Multiple subpixels located in the same subpixel row include multiple subpixel groups. Each subpixel group includes a first subpixel, a second subpixel, and a third subpixel arranged along the first direction. Multiple subpixels located in the same subpixel column have the same emission color.

13. The array substrate according to any one of claims 1-11, wherein, The array substrate further includes multiple support structures, and the multiple sub-pixels include a fourth sub-pixel. The support structures and the gates of the thin-film transistors of the fourth sub-pixel are disposed opposite to each other in the second direction. The plurality of gate lines includes a plurality of fifth gate lines. The support structure is electrically connected to the fifth gate lines. The fifth gate lines and the gate lines electrically connected to the fourth sub-pixel are respectively located on opposite sides of the pixel electrode of the fourth sub-pixel in the second direction.

14. The array substrate according to claim 13, wherein, The gate of the thin-film transistor of the sub-pixel includes at least one first chamfer, and the support structure includes at least one second chamfer, wherein the first chamfer is not larger than the second chamfer.

15. The array substrate according to claim 13, wherein, The fourth sub-pixel is configured to emit blue light.

16. The array substrate according to any one of claims 1-15, wherein, The gate of the thin-film transistor of the sub-pixel is located on the same layer as the pixel electrode, and the minimum distance between the gate and the pixel electrode is D, where D satisfies: D≤(f1) 2 +d1 2 +f2 2 +d2 2 ) 0.5 In the formula, f1 represents the process fluctuation value of the gate, d1 represents the alignment deviation of the gate, f2 represents the process fluctuation value of the pixel electrode, and d2 represents the alignment deviation of the pixel electrode.

17. A display device, comprising: The array substrate according to any one of claims 1-16; The opposing substrate is disposed opposite to the array substrate; as well as A liquid crystal layer is located between the array substrate and the opposing substrate.

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