Array substrate and repair method therefor, and display panel and display apparatus

Abstract

The array substrate (10) comprises a first base (110), a plurality of gate lines (40), a plurality of data lines (30), a first bridging line (50) and a plurality of pixel electrodes (120). The plurality of data lines (30) and the plurality of gate lines (40) intersect to define a plurality of pixel regions (M), and each pixel region (M) comprises at least one pixel sub-region. At least one of the data lines (30) or the gate lines (40) has a first fracture (S1), and the data line (30) or the gate line (40) having the first fracture (S1) is a target signal line (60). Two ends of the first fracture (S1) of the target signal line (60) are connected by the first bridging line (50). One pixel electrode (120) is located in one pixel sub-region. The first bridging line (50) overlaps at least one pixel electrode (120). The pixel sub-region overlapping the first bridging line (50) is a target pixel sub-region, the pixel electrodes (120) located in the target pixel sub-region comprise a first target pixel electrode (71), the first target pixel electrode (71) comprises a first sub-electrode (711) and a second sub-electrode (712), the first sub-electrode (711) and the second sub-electrode (712) are spaced apart, and in the orthographic projection onto the first base (110), the first sub-electrode (711) overlaps the first bridging line (50), and the second sub-electrode (712) is offset from the first bridging line (50).

Description

Array substrate and its repair method, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and its repair method, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, liquid crystal displays (LCDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as small size, low power consumption, low cost, high brightness, and high reliability. Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a first substrate, a plurality of gate lines, a plurality of data lines, a first bridging wire, and a plurality of pixel electrodes. The gate lines are disposed on the first substrate. The gate lines extend along a first direction, and the plurality of gate lines are spaced apart along a second direction; the first direction and the second direction intersect. The data lines are disposed on the first substrate. The data lines extend along the second direction, and the plurality of data lines are spaced apart along the first direction. The plurality of data lines and the plurality of gate lines intersect to define a plurality of pixel regions, each pixel region including at least one pixel sub-region. The first bridging wire is disposed on the first substrate. At least one of the data lines or the gate lines has a first break, and the data line or the gate line with the first break is a target signal line. The two ends of the first break of the target signal line are connected by the first bridging wire. One pixel electrode is located in one pixel sub-region. In a projected orthographic projection onto the first substrate, the first bridging wire overlaps with at least one pixel sub-region.

[0004] The pixel sub-region overlapping with the first bridging line is the target pixel sub-region, and the pixel electrode located in the target pixel sub-region is the target pixel electrode. The target pixel electrode includes a first target pixel electrode, which includes a first sub-electrode and a second sub-electrode. The first sub-electrode and the second sub-electrode are spaced apart and, in their orthogonal projection onto the first substrate, the first sub-electrode overlaps with the first bridging line, and the second sub-electrode is offset from the first bridging line.

[0005] In some embodiments, the gate line is the target signal line.

[0006] In some embodiments, the array substrate includes multiple common voltage signal lines disposed on the first substrate. Each common voltage signal line includes a first trace segment and a second trace segment. The first trace segment extends along a first direction, and the second trace segment extends along a second direction. In its orthographic projection onto the first substrate, the second trace segment overlaps with the pixel electrode. The second trace segment overlapping the target pixel electrode includes a first sub-segment and a second sub-segment. The first sub-segment is connected to the first bridging wire, and the second sub-segment is connected to the first trace segment. A second break exists between the first sub-segment and the second sub-segment.

[0007] In some embodiments, a first gap exists between the first sub-electrode and the second sub-electrode. In a positive projection onto the first substrate, in a second trace segment overlapping the first target pixel electrode, the first sub-segment and the first sub-electrode at least partially overlap, and the end of the second sub-segment near the first sub-segment does not overlap with the first sub-electrode.

[0008] In some embodiments, a first gap exists between the first sub-electrode and the second sub-electrode. In a positive projection onto the first substrate, in a second trace segment overlapping the first target pixel electrode, the first sub-segment and the first sub-electrode at least partially overlap, and the second sub-segment overlaps with the first sub-electrode near the end of the first sub-segment.

[0009] In some embodiments, the array substrate includes multiple common voltage signal lines disposed on the first substrate. Each common voltage signal line includes a first trace segment and a third trace segment. The first trace segment extends along a first direction, and the third trace segment extends along a second direction. In its orthographic projection onto the first substrate, the third trace segment is at least partially located between the pixel electrodes. The third trace segment, at least partially located between two adjacent target pixel electrodes, includes a third sub-segment and a fourth sub-segment. The third sub-segment is connected to the first bridging wire, and the fourth sub-segment is connected to the first trace segment. A third break is present between the third sub-segment and the fourth sub-segment.

[0010] In some embodiments, a first gap exists between the first sub-electrode and the second sub-electrode. In an orthographic projection onto the first substrate, in a third trace segment adjacent to the first target pixel electrode, the third sub-segment and the first sub-electrode at least partially overlap, and the end of the fourth sub-segment near the third sub-segment does not overlap with the first sub-electrode.

[0011] In some embodiments, a first gap exists between the first sub-electrode and the second sub-electrode. In an orthographic projection onto the first substrate, in a third trace segment adjacent to the first target pixel electrode, the third sub-segment and the first sub-electrode at least partially overlap, and the fourth sub-segment near the end of the third sub-segment overlaps with the first sub-electrode.

[0012] In some embodiments, the first bridging wire is made of the same material as the target signal line and is disposed in the same layer.

[0013] In some embodiments, the array substrate further includes a first transistor and a first interconnect line. The first transistor is disposed on the first substrate. A first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to the pixel electrode, and a control electrode of the first transistor is connected to the gate line. The first interconnect line is disposed on the first substrate. One end of the first interconnect line is connected to the second electrode of the first transistor, and the other end is connected to the pixel electrode. The first interconnect line connected to the first target pixel electrode is a first target interconnect line. The second sub-electrode is connected to the second electrode of the first transistor through the first target interconnect line. In a projected image onto the first substrate, the first target interconnect line is offset from the first bridging line, and the gap between the first sub-electrode and the second sub-electrode is located between the first target interconnect line and the first bridging line.

[0014] In some embodiments, the target pixel electrode further includes a second target pixel electrode, which is an integral structure. In a normal projection onto the first substrate, the second target pixel electrode is offset from the first bridge line. And / or, the array substrate further includes a common voltage signal line, to which the second target pixel electrode is connected.

[0015] In some embodiments, the array substrate further includes a common voltage signal line, and the second target pixel electrode is connected to the common voltage signal line. The array substrate also includes a first transistor and a first connection line. The first transistor is disposed on the first substrate. A first electrode of the first transistor is connected to the data line, a second electrode of the first transistor is connected to the pixel electrode, and a control electrode of the first transistor is connected to the gate line. The first connection line is disposed on the first substrate. One end of the first connection line is connected to the second electrode of the first transistor, and the other end is connected to the pixel electrode. The first connection line connected to the second target pixel electrode is a second target connection line, and in its orthographic projection onto the first substrate, the second target connection line overlaps with the first bridging line.

[0016] In some embodiments, a first gap is provided between the first sub-electrode and the second sub-electrode, and the orthographic projection of the first gap onto the first substrate is L-shaped.

[0017] In some embodiments, the plurality of pixel electrodes are arranged in an array along the first direction and the second direction. Along the second direction, a gate line is respectively disposed on each opposite side of the plurality of pixel electrodes, and two gate lines are disposed between two adjacent rows of pixel electrodes. Two columns of pixel electrodes are disposed between each pair of adjacent data lines. A pixel region is defined between two adjacent data lines and two adjacent gate lines on opposite sides of a row of pixel electrodes, and each pixel region is provided with two pixel electrodes.

[0018] In some embodiments, pixel electrodes located in the same pixel region are connected to the same data line, and pixel electrodes in two adjacent pixel regions in the second direction are connected to different data lines. Furthermore, the plurality of data lines includes a plurality of first data lines and a plurality of second data lines, which are arranged alternately along the first direction.

[0019] In this design, two pixel electrodes located within the same pixel region are designated as a first pixel electrode and a second pixel electrode. The first pixel electrode is positioned between the second pixel electrode and the connected data line. The first data line is connected to the first pixel electrode on a first side of the pixel region and to the second pixel electrode on a second side of the pixel region. The second data line is connected to the first pixel electrode on a second side of the pixel region and to the second pixel electrode on a first side of the pixel region. The first and second sides of the pixel region are opposite sides of the pixel region in the second direction.

[0020] In some embodiments, the gate line is the target signal line, and the first bridging line is located on the side of the target signal line near the adjacent pixel region.

[0021] On the other hand, a display panel is provided. The display panel includes an array substrate, a color filter substrate, and a liquid crystal layer. The array substrate is an array substrate as described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0022] In another aspect, a display device is provided. The display device includes a display panel and a circuit board, wherein the display panel is the display panel as described in any of the above embodiments, and the circuit board is connected to the display panel.

[0023] Furthermore, a method for repairing an array substrate is provided. The method for repairing the array substrate includes:

[0024] An array substrate is fabricated. The array substrate includes a first substrate and a plurality of signal lines disposed on the first substrate; the plurality of signal lines include a plurality of gate lines, or the plurality of signal lines include a plurality of gate lines and a plurality of data lines; wherein the gate lines extend along a first direction, and the plurality of gate lines are spaced apart along a second direction; the first direction intersects the second direction; the data lines extend along the second direction, and the plurality of data lines are spaced apart along the first direction; the plurality of data lines and the plurality of gate lines intersect to define a plurality of pixel regions, each pixel region including at least one pixel sub-region.

[0025] A target signal line is determined; the target signal line is the data line or the gate line having the first break. A first bridging wire is formed; the two ends of the first break of the target signal line are connected through the first bridging wire. A pixel electrode is formed; one pixel electrode is located in one pixel sub-region; in orthographic projection onto the first substrate, the first bridging wire overlaps with at least one pixel sub-region. The pixel sub-region overlapping with the first bridging wire is the target pixel sub-region, and the pixel electrode located in the target pixel sub-region is the target pixel electrode. The target pixel electrode includes the first target pixel electrode.

[0026] A portion of the first target pixel electrode is stripped to form a first sub-electrode and a second sub-electrode; the first sub-electrode and the second sub-electrode are spaced apart and, in their orthogonal projection onto the first substrate, the first sub-electrode overlaps with the first bridging line, and the second sub-electrode is offset from the first bridging line.

[0027] In some embodiments, the array substrate further includes multiple common voltage signal lines disposed on the first substrate. Each common voltage signal line includes a first trace segment and a second trace segment. The first trace segment extends along a first direction, and the second trace segment extends along a second direction. In its orthographic projection onto the first substrate, the second trace segment overlaps with the pixel electrode. The second trace segment overlapping the target pixel electrode is connected to the first bridging line.

[0028] After forming the first bridging wire, the repair method further includes cutting the second trace segment overlapping the target pixel electrode to form a first sub-segment and a second sub-segment. The first sub-segment is connected to the first bridging wire, the second sub-segment is connected to the first trace segment, and a second break is formed between the first sub-segment and the second sub-segment.

[0029] In some embodiments, the target pixel electrode further includes a second target pixel electrode. After forming the pixel electrode, the repair method further includes: stripping a portion of the second target pixel electrode, such that the second target pixel electrode is offset from the first bridge wire. And / or, the array substrate further includes a common voltage signal line, and after forming the pixel electrode, the repair method further includes: connecting the second target pixel electrode to the common voltage signal line. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 is a structural diagram of a display device according to some embodiments;

[0032] Figure 2 is a cross-sectional view along section line AA' in Figure 1;

[0033] Figure 3 is a cross-sectional view of a display panel according to some embodiments;

[0034] Figure 4 is a top view of a display panel according to some embodiments;

[0035] Figure 5 is a structural diagram of an array substrate according to some embodiments;

[0036] Figure 6 is a structural diagram of another array substrate according to some embodiments;

[0037] Figure 7 is a structural diagram of another array substrate according to some embodiments;

[0038] Figure 8 is a structural diagram of another array substrate according to some embodiments;

[0039] Figure 9 is a structural diagram of another array substrate according to some embodiments;

[0040] Figure 10 shows the test results of the display panel lighting up, including the array substrate shown in Figure 8;

[0041] Figure 11 shows the test results of the display panel lighting up, including the array substrate shown in Figure 9;

[0042] Figure 12 is a characteristic test analysis diagram of the first transistor on the array substrate shown in Figures 8 and 9;

[0043] Figure 13 is a scanning electron microscope (SEM) image of the indium element in the array substrate according to some embodiments;

[0044] Figure 14 is a flowchart of a method for repairing an array substrate according to some embodiments;

[0045] Figure 15 is a flowchart of a method for repairing an array substrate according to some embodiments;

[0046] Figure 16 is a flowchart of a method for repairing an array substrate according to some embodiments;

[0047] Figure 17 is a flowchart of a method for repairing an array substrate according to some embodiments. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0051] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0052] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0053] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, “vertical” includes the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “vertical” includes absolute verticality and approximate verticality, where an acceptable range of deviation for approximate verticality could, for example, be within 5°.

[0055] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0056] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0057] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0058] As shown in Figure 1, some embodiments of this disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image. Exemplarily, the display device 1000 can be any product or component with display functionality, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, in-vehicle display, in-flight display, wearable device, virtual reality (VR) device, signboard, electronic billboard, and shopping mall display. For example, the display device 1000 can be the television shown in Figure 1.

[0059] In some embodiments, referring to FIG2, the display device 1000 includes a display panel 100 and a circuit board 200. The circuit board 200 may include, for example, a timing controller (TCON), a power management chip (DC / DC), and a variable resistor voltage divider circuit (generating Vcom), etc. Of course, the circuit board 200 may also include other circuit structures, which will not be listed here. The circuit board 200 is electrically connected to the display panel 100 and is used to transmit control signals to the display panel 100 to drive the display panel 100 to achieve image display.

[0060] Referring to Figure 2, the display device 1000 may further include a frame 300 and a cover plate 400. The longitudinal section of the frame 300 is, for example, U-shaped. The display panel 100 and the circuit board 200 may be disposed within the frame 300, and the cover plate 400 is disposed at the opening of the frame 300. Of course, the display device 1000 may also omit the cover plate 400, and this embodiment does not specifically limit this.

[0061] Referring to Figure 2, the display device 1000 may further include a backlight module 500 disposed on the backlight side of the display panel 100. The backlight module 500 may be disposed, for example, on the side of the display panel 100 away from the cover plate 400, and the circuit board 200 may be disposed on the side of the backlight module 500 away from the cover plate 400. The backlight module 500 may be a direct-lit backlight module or an edge-lit backlight module, etc., and is used to provide a light source for the display panel 100. The display panel 100 adjusts the amount of light passing through it to display different gray levels, thereby achieving the purpose of image display.

[0062] In some embodiments, as shown in FIG2, the display panel 100 may include an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and a liquid crystal layer 15 disposed between the array substrate 10 and the color filter substrate 20. The array substrate 10 and the color filter substrate 20 are joined together by an adhesive 350, thereby confining the liquid crystal layer 15 within the area enclosed by the adhesive 350. The color filter substrate 20 may also be referred to as an opposing substrate or an encapsulation substrate. For example, the color filter substrate 20 may filter light incident on it to emit light of multiple colors (such as red, green, or blue) to achieve color display.

[0063] In some embodiments, as shown in FIG3, the array substrate 10 includes a first substrate 110, and pixel electrodes 120 and a common electrode 130 disposed on the first substrate 110. The common electrode 130 is disposed on the side of the pixel electrodes 120 away from the first substrate 110, and multiple pixel electrodes 120 are spaced apart. The common electrode 130 is a single integral structure, and multiple slits S can be formed on the common electrode 130, exposing portions of the pixel electrodes 120. In this case, a multidimensional electric field is formed by the electric field generated at the edge of the slits of the common electrode 130 in the same plane, and the electric field generated between the common electrode 130 and the pixel electrodes 120, enabling all oriented liquid crystal molecules in the liquid crystal layer 15 to rotate, thereby improving the liquid crystal working efficiency and increasing the light transmittance. Of course, the structure of the pixel electrode 120 and the common electrode 130 is not limited to this. For example, the pixel electrode 120 and the common electrode 130 are arranged in the same layer, or multiple pixel electrodes 120 are arranged at intervals, and the common electrode 130 is a continuous whole-surface structure (i.e., the common electrode 130 does not have slits) and is arranged between the film layer where the pixel electrode 120 is located and the first substrate 110. These will not be listed one by one here.

[0064] Referring to Figure 3, the color filter substrate 20 may include, for example, a second substrate 210 and a color filter layer 220 disposed on the second substrate 210. The color filter layer 220 includes a plurality of filter portions 221, which include red, green, and blue filter portions. These red, green, and blue filter portions are respectively configured to transmit red, green, and blue light, thereby achieving color display. Furthermore, the color filter substrate 20 may also include, for example, a black matrix pattern 230 disposed on the second substrate 210, which serves to separate the different filter portions 221.

[0065] In some embodiments, referring to FIG4, the display panel 100 may include a display area AA and a peripheral area BB disposed on at least one side of the display area AA. FIG4 shows an example where the peripheral area BB surrounds the display area AA. The display area AA is the area for displaying an image and is configured to have multiple sub-pixels P, where each sub-pixel P can be understood as the smallest light-emitting unit in the display panel 100. The peripheral area BB may have circuit structures, such as a gate driving circuit 111 and a source driving circuit 112.

[0066] As shown in Figure 4, the display area AA includes multiple sub-pixels P. These sub-pixels P can be arranged in multiple rows and columns within the display area AA. Each column includes at least two sub-pixels P arranged along a first direction X, and each row includes at least two sub-pixels P arranged along a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0067] Referring to Figures 3 and 4, the sub-pixel P may include a pixel circuit, a pixel electrode 120, and a filter section 221. The pixel circuit includes a first transistor 12, which includes an active layer 121, a first electrode 122, a second electrode 123, a control electrode 124, and a gate insulating layer 125. The first electrode 122 and the second electrode 123 are respectively in contact with the active layer 121, and the pixel electrode 120 is connected to the second electrode 123 of the first transistor 12. In this case, the pixel electrodes 120 are arranged in an array along the first direction X and the second direction Y. Furthermore, the material of the active layer 121 includes oxide semiconductor and / or low-temperature polycrystalline silicon; for example, the material of the active layer 121 includes indium gallium zinc oxide.

[0068] In this paper, the sub-pixel P including the red filter is called the red sub-pixel R, the sub-pixel P including the green filter is called the green sub-pixel G, and the sub-pixel P including the blue filter is called the blue sub-pixel B.

[0069] Referring to Figure 4, the multiple sub-pixels P may include red sub-pixels R, green sub-pixels G, and blue sub-pixels B. The red sub-pixels R, green sub-pixels G, and blue sub-pixels B can be arranged in a column along the second direction Y, and along the first direction X, a column of red sub-pixels R, a column of green sub-pixels G, and a column of blue sub-pixels B are arranged cyclically. Of course, the red sub-pixels R, green sub-pixels G, and blue sub-pixels B can also be arranged in other ways, and this embodiment is not limited to this.

[0070] Please refer to Figure 4. The array substrate 10 (see Figure 3) also includes multiple data lines 30. The multiple data lines 30 are disposed on the first substrate 110. The multiple data lines 30 are arranged at intervals along the first direction X and extend generally along the second direction Y. The source driving circuit 112 is electrically connected to the sub-pixel P through the data lines 30 to provide data signals to the sub-pixel P. The data lines 30 can be straight lines or broken lines in their extension direction. This embodiment does not specifically limit this.

[0071] Please refer to Figure 4. The array substrate 10 (see Figure 3) also includes multiple gate lines 40. The multiple gate lines 40 are disposed on the first substrate 110. The multiple gate lines 40 are arranged at intervals along the second direction Y and extend generally along the first direction X. The gate driving circuit 111 is connected to the sub-pixel P through the gate lines 40 to provide gate signals. The gate lines 40 can be straight lines or broken lines in their extension direction. This embodiment does not specifically limit this.

[0072] Based on this, and referring to Figures 4 and 5, multiple data lines 30 and multiple gate lines 40 intersect to define multiple pixel regions M. Each pixel region M includes at least one pixel sub-region, and one pixel electrode 120 is located in one pixel sub-region. That is, each pixel region M is provided with at least one pixel electrode 120. Here, the pixel sub-region is the area designed for the pixel electrode 120, which can be understood as the area where the pixel electrode 120 is located without being stripped in the following text.

[0073] It should be understood that the arrangement of the multiple data lines 30 and multiple gate lines 40 is not unique. For example, as shown in Figures 4 and 5, along the second direction Y, a gate line 40 is respectively provided on both sides of the multiple pixel electrodes 120, and two gate lines 40 are provided between two adjacent rows of pixel electrodes 120. Two columns of pixel electrodes 120 are provided between each pair of adjacent data lines 30. A pixel region M is defined between the two adjacent data lines 30 and the two gate lines 40 adjacent to the two sides of a row of sub-pixels P. Each pixel region M is provided with two pixel electrodes 120. This can reduce the number of data lines 30, reduce the number of signal channels output by the source driving circuit 112, and thus reduce the cost of the source driving circuit 112.

[0074] Based on this, referring to Figures 4 and 5, pixel electrodes 120 located in the same pixel region M are connected to the same data line 30, and pixel electrodes 120 of two adjacent pixel regions M in the second direction Y are connected to different data lines 30.

[0075] For example, as shown in Figure 4, the multiple data lines 30 include multiple first data lines 31 and multiple second data lines 32, arranged alternately along the first direction X. At this time, in the second direction Y, the pixel electrodes 120 of two adjacent pixel regions M are connected to the first data line 31 and the other to the second data line 32.

[0076] As shown in Figure 5, two pixel electrodes 120 located in the same pixel region M are a first pixel electrode 120a and a second pixel electrode 120b, respectively. The first pixel electrode 120a is located between the second pixel electrode 120b and the connected data line 30.

[0077] In this configuration, the first data line 31 is electrically connected to the first pixel electrode 120a in pixel region M on the first side of pixel region M, and to the second pixel electrode 120b in pixel region M on the second side of pixel region M. The second data line 32 is connected to the first pixel electrode 120a in pixel region M on the second side of pixel region M, and to the second pixel electrode 120b in pixel region M on the first side of pixel region M. This allows for the input of independent data signals to different sub-pixels P in the same row using fewer data lines 30, resulting in a more detailed display and improved display quality. The first and second sides of pixel region M are opposite sides of pixel region M in the second direction Y. Figure 4 illustrates this with the first side as the upper side and the second side as the lower side.

[0078] During the manufacturing process of display devices, foreign objects or corrosion can easily cause data lines or gate lines to break. Therefore, it is necessary to repair the break points to avoid circuit malfunction and product scrapping. In related technologies, the method for repairing broken data lines or gate lines is to add connecting wires. However, during the display process, the connecting wires may overlap with the pixel electrodes, creating parasitic capacitance between the pixel electrode and the connecting wire. When the connecting wire transmits signals, it can cause bright spots to form at the pixel electrode, resulting in poor display quality.

[0079] To solve the above-mentioned technical problems, referring to Figures 3, 5 and 6, the array substrate 10 provided in some embodiments of this disclosure further includes a first bridge connection 50, which is disposed on the first substrate 110.

[0080] At least one data line 30 or gate line 40 has a first break S1, and the data line 30 or gate line 40 with the first break S1 is the target signal line 60. That is, the target signal line 60 is broken, and the break point of the target signal line 60 needs to be repaired. At this time, the two ends of the first break S1 of the target signal line 60 are connected through the first bridge wire 50 to repair the target signal line 60. Referring to Figures 7 and 8, the data line 30 or gate line 40 may have one or more first breaks S1, and this embodiment of the present disclosure does not specifically limit this.

[0081] Please refer to Figure 5. In the orthographic projection onto the first substrate 110, the first bridging line 50 overlaps with at least one pixel sub-region. The pixel sub-region overlapping with the first bridging line 50 is a target pixel sub-region, and the pixel electrode 120 located in the target pixel sub-region is a target pixel electrode 70. The target pixel electrode 70 includes a first target pixel electrode 71, which includes a first sub-electrode 711 and a second sub-electrode 712. The first sub-electrode 711 and the second sub-electrode 712 are spaced apart. In the orthographic projection onto the first substrate 110, in a direction perpendicular to the first substrate 110, the first sub-electrode 711 overlaps with the first bridging line 50, and the second sub-electrode 712 is offset from the first bridging line 50.

[0082] In this configuration, the first sub-electrode 711 and the second sub-electrode 712 are separated. The first bridging wire 50 forms a parasitic capacitance with the overlapping first sub-electrode 711, but not with the second sub-electrode 712. When the first bridging wire 50 transmits signals, it does not directly cause voltage generation at the second sub-electrode 712, thus improving or preventing bright spots at the second sub-electrode 712 and improving the display effect. Furthermore, the second sub-electrode 712 can still display normally without the need for darkening processing, further enhancing the display effect. In addition, the amount of stripping of the first target pixel electrode 71 is less, resulting in higher production yield and efficiency.

[0083] The first bridge wire 50 and the target signal line 60 are made of the same material and are disposed in the same layer. This simplifies the fabrication process of the first bridge wire 50, eliminating the need for cross-layer drilling connections, resulting in low production costs and high production efficiency. Of course, the first bridge wire 50 and the target signal line 60 can also be located in different layers; this embodiment does not specifically limit this.

[0084] A first gap G1 is provided between the first sub-electrode 711 and the second sub-electrode 712. The orthographic projection of the first gap G1 onto the first substrate 110 is L-shaped. This reduces the relative area of ​​the first sub-electrode 711 and increases the relative area of ​​the second sub-electrode 712, thereby reducing the area of ​​the bright spot formed by the first sub-electrode 711 and facilitating a better display effect. Of course, the first gap G1 can also be any other suitable shape, such as a line or a U-shape, as long as it can form the first sub-electrode 711 and the second sub-electrode 712. This embodiment does not specifically limit this.

[0085] The width of the first gap G1 is 9μm to 15μm. For example, the width of the first gap G1 is any one of 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, and 15μm. This configuration places lower requirements on the precision of the process equipment, and the smaller width of the first gap G1 results in higher production efficiency.

[0086] The following describes some embodiments of this disclosure using gate line 40 as an example of target signal line 60, but the embodiments of this disclosure are not limited thereto. In this case, the first bridging line 50 may be located, for example, on the side of the target signal line 60 (i.e., gate line 40) close to the adjacent pixel region M, so that the first bridging line 50 will not overlap with other gate lines 40, which is convenient for fabrication.

[0087] In some embodiments, as shown in Figures 3, 5, 7, and 8, the array substrate 10 includes multiple common voltage signal lines 80. The common voltage signal lines 80 are disposed on the first substrate 110, and the common voltage signal lines 80 may, for example, be made of the same material as the gate lines 40 and disposed in the same layer. The common voltage signal lines 80 include a first trace segment 81 and a second trace segment 82. The first trace segment 81 extends along a first direction X, and the second trace segment 82 extends along a second direction Y. In its orthographic projection onto the first substrate 110, the second trace segment 82 overlaps with the pixel electrode 120. Optionally, the first trace segment 81 is disposed at a position passing through or near the center region of the pixel electrode 120.

[0088] Based on this, the second trace segment 82 overlapping with the target pixel electrode 70 (including the first target pixel electrode 71 and the second target pixel electrode 72 mentioned below) includes a first sub-segment 821 and a second sub-segment 822. The first sub-segment 821 is connected to the first bridging wire 50. For example, the common voltage signal line 80 and the gate line 40 are made of the same material and are arranged in the same layer. The first sub-segment 821 is directly connected to the first bridging wire 50. Furthermore, the second sub-segment 822 is connected to the first trace segment 81. There is a second break S2 between the first sub-segment 821 and the second sub-segment 822, so that an open circuit is formed between the first bridging wire 50 and the first trace segment 81, preventing the common voltage signal line 80 from being short-circuited with the gate line 40. Other second trace segments 82 (i.e., second trace segments 82 that do not overlap with the target pixel electrode 70) are integral structures and do not have breaks.

[0089] It should be noted that, as shown in Figures 8 and 9, the first segment 821 can also be insulated from the first bridge wire 50. That is, in the orthographic projection onto the first substrate 110 (see Figure 3), there is a gap between the first segment 821 and the first bridge wire 50. In this case, there is a second break S2 between the first segment 821 and the second segment 822, which can avoid the risk of short-circuiting between the common voltage signal line 80 and the gate line 40 due to the close proximity of the first segment 821 and the first bridge wire 50.

[0090] In some examples, as shown in Figures 7 and 8, in the orthographic projection onto the first substrate 110 (see Figure 3), in the second trace segment 82 overlapping the first target pixel electrode 71, the first sub-segment 821 and the first sub-electrode 711 at least partially overlap, and the end of the second sub-segment 822 near the first sub-segment 821 does not overlap with the first sub-electrode 711, that is, the second sub-segment 822 is located on the side of the first sub-electrode 711 near the second sub-electrode 712. In this case, the second sub-segment 822 does not overlap with the first sub-electrode 711, and no parasitic capacitance is formed between the second sub-segment 822 and the first sub-electrode 711. At this time, the lighting test results are shown in Figure 10. As can be seen from Figure 10, when the first bridge wire 50 transmits signals, it causes the first sub-electrode 711 to generate voltage. The voltage change of the first sub-electrode 711 will not cause the voltage change of the second sub-segment 822. This can avoid the voltage change of the second sub-segment 822 from causing the second sub-electrode 712 to generate voltage, thereby avoiding the deflection of liquid crystal molecules in the area corresponding to the second sub-electrode 712 and avoiding the formation of bright spots at the second sub-electrode 712, thus improving the display effect.

[0091] For example, as shown in Figure 8, the end of the second segment 822 near the first segment 821 does not overlap with the first gap G1. Alternatively, the second segment 822 extends and terminates within the first gap G1, that is, the end of the second segment 822 near the first segment 821 overlaps with the first gap G1, and the end of the second segment 822 near the first segment 811 is located within the first gap G1.

[0092] In other examples, as shown in Figure 9, in the orthographic projection onto the first substrate 110 (see Figure 3), in the second trace segment 82 overlapping the first target pixel electrode 71, the first sub-segment 821 and the first sub-electrode 711 at least partially overlap, and the end of the second sub-segment 822 near the first sub-segment 821 overlaps with the first sub-electrode 711. In this case, the lighting test results are shown in Figure 11. As can be seen from Figure 11, when the first bridging line 50 transmits a signal, it causes the first sub-electrode 711 to generate a voltage. The voltage change of the first sub-electrode 711 causes a voltage change at the end of the second sub-segment 822 near the first sub-segment 821 (such as the part where the second sub-segment 822 overlaps with the first sub-electrode 711). This only causes a local voltage to be generated at the edge of the second sub-electrode 712 near the first sub-electrode 711. That is, when the first bridging line 50 transmits a signal, it indirectly causes a local voltage to be generated at the edge of the second sub-electrode 712 near the first sub-electrode 711, which can improve the bright spots formed at the second sub-electrode 712, thereby improving the display effect.

[0093] In addition, referring to Figures 8 and 9, the common voltage signal line 80 may also include a third trace segment 83, which extends along the second direction Y, and in its orthographic projection onto the first substrate 110, the third trace segment 83 is at least partially located between the pixel electrodes 120.

[0094] Based on this, as shown in Figures 7, 8, and 9, the third trace segment 83, at least partially located between two adjacent target pixel electrodes 70, includes a third sub-segment 831 and a fourth sub-segment 832. The third sub-segment 831 is connected to the first bridging wire 50. For example, the common voltage signal line 80 and the gate line 40 are made of the same material and are disposed in the same layer, and the third sub-segment 831 is directly connected to the first bridging wire 50. Furthermore, the fourth sub-segment 832 is connected to the first trace segment 81. A third break S3 exists between the third sub-segment 831 and the fourth sub-segment 832 to create an open circuit between the first bridging wire 50 and the first trace segment 81, preventing a short circuit between the common voltage signal line 80 and the gate line 40. Other third trace segments 83 (those not located between two adjacent target pixel electrodes 70) are integral structures and do not have breaks.

[0095] Here, the third trace segment 83 may include, for example, a first type of third trace segment 83a and a second type of third trace segment 83b. The first type of third trace segment 83a is located between the pixel electrode 120 and the data line 30, and the second type of third trace segment 83b is located between two adjacent pixel electrodes 120 in a pixel region M. Furthermore, in the orthographic projection onto the first substrate 110, the first type of third trace segment 83a may partially overlap with the pixel electrode 120 or may not overlap with the pixel electrode 120; the second type of third trace segment 83b may partially overlap with the pixel electrode 120 or may not overlap with the pixel electrode 120.

[0096] In some examples, as shown in Figures 8 and 9, in the orthographic projection onto the first substrate 110 (see Figure 3), in the third trace segment 83 (second type third trace segment 83b) adjacent to the first target pixel electrode 71, the third sub-segment 831 and the first sub-electrode 711 at least partially overlap, and the end of the fourth sub-segment 832 near the third sub-segment 831 does not overlap with the first sub-electrode 711, that is, the fourth sub-segment 832 is located on the side of the first sub-electrode 711 near the second sub-electrode 712. In this case, the fourth sub-segment 832 does not overlap with the first sub-electrode 711, and no parasitic capacitance is formed between the fourth sub-segment 832 and the first sub-electrode 711. When the first bridge connection 50 transmits signals, it causes the first sub-electrode 711 to generate voltage. The voltage change of the first sub-electrode 711 will not cause the voltage change of the fourth sub-segment 832. This can prevent the voltage change of the fourth sub-segment 832 from causing the second sub-electrode 712 to generate voltage, thereby preventing the liquid crystal molecules in the area corresponding to the second sub-electrode 712 from being deflected and preventing the formation of bright spots at the second sub-electrode 712, thus improving the display effect.

[0097] For example, as shown in Figure 8, the end of the fourth sub-segment 832 near the third sub-segment 831 does not overlap with the first gap G1. Alternatively, the fourth sub-segment 832 extends and terminates within the first gap G1, that is, the end of the fourth sub-segment 832 near the third sub-segment 831 overlaps with the first gap G1, and the end of the fourth sub-segment 832 near the third sub-segment 831 is located within the first gap G1.

[0098] In other examples, as shown in Figure 9, in the orthographic projection onto the first substrate 110 (see Figure 3), in the third trace segment 83 (second type third trace segment 83b) adjacent to the first target pixel electrode 71, the third sub-segment 831 and the first sub-electrode 711 at least partially overlap, and the end of the fourth sub-segment 832 near the third sub-segment 831 overlaps with the first sub-electrode 711. In this case, when the first bridging line 50 transmits a signal, it causes a voltage to be generated in the first sub-electrode 711. The voltage change of the first sub-electrode 711 causes a voltage change in the end of the fourth sub-segment 832 near the third sub-segment 831 (such as the part where the fourth sub-segment 832 overlaps with the first sub-electrode 711). This only causes a local voltage to be generated at the edge of the second sub-electrode 712 near the fourth sub-segment 832. That is, when the first bridging line 50 transmits a signal, it indirectly causes a local voltage to be generated at the edge of the second sub-electrode 712, which can improve the bright spots formed at the second sub-electrode 712, thereby improving the display effect.

[0099] In some embodiments, referring to Figures 5, 7, 8, and 9, the target pixel electrode 70 further includes a second target pixel electrode 72, which is an integral structure. In its orthographic projection onto the first substrate 110, the second target pixel electrode 712 is offset from the first bridging line 50; for example, the second target pixel electrode 712 is located on the side of the first bridging line 50 away from the connected target signal line 60. For instance, the second target pixel electrode 712 can be formed by peeling away a normal pixel electrode 120, so that the second target pixel electrode 712 is located on the side of the first bridging line 50 away from the connected target signal line 60, thereby avoiding parasitic capacitance between the first bridging line 50 and the second target pixel electrode 712 when transmitting signals, and preventing the formation of bright spots at the second target pixel electrode 712. In this case, the second target pixel electrode 712 can be normally connected to the data line 30 for display, or it can be connected to a constant voltage signal for dimming, such as being connected to the common voltage signal line 80 mentioned below.

[0100] In some embodiments, referring to Figures 5, 7, 8, and 9, the array substrate 10 further includes a common voltage signal line 80, to which the second target pixel electrode 72 can be connected, for example, to the common voltage signal line 80. In this case, the second target pixel electrode 72 is darkened, and no bright spots are formed at the second target pixel electrode 712. Furthermore, in its orthographic projection onto the first substrate 110, the second target pixel electrode 712 can overlap with the first bridging line 50, for example, eliminating the need for a stripping process and reducing costs.

[0101] Example 1, as shown in Figure 8, the first bridging line 50 overlaps with two adjacent pixel electrodes 120. One pixel electrode 120 is the first target pixel electrode 71, and the other pixel electrode 120 is the second target pixel electrode 72. The second target pixel electrode 712 is located on the side of the first bridging line 50 away from the target signal line 60 it is connected to.

[0102] Example 2, as shown in Figure 5, involves the first bridging wire 50 overlapping with three adjacent pixel electrodes 120. One pixel electrode 120 is the first target pixel electrode 71, and the remaining two pixel electrodes 120 are the second target pixel electrodes 72, which are adjacent to each other. For example, both second target pixel electrodes 72 can be connected to a common voltage signal line 80.

[0103] In some embodiments, referring to Figures 5, 7, 8, and 9, the array substrate 10 includes a first transistor 12 and a first interconnect line 90. The first transistor 12 is disposed on a first substrate 110. The first electrode 122 of the first transistor 12 is connected to the data line 30, the second electrode 123 of the first transistor 12 is connected to the pixel electrode 120, and the control electrode 124 of the first transistor 12 is connected to the gate line 40. The first interconnect line 90 is disposed on the first substrate 110, with one end connected to the second electrode 123 of the first transistor 12 and the other end connected to the pixel electrode 120. That is, the data line 30 is connected to the pixel electrode 120 through the first transistor 12 and the first interconnect line 90. Here, the first interconnect line 90 can, for example, be made of the same material as the data line 30 and disposed in the same layer, so that the first interconnect line 90 can be formed in the same process step as the data line 30, facilitating fabrication.

[0104] Based on this, the first connection line 90 connected to the first target pixel electrode 71 is the first target connection line 91, and the second sub-electrode 712 is connected to the second pole 123 of the first transistor 12 through the first target connection line 91. In the orthographic projection onto the first substrate 110, the first target connection line 91 and the first bridge line 50 are staggered, that is, the first target connection line 91 and the first bridge line 50 do not overlap. The gap between the first sub-electrode 711 and the second sub-electrode 712 (i.e., the first gap G1) is located between the first target connection line 91 and the first bridge line 50, that is, the first gap G1 does not overlap with either the first target connection line 91 or the first bridge line 50. In this case, during the process of stripping the pixel electrode 120 located at the first gap G1 to form the first target pixel electrode 71, the first gap G1 does not overlap with the first target connection line 91 and the first bridging line 50. This can avoid the risk of short-circuiting the first target connection line 91 and the first target pixel electrode 71 during the process of stripping the pixel electrode 120, as well as the risk of short-circuiting the first bridging line 50 and the first target pixel electrode 71.

[0105] Furthermore, the first connection line 90 connected to the second target pixel electrode 72 is the second target connection line 92. In its orthographic projection onto the first substrate 110, the second target connection line 92 overlaps with the first bridging line 50. In this case, the second target pixel electrode 72 can be directly connected to the common voltage signal line 80, for example. This eliminates the need for a stripping process to form the second target pixel electrode 72, thus avoiding the risk of short-circuiting between the second target connection line 92 and the second target pixel electrode 72 during the stripping of the pixel electrode 120.

[0106] Figure 12 is a characteristic test analysis diagram of the first transistor of the array substrate shown in Figures 8 and 9. In Example 1, the characteristic test curve of the first transistor of the array substrate shown in Figure 8 is shown; in Example 2, the characteristic test curve of the first transistor 12 of the array substrate 10 shown in Figure 9 is shown. The index is the design benchmark for the characteristic test curve of the first transistor 12 of the array substrate 10. As can be seen from Figure 12, the characteristics of the first transistor 12 of the array substrate 10 in this embodiment of the present disclosure are not abnormal, that is, the characteristics of the first transistor 12 of the repaired array substrate 10 are not abnormal. Specific repair processes can be referred to below.

[0107] Some embodiments of this disclosure also provide a method for repairing an array substrate, used to form the array substrate 10 of any of the above embodiments. Referring to FIG14, the repair method includes S100 to S500.

[0108] S100: Fabrication of array substrate.

[0109] Referring to Figures 3, 4, and 5, the array substrate 10 includes a first substrate 110 and a plurality of signal lines disposed on the first substrate 110. The plurality of signal lines include a plurality of gate lines 40, or the plurality of signal lines include a plurality of gate lines 40 and a plurality of data lines 30. The gate lines 40 extend along a first direction X, and the plurality of gate lines 40 are spaced apart along a second direction Y. The first direction X intersects with the second direction Y. The data lines 30 extend along the second direction Y, and the plurality of data lines 30 are spaced apart along the first direction X. The intersection of the plurality of data lines 30 and the plurality of gate lines 40 defines a plurality of pixel regions M.

[0110] It should be noted that the position and structure of the data line 30 and the gate line 40 can be referred to the above, and will not be repeated here in the embodiments disclosed herein.

[0111] S200: Determine the target signal line.

[0112] In the above steps, referring to Figures 5 and 6, the target signal line 60 is a data line 30 or a gate line 40 with a first break S1. The figures illustrate data line 30 as an example, and gate line 40 as an example. Whether data line 30 or gate line 40 has a break can be determined by current and voltage detection. When data line 30 or gate line 40 has a break, it is an open circuit, and there is no current or voltage signal, thus identifying the target signal line 60.

[0113] S300: Form the first bridge connection.

[0114] In the above steps, referring to Figures 5 and 6, the two ends of the first break S1 of the target signal line 60 are connected by a first bridging wire 50, which can be formed by laser deposition. Furthermore, the first bridging wire 50 can be made of the same material as the target signal line 60 and be disposed in the same layer, resulting in lower manufacturing costs. Of course, the first bridging wire 50 can also be located in a different layer from the target signal line 60. For example, if the target signal line 60 is a gate line 40, the first bridging wire 50 can be made of the same material as the data line 30 and be disposed in the same layer. This embodiment does not specifically limit this approach.

[0115] S400: Forms pixel electrodes.

[0116] In the above steps, referring to Figures 5 and 6, the pixel electrode 120 is located in the pixel region M. In the orthographic projection onto the first substrate 110, the first bridging line 50 overlaps with at least one pixel electrode 120. The pixel electrode 120 overlapping with the first bridging line 50 is the target pixel electrode 70, which includes a first target pixel electrode 71.

[0117] S500: Strip a portion of the first target pixel electrode to form a first sub-electrode and a second sub-electrode.

[0118] In the above steps, referring to Figures 5 and 6, the first sub-electrode 711 and the second sub-electrode 712 are spaced apart, and in their orthogonal projection onto the first substrate 110, the first sub-electrode 711 overlaps with the first bridge connection 50, while the second sub-electrode 712 is offset from the first bridge connection 50. A portion of the first target pixel electrode 71 can be removed using laser cutting, or other processes can be used, such as etching. This embodiment does not specifically limit the removal of the first target pixel electrode 71. Furthermore, whether the removal of the first target pixel electrode 71 is complete can be determined by scanning electron microscopy (SEM) analysis. For example, the material of the first target pixel electrode 71 is indium tin oxide (ITO). In this case, indium is analyzed using SEM. Figure 13 is a SEM analysis of the indium content of an array substrate according to some embodiments. As shown in Figure 13, no indium atoms are present in the gaps, indicating that the indium atoms have been completely removed.

[0119] The method for repairing an array substrate provided in this disclosure has the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here.

[0120] In some embodiments, referring to Figures 5 and 6, the array substrate 10 further includes a plurality of common voltage signal lines 80, which are disposed on the first substrate 110, and the common voltage signal lines 80 may, for example, be made of the same material as the gate lines 40 and disposed in the same layer. In this case, the common voltage signal lines 80 may, for example, be formed synchronously with the gate lines 40 in the same process step.

[0121] The common voltage signal line 80 includes a first trace segment 81 and a second trace segment 82. The first trace segment 81 extends along a first direction X, and the second trace segment 82 extends along a second direction Y. In its orthographic projection onto the first substrate 110, the second trace segment 82 overlaps with the pixel electrode 120. Furthermore, the second trace segment 82 that overlaps with the target pixel electrode 70 (including the first target pixel electrode 71 and the second target pixel electrode 72 mentioned below) is connected to the first bridging line 50.

[0122] At this point, referring to Figure 15, after S300, the repair method also includes S600.

[0123] S600: Cut the second trace segment that overlaps with the target pixel electrode to form the first sub-segment and the second sub-segment.

[0124] In the above steps, the first sub-segment 821 is connected to the first bridge wire 50, and the second sub-segment 822 is connected to the first trace segment 81, with a second break S2 between the first sub-segment 821 and the second sub-segment 822. The second trace segment 82 can be cut using laser ablation, or other processes such as etching can be used; this embodiment does not specifically limit the method used.

[0125] In some embodiments, referring to FIG5 and FIG7, the array substrate 10 further includes a common voltage signal line 80, and the target pixel electrode 70 further includes a second target pixel electrode 72. Referring to FIG16 and FIG17, after S400, the repair method further includes S700 and / or S800.

[0126] S700: Part of the second target pixel electrode is stripped so that the second target pixel electrode is staggered from the first bridge wire.

[0127] In the above steps, the second target pixel electrode 712 can be located, for example, on the side of the first bridge connection 50 away from the connected target signal line 60. A portion of the second target pixel electrode 72 can be removed using a laser cutting method, or other processes can be used, such as etching. This embodiment does not specifically limit the method used.

[0128] It should be noted that S500 and S700 can be prepared in the same process or separately, and there is no difference in the order of preparation. For example, S500 can be performed first and then S700 can be performed. This disclosure does not specifically limit this.

[0129] S800: Connect the second target pixel electrode to the common voltage signal line.

[0130] In the above steps, a laser can be used to break down the film layer between the second target pixel electrode 72 and the common voltage signal line 80, and melt the second target pixel electrode 72, thereby connecting the second target pixel electrode 72 and the common voltage signal line 80. Alternatively, conductive material can be deposited separately into the holes of the film layer between the second target pixel electrode 72 and the common voltage signal line 80 to connect the second target pixel electrode 72 and the common voltage signal line 80; this embodiment does not specifically limit this approach.

[0131] It should be noted that S500, S700 and S800 can be prepared separately, and there is no specific order to them. For example, S500 can be performed first, followed by S700 and S800 in sequence. This embodiment does not specifically limit this.

[0132] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0133] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: First substrate; Multiple gate lines are disposed on the first substrate; The grid lines extend along a first direction, and the plurality of grid lines are spaced apart along a second direction; The first direction intersects with the second direction; Multiple data lines are disposed on the first substrate; the data lines extend along the second direction and are spaced apart along the first direction; the multiple data lines and the multiple gate lines intersect to define multiple pixel regions, each pixel region including at least one pixel sub-region; A first bridge connection is disposed on the first substrate; at least one of the data lines or the gate line has a first break, and the data line or the gate line with the first break is a target signal line; the two ends of the first break of the target signal line are connected through the first bridge connection. Multiple pixel electrodes are disposed on the first substrate, and one pixel electrode is located in one pixel sub-region; In the orthographic projection onto the first substrate, the first bridging line overlaps with at least one of the pixel sub-regions; wherein the pixel sub-region overlapping with the first bridging line is a target pixel sub-region, and the pixel electrode located in the target pixel sub-region is a target pixel electrode; The target pixel electrode includes a first target pixel electrode, the first target pixel electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are spaced apart and projected onto the first substrate, the first sub-electrode overlaps with the first bridging line, and the second sub-electrode is offset from the first bridging line.

2. The array substrate according to claim 1, wherein, The gate line is the target signal line.

3. The array substrate according to claim 2, comprising: Multiple common voltage signal lines are disposed on the first substrate; The common voltage signal line includes a first trace segment and a second trace segment. The first trace segment extends along the first direction, and the second trace segment extends along the second direction. In the orthographic projection onto the first substrate, the second trace segment overlaps with the pixel electrode. The second trace segment overlapping with the target pixel electrode includes a first sub-segment and a second sub-segment. The first sub-segment is connected to the first bridging wire, and the second sub-segment is connected to the first trace segment. A second break is present between the first sub-segment and the second sub-segment.

4. The array substrate according to claim 3, wherein, There is a first gap between the first sub-electrode and the second sub-electrode; in the orthographic projection onto the first substrate, in the second trace segment that overlaps with the first target pixel electrode, the first sub-segment and the first sub-electrode at least partially overlap, and the end of the second sub-segment near the first sub-segment does not overlap with the first sub-electrode.

5. The array substrate according to claim 4, wherein, There is a first gap between the first sub-electrode and the second sub-electrode; in the orthographic projection onto the first substrate, in the second trace segment that overlaps with the first target pixel electrode, the first sub-segment and the first sub-electrode at least partially overlap, and the end of the second sub-segment near the first sub-segment overlaps with the first sub-electrode.

6. The array substrate according to any one of claims 2 to 5, comprising: Multiple common voltage signal lines are disposed on the first substrate; The common voltage signal line includes a first trace segment and a third trace segment. The first trace segment extends along the first direction, and the third trace segment extends along the second direction. In a positive projection onto the first substrate, the third trace segment is at least partially located between the pixel electrodes. A third trace segment, at least partially located between two adjacent target pixel electrodes, includes a third sub-segment and a fourth sub-segment. The third sub-segment is connected to the first bridging wire, and the fourth sub-segment is connected to the first trace segment. A third break is present between the third sub-segment and the fourth sub-segment.

7. The array substrate according to claim 6, wherein, There is a first gap between the first sub-electrode and the second sub-electrode; in the orthographic projection onto the first substrate, in the third trace segment adjacent to the first target pixel electrode, the third sub-segment and the first sub-electrode at least partially overlap, and the end of the fourth sub-segment near the third sub-segment does not overlap with the first sub-electrode.

8. The array substrate according to claim 6, wherein, There is a first gap between the first sub-electrode and the second sub-electrode; in the orthographic projection onto the first substrate, in the third trace segment adjacent to the first target pixel electrode, the third sub-segment and the first sub-electrode at least partially overlap, and the fourth sub-segment near the end of the third sub-segment overlaps with the first sub-electrode.

9. The array substrate according to any one of claims 1 to 8, wherein, The first bridge wire is made of the same material as the target signal wire and is installed in the same layer.

10. The array substrate according to any one of claims 1 to 9, further comprising: A first transistor is disposed on the first substrate; the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the pixel electrode, and the control electrode of the first transistor is connected to the gate line. A first connecting line is disposed on the first substrate; one end of the first connecting line is connected to the second electrode of the first transistor, and the other end is connected to the pixel electrode; wherein, the first connecting line connected to the first target pixel electrode is a first target connecting line, the second sub-electrode is connected to the second electrode of the first transistor through the first target connecting line, and in the orthographic projection onto the first substrate, the first target connecting line is staggered from the first bridging line, and the gap between the first sub-electrode and the second sub-electrode is located between the first target connecting line and the first bridging line.

11. The array substrate according to any one of claims 1 to 10, wherein, The target pixel electrode further includes a second target pixel electrode, which is an integral structure; In a projection onto the first substrate, the second target pixel electrode is offset from the first bridge line; and / or, the array substrate further includes a common voltage signal line, to which the second target pixel electrode is connected.

12. The array substrate according to claim 11, wherein, The array substrate further includes a common voltage signal line, and the second target pixel electrode is connected to the common voltage signal line; the array substrate further includes: A first transistor is disposed on the first substrate; the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the pixel electrode, and the control electrode of the first transistor is connected to the gate line. A first connecting line is disposed on the first substrate; one end of the first connecting line is connected to the second electrode of the first transistor, and the other end is connected to the pixel electrode; the first connecting line connected to the second target pixel electrode is the second target connecting line, and in the orthographic projection onto the first substrate, the second target connecting line overlaps with the first bridging line.

13. The array substrate according to any one of claims 1 to 12, wherein, There is a first gap between the first sub-electrode and the second sub-electrode, and the orthographic projection of the first gap on the first substrate is L-shaped.

14. The array substrate according to any one of claims 1 to 13, wherein, The plurality of pixel electrodes are arranged in an array along the first direction and the second direction; Along the second direction, a gate line is respectively provided on each of the opposite sides of the plurality of pixel electrodes, and two gate lines are provided between two adjacent rows of pixel electrodes; two columns of pixel electrodes are provided between each pair of adjacent data lines; a pixel region is defined between the two adjacent data lines and the two gate lines adjacent to the opposite sides of a row of pixel electrodes, and each pixel region is provided with two pixel electrodes.

15. The array substrate according to claim 14, wherein, Pixel electrodes located in the same pixel region are connected to the same data line, and pixel electrodes of two adjacent pixel regions in the second direction are connected to different data lines; and the multiple data lines include multiple first data lines and multiple second data lines, and the first data lines and second data lines are arranged alternately along the first direction; In this configuration, two pixel electrodes located within the same pixel region are designated as a first pixel electrode and a second pixel electrode, respectively. The first pixel electrode is located between the second pixel electrode and the connected data line. The first data line is connected to the first pixel electrode in the pixel region on a first side of the pixel region and to the second pixel electrode in the pixel region on a second side of the pixel region. The second data line is connected to the first pixel electrode in the pixel region on a second side of the pixel region and to the second pixel electrode in the pixel region on a first side of the pixel region. The first side and the second side of the pixel region are opposite sides of the pixel region in the second direction.

16. The array substrate according to claim 14 or 15, wherein, The gate line is the target signal line, and the first bridging line is located on the side of the target signal line near the adjacent pixel area.

17. A display panel, comprising: The array substrate as described in any one of claims 1 to 16; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

18. A display device, comprising: The display panel as described in claim 17; The circuit board is connected to the display panel.

19. A method for repairing an array substrate, comprising: An array substrate is fabricated; the array substrate includes a first substrate and a plurality of signal lines disposed on the first substrate; the plurality of signal lines include a plurality of gate lines, or the plurality of signal lines include a plurality of gate lines and a plurality of data lines; wherein the gate lines extend along a first direction, and the plurality of gate lines are spaced apart along a second direction; the first direction intersects the second direction; the data lines extend along the second direction, and the plurality of data lines are spaced apart along the first direction; the plurality of data lines and the plurality of gate lines intersect to define a plurality of pixel regions, each pixel region including at least one pixel sub-region; Identify the target signal line; the target signal line is the data line or the gate line having the first break. A first bridge connection is formed; the two ends of the first break of the target signal line are connected through the first bridge connection; A pixel electrode is formed; one of the pixel electrodes is located in one of the pixel sub-regions; in a positive projection onto the first substrate, the first bridging line overlaps with at least one of the pixel sub-regions; the pixel sub-region overlapping with the first bridging line is a target pixel sub-region, and the pixel electrode located in the target pixel sub-region is a target pixel electrode; the target pixel electrode includes the first target pixel electrode; A portion of the first target pixel electrode is stripped to form a first sub-electrode and a second sub-electrode; the first sub-electrode and the second sub-electrode are spaced apart and, in their orthogonal projection onto the first substrate, the first sub-electrode overlaps with the first bridging line, and the second sub-electrode is offset from the first bridging line.

20. The method for repairing an array substrate according to claim 19, wherein, The array substrate further includes multiple common voltage signal lines disposed on the first substrate; the common voltage signal lines include a first trace segment and a second trace segment, the first trace segment extends along the first direction, the second trace segment extends along the second direction, and in the orthographic projection onto the first substrate, the second trace segment overlaps with the pixel electrode; The second trace segment overlapping the target pixel electrode is connected to the first bridging wire; After the formation of the first bridge connection, the repair method further includes: The second trace segment overlapping with the target pixel electrode is cut off to form a first sub-segment and a second sub-segment; The first sub-segment is connected to the first bridge wire, the second sub-segment is connected to the first wiring segment, and there is a second break between the first sub-segment and the second sub-segment.

21. The method for repairing an array substrate according to claim 19 or 20, wherein, The target pixel electrode further includes the second target pixel electrode; After forming the pixel electrode, the repair method further includes: peeling off a portion of the second target pixel electrode, such that the second target pixel electrode is offset from the first bridging wire; and / or, The array substrate also includes a common voltage signal line. After the pixel electrode is formed, the repair method further includes connecting the second target pixel electrode to the common voltage signal line.

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