Pixel circuit, driving method, and display apparatus

Abstract

Provided are a pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises a first pixel driving circuit (11), a second pixel driving circuit (12), and a display control circuit (13). Under the control of a first data voltage (DTA), the first pixel driving circuit (11) controls whether to provide a first driving current to a display node (ND). Under the control of a second data voltage (DTB), the second pixel driving circuit (12) controls whether to provide a second driving current to a writing node (NW). Under the control of a display control scan signal (GT), the display control circuit (13) controls whether to write the second driving current to the writing node (NW) according to a control data voltage (DT). The pixel circuit, the driving method, and the display apparatus achieve low-power display.

Description

Pixel circuits, driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, driving method, and display device. Background Technology

[0002] MLED devices (which can include Micro LEDs or Mini-LEDs) are considered next-generation display panel technologies due to their low driving voltage, ultra-high brightness, long lifespan, and high temperature resistance. Compared to the tens of nA-level current driving of OLEDs (Organic Light Emitting Diodes), the pixel current of Micro LEDs / Mini-LEDs is in the μA or mA level. If the pixels are driven using only pulse amplitude modulation, the pixel current will be too large, requiring the driving transistors in the pixel circuit to use a larger gate-source voltage. To ensure the driving transistors operate in the saturation region, the drain-source voltage Vds of the driving transistors needs to be increased to control the pixel current. However, increasing Vds will increase the power consumption of the display panel; if Vds is decreased, the driving transistors will operate in the linear region, making grayscale control difficult. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a pixel circuit, including a first pixel driving circuit, a second pixel driving circuit, and a display control circuit;

[0004] The first pixel driving circuit is electrically connected to the first data voltage terminal and the display node respectively, and is used to control whether to provide a first driving current to the display node under the control of the first data voltage provided by the first data voltage terminal;

[0005] The second pixel driving circuit is electrically connected to the second data voltage terminal and the write node respectively, and is used to control whether to provide a second driving current to the write node under the control of the second data voltage provided by the second data voltage terminal;

[0006] The display control circuit is electrically connected to the display control scanning terminal, the control data voltage terminal, the writing node, and the display node, respectively, and is used to control whether to write the second driving current to the writing node according to the control data voltage provided by the control data voltage terminal under the control of the display control scanning signal provided by the display control scanning terminal.

[0007] Optionally, the display control circuit is also electrically connected to the switch control voltage terminal, and is used to control whether to write the second drive current into the write node under the control of the display control scan signal, based on the control data voltage and the switch control voltage provided by the switch control voltage terminal.

[0008] Optionally, the display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit;

[0009] The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node;

[0010] The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal and the display control node respectively, and is used to write the control data voltage into the display control node under the control of the display control scanning signal;

[0011] The display control reset circuit is electrically connected to the display reset control terminal and the display control node, respectively. The display control reset circuit is also electrically connected to the display reset voltage terminal or the first voltage terminal, and is used to write the display reset voltage provided by the display reset voltage terminal or the first voltage signal provided by the first voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal.

[0012] The first terminal of the first energy storage circuit is electrically connected to the display control node, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal.

[0013] Optionally, the display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, a first energy storage circuit, and a control circuit;

[0014] The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node;

[0015] The control circuit is electrically connected to the control node, the second voltage terminal, the third voltage terminal and the display control node respectively, and is used to control the display control node to connect with the second voltage terminal or the third voltage terminal under the control of the potential of the control node;

[0016] The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal and the control node respectively, and is used to write the control data voltage into the control node under the control of the display control scanning signal;

[0017] The display control reset circuit is electrically connected to the display reset control terminal, the display reset voltage terminal, and the display control node, respectively, and is used to write the display reset voltage provided by the display reset voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal;

[0018] The first terminal of the first energy storage circuit is electrically connected to the control node, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal.

[0019] Optionally, the display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit;

[0020] The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node;

[0021] The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal, and the display control node, respectively, and is used to control the connection or disconnection between the control data voltage terminal and the display control node under the control of the display control scanning signal;

[0022] The display control reset circuit is electrically connected to the display reset control terminal, the display reset voltage terminal, and the display control node, respectively, and is used to write the display reset voltage provided by the display reset voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal;

[0023] The first terminal of the first energy storage circuit is electrically connected to the display control node, and the second terminal of the first energy storage circuit is electrically connected to the switch control voltage terminal.

[0024] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor;

[0025] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0026] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the display control node.

[0027] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node.

[0028] The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

[0029] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the control circuit includes a fourth transistor and a fifth transistor;

[0030] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0031] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the control node.

[0032] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node.

[0033] The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

[0034] The gate of the fourth transistor is electrically connected to the control node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the display control node.

[0035] The gate of the fifth transistor is electrically connected to the control node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the display control node.

[0036] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor and a sixth transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor;

[0037] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0038] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor, the gate of the sixth transistor, and the second terminal of the sixth transistor are electrically connected, and the second terminal of the second transistor is electrically connected to the display control node;

[0039] The first terminal of the sixth transistor is electrically connected to the control data voltage terminal.

[0040] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node.

[0041] The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the switch control voltage terminal.

[0042] Optionally, the pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element; the first pixel driving circuit includes a first driving circuit; the first driving circuit is used to control whether to generate a first driving current under the control of the first data voltage; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal;

[0043] The display node is electrically connected to the first terminal of the light-emitting element; or, the display node is electrically connected to the second terminal of the first driving circuit.

[0044] Optionally, the first pixel driving circuit further includes a first light emission control circuit;

[0045] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0046] Optionally, the first pixel driving circuit further includes a second light emission control circuit, a first data writing circuit, a first compensation control circuit, a first initialization circuit, and a second energy storage circuit.

[0047] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first power supply voltage terminal, and the first terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0048] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first terminal of the first driving circuit, respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first terminal of the first driving circuit under the control of the first scanning signal provided by the first scanning terminal.

[0049] The first compensation control circuit is electrically connected to the first scanning terminal, the control terminal of the first driving circuit, and the second terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the control terminal of the first driving circuit and the second terminal of the first driving circuit under the control of the first scanning signal.

[0050] The first initialization circuit is electrically connected to the first reset control terminal, the second initial voltage terminal, and the control terminal of the first driving circuit, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the first driving circuit under the control of the first reset control signal provided by the first reset control terminal.

[0051] The second energy storage circuit is electrically connected to the control terminal of the first drive circuit to maintain the potential of the control terminal of the first drive circuit.

[0052] Optionally, the first pixel driving circuit further includes a second initialization circuit;

[0053] The second initialization circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0054] Optionally, the second pixel driving circuit includes a second driving circuit, a third light emission control circuit, a second data writing circuit, a second compensation control circuit, a third initialization circuit, and a third energy storage circuit.

[0055] The second terminal of the second driving circuit is electrically connected to the write node; the second driving circuit is used to control whether to generate a second driving current under the control of the second data voltage;

[0056] The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal.

[0057] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the first terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal into the first terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal;

[0058] The second compensation control circuit is electrically connected to the second scanning terminal, the control terminal of the second driving circuit, and the second terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit and the second terminal of the second driving circuit under the control of the second scanning signal.

[0059] The third initialization circuit is electrically connected to the third reset control terminal, the fourth initial voltage terminal and the control terminal of the second drive circuit, respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the control terminal of the second drive circuit under the control of the third reset control signal provided by the third reset control terminal.

[0060] The third energy storage circuit is electrically connected to the control terminal of the second drive circuit and is used to maintain the potential of the control terminal of the second drive circuit.

[0061] Optionally, at least two of the display reset control terminal, the first reset control terminal, the second reset control terminal, and the third reset control terminal are the same reset control terminal; and / or,

[0062] The first scanning end and the second scanning end are the same scanning end; and / or,

[0063] At least two of the first initial voltage terminal, the second initial voltage terminal, the third initial voltage terminal, and the fourth initial voltage terminal are the same initial voltage terminal.

[0064] Optionally, the first data voltage terminal, the second data voltage terminal, and the control data voltage terminal are the same data voltage terminal;

[0065] The first scanning end is the nth level scanning end, the second scanning end is the (n+1)th level scanning end, and the display control scanning end is the (n+2)th level scanning end;

[0066] n is a positive integer.

[0067] Optionally, at least one of the transistors included in the first initialization circuit, the first compensation control circuit, the third initialization circuit, the second compensation control circuit, the display control writing circuit, the display control reset circuit, the first data writing circuit, and the second data writing circuit is an n-type transistor; and / or,

[0068] At least one of the transistors included in the first driving circuit, the transistors included in the second driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the third light-emitting control circuit, and the transistors included in the on / off control circuit is a p-type transistor.

[0069] Optionally, the first pixel driving circuit further includes a fourth energy storage circuit, a first data writing circuit, and a switch control circuit.

[0070] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the control terminal of the first driving circuit, respectively, and is used to write the first data voltage provided by the first data voltage terminal to the control terminal of the first driving circuit under the control of the first scanning signal provided by the first scanning terminal.

[0071] The first terminal of the fourth energy storage circuit is electrically connected to the control terminal of the first drive circuit, and the second terminal of the fourth energy storage circuit is electrically connected to the second terminal of the first drive circuit.

[0072] The switch control circuit is electrically connected to the third scanning terminal, the external compensation sensing line, and the second terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the second terminal of the first driving circuit under the control of the third scanning signal provided by the third scanning terminal.

[0073] Optionally, the first pixel driving circuit further includes a second light emission control circuit;

[0074] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first power supply voltage terminal, and the first terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal; or...

[0075] The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0076] Optionally, the first pixel driving circuit further includes a first switching circuit and a second switching circuit.

[0077] The first switching circuit is electrically connected to the first switching control terminal, the external compensation sensing line, and the reference voltage terminal, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the external compensation sensing line under the control of the first switching control signal provided by the first switching control terminal.

[0078] The second switching circuit is electrically connected to the second switch control terminal, the external compensation sensing line, and the sensing terminal, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the sensing terminal under the control of the second switch control signal provided by the second switch control terminal.

[0079] Optionally, the second pixel driving circuit includes a second driving circuit, a second data writing circuit, and a third energy storage circuit;

[0080] The first end of the second driving circuit is electrically connected to the second power supply voltage terminal, and the second end of the second driving circuit is electrically connected to the write node;

[0081] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal, and the control terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal to the control terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal.

[0082] The first end of the third energy storage circuit is electrically connected to the control end of the second driving circuit, and the second end of the third energy storage circuit is electrically connected to the write node.

[0083] Optionally, the second pixel driving circuit further includes a third light emission control circuit;

[0084] The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal.

[0085] Optionally, the first pixel driving circuit further includes a second light emission control circuit;

[0086] The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0087] The display node is electrically connected to the second terminal of the first driving circuit.

[0088] Optionally, the first light-emitting control circuit includes a seventh transistor; the first driving circuit includes a first driving transistor.

[0089] The gate of the seventh transistor is electrically connected to the first light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0090] The second light-emitting control circuit includes an eighth transistor, the first data writing circuit includes a ninth transistor, the first compensation control circuit includes a tenth transistor, the first initialization circuit includes an eleventh transistor, and the second energy storage circuit includes a second capacitor.

[0091] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor.

[0092] The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first terminal of the first driving transistor.

[0093] The gate of the tenth transistor is electrically connected to the first scan terminal, the first terminal of the tenth transistor is electrically connected to the gate of the first driving transistor, and the second terminal of the tenth transistor is electrically connected to the second terminal of the first driving transistor.

[0094] The gate of the eleventh transistor is electrically connected to the first reset control terminal, the first terminal of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the gate of the first driving transistor.

[0095] The first terminal of the second capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the second capacitor is electrically connected to the first DC voltage terminal.

[0096] The second initialization circuit includes a twelfth transistor;

[0097] The gate of the twelfth transistor is electrically connected to the second reset control terminal, the first terminal of the twelfth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the first terminal of the light-emitting element.

[0098] Optionally, the second driving circuit includes a second driving transistor, the third light-emitting control circuit includes a thirteenth transistor, the second data writing circuit includes a fourteenth transistor, the second compensation control circuit includes a fifteenth transistor, the third initialization circuit includes a sixteenth transistor, and the third energy storage circuit includes a third capacitor.

[0099] The second terminal of the second driving transistor is electrically connected to the write node;

[0100] The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor.

[0101] The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the second drive transistor.

[0102] The gate of the fifteenth transistor is electrically connected to the second scan terminal, the first terminal of the fifteenth transistor is electrically connected to the gate of the second driving transistor, and the second terminal of the fifteenth transistor is electrically connected to the second terminal of the second driving transistor.

[0103] The gate of the sixteenth transistor is electrically connected to the third reset control terminal, the first terminal of the sixteenth transistor is electrically connected to the fourth initial voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the gate of the second driving transistor.

[0104] The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the second DC voltage terminal.

[0105] Optionally, the first driving circuit includes a first driving transistor; the fourth energy storage circuit includes a fourth capacitor; the first terminal of the fourth capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the fourth capacitor is electrically connected to the second terminal of the first driving transistor.

[0106] The first data writing circuit includes a ninth transistor, and the switch control circuit includes a seventeenth transistor;

[0107] The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the gate of the first driving transistor.

[0108] The gate of the seventeenth transistor is electrically connected to the third scanning terminal, the first terminal of the seventeenth transistor is electrically connected to the external compensation sensing line, and the second terminal of the seventeenth transistor is electrically connected to the second terminal of the first driving transistor.

[0109] Optionally, the second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor.

[0110] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor; or...

[0111] The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal; the gate of the eighth transistor is electrically connected to the second light-emitting control terminal; the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor; and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0112] Optionally, the first switching circuit includes a first switch, and the second switching circuit includes a second switch;

[0113] The control terminal of the first switch is electrically connected to the control terminal of the first switch, the first terminal of the first switch is electrically connected to the external compensation sensing line, and the second terminal of the first switch is electrically connected to the reference voltage terminal.

[0114] The control terminal of the second switch is electrically connected to the control terminal of the second switch, the first terminal of the second switch is electrically connected to the external compensation sensing line, and the second terminal of the second switch is electrically connected to the sensing terminal.

[0115] Optionally, the second driving circuit includes a second driving transistor, the second data writing circuit includes a fourteenth transistor, and the third energy storage circuit includes a third capacitor;

[0116] The first terminal of the second driving transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the second driving transistor is electrically connected to the write node;

[0117] The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the gate of the second driving transistor.

[0118] The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the write node.

[0119] Optionally, the third light-emitting control circuit includes a thirteenth transistor;

[0120] The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor.

[0121] Optionally, the second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor.

[0122] The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal;

[0123] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0124] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned pixel circuit, the driving method comprising:

[0125] The first pixel driving circuit, under the control of the first data voltage, controls whether to provide the first driving current to the display node;

[0126] The second pixel driving circuit, under the control of the second data voltage, controls whether to provide the second driving current to the write node;

[0127] Under the control of the display control scan signal, the display control circuit controls whether to write the second drive current into the write node according to the control data voltage.

[0128] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0129] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0130] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0131] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0132] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0133] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0134] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0135] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0136] Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0137] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0138] Figure 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0139] Figure 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0140] Figure 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0141] Figure 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0142] Figure 14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0143] Figure 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0144] Figure 16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0145] Figure 17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0146] Figure 18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0147] Figure 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0148] Figure 20A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 19 of this disclosure;

[0149] Figure 20B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 19 of this disclosure;

[0150] Figures 21A, 21B, 21C, 21D and 21E are schematic diagrams of the working state of at least one embodiment of the pixel circuit shown in Figure 19;

[0151] Figure 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0152] Figure 23 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 22 of this disclosure;

[0153] Figure 24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0154] Figure 25 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 24 of this disclosure;

[0155] Figure 26 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0156] Figure 27 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 26 of this disclosure;

[0157] Figure 28 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0158] Figure 29 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0159] Figure 30 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 29 of this disclosure;

[0160] Figures 31A, 31B, 31C and 31D are schematic diagrams of the working state of at least one embodiment of the pixel circuit shown in Figure 30;

[0161] Figure 32 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0162] Figure 33 is a circuit diagram showing at least one embodiment of the control circuit;

[0163] Figure 34 is a circuit diagram showing at least one embodiment of the control circuit;

[0164] Figure 35 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0165] Figure 36 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0166] Figures 37A, 37B, 37C, 37D, 37E and 37F are schematic diagrams of the working state of at least one embodiment of the pixel circuit shown in Figure 35;

[0167] Figure 38 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0168] Figure 39 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0169] Figure 40A is a schematic diagram of the light emission state of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0170] Figure 40B is a schematic diagram of the light emission state of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0171] Figure 41A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0172] Figure 41B is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure;

[0173] Figure 42 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0174] Figure 43 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 42 of this disclosure. Detailed Implementation

[0175] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0176] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0177] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0178] As shown in Figure 1, the pixel circuit of this embodiment includes a first pixel driving circuit 11, a second pixel driving circuit 12, and a display control circuit 13.

[0179] The first pixel driving circuit 11 is electrically connected to the first data voltage terminal DTA and the display node ND respectively, and is used to control whether to provide a first driving current to the display node ND under the control of the first data voltage provided by the first data voltage terminal DTA.

[0180] The second pixel driving circuit 12 is electrically connected to the second data voltage terminal DTB and the write node NW respectively, and is used to control whether to provide a second driving current to the write node NW under the control of the second data voltage provided by the second data voltage terminal DTB.

[0181] The display control circuit 13 is electrically connected to the display control scanning terminal GT, the control data voltage terminal DT, the write node NW, and the display node ND, respectively. It is used to control whether to write the second driving current into the write node NW according to the control data voltage provided by the control data voltage terminal DT under the control of the display control scanning signal provided by the display control scanning terminal GT.

[0182] This disclosure provides a pixel circuit that drives a light-emitting element together through a first pixel driving circuit 11, a second pixel driving circuit 12, and a display control circuit 13. By increasing the current, the driving current generated by the first pixel driving circuit 11 and the second pixel driving circuit 12 is reduced, thereby reducing the voltage across the first driving transistor in the first pixel driving circuit 11 and the voltage across the second driving transistor in the second pixel driving circuit 12. This reduces the power consumption damage of the first driving transistor and the power consumption loss of the second driving transistor, achieving a low-power display.

[0183] In at least one embodiment of this disclosure, the cross voltage of the driving transistor can be the drain-source voltage Vds of the driving transistor, but is not limited thereto.

[0184] In practical implementation, when the pixel current flowing through the light-emitting element is Id, the driving current generated by the first pixel driving circuit 11 and the second pixel driving circuit 12 is 0.5Id, which is sufficient to meet the light-emitting requirements of the light-emitting element. For example, when the current value of Id is 30μA, the drain-source current Vds1 of the first driving transistor and the drain-source voltage Vds2 of the second driving transistor can be reduced by 25%.

[0185] When the pixel circuit described in the embodiments of this disclosure is in operation...

[0186] When performing high grayscale display, the first pixel driving circuit 11 and the second pixel driving circuit 12 can be used together to provide the pixel current Id;

[0187] When displaying low to medium grayscale levels, the display control circuit 13 can control the disconnection between the write node NW and the display node ND, and drive the light-emitting element to emit light through the first pixel driving circuit 11, which can reduce the bias time of the second driving transistor included in the second pixel driving circuit 12; or,

[0188] When performing low-to-medium grayscale display, the display control circuit 13 can control the connection between the write node NW and the display node ND. By controlling the driving current generated by the first pixel driving circuit 11 to be 0 through the first data voltage, and by providing the pixel current Id through the second pixel driving circuit 12, the bias time of the first driving transistor included in the first pixel driving circuit 11 can be reduced.

[0189] The pixel circuit described in at least one embodiment of this disclosure can reduce the power consumption of the driving transistor and the power consumption of the backplane. By adopting a redundant pixel driving circuit design, the bias time of the driving transistor can be reduced when performing medium and low grayscale display, thereby improving the lifespan and stability of the driving transistor.

[0190] As shown in Figure 2, based on the pixel circuit embodiment shown in Figure 1, in the pixel circuit described in at least one embodiment of this disclosure, the display control circuit 13 is also electrically connected to the switch control voltage terminal SW, and is used to control whether to write the second driving current to the write node NW according to the control data voltage and the switch control voltage provided by the switch control voltage terminal SW under the control of the display control scan signal.

[0191] In at least one embodiment of the pixel circuit shown in Figure 2 of this disclosure, when in operation, the conduction time between the write node NW and the display node ND can be controlled by the switch control voltage provided by the switch control voltage terminal SW, so as to control the time when the second pixel driving circuit 12 provides driving current to the light-emitting element, thereby controlling the light-emitting time of the light-emitting element for grayscale display control.

[0192] In at least one embodiment of this disclosure, the display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit;

[0193] The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node;

[0194] The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal and the display control node respectively, and is used to write the control data voltage into the display control node under the control of the display control scanning signal;

[0195] The display control reset circuit is electrically connected to the display reset control terminal and the display control node, respectively. The display control reset circuit is also electrically connected to the display reset voltage terminal or the first voltage terminal, and is used to write the display reset voltage provided by the display reset voltage terminal or the first voltage signal provided by the first voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal.

[0196] The first terminal of the first energy storage circuit is electrically connected to the display control node, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal.

[0197] In a specific implementation, the display control circuit may include an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit;

[0198] The on / off control circuit controls the connection or disconnection between the display node and the writing node under the control of the potential of the display control node; the display control writing circuit writes the control data voltage to the display control node under the control of the display control scan signal; the display control reset circuit writes the display reset voltage or the first voltage signal to the display control node under the control of the display reset control signal; the first energy storage circuit can store electrical energy to maintain the potential of the display control node.

[0199] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the display control circuit includes an on / off control circuit 31, a display control writing circuit 32, a display control reset circuit 33, and a first energy storage circuit 34.

[0200] The control terminal of the on / off control circuit 31 is electrically connected to the display control node NDC, the display node ND, and the write node NW, and is used to control the connection or disconnection between the display node ND and the write node NW under the control of the potential of the display control node NDC.

[0201] The display control writing circuit 32 is electrically connected to the display control scanning terminal GT, the control data voltage terminal DT, and the display control node NDC, respectively, and is used to write the control data voltage into the display control node NDC under the control of the display control scanning signal.

[0202] The display control reset circuit 33 is electrically connected to the display reset control terminal RSTT and the display control node NDC respectively. The display control reset circuit 33 is also electrically connected to the display reset voltage terminal I0, and is used to write the display reset voltage Vinit0 provided by the display reset voltage terminal I0 into the display control node NDC under the control of the display reset control signal provided by the display reset control terminal RSTT.

[0203] The first terminal of the first energy storage circuit 34 is electrically connected to the display control node NDC, and the second terminal of the first energy storage circuit 34 is electrically connected to the first initial voltage terminal I1.

[0204] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 1, the display control circuit includes an on / off control circuit 31, a display control writing circuit 32, a display control reset circuit 33, and a first energy storage circuit 34.

[0205] The control terminal of the on / off control circuit 31 is electrically connected to the display control node NDC, the display node ND, and the write node NW, and is used to control the connection or disconnection between the display node ND and the write node NW under the control of the potential of the display control node NDC.

[0206] The display control writing circuit 32 is electrically connected to the display control scanning terminal GT, the control data voltage terminal DT, and the display control node NDC, respectively, and is used to write the control data voltage into the display control node NDC under the control of the display control scanning signal.

[0207] The display control reset circuit 33 is electrically connected to the display reset control terminal RSTT and the display control node NDC respectively. The display control reset circuit 33 is also electrically connected to the first voltage terminal V1, and is used to write the first voltage signal provided by the first voltage terminal V1 into the display control node NDC under the control of the display reset control signal provided by the display reset control terminal RSTT.

[0208] The first terminal of the first energy storage circuit 34 is electrically connected to the display control node NDC, and the second terminal of the first energy storage circuit 34 is electrically connected to the first initial voltage terminal I1.

[0209] Optionally, the first voltage terminal can be a high voltage terminal.

[0210] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 1, the display control circuit includes an on / off control circuit 31, a display control writing circuit 32, a display control reset circuit 33, a first energy storage circuit 34, and a control circuit 35.

[0211] The control terminal of the on / off control circuit 31 is electrically connected to the display control node NDC, the display node ND, and the write node NW, and is used to control the connection or disconnection between the display node ND and the write node NW under the control of the potential of the display control node NDC.

[0212] The control circuit 35 is electrically connected to the control node NC, the second voltage terminal V2, the third voltage terminal V3 and the display control node NDC respectively, and is used to control the display control node NDC to connect with the second voltage terminal V2 or the third voltage terminal V3 under the control of the potential of the control node NC.

[0213] The display control writing circuit 32 is electrically connected to the display control scanning terminal GT, the control data voltage terminal DT, and the control node NC, respectively, and is used to write the control data voltage into the control node NC under the control of the display control scanning signal;

[0214] The display control reset circuit 33 is electrically connected to the display reset control terminal RSTT, the display reset voltage terminal I0 and the display control node NDC, respectively, and is used to write the display reset voltage Vinit0 provided by the display reset voltage terminal I0 into the display control node NDC under the control of the display reset control signal provided by the display reset control terminal RSTT.

[0215] The first terminal of the first energy storage circuit 34 is electrically connected to the control node NC, and the second terminal of the first energy storage circuit 34 is electrically connected to the first initial voltage terminal I1.

[0216] Optionally, the second voltage terminal can be a low voltage terminal, and the third voltage terminal can be a high voltage terminal.

[0217] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 2, the display control circuit includes an on / off control circuit 31, a display control writing circuit 32, a display control reset circuit 33, and a first energy storage circuit 34.

[0218] The control terminal of the on / off control circuit 31 is electrically connected to the display control node NDC, the display node ND, and the write node NW, and is used to control the connection or disconnection between the display node ND and the write node NW under the control of the potential of the display control node NDC.

[0219] The display control writing circuit 32 is electrically connected to the display control scanning terminal GT, the control data voltage terminal DT, and the display control node NDC, respectively, and is used to control the connection or disconnection between the control data voltage terminal DT and the display control node NDC under the control of the display control scanning signal;

[0220] The display control reset circuit 33 is electrically connected to the display reset control terminal RSTT, the display reset voltage terminal I0 and the display control node NDC, respectively, and is used to write the display reset voltage Vinit0 provided by the display reset voltage terminal I9 into the display control node NDC under the control of the display reset control signal provided by the display reset control terminal RSTT.

[0221] The first terminal of the first energy storage circuit 34 is electrically connected to the display control node NDC, and the second terminal of the first energy storage circuit 34 is electrically connected to the switch control voltage terminal SW.

[0222] In at least one embodiment of the pixel circuit shown in FIG6 of this disclosure, when in operation, the first energy storage circuit 34 can control the potential of the display control node NDC according to the switch control voltage provided by the switch control voltage terminal SW.

[0223] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor;

[0224] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0225] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the display control node.

[0226] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node.

[0227] The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

[0228] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the control circuit includes a fourth transistor and a fifth transistor;

[0229] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0230] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the control node.

[0231] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the control node.

[0232] The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

[0233] The gate of the fourth transistor is electrically connected to the control node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the display control node.

[0234] The gate of the fifth transistor is electrically connected to the control node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the display control node.

[0235] Optionally, the on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor and a sixth transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor;

[0236] The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node;

[0237] The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor, the gate of the sixth transistor, and the second terminal of the sixth transistor are electrically connected, and the second terminal of the second transistor is electrically connected to the display control node;

[0238] The first terminal of the sixth transistor is electrically connected to the control data voltage terminal.

[0239] The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node.

[0240] The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the switch control voltage terminal.

[0241] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element; the first pixel driving circuit includes a first driving circuit; the first driving circuit is used to control whether to generate a first driving current under the control of the first data voltage; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal;

[0242] The display node is electrically connected to the first terminal of the light-emitting element; or, the display node is electrically connected to the second terminal of the first driving circuit.

[0243] In a specific implementation, the pixel circuit may further include a light-emitting element, and the first pixel driving circuit includes a first driving circuit that controls whether to generate a first driving current under the control of the first data voltage.

[0244] Optionally, the fourth voltage terminal can be a low-level terminal.

[0245] In at least one embodiment of this disclosure, the first pixel driving circuit;

[0246] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0247] Optionally, the light-emitting element can be an MLED, but is not limited thereto; the light-emitting element can also be other types of light-emitting diodes, for example, an organic light-emitting diode.

[0248] MLEDs can include Micro LEDs (micro diodes) and Mini-LEDs (mini light-emitting diodes).

[0249] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1;

[0250] The first pixel driving circuit includes a first driving circuit 70 and a first light emission control circuit 71;

[0251] The first driving circuit 70 is used to control whether to generate a first driving current under the control of the first data voltage provided by the first data voltage terminal; the second electrode of the light-emitting element E1 is electrically connected to the fourth voltage terminal V4;

[0252] The display node ND is electrically connected to the first electrode of the light-emitting element E1;

[0253] The first light-emitting control circuit 71 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the first driving circuit 70, and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit 70 and the first electrode of the light-emitting element E1 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0254] As shown in Figure 8, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1;

[0255] The first pixel driving circuit includes a first driving circuit 70 and a first light emission control circuit 71;

[0256] The first driving circuit 70 is used to control whether to generate a first driving current under the control of the first data voltage provided by the first data voltage terminal; the second electrode of the light-emitting element E1 is electrically connected to the fourth voltage terminal V4;

[0257] The display node ND is electrically connected to the second terminal of the first driving circuit 70;

[0258] The first light-emitting control circuit 71 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the first driving circuit 70, and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit 70 and the first electrode of the light-emitting element E1 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0259] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 7, the first pixel driving circuit further includes a second light emission control circuit 91, a first data writing circuit 92, a first compensation control circuit 93, a first initialization circuit 94, and a second energy storage circuit 95.

[0260] The second light-emitting control circuit 91 is electrically connected to the second light-emitting control terminal EM2, the first power supply voltage terminal VDD1, and the first terminal of the first driving circuit 70, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal VDD1 and the first terminal of the first driving circuit 70 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0261] The first data writing circuit 92 is electrically connected to the first scanning terminal GTA, the first data voltage terminal DTA and the first terminal of the first driving circuit 70 respectively, and is used to write the first data voltage VdataA provided by the first data voltage terminal DTA into the first terminal of the first driving circuit 70 under the control of the first scanning signal provided by the first scanning terminal GTA.

[0262] The first compensation control circuit 93 is electrically connected to the first scanning terminal GTA, the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 respectively, and is used to control the connection or disconnection between the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 under the control of the first scanning signal.

[0263] The first initialization circuit 94 is electrically connected to the first reset control terminal RSTA, the second initial voltage terminal I2 and the control terminal of the first drive circuit 70, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the control terminal of the first drive circuit 70 under the control of the first reset control signal provided by the first reset control terminal RSTA.

[0264] The second energy storage circuit 95 is electrically connected to the control terminal of the first drive circuit 70 to maintain the potential of the control terminal of the first drive circuit 70.

[0265] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 8, the first pixel driving circuit further includes a second light emission control circuit 91, a first data writing circuit 92, a first compensation control circuit 93, a first initialization circuit 94, and a second energy storage circuit 95.

[0266] The second light-emitting control circuit 91 is electrically connected to the second light-emitting control terminal EM2, the first power supply voltage terminal VDD1, and the first terminal of the first driving circuit 70, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal VDD1 and the first terminal of the first driving circuit 70 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0267] The first data writing circuit 92 is electrically connected to the first scanning terminal GTA, the first data voltage terminal DTA and the first terminal of the first driving circuit 70 respectively, and is used to write the first data voltage VdataA provided by the first data voltage terminal DTA into the first terminal of the first driving circuit 70 under the control of the first scanning signal provided by the first scanning terminal GTA.

[0268] The first compensation control circuit 93 is electrically connected to the first scanning terminal GTA, the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 respectively, and is used to control the connection or disconnection between the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 under the control of the first scanning signal.

[0269] The first initialization circuit 94 is electrically connected to the first reset control terminal RSTA, the second initial voltage terminal I2 and the control terminal of the first drive circuit 70, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the control terminal of the first drive circuit 70 under the control of the first reset control signal provided by the first reset control terminal RSTA.

[0270] The second energy storage circuit 95 is electrically connected to the control terminal of the first drive circuit 70 to maintain the potential of the control terminal of the first drive circuit 70.

[0271] In at least one embodiment of this disclosure, the first pixel driving circuit further includes a second initialization circuit;

[0272] The second initialization circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0273] In a specific implementation, the first pixel driving circuit may further include a second initialization circuit. Under the control of the second reset control signal, the second initialization circuit can write a third initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0274] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 9, the first pixel driving circuit further includes a second initialization circuit 96.

[0275] The second initialization circuit 96 is electrically connected to the second reset control terminal RSTC, the third initial voltage terminal I3 and the first pole of the light-emitting element E1, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RSTC.

[0276] As shown in Figure 12, based on at least one embodiment of the pixel circuit shown in Figure 10, the first pixel driving circuit further includes a second initialization circuit 96.

[0277] The second initialization circuit 96 is electrically connected to the second reset control terminal RSTC, the third initial voltage terminal I3 and the first pole of the light-emitting element E1, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RSTC.

[0278] As shown in Figure 13, based on at least one embodiment of the pixel circuit shown in Figure 6, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1;

[0279] The first pixel driving circuit includes a first driving circuit 70 and a first light emission control circuit 71;

[0280] The first terminal of the first driving circuit 70 is electrically connected to the first data voltage terminal DTA, and is used to control whether to generate the first driving current under the control of the first data voltage VdataA provided by the first data voltage terminal DTA; the second terminal of the light-emitting element E1 is electrically connected to the fourth voltage terminal V4.

[0281] The display node ND is electrically connected to the first electrode of the light-emitting element E1;

[0282] The first light-emitting control circuit 71 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the first driving circuit 70, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit 70 and the first pole of the light-emitting element E1 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0283] The first pixel driving circuit further includes a second light emission control circuit 91, a first data writing circuit 92, a first compensation control circuit 93, a first initialization circuit 94, and a second energy storage circuit 95.

[0284] The second light-emitting control circuit 91 is electrically connected to the second light-emitting control terminal EM2, the first power supply voltage terminal VDD1, and the first terminal of the first driving circuit 70, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal VDD1 and the first terminal of the first driving circuit 70 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0285] The first data writing circuit 92 is electrically connected to the first scanning terminal GTA, the first data voltage terminal DTA and the first terminal of the first driving circuit 70 respectively, and is used to write the first data voltage VdataA provided by the first data voltage terminal DTA into the first terminal of the first driving circuit 70 under the control of the first scanning signal provided by the first scanning terminal GTA.

[0286] The first compensation control circuit 93 is electrically connected to the first scanning terminal GTA, the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 respectively, and is used to control the connection or disconnection between the control terminal of the first driving circuit 70 and the second terminal of the first driving circuit 70 under the control of the first scanning signal.

[0287] The first initialization circuit 94 is electrically connected to the first reset control terminal RSTA, the second initial voltage terminal I2 and the control terminal of the first drive circuit 70, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the control terminal of the first drive circuit 70 under the control of the first reset control signal provided by the first reset control terminal RSTA.

[0288] The second energy storage circuit 95 is electrically connected to the control terminal of the first drive circuit 70 to maintain the potential of the control terminal of the first drive circuit 70.

[0289] The first pixel driving circuit also includes a second initialization circuit 96;

[0290] The second initialization circuit 96 is electrically connected to the second reset control terminal RSTC, the third initial voltage terminal I3 and the first pole of the light-emitting element E1, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RSTC.

[0291] At least one embodiment of the pixel circuit shown in FIG13 of this disclosure achieves different current control and multi-pulse width modulation by driving the high and low grayscale displays with different pixel driving circuits and controlling them with the display control circuit 13.

[0292] In at least one embodiment of the pixel circuit shown in FIG13 of this disclosure, when in operation, the first pixel driving circuit 11 drives and controls the high grayscale display, and the second pixel driving circuit 12 drives the medium and low grayscale display.

[0293] When performing high grayscale display, the display control circuit 13 can control the disconnection between the write node NW and the display node ND. The first light emission control signal provided by EMA can be a long pulse width light emission control signal, a single pulse width duration control signal, or a high frequency pulse width control signal. The total pulse width (long duration light emission) within a frame matches the high current driving backplane to achieve high grayscale display.

[0294] When performing low-to-medium grayscale display, the first data voltage can be controlled so that the first driving current Id1 generated by the first driving circuit 70 is 0. The on-time of the on-off control circuit 31 can be controlled by the switching control voltage provided by the switching control voltage terminal SW, thereby realizing the pulse width control of low-to-medium grayscale. When the on-off control circuit 31 controls the connection between the write node NW and the display node ND, the light-emitting element E1 is driven to emit light by the second pixel driving circuit 12.

[0295] At least one embodiment of this disclosure provides a PAM (Pulse Amplitude Modulation) + PWM (Pulse Width Modulation) pixel circuit, namely a pixel circuit with amplitude control + pulse width control, which can improve the uniformity of low grayscale brightness; and, at least one embodiment of this disclosure adopts high current drive, and the light-emitting element operates in the high efficiency region, which can achieve low power consumption.

[0296] The pixel circuit described in at least one embodiment of this disclosure can be applied to glass-based display panels, but is not limited thereto.

[0297] In at least one embodiment of this disclosure, the second pixel driving circuit includes a second driving circuit, a third light emission control circuit, a second data writing circuit, a second compensation control circuit, a third initialization circuit, and a third energy storage circuit.

[0298] The second terminal of the second driving circuit is electrically connected to the write node; the second driving circuit is used to control whether to generate a second driving current under the control of the second data voltage;

[0299] The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal.

[0300] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the first terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal into the first terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal;

[0301] The second compensation control circuit is electrically connected to the second scanning terminal, the control terminal of the second driving circuit, and the second terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit and the second terminal of the second driving circuit under the control of the second scanning signal.

[0302] The third initialization circuit is electrically connected to the third reset control terminal, the fourth initial voltage terminal and the control terminal of the second drive circuit, respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the control terminal of the second drive circuit under the control of the third reset control signal provided by the third reset control terminal.

[0303] The third energy storage circuit is electrically connected to the control terminal of the second drive circuit and is used to maintain the potential of the control terminal of the second drive circuit.

[0304] As shown in FIG14, based on at least one embodiment of the pixel circuit shown in FIG11, the second pixel driving circuit includes a second driving circuit 141, a third light emission control circuit 142, a second data writing circuit 143, a second compensation control circuit 144, a third initialization circuit 145, and a third energy storage circuit 146.

[0305] The second terminal of the second driving circuit 141 is electrically connected to the write node NW;

[0306] The third light-emitting control circuit 142 is electrically connected to the third light-emitting control terminal EM3, the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 under the control of the third light-emitting control signal provided by the third light-emitting control terminal EM3.

[0307] The second data writing circuit 143 is electrically connected to the second scanning terminal GTB, the second data voltage terminal DTB, and the first terminal of the second driving circuit 141, respectively, and is used to write the second data voltage VataB provided by the second data voltage terminal DTB into the first terminal of the second driving circuit 141 under the control of the second scanning signal provided by the second scanning terminal GTB.

[0308] The second compensation control circuit 144 is electrically connected to the second scanning terminal GTB, the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 under the control of the second scanning signal.

[0309] The third initialization circuit 145 is electrically connected to the third reset control terminal RSTB, the fourth initial voltage terminal I4 and the control terminal of the second driving circuit 141, respectively, and is used to write the fourth initial voltage Vinit4 provided by the fourth initial voltage terminal I4 into the control terminal of the second driving circuit 141 under the control of the third reset control signal provided by the third reset control terminal RSTB.

[0310] The third energy storage circuit 146 is electrically connected to the control terminal of the second drive circuit 141 and is used to maintain the potential of the control terminal of the second drive circuit 141.

[0311] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 12, the second pixel driving circuit includes a second driving circuit 141, a third light emission control circuit 142, a second data writing circuit 143, a second compensation control circuit 144, a third initialization circuit 145, and a third energy storage circuit 146.

[0312] The second terminal of the second driving circuit 141 is electrically connected to the write node NW;

[0313] The third light-emitting control circuit 142 is electrically connected to the third light-emitting control terminal EM3, the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 under the control of the third light-emitting control signal provided by the third light-emitting control terminal EM3.

[0314] The second data writing circuit 143 is electrically connected to the second scanning terminal GTB, the second data voltage terminal DTB, and the first terminal of the second driving circuit 141, respectively, and is used to write the second data voltage VataB provided by the second data voltage terminal DTB into the first terminal of the second driving circuit 141 under the control of the second scanning signal provided by the second scanning terminal GTB.

[0315] The second compensation control circuit 144 is electrically connected to the second scanning terminal GTB, the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 under the control of the second scanning signal.

[0316] The third initialization circuit 145 is electrically connected to the third reset control terminal RSTB, the fourth initial voltage terminal I4 and the control terminal of the second driving circuit 141, respectively, and is used to write the fourth initial voltage Vinit4 provided by the fourth initial voltage terminal I4 into the control terminal of the second driving circuit 141 under the control of the third reset control signal provided by the third reset control terminal RSTB.

[0317] The third energy storage circuit 146 is electrically connected to the control terminal of the second drive circuit 141 and is used to maintain the potential of the control terminal of the second drive circuit 141.

[0318] As shown in Figure 16, based on at least one embodiment of the pixel circuit shown in Figure 13, the second pixel driving circuit includes a second driving circuit 141, a third light emission control circuit 142, a second data writing circuit 143, a second compensation control circuit 144, a third initialization circuit 145, and a third energy storage circuit 146.

[0319] The second terminal of the second driving circuit 141 is electrically connected to the write node NW;

[0320] The third light-emitting control circuit 142 is electrically connected to the third light-emitting control terminal EM3, the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 under the control of the third light-emitting control signal provided by the third light-emitting control terminal EM3.

[0321] The second data writing circuit 143 is electrically connected to the second scanning terminal GTB, the second data voltage terminal DTB, and the first terminal of the second driving circuit 141, respectively, and is used to write the second data voltage VataB provided by the second data voltage terminal DTB into the first terminal of the second driving circuit 141 under the control of the second scanning signal provided by the second scanning terminal GTB.

[0322] The second compensation control circuit 144 is electrically connected to the second scanning terminal GTB, the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit 141 and the second terminal of the second driving circuit 141 under the control of the second scanning signal.

[0323] The third initialization circuit 145 is electrically connected to the third reset control terminal RSTB, the fourth initial voltage terminal I4 and the control terminal of the second driving circuit 141, respectively, and is used to write the fourth initial voltage Vinit4 provided by the fourth initial voltage terminal I4 into the control terminal of the second driving circuit 141 under the control of the third reset control signal provided by the third reset control terminal RSTB.

[0324] The third energy storage circuit 146 is electrically connected to the control terminal of the second drive circuit 141 and is used to maintain the potential of the control terminal of the second drive circuit 141.

[0325] Optionally, at least two of the display reset control terminal, the first reset control terminal, the second reset control terminal, and the third reset control terminal are the same reset control terminal; and / or,

[0326] The first scanning end and the second scanning end are the same scanning end; and / or,

[0327] At least two of the first initial voltage terminal, the second initial voltage terminal, the third initial voltage terminal, and the fourth initial voltage terminal are the same initial voltage terminal.

[0328] In specific implementation, at least two of the display reset control terminal, the first reset control terminal, the second reset control terminal, and the third reset control terminal can be the same reset control terminal to reduce the number of reset control terminals and reset control signals used.

[0329] The first scanning end and the second scanning end can be the same scanning end to reduce the number of scanning ends and scanning signals used;

[0330] At least two of the first initial voltage terminal, the second initial voltage terminal, the third initial voltage terminal, and the fourth initial voltage terminal are the same initial voltage terminal, so as to reduce the number of initial voltage terminals and initial voltages used.

[0331] Optionally, the first data voltage terminal, the second data voltage terminal, and the control data voltage terminal are the same data voltage terminal;

[0332] The first scanning end is the nth level scanning end, the second scanning end is the (n+1)th level scanning end, and the display control scanning end is the (n+2)th level scanning end;

[0333] n is a positive integer.

[0334] In specific implementation, the first data voltage terminal, the second data voltage terminal, and the control data voltage terminal can be the same data voltage terminal to reduce the number of data voltage terminals used.

[0335] The first scanning end can be the nth level scanning end, the second scanning end can be the (n+1)th level scanning end, and the display control scanning end can be the (n+2)th level scanning end, so as to reduce the number of GOA modules used.

[0336] Optionally, at least one of the transistors included in the first initialization circuit, the first compensation control circuit, the third initialization circuit, the second compensation control circuit, the display control writing circuit, the display control reset circuit, the first data writing circuit, and the second data writing circuit is an n-type transistor; and / or,

[0337] At least one of the transistors included in the first driving circuit, the transistors included in the second driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the third light-emitting control circuit, and the transistors included in the on / off control circuit is a p-type transistor.

[0338] In at least one embodiment of this disclosure, the pixel circuit employs LTPO (Low Temperature Polycrystalline Oxide) technology. Leveraging the low leakage current advantage of Oxide TFTs (Thin Film Transistors), leakage current is reduced. At least one of the transistors included in the first initialization circuit, the first compensation control circuit, the third initialization circuit, the second compensation control circuit, the display control writing circuit, the display control reset circuit, the first data writing circuit, and the second data writing circuit can be configured as an NMOS TFT. Utilizing the high mobility of PMOS transistors, at least one of the transistors included in the first driving circuit, the second driving circuit, the first light emission control circuit, the second light emission control circuit, the third light emission control circuit, and the on / off control circuit can be configured as a PMOS TFT. This facilitates a reduction in threshold voltage compensation time. During the light emission stage, the compensation time for the control terminal of the first driving circuit is reduced, meeting current driving requirements and reducing capacitor area, further improving display performance.

[0339] In at least one embodiment of this disclosure, the first pixel driving circuit further includes a fourth energy storage circuit, a first data writing circuit, and a switch control circuit;

[0340] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the control terminal of the first driving circuit, respectively, and is used to write the first data voltage provided by the first data voltage terminal to the control terminal of the first driving circuit under the control of the first scanning signal provided by the first scanning terminal.

[0341] The first terminal of the fourth energy storage circuit is electrically connected to the control terminal of the first drive circuit, and the second terminal of the fourth energy storage circuit is electrically connected to the second terminal of the first drive circuit.

[0342] The switch control circuit is electrically connected to the third scanning terminal, the external compensation sensing line, and the second terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the second terminal of the first driving circuit under the control of the third scanning signal provided by the third scanning terminal.

[0343] In a specific implementation, the first pixel driving circuit may further include a fourth energy storage circuit, a first data writing circuit, and a switch control circuit; the first data writing circuit, under the control of the first scan signal, writes the first data voltage into the control terminal of the first driving circuit; the fourth energy storage circuit controls the potential of the control terminal of the first driving circuit according to the potential of the second terminal of the first driving circuit; the switch control circuit, under the control of the third scan signal, controls the connection or disconnection between the external compensation sensing line and the second terminal of the first driving circuit.

[0344] In at least one embodiment of this disclosure, the first pixel driving circuit further includes a second light emission control circuit;

[0345] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first power supply voltage terminal, and the first terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal; or...

[0346] The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0347] In a specific implementation, the first pixel driving circuit may further include a second light-emitting control circuit; the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit; or, the first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit, under the control of the second light-emitting control signal, controls the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element.

[0348] In at least one embodiment of this disclosure, the first pixel driving circuit further includes a first switching circuit and a second switching circuit;

[0349] The first switching circuit is electrically connected to the first switching control terminal, the external compensation sensing line, and the reference voltage terminal, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the external compensation sensing line under the control of the first switching control signal provided by the first switching control terminal.

[0350] The second switching circuit is electrically connected to the second switch control terminal, the external compensation sensing line, and the sensing terminal, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the sensing terminal under the control of the second switch control signal provided by the second switch control terminal.

[0351] In a specific implementation, the first pixel driving circuit may further include a first switching circuit and a second switching circuit; the first switching circuit, under the control of the first switching control signal, writes the reference voltage into the external compensation sensing line; the second switching circuit, under the control of the second switching control signal, controls the connection or disconnection between the external compensation sensing line and the sensing end.

[0352] In at least one embodiment of this disclosure, the second pixel driving circuit includes a second driving circuit, a second data writing circuit, and a third energy storage circuit;

[0353] The first end of the second driving circuit is electrically connected to the second power supply voltage terminal, and the second end of the second driving circuit is electrically connected to the write node;

[0354] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal, and the control terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal to the control terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal.

[0355] The first end of the third energy storage circuit is electrically connected to the control end of the second driving circuit, and the second end of the third energy storage circuit is electrically connected to the write node.

[0356] In a specific implementation, the second pixel driving circuit may include a second driving circuit, a second data writing circuit, and a third energy storage circuit; the first terminal of the second driving circuit is electrically connected to the second power supply voltage terminal, and the second terminal of the second driving circuit is electrically connected to the writing node; under the control of the second scan signal, the second data writing circuit writes the second data voltage to the control terminal of the second driving circuit; the third energy storage circuit controls the potential of the writing node according to the potential of the control terminal of the second driving circuit.

[0357] In at least one embodiment of this disclosure, the second pixel driving circuit further includes a third light emission control circuit;

[0358] The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal.

[0359] In a specific implementation, the second pixel driving circuit may further include a third light-emitting control circuit; under the control of a third light-emitting control signal, the third light-emitting control circuit controls the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit to perform light-emitting control.

[0360] In at least one embodiment of this disclosure, the first pixel driving circuit further includes a second light emission control circuit;

[0361] The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0362] The display node is electrically connected to the second terminal of the first driving circuit.

[0363] In a specific implementation, the first pixel driving circuit may further include a second light-emitting control circuit; the first end of the first driving circuit is electrically connected to the first power supply voltage terminal; under the control of the second light-emitting control signal, the second light-emitting control circuit controls the connection or disconnection between the second end of the first driving circuit and the first electrode of the light-emitting element to perform light-emitting control; the display node is electrically connected to the second end of the first driving circuit.

[0364] As shown in Figure 17, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1; the second electrode of the light-emitting element E1 is electrically connected to the fourth voltage terminal V4.

[0365] The first pixel driving circuit includes a first driving circuit 70; the display node ND is electrically connected to the first electrode of the light-emitting element E1; the second terminal of the first driving circuit 70 is electrically connected to the first electrode of the light-emitting element E1.

[0366] The first pixel driving circuit also includes a fourth energy storage circuit 171, a first data writing circuit 92, and a switch control circuit 172;

[0367] The first data writing circuit 92 is electrically connected to the first scanning terminal GTA, the first data voltage terminal DTA, and the control terminal of the first driving circuit 70, respectively, and is used to write the first data voltage VdataA provided by the first data voltage terminal DTA into the control terminal of the first driving circuit 70 under the control of the first scanning signal provided by the first scanning terminal GTA.

[0368] The first end of the fourth energy storage circuit 171 is electrically connected to the control end of the first drive circuit 70, and the second end of the fourth energy storage circuit 171 is electrically connected to the second end of the first drive circuit 70.

[0369] The switch control circuit 172 is electrically connected to the third scanning terminal GTC, the external compensation sensing line SL and the second terminal of the first driving circuit 70 respectively, and is used to control the connection or disconnection between the external compensation sensing line SL and the second terminal of the first driving circuit 70 under the control of the third scanning signal provided by the third scanning terminal GTC.

[0370] The first pixel driving circuit also includes a second light emission control circuit 91;

[0371] The second light-emitting control circuit 91 is electrically connected to the second light-emitting control terminal EM2, the first power supply voltage terminal VDD1, and the first terminal of the first driving circuit 70, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal VDD1 and the first terminal of the first driving circuit 70 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0372] The first pixel driving circuit also includes a first switching circuit 173 and a second switching circuit 174;

[0373] The first switching circuit 173 is electrically connected to the first switching control terminal SC1, the external compensation sensing line SL, and the reference voltage terminal REF, respectively, and is used to write the reference voltage VREF provided by the reference voltage terminal REF into the external compensation sensing line SL under the control of the first switching control signal provided by the first switching control terminal SC1.

[0374] The second switch circuit 174 is electrically connected to the second switch control terminal SC2, the external compensation sensing line SL, and the sensing terminal SENS, respectively, and is used to control the connection or disconnection between the external compensation sensing line SL and the sensing terminal SENS under the control of the second switch control signal provided by the second switch control terminal SC2.

[0375] The second pixel driving circuit includes a second driving circuit 141, a second data writing circuit 143, and a third energy storage circuit 146;

[0376] The second terminal of the second driving circuit 141 is electrically connected to the write node NW;

[0377] The second data writing circuit 143 is electrically connected to the second scanning terminal GTB, the second data voltage terminal DTB, and the control terminal of the second driving circuit 141, respectively, and is used to write the second data voltage VdataB provided by the second data voltage terminal DTB into the control terminal of the second driving circuit 141 under the control of the second scanning signal provided by the second scanning terminal GTB.

[0378] The first end of the third energy storage circuit 146 is electrically connected to the control end of the second drive circuit 141, and the second end of the third energy storage circuit 146 is electrically connected to the write node NW.

[0379] The second pixel driving circuit also includes a third light emission control circuit 175;

[0380] The third light-emitting control circuit 175 is electrically connected to the third light-emitting control terminal EM3, the second power supply voltage terminal VDD2, and the first terminal of the second driving circuit 141, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal VDD2 and the first terminal of the second driving circuit 141 under the control of the third light-emitting control signal provided by the third light-emitting control terminal EM3.

[0381] As shown in Figure 18, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1; the second electrode of the light-emitting element E1 is electrically connected to the fourth voltage terminal V4.

[0382] The first pixel driving circuit includes a first driving circuit 70; the display node ND is electrically connected to the first electrode of the light-emitting element E1;

[0383] The first pixel driving circuit also includes a fourth energy storage circuit 171, a first data writing circuit 92, and a switch control circuit 172;

[0384] The first data writing circuit 92 is electrically connected to the first scanning terminal GTA, the first data voltage terminal DTA, and the control terminal of the first driving circuit 70, respectively, and is used to write the first data voltage VdataA provided by the first data voltage terminal DTA into the control terminal of the first driving circuit 70 under the control of the first scanning signal provided by the first scanning terminal GTA.

[0385] The first end of the fourth energy storage circuit 171 is electrically connected to the control end of the first drive circuit 70, and the second end of the fourth energy storage circuit 171 is electrically connected to the second end of the first drive circuit 70.

[0386] The switch control circuit 172 is electrically connected to the third scanning terminal GTC, the external compensation sensing line SL and the second terminal of the first driving circuit 70 respectively, and is used to control the connection or disconnection between the external compensation sensing line SL and the second terminal of the first driving circuit 70 under the control of the third scanning signal provided by the third scanning terminal GTC.

[0387] The first pixel driving circuit also includes a second light emission control circuit 91;

[0388] The first terminal of the first driving circuit 70 is electrically connected to the first power supply voltage terminal VDD1;

[0389] The second light-emitting control circuit 91 is electrically connected to the second light-emitting control terminal EM2, the second terminal of the first driving circuit 70, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit 70 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0390] The first pixel driving circuit also includes a first switching circuit 173 and a second switching circuit 174;

[0391] The first switching circuit 173 is electrically connected to the first switching control terminal SC1, the external compensation sensing line SL, and the reference voltage terminal REF, respectively, and is used to write the reference voltage VREF provided by the reference voltage terminal REF into the external compensation sensing line SL under the control of the first switching control signal provided by the first switching control terminal SC1.

[0392] The second switch circuit 174 is electrically connected to the second switch control terminal SC2, the external compensation sensing line SL, and the sensing terminal SENS, respectively, and is used to control the connection or disconnection between the external compensation sensing line SL and the sensing terminal SENS under the control of the second switch control signal provided by the second switch control terminal SC2.

[0393] The second pixel driving circuit includes a second driving circuit 141, a second data writing circuit 143, and a third energy storage circuit 146;

[0394] The first terminal of the second driving circuit 141 is electrically connected to the second power supply voltage terminal VDD2, and the second terminal of the second driving circuit 141 is electrically connected to the write node NW.

[0395] The second data writing circuit 143 is electrically connected to the second scanning terminal GTB, the second data voltage terminal DTB, and the control terminal of the second driving circuit 141, respectively, and is used to write the second data voltage VdataB provided by the second data voltage terminal DTB into the control terminal of the second driving circuit 141 under the control of the second scanning signal provided by the second scanning terminal GTB.

[0396] The first end of the third energy storage circuit 146 is electrically connected to the control end of the second drive circuit 141, and the second end of the third energy storage circuit 146 is electrically connected to the write node NW.

[0397] Optionally, the first light-emitting control circuit includes a seventh transistor; the first driving circuit includes a first driving transistor.

[0398] The gate of the seventh transistor is electrically connected to the first light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0399] The second light-emitting control circuit includes an eighth transistor, the first data writing circuit includes a ninth transistor, the first compensation control circuit includes a tenth transistor, the first initialization circuit includes an eleventh transistor, and the second energy storage circuit includes a second capacitor.

[0400] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor.

[0401] The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first terminal of the first driving transistor.

[0402] The gate of the tenth transistor is electrically connected to the first scan terminal, the first terminal of the tenth transistor is electrically connected to the gate of the first driving transistor, and the second terminal of the tenth transistor is electrically connected to the second terminal of the first driving transistor.

[0403] The gate of the eleventh transistor is electrically connected to the first reset control terminal, the first terminal of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the gate of the first driving transistor.

[0404] The first terminal of the second capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the second capacitor is electrically connected to the first DC voltage terminal.

[0405] The second initialization circuit includes a twelfth transistor;

[0406] The gate of the twelfth transistor is electrically connected to the second reset control terminal, the first terminal of the twelfth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the first terminal of the light-emitting element.

[0407] Optionally, the second driving circuit includes a second driving transistor, the third light-emitting control circuit includes a thirteenth transistor, the second data writing circuit includes a fourteenth transistor, the second compensation control circuit includes a fifteenth transistor, the third initialization circuit includes a sixteenth transistor, and the third energy storage circuit includes a third capacitor.

[0408] The second terminal of the second driving transistor is electrically connected to the write node;

[0409] The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor.

[0410] The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the second drive transistor.

[0411] The gate of the fifteenth transistor is electrically connected to the second scan terminal, the first terminal of the fifteenth transistor is electrically connected to the gate of the second driving transistor, and the second terminal of the fifteenth transistor is electrically connected to the second terminal of the second driving transistor.

[0412] The gate of the sixteenth transistor is electrically connected to the third reset control terminal, the first terminal of the sixteenth transistor is electrically connected to the fourth initial voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the gate of the second driving transistor.

[0413] The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the second DC voltage terminal.

[0414] Optionally, the first driving circuit includes a first driving transistor; the fourth energy storage circuit includes a fourth capacitor; the first terminal of the fourth capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the fourth capacitor is electrically connected to the second terminal of the first driving transistor.

[0415] The first data writing circuit includes a ninth transistor, and the switch control circuit includes a seventeenth transistor;

[0416] The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the gate of the first driving transistor.

[0417] The gate of the seventeenth transistor is electrically connected to the third scanning terminal, the first terminal of the seventeenth transistor is electrically connected to the external compensation sensing line, and the second terminal of the seventeenth transistor is electrically connected to the second terminal of the first driving transistor.

[0418] Optionally, the second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor.

[0419] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor; or...

[0420] The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal; the gate of the eighth transistor is electrically connected to the second light-emitting control terminal; the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor; and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0421] Optionally, the first switching circuit includes a first switch, and the second switching circuit includes a second switch;

[0422] The control terminal of the first switch is electrically connected to the control terminal of the first switch, the first terminal of the first switch is electrically connected to the external compensation sensing line, and the second terminal of the first switch is electrically connected to the reference voltage terminal.

[0423] The control terminal of the second switch is electrically connected to the control terminal of the second switch, the first terminal of the second switch is electrically connected to the external compensation sensing line, and the second terminal of the second switch is electrically connected to the sensing terminal.

[0424] Optionally, the second driving circuit includes a second driving transistor, the second data writing circuit includes a fourteenth transistor, and the third energy storage circuit includes a third capacitor;

[0425] The first terminal of the second driving transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the second driving transistor is electrically connected to the write node;

[0426] The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the gate of the second driving transistor.

[0427] The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the write node.

[0428] Optionally, the third light-emitting control circuit includes a thirteenth transistor;

[0429] The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor.

[0430] Optionally, the second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor.

[0431] The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal;

[0432] The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

[0433] As shown in Figure 19, based on at least one embodiment of the pixel circuit shown in Figure 14, the on / off control circuit includes a first transistor T1, the display control writing circuit includes a second transistor T2, the display control reset circuit includes a third transistor T3, and the first energy storage circuit includes a first capacitor C1.

[0434] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW.

[0435] The gate of the second transistor T2 is electrically connected to the display control scan terminal GT, the source of the second transistor T2 is electrically connected to the control data voltage terminal DT, and the drain of the second transistor T2 is electrically connected to the display control node NDC.

[0436] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the display reset voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the display control node NDC; the display reset voltage terminal I0 is used to provide the display reset voltage Vinit0.

[0437] The first terminal of the first capacitor C1 is electrically connected to the display control node NDC, and the second terminal of the first capacitor C1 is electrically connected to the first initial voltage terminal I1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0438] The first light-emitting control circuit includes a seventh transistor T7; the first driving circuit includes a first driving transistor TD1; the light-emitting element is a miniature light-emitting diode M1;

[0439] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control terminal EM1, the source of the seventh transistor T7 is electrically connected to the drain of the first driving transistor TD1, and the drain of the seventh transistor T7 is electrically connected to the anode of M1.

[0440] The second light-emitting control circuit includes an eighth transistor T8, the first data writing circuit includes a ninth transistor T9, the first compensation control circuit includes a tenth transistor T10, the first initialization circuit includes an eleventh transistor T11, and the second energy storage circuit includes a second capacitor C2.

[0441] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1, the source of the eighth transistor T8 is electrically connected to the first power supply voltage terminal VDD1, and the drain of the eighth transistor T8 is electrically connected to the source of the first driving transistor TD1; the first light-emitting control terminal and the second light-emitting control terminal are the same light-emitting control terminal.

[0442] The gate of the ninth transistor T9 is electrically connected to the first scan terminal GTA, the source of the ninth transistor T9 is electrically connected to the first data voltage terminal DTA, and the drain of the ninth transistor T9 is electrically connected to the source of the first driving transistor TD1.

[0443] The gate of the tenth transistor T10 is electrically connected to the first scan terminal GTA, the source of the tenth transistor T10 is electrically connected to the gate of the first driving transistor TD1, and the drain of the tenth transistor T10 is electrically connected to the drain of the first driving transistor TD1.

[0444] The gate of the eleventh transistor T11 is electrically connected to the first reset control terminal RSTA, the source of the eleventh transistor T11 is electrically connected to the second initial voltage terminal I2, and the drain of the eleventh transistor T11 is electrically connected to the gate of the first driving transistor TD1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0445] The first terminal of the second capacitor C2 is electrically connected to the gate of the first driving transistor TD1, and the second terminal of the second capacitor C2 is electrically connected to the first power supply voltage terminal VDD1; the first DC voltage terminal is the first power supply voltage terminal VDD1.

[0446] The second initialization circuit includes a twelfth transistor T12;

[0447] The gate of the twelfth transistor T12 is electrically connected to the second reset control terminal RSTC, the source of the twelfth transistor T12 is electrically connected to the third initial voltage terminal I3, and the drain of the twelfth transistor T12 is electrically connected to the anode of M1; the third initial voltage terminal I3 is used to provide the third initial voltage Vinit3; the cathode of M1 is electrically connected to the low-level terminal VSS; the fourth voltage terminal is the low-level terminal VSS;

[0448] The second driving circuit includes a second driving transistor TD2, the third light-emitting control circuit includes a thirteenth transistor T13, the second data writing circuit includes a fourteenth transistor T14, the second compensation control circuit includes a fifteenth transistor T15, the third initialization circuit includes a sixteenth transistor T16, and the third energy storage circuit includes a third capacitor C3.

[0449] The drain of the second driving transistor TD2 is electrically connected to the write node NW;

[0450] The gate of the thirteenth transistor T13 is electrically connected to the third light-emitting control terminal EM3, the source of the thirteenth transistor T13 is electrically connected to the second power supply voltage terminal VDD2, and the drain of the thirteenth transistor T13 is electrically connected to the source of the second driving transistor TD2.

[0451] The gate of the fourteenth transistor T14 is electrically connected to the second scan terminal GTB, the source of the fourteenth transistor T14 is electrically connected to the second data voltage terminal DTB, and the drain of the fourteenth transistor T14 is electrically connected to the source of the second driving transistor TD2.

[0452] The gate of the fifteenth transistor T15 is electrically connected to the second scan terminal GTB, the source of the fifteenth transistor T15 is electrically connected to the gate of the second driving transistor TD2, and the drain of the fifteenth transistor T15 is electrically connected to the drain of the second driving transistor TD2.

[0453] The gate of the sixteenth transistor T16 is electrically connected to the third reset control terminal RSTB, the source of the sixteenth transistor T16 is electrically connected to the fourth initial voltage terminal I4, and the drain of the sixteenth transistor T16 is electrically connected to the gate of the second driving transistor TD2; the fourth initial voltage terminal I4 is used to provide the fourth initial voltage Vinit4.

[0454] The first terminal of the third capacitor C3 is electrically connected to the gate of the second driving transistor TD2, and the second terminal of the third capacitor C3 is electrically connected to the second power supply voltage terminal VDD2; the second DC voltage terminal is the second power supply voltage terminal VDD2.

[0455] In at least one embodiment of the pixel circuit shown in Figure 19, all transistors are p-type transistors.

[0456] The pixel circuit shown in Figure 19 of this disclosure is a novel low-power pixel circuit. It uses a first pixel driving circuit, a second pixel driving circuit, and a display control circuit to jointly drive M1. By increasing the current, the current values ​​of the driving currents generated by the first pixel driving circuit and the second pixel driving circuit are reduced, thereby reducing the voltage across the first driving transistor TD1 and the voltage across the second driving transistor TD2, reducing the power consumption of the first driving transistor TD1 and the second driving transistor TD2, and realizing low-power display.

[0457] In at least one embodiment of the pixel circuit shown in Figure 19 of this disclosure, when the pixel current flowing through M1 is Id, TD1 and TD2 each provide 0.5Id to meet the pixel circuit requirements of M1; taking a current value of 30μA for example, the drain-source current Vds1 of the first driving transistor TD1 and the drain-source voltage Vds2 of the second driving transistor TD2 can be reduced by 25%. In at least one embodiment of the pixel circuit shown in Figure 19 of this disclosure, when operating...

[0458] When displaying high grayscale, TD1 and TD2 jointly provide pixel current;

[0459] When displaying at low to medium grayscale, T1 is off, and TD1 provides pixel current; or...

[0460] When displaying in low to medium grayscale, T1 is turned on. By controlling the voltage value of the first data voltage, the current value of the first driving current Id1 generated by TD1 can be made 0, and TD2 provides the pixel current.

[0461] When displaying in low to medium grayscale, the bias time of TD1 or the bias time of TD2 can be reduced.

[0462] In at least one embodiment of this disclosure, in order to reduce backplane power consumption, the channel width-to-length ratio of TD1 and the channel width-to-length ratio of TD2 can be designed to be the same, and the channel width-to-length ratio of TD1 and the channel width-to-length ratio of TD2 only need to satisfy 0.5Id; T1 is a selection switch transistor, and the channel width-to-length ratio of T1 only needs to satisfy 0.5Id.

[0463] Furthermore, the channel width-to-length ratios of T8, T7, T13, and T1 can be designed to be the same, and the drain-source voltage Vds of each transistor decreases as the current decreases, further reducing the channel width of each transistor.

[0464] In at least one embodiment of the pixel circuit shown in Figure 19, the gate of TD1 is electrically connected to the first node N1, and the gate of TD2 is electrically connected to the fifth node N5.

[0465] In at least one embodiment of the pixel circuit shown in Figure 19, the second node N2 is electrically connected to the source of TD1, the third node N3 is electrically connected to the drain of TD1, and ND can be a fourth node.

[0466] As shown in FIG20A, when at least one embodiment of the pixel circuit shown in FIG19 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0467] In the first stage P1 (which can be a reset stage), RSTA, RSTB, and RSTT all provide low voltage signals, as shown in Figure 21A. T11, T16, and T3 are turned on to reset N1, N5, and NDC. It should be noted that the second initial voltage Vinit2 provided by I2 and the fourth initial voltage Vinit4 provided by I4 are low voltage signals (the voltage values ​​of Vinit2 and Vinit4 can be the same as the voltage values ​​of the low voltage signals provided by VSS). When N1 and N5 are reset, TD1 and TD2 are ensured to be in the on state. The display reset voltage Vinit0 provided by I0 is a high voltage signal used to reset NDC. Its purpose is to control T1 to be turned off from the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing the data voltage writing and threshold voltage compensation of the second pixel driving circuit from being affected, as well as the leakage of M1.

[0468] In the second stage P2 (which can be the data writing stage), RSTA, RSTB, RSTC, and RSTT all provide high voltage signals, while GTA and GTB provide low voltage signals, as shown in Figure 21B. T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA, and DTB provides the second data voltage VdataB. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. This ensures that TD1 and TD2 are turned on at the beginning of the second stage P2. When the potential of N1 is VdataA + Vth1, TD1 is turned off, and when the potential of N5 is VdataB + Vth2, TD2 is turned off to perform threshold voltage compensation. Vth1 is the threshold voltage of TD1, and Vth2 is the threshold voltage of TD2.

[0469] In the third stage P3, RSTC provides a low voltage signal, as shown in Figure 21C. T12 is turned on, and I3 provides a third initial voltage Vinit3 to the anode of M1. Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0470] In the fourth stage P4, GT provides a low voltage signal, as shown in Figure 21D, T2 turns on, and the control data voltage Vdata provided by DT is written to NDC; Vdata is a low voltage signal to control T16 to turn on.

[0471] In the fifth stage P5 (which can be the light-emitting stage), EM1 and EM3 provide low voltage signals, as shown in Figure 21E. T7, T8, T13, TD1, TD2 and T1 are turned on. When displaying high grayscale, TD1 and TD2 jointly drive M1 to emit light. TD1 generates the first driving current Id1 and TD2 generates the second driving current Id2 to drive M1 to emit light. The pixel current Id flowing through M1 is equal to Id1 + Id2.

[0472] In at least one embodiment of the pixel circuit shown in Figure 19 of this disclosure, during low-to-medium grayscale display, in the fifth stage P5, T1 can be turned on, TD2 generates Id2 to drive M1 to emit light, and by adjusting VdataA, Id1 can be made to be 0.

[0473] As shown in FIG20B, when at least one embodiment of the pixel circuit shown in FIG19 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0474] In the first stage P1 (which can be a reset stage), RSTA, RSTB, and RSTT all provide low voltage signals, and T11, T16, and T3 are turned on to reset N1, N5, and NDC. It should be noted that the second initial voltage Vinit2 provided by I2 and the fourth initial voltage Vinit4 provided by I4 are low voltage signals (the voltage values ​​of Vinit2 and Vinit4 can be the same as the voltage values ​​of the low voltage signals provided by VSS). When N1 and N5 are reset, TD1 and TD2 are ensured to be in the on state. The display reset voltage Vinit0 provided by I0 is a high voltage signal used to reset NDC. Its purpose is to control T1 to be turned off from the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing the data voltage writing and threshold voltage compensation of the second pixel driving circuit from being affected, as well as the leakage of M1.

[0475] In the second stage P2 (which can be the data writing stage), RSTA, RSTB, RSTC, and RSTT all provide high voltage signals, GTA and GTB all provide low voltage signals, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA, DTB provides the second data voltage VdataB, and the voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. This ensures that TD1 and TD2 are turned on at the beginning of the second stage P2. When the potential of N1 is VdataA + Vth1, TD1 is turned off, and when the potential of N5 is VdataB + Vth2, TD2 is turned off to perform threshold voltage compensation. Vth1 is the threshold voltage of TD1, and Vth2 is the threshold voltage of TD2.

[0476] In the third stage P3, RSTC provides a low voltage signal, T12 turns on, and I3 provides a third initial voltage Vinit3 to the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0477] In the fourth stage P4, GT provides a low voltage signal, T2 turns on, and the control data voltage Vdata provided by DT is written to NDC; Vdata is a high voltage signal to control T16 to turn off.

[0478] In the fifth stage P5 (which can be the light-emitting stage), EM1 and EM3 provide low voltage signals, T16 is turned off, and T8, TD1 and T7 are turned on. TD1 drives M1 to emit light for medium and low grayscale display.

[0479] As shown in Figure 20B, at least one embodiment of the pixel circuit shown in Figure 19 performs low-to-medium grayscale display and can provide the previous frame's second data voltage, black state data voltage, or high voltage signal to the second data voltage terminal DTB, further reducing logic power consumption.

[0480] The differences between at least one embodiment of the pixel circuit shown in Figure 22 and at least one embodiment of the pixel circuit shown in Figure 19 are as follows:

[0481] The gate of the third transistor T3 is electrically connected to the reset control terminal RST;

[0482] The gate of the eleventh transistor T11 is electrically connected to the reset control terminal RST.

[0483] The gate of the twelfth transistor T12 is electrically connected to the reset control terminal RST;

[0484] The gate of the sixteenth transistor T16 is electrically connected to the reset control terminal RST.

[0485] The gates of T14 and T15 are both electrically connected to the first scan terminal GTA;

[0486] The source of T11 and the source of T12 are both electrically connected to the first initial voltage terminal I1;

[0487] The source of T16 is electrically connected to the first initial voltage terminal I1.

[0488] In at least one embodiment of the pixel circuit shown in Figure 22, the gates of T3, T11, T12 and T16 are all electrically connected to the reset control terminal RST, the gates of T14 and T15 are all electrically connected to the first scan terminal GTA, and the second terminal of C1, the source of T11, the source of T12 and the source of T16 are all electrically connected to the first initial voltage terminal I1, so as to reduce the number of reset control terminals used, reduce the number of scan terminals used, and reduce the number of initial voltage terminals used.

[0489] Figure 23 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 22.

[0490] As shown in FIG23, when at least one embodiment of the pixel circuit shown in FIG22 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0491] In the first stage P1 (which can be a reset stage), RST provides a low voltage signal, T3, T11, and T16 are turned on, I1 writes the first initial voltage Vinit1 to N1 and N5, and I0 provides the display reset voltage Vinit0 to NDC. The first initial voltage Vinit1 provided by I1 is a low voltage signal (the voltage value of Vinit1 can be the same as the voltage value of the low voltage signal provided by VSS). When N1 and N5 are reset, it ensures that TD1 and TD2 are in the on state. The display reset voltage Vinit0 provided by I0 is a high voltage signal used to reset NDC. The purpose is to control T1 to be turned off from the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing the data voltage writing, threshold voltage compensation, and leakage of M1 from affecting the second pixel driving circuit. When T12 is turned on, I1 provides the first initial voltage Vinit1 to the anode of M1 to clear the residual charge on the anode of M1 and ensure that M1 is turned off.

[0492] In the second stage P2 (which can be the data writing stage), GTA provides a low voltage signal, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA, and DTB provides the second data voltage VdataB. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. This ensures that TD1 and TD2 are turned on at the beginning of the second stage P2. When the potential of N1 is VdataA + Vth1, TD1 is turned off, and when the potential of N5 is VdataB + Vth2, TD2 is turned off to perform threshold voltage compensation. Vth1 is the threshold voltage of TD1, and Vth2 is the threshold voltage of TD2.

[0493] In the third stage P3, EM1, RST, GT, EM3 and GT all provide high voltage signals;

[0494] In the fourth stage P4, GT provides a low voltage signal, DT provides a low voltage signal, T2 turns on, and the control data voltage Vdata provided by DT is written to NDC; Vdata is a low voltage signal to control T16 to turn on;

[0495] In the fifth stage P5 (which can be the light-emitting stage), EM1 and EM3 provide low voltage signals, and T7, T8, T13, TD1, TD2 and T1 are turned on. When performing high grayscale display, TD1 and TD2 jointly drive M1 to emit light. TD1 generates the first driving current Id1, and TD2 generates the second driving current Id2 to drive M1 to emit light. The pixel current Id flowing through M1 is equal to Id1 + Id2.

[0496] In at least one embodiment of the pixel circuit shown in Figure 22 of this disclosure, when performing low-to-medium grayscale display, in the fifth stage P5, T1 can be turned on, TD2 generates Id2 to drive M1 to emit light, and by adjusting VdataA, Id1 can be made to be 0.

[0497] In at least one embodiment of the pixel circuit shown in FIG22 of this disclosure, when performing low grayscale display, DT can provide a high voltage signal in the fourth stage P4 to control T1 to turn off in the fourth stage P4 and the fifth stage P5, and in the fifth stage P5, M1 is driven to emit light by TD1.

[0498] The differences between at least one embodiment of the pixel circuit shown in Figure 24 and at least one embodiment of the pixel circuit shown in Figure 22 are as follows:

[0499] The source of the second transistor T2 is electrically connected to the data line DA, and the sources of T9 and T14 are also electrically connected to the data line DA.

[0500] The gates of T9 and T10 are electrically connected to the nth scan terminal GT(n), the gates of T14 and T15 are electrically connected to the (n+1)th scan terminal GT(n+1), and the gate of T2 is electrically connected to the (n+2)th scan terminal GT(n+2).

[0501] Compared with at least one embodiment of the pixel circuit shown in FIG19 of this disclosure, at least one embodiment of the pixel circuit shown in FIG24 of this disclosure reduces the number of data lines used and reduces the influence of signal line crosstalk; GT(n), GT(n+1) and GT(n+2) share a set of GOA modules and write the corresponding data voltages in a time-division manner to reduce the number of GOA modules used, which is beneficial to achieving a narrow bezel.

[0502] Figure 25 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 24.

[0503] As shown in Figure 25, when at least one embodiment of the pixel circuit shown in Figure 24 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0504] In the first stage P1 (which can be a reset stage), RST provides a low voltage signal, T3, T11, and T16 are turned on, I1 writes the first initial voltage Vinit1 to N1 and N5, and I0 provides the display reset voltage Vinit0 to NDC. The first initial voltage Vinit1 provided by I1 is a low voltage signal (the voltage value of Vinit1 can be the same as the voltage value of the low voltage signal provided by VSS). When N1 and N5 are reset, it ensures that TD1 and TD2 are in the on state. The display reset voltage Vinit0 provided by I0 is a high voltage signal used to reset NDC. The purpose is to control T1 to be turned off from the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing the data voltage writing, threshold voltage compensation, and leakage of M1 from affecting the second pixel driving circuit. When T12 is turned on, I1 provides the first initial voltage Vinit1 to the anode of M1 to clear the residual charge on the anode of M1 and ensure that M1 is turned off.

[0505] In the second stage P2 (which can be the data writing stage), GT(n) provides a low voltage signal, T9 and T10 are turned on, DA provides the first data voltage VdataA, and the voltage value of Vinit2 is lower than the voltage value of VdataA, so that TD1 is turned on at the beginning of the second stage P2, and TD1 is turned off when the potential of N1 is VdataA+Vth1, in order to perform threshold voltage compensation, where Vth1 is the threshold voltage of TD1;

[0506] In the third stage P3, GT(n+1) provides a low voltage signal, T14 and T15 are both turned on, DA provides the second data voltage VdataB, the voltage value of Vinit4 is less than the voltage value of VdataB, so that TD2 is turned on at the beginning of the second stage P2, and TD2 is turned off when the potential of N5 is VdataB+Vth2, in order to perform threshold voltage compensation, where Vth2 is the threshold voltage of TD2;

[0507] In the fourth stage P4, GT(n+2) provides a low voltage signal, T2 turns on, and DA provides the control data voltage Vdata to NDC;

[0508] In the fifth stage, P5, EM1 and EM3 provide low voltage signals, and T7, T8, T13, TD1, TD2 and T1 are turned on;

[0509] When performing high grayscale display, Vdata can be a low voltage signal in the fourth stage P4. In the fifth stage P5, T1 is turned on, and TD1 and TD2 jointly drive M1 to emit light. TD1 generates the first driving current Id1, and TD2 generates the second driving current Id2 to drive M1 to emit light. The pixel current Id flowing through M1 is equal to Id1 + Id2.

[0510] When displaying low to medium grayscale, Vdata can be a low voltage signal in the fourth stage P4, and T1 can be turned on in the fifth stage P5. TD2 generates Id2 to drive M1 to emit light. By adjusting VdataA, Id1 can be made to be 0.

[0511] When displaying low to medium grayscale, DA can provide a high voltage signal in the fourth stage P4 to control T1 to turn off in the fourth stage P4 and the fifth stage P5. In the fifth stage P5, M1 is driven to emit light by TD1.

[0512] The difference between at least one embodiment of the pixel circuit shown in Figure 26 and at least one embodiment of the pixel circuit shown in Figure 19 is as follows: T2 and T3 are n-type transistors, T9, T10 and T11 are n-type transistors, T14, T15 and T16 are n-type transistors; the other transistors are p-type transistors.

[0513] Figure 27 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 26.

[0514] In at least one embodiment of this disclosure, by taking advantage of the low leakage current of Oxide TFT, the leakage current of the node electrically connected to the gate of TD1, the node electrically connected to the gate of TD2, and NDC can be reduced, and all or part of T2, T3, T9, T10, T11, T14, T15, and T16 can be changed from PMOS TFT to NMOS TFT.

[0515] Taking advantage of the high mobility of PMOS TFTs, all or some of TD1, T7, T8, TD2, T1, and T13 can be set as PMOS TFTs. This is beneficial for reducing threshold voltage compensation and the compensation time at point N1 during the light emission stage, meeting current drive requirements, reducing capacitor area, and further improving display performance.

[0516] In at least one embodiment of this disclosure, the gate of TD1 is electrically connected to the first node N1.

[0517] As shown in FIG27, when at least one embodiment of the pixel circuit shown in FIG26 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0518] In the first stage P1 (which can be a reset stage), EM1 provides a high voltage signal, RSTA provides a high voltage signal, RSTC provides a high voltage signal, GTA provides a low voltage signal, EM3 provides a high voltage signal, RSTB provides a high voltage signal, GTB provides a low voltage signal, RSTT provides a high voltage signal, and GT provides a low voltage signal. T3, T11, and T16 are turned on. I2 writes the second initial voltage Vinit2 to N1, I4 writes the second initial voltage Vinit2 to N5, and I0 provides the display reset voltage Vinit0 to NDC. The fourth initial voltage Vinit4 provided by Vinit2 and I4 is a low voltage signal (the voltage values ​​of Vinit2 and Vinit4 can be the same as the low voltage signal provided by VSS). When N1 and N5 are reset, it ensures that TD1 and TD2 are in the open state. The display reset voltage Vinit0 provided by I0 is a high voltage signal, which is used to reset NDC. Its purpose is to control T1 to turn off in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing the data voltage writing, threshold voltage compensation and leakage of M1 from affecting the second pixel driving circuit.

[0519] In the second stage P2 (which can be the data writing stage), EM1 provides a high voltage signal, RSTA provides a low voltage signal, RSTC provides a low voltage signal, GTA provides a high voltage signal, EM3 provides a high voltage signal, RSTB provides a low voltage signal, GTB provides a high voltage signal, RSTT provides a low voltage signal, GT provides a low voltage signal, T9, T10, T14, and T15 are all turned on, DTA provides the first data voltage VdataA, DTB provides the second data voltage VdataB, the voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is less than the voltage value of VdataB, so that TD1 and TD2 are turned on at the beginning of the second stage P2. When the potential of N1 is VdataA + Vth1, TD1 is turned off, and when the potential of N5 is VdataB + Vth2, TD2 is turned off for threshold voltage compensation. Vth1 is the threshold voltage of TD1, and Vth2 is the threshold voltage of TD2.

[0520] In the third stage P3, EM1 provides a high voltage signal, RSTA provides a low voltage signal, RSTC provides a low voltage signal, GTA provides a low voltage signal, EM3 provides a high voltage signal, RSTB provides a low voltage signal, GTB provides a low voltage signal, RSTT provides a low voltage signal, GT provides a low voltage signal, T12 is turned on, and I3 provides a third initial voltage Vinit3 to the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0521] In the fourth stage P4, EM1 provides a high voltage signal, RSTA provides a low voltage signal, RSTC provides a high voltage signal, GTA provides a low voltage signal, EM3 provides a high voltage signal, RSTB provides a low voltage signal, GTB provides a low voltage signal, RSTT provides a low voltage signal, GT provides a high voltage signal, and DT provides a low voltage signal to control T16 to turn on.

[0522] In the fifth stage P5 (which can be the light-emitting stage), EM1 and EM3 provide low voltage signals, and T7, T8, T13, TD1, TD2 and T1 are turned on. When performing high grayscale display, TD1 and TD2 jointly drive M1 to emit light. TD1 generates the first driving current Id1, and TD2 generates the second driving current Id2 to drive M1 to emit light. The pixel current Id flowing through M1 is equal to Id1 + Id2.

[0523] In at least one embodiment of the pixel circuit shown in Figure 26 of this disclosure, when performing low-to-medium grayscale display, in the fifth stage P5, T1 can be turned on, TD2 generates Id2 to drive M1 to emit light, and by adjusting VdataA, Id1 can be made to be 0.

[0524] In at least one embodiment of the pixel circuit shown in Figure 26 of this disclosure, during operation, when performing low-to-medium grayscale display, DT can provide a high voltage signal in the fourth stage P4 to control T1 to turn off in the fourth stage P4 and the fifth stage P5, and in the fifth stage P5, M1 is driven to emit light by TD1.

[0525] The difference between at least one embodiment of the pixel circuit shown in Figure 28 and at least one embodiment of the pixel circuit shown in Figure 19 is as follows: the drains of ND and TD1 are electrically connected.

[0526] The gate of T8 is electrically connected to the second light-emitting control terminal EM2.

[0527] In at least one embodiment of the pixel circuit shown in Figure 28, the driving timing of the first light emission control signal provided by EM1 and the driving timing of the second light emission control signal provided by EM2 can be the same during operation.

[0528] As shown in Figure 29, based on at least one embodiment of the pixel circuit shown in Figure 17,

[0529] The on / off control circuit includes a first transistor T1, the display control writing circuit includes a second transistor T2, the display control reset circuit includes a third transistor T3, the first energy storage circuit includes a first capacitor C1, and the light-emitting element is a miniature light-emitting diode M1.

[0530] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW; ND is electrically connected to the anode of M1.

[0531] The gate of the second transistor T2 is electrically connected to the display control scan terminal GT, the source of the second transistor T2 is electrically connected to the control data voltage terminal DT, and the drain of the second transistor T2 is electrically connected to the display control node NDC.

[0532] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the display reset voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the display control node NDC; the display reset voltage terminal I0 is used to provide the display reset voltage Vinit0.

[0533] The first terminal of the first capacitor C1 is electrically connected to the display control node NDC, and the second terminal of the first capacitor C1 is electrically connected to the first initial voltage terminal I1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0534] The first driving circuit includes a first driving transistor TD1; the fourth energy storage circuit includes a fourth capacitor C4;

[0535] The drain of TD1 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low-level terminal VSS.

[0536] The first terminal of the fourth capacitor C4 is electrically connected to the gate of the first driving transistor TD1, and the second terminal of the fourth capacitor C4 is electrically connected to the drain of the first driving transistor TD1.

[0537] The first data writing circuit includes a ninth transistor T9, and the switch control circuit includes a seventeenth transistor T17;

[0538] The gate of the ninth transistor T9 is electrically connected to the first scan terminal GTA, the source of the ninth transistor T9 is electrically connected to the first data voltage terminal DTA, and the drain of the ninth transistor T9 is electrically connected to the gate of the first driving transistor TD1.

[0539] The gate of the seventeenth transistor T17 is electrically connected to the third scanning terminal GTC, the source of the seventeenth transistor T17 is electrically connected to the external compensation sensing line SL, and the drain of the seventeenth transistor T17 is electrically connected to the drain of the first driving transistor TD1.

[0540] The second light-emitting control circuit includes an eighth transistor T8;

[0541] The gate of the eighth transistor T8 is electrically connected to the second light-emitting control terminal EM2, the source of the eighth transistor T8 is electrically connected to the first power supply voltage terminal VDD1, and the drain of the eighth transistor T8 is electrically connected to the source of the first driving transistor TD1.

[0542] The first switching circuit includes a first switch K1, and the second switching circuit includes a second switch K2;

[0543] The control terminal of the first switch K1 is electrically connected to the first switch control terminal SC1, the first terminal of the first switch K1 is electrically connected to the external compensation sensing line SL, and the second terminal of the first switch K1 is electrically connected to the reference voltage terminal REF.

[0544] The control terminal of the second switch K2 is electrically connected to the control terminal SC2 of the second switch, the first terminal of the second switch K2 is electrically connected to the external compensation sensing line SL, and the second terminal of the second switch K2 is electrically connected to the sensing terminal SENS.

[0545] The second driving circuit includes a second driving transistor TD2, the second data writing circuit includes a fourteenth transistor T14, and the third energy storage circuit includes a third capacitor C3.

[0546] The drain of the second driving transistor TD2 is electrically connected to the write node NW;

[0547] The gate of the fourteenth transistor T14 is electrically connected to the second scan terminal GTB, the source of the fourteenth transistor T14 is electrically connected to the second data voltage terminal DTB, and the drain of the fourteenth transistor T14 is electrically connected to the gate of the second driving transistor TD2.

[0548] The first terminal of the third capacitor C3 is electrically connected to the gate of the second driving transistor TD2, and the second terminal of the third capacitor C3 is electrically connected to the write node NW.

[0549] The third light-emitting control circuit includes a thirteenth transistor T13;

[0550] The gate of the thirteenth transistor T13 is electrically connected to the third light-emitting control terminal EM3, the source of the thirteenth transistor T13 is electrically connected to the second power supply voltage terminal VDD2, and the second terminal of the thirteenth transistor T13 is electrically connected to the source of the second driving transistor TD2.

[0551] In at least one embodiment of the pixel circuit shown in Figure 29, all transistors are n-type transistors.

[0552] In at least one embodiment of the pixel circuit shown in Figure 29, the first pixel driving circuit and the second pixel driving circuit share a set of external compensation circuits. After extracting the threshold voltage or driving current, the compensation is applied to the first pixel driving circuit and the second pixel driving circuit through DTA and DTB, respectively.

[0553] Figure 30 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 29.

[0554] As shown in Figure 30, when at least one embodiment of the pixel circuit shown in Figure 29 is in operation, a frame time may include a display stage TD and a compensation stage TC set sequentially. The display stage TD may include a first stage P1, a second stage P2, a third stage P3 and a fourth stage P4 set sequentially.

[0555] In the first stage P1 (the first stage can be the reset stage), RSTT provides a high voltage signal, T3 is turned on, and I0 will display the reset voltage Vinit0 to NDC, as shown in Figure 31A, with T1 turned on.

[0556] In the second stage P2 (which can be the data writing stage), both GTA and GTB provide high voltage signals, as shown in Figure 31B. T9 and T14 are both turned on. DTA provides the first data voltage VdataA to the gate of TD1, and DTB provides the second data voltage VdataB to the gate of TD2. GTC provides a high voltage signal, and T17 is turned on. At the same time, SC1 is turned on, and REF provides the reference voltage Vref to SL. Vref is then written to the anode of M1 through T17. Since the potential of NDC is maintained at Vinit0, T1 is turned on to reset the potential of NW.

[0557] In the third stage P3, GT provides a high voltage signal, as shown in Figure 31C, T2 is turned on, and DT provides control data voltage Vdata to NDC; when displaying high grayscale, DT provides a high voltage signal and T1 is turned on; when displaying medium and low grayscale, DT provides a low voltage signal and T1 is turned off.

[0558] In the fourth stage P4 (the fourth stage can be the light emission stage), both EM2 and EM3 provide high voltage signals, as shown in Figure 31D, and T8 and T13 are turned on.

[0559] When performing high grayscale display, T1 is turned on, and TD1 and TD2 together drive M1 to emit light; TD1 generates the first driving current Id1, TD2 generates the second driving current Id2, and the pixel current Id flowing through M1 is equal to Id1 + Id2;

[0560] When displaying low to medium grayscale, T1 is off, TD1 drives M1 to emit light, TD1 generates a first driving current Id1, and the pixel current Id flowing through M1 is equal to Id1; or...

[0561] When displaying low to medium grayscale, T1 is turned on, TD2 generates a second driving current Id2, and the pixel current Id flowing through M1 is equal to Id2; by adjusting the first data voltage provided by DTA, Id1 generated by TD1 can be made equal to 0.

[0562] It should be noted that when displaying low to medium grayscale, if pixel current is provided through TD1, the DTB can be supplied with signals such as the second data voltage of the previous frame, the black state data voltage, or a high voltage signal, which can further reduce logic power consumption.

[0563] As shown in Figure 30, when at least one embodiment of the pixel circuit shown in Figure 29 is working, the compensation stage TC may include a reset time period S1, a threshold compensation time period S2, and an extraction time period S3 set sequentially.

[0564] During the compensation phase, GTA, GTB, and GTC all provide high voltage signals, and T9, T14, and T17 are all turned on; EM2 and EM3 all provide high voltage signals; and T8 and T13 are all turned on.

[0565] During the reset period S1, SC1 provides a high voltage signal to control K1 to turn on, REF provides the reference voltage Vref to SL, T17 turns on to write Vref to the anode of M1; SC1 provides a low voltage signal, and K2 turns off.

[0566] During the compensation period S2, SC1 provides a low voltage signal, SC2 provides a low voltage signal, K1 and K2 are both disconnected, and T9, T14 and T17 are all open.

[0567] During the compensation period S2, when the potential of NDC is low, T1 is turned on, and TD1 and TD2 provide the current generated by them to SL to raise the potential of SL; during the advance period S3, SC1 provides a low voltage signal, SC2 provides a high voltage signal, K1 is turned off, K2 is turned on, and SENS and SL are connected. Threshold voltage compensation can be performed on the first data voltage and the second data voltage according to the sensing voltage provided by SEN.

[0568] During the compensation period S2, when the potential of NDC is high, T1 is turned off, and TD1 provides the current it generates to SL to raise the potential of SL. During the advance period S3, SC1 provides a low voltage signal, SC2 provides a high voltage signal, K1 is turned off, K2 is turned on, and SENS and SL are connected. The threshold voltage compensation of the first data voltage can be performed according to the sensing voltage provided by SEN.

[0569] As shown in Figure 32, based on at least one embodiment of the pixel circuit shown in Figure 18,

[0570] The on / off control circuit includes a first transistor T1, the display control writing circuit includes a second transistor T2, the display control reset circuit includes a third transistor T3, the first energy storage circuit includes a first capacitor C1, and the light-emitting element is a miniature light-emitting diode M1.

[0571] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW; ND is electrically connected to the anode of M1.

[0572] The gate of the second transistor T2 is electrically connected to the display control scan terminal GT, the source of the second transistor T2 is electrically connected to the control data voltage terminal DT, and the drain of the second transistor T2 is electrically connected to the display control node NDC.

[0573] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the display reset voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the display control node NDC; the display reset voltage terminal I0 is used to provide the display reset voltage Vinit0.

[0574] The first terminal of the first capacitor C1 is electrically connected to the display control node NDC, and the second terminal of the first capacitor C1 is electrically connected to the first initial voltage terminal I1; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0575] The first driving circuit includes a first driving transistor TD1; the fourth energy storage circuit includes a fourth capacitor C4;

[0576] The drain of TD1 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low-level terminal VSS.

[0577] The first terminal of the fourth capacitor C4 is electrically connected to the gate of the first driving transistor TD1, and the second terminal of the fourth capacitor C4 is electrically connected to the drain of the first driving transistor TD1.

[0578] The first data writing circuit includes a ninth transistor T9, and the switch control circuit includes a seventeenth transistor T17;

[0579] The gate of the ninth transistor T9 is electrically connected to the first scan terminal GTA, the source of the ninth transistor T9 is electrically connected to the first data voltage terminal DTA, and the drain of the ninth transistor T9 is electrically connected to the gate of the first driving transistor TD1.

[0580] The gate of the seventeenth transistor T17 is electrically connected to the third scanning terminal GTC, the source of the seventeenth transistor T17 is electrically connected to the external compensation sensing line SL, and the drain of the seventeenth transistor T17 is electrically connected to the drain of the first driving transistor TD1.

[0581] The second light-emitting control circuit includes an eighth transistor T8; the first driving circuit includes a first driving transistor TD1;

[0582] The source of the first driving transistor TD1 is electrically connected to the first power supply voltage terminal VDD1;

[0583] The gate of the eighth transistor T8 is electrically connected to the second light-emitting control terminal EM2, the source of the eighth transistor T8 is electrically connected to the drain of the first driving transistor TD1, and the drain of the eighth transistor T8 is electrically connected to the anode of M1.

[0584] The first switching circuit includes a first switch K1, and the second switching circuit includes a second switch K2;

[0585] The control terminal of the first switch K1 is electrically connected to the first switch control terminal SC1, the first terminal of the first switch K1 is electrically connected to the external compensation sensing line SL, and the second terminal of the first switch K1 is electrically connected to the reference voltage terminal REF.

[0586] The control terminal of the second switch K2 is electrically connected to the control terminal SC2 of the second switch, the first terminal of the second switch K2 is electrically connected to the external compensation sensing line SL, and the second terminal of the second switch K2 is electrically connected to the sensing terminal SENS.

[0587] The second driving circuit includes a second driving transistor TD2, the second data writing circuit includes a fourteenth transistor T14, and the third energy storage circuit includes a third capacitor C3.

[0588] The source of the second driving transistor TD2 is electrically connected to the second power supply voltage terminal VDD2, and the drain of the second driving transistor TD2 is electrically connected to the write node NW.

[0589] The gate of the fourteenth transistor T14 is electrically connected to the second scan terminal GTB, the source of the fourteenth transistor T14 is electrically connected to the second data voltage terminal DTB, and the drain of the fourteenth transistor T14 is electrically connected to the gate of the second driving transistor TD2.

[0590] The first terminal of the third capacitor C3 is electrically connected to the gate of the second driving transistor TD2, and the second terminal of the third capacitor C3 is electrically connected to the write node NW.

[0591] In at least one embodiment shown in Figure 32, all transistors are n-type transistors.

[0592] As shown in Figure 33, based on at least one embodiment shown in Figure 5...

[0593] The on / off control circuit includes a first transistor T1, the display control writing circuit includes a second transistor T2, the display control reset circuit includes a third transistor T3, and the first energy storage circuit includes a first capacitor C1; the control circuit includes a fourth transistor T4 and a fifth transistor T5.

[0594] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW.

[0595] The gate of the second transistor T2 is electrically connected to the display control scanning terminal GT, the source of the second transistor T2 is electrically connected to the control data voltage terminal DT, and the drain of the second transistor T2 is electrically connected to the control node NC.

[0596] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the display reset voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the display control node NDC.

[0597] The first terminal of the first capacitor C1 is electrically connected to the control node NC, and the second terminal of the first capacitor C1 is electrically connected to the first initial voltage terminal I1.

[0598] The gate of the fourth transistor T4 is electrically connected to the control node NC, the source of the fourth transistor T4 is electrically connected to the low voltage terminal VGL, and the drain of the fourth transistor T4 is electrically connected to the display control node NDC.

[0599] The gate of the fifth transistor T5 is electrically connected to the control node NC, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the display control node NDC.

[0600] In at least one embodiment shown in Figure 33, T1, T2, T3 and T5 are all p-type transistors, and T4 is an n-type transistor.

[0601] In at least one embodiment shown in Figure 33, during operation, in the first stage, RSTT can provide a low voltage signal, T3 is turned on, and I0 provides the display reset voltage Vinit0 to NDC to reset NDC. The purpose is to control T1 to be turned off in the first to third stages, so that the display control circuit is in the off state.

[0602] In the fourth stage, GT provides a low voltage signal, T2 is turned on, and DT provides control data voltage Vdata to NC; when DT provides a low voltage signal, T4 is turned off, T5 is turned on, NDC and VGH are connected, and T1 is turned off; when DT provides a high voltage signal, T4 is turned on, T5 is turned off, NC and VGL are connected, and T1 is turned on.

[0603] As shown in Figure 34, based on at least one embodiment shown in Figure 4...

[0604] The on / off control circuit includes a first transistor T1, the display control writing circuit includes a second transistor T2, the display control reset circuit includes a third transistor T3, and the first energy storage circuit includes a first capacitor C1.

[0605] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW.

[0606] The gate of the second transistor T2 is electrically connected to the display control scan terminal GT, the source of the second transistor T2 is electrically connected to the control data voltage terminal DT, and the drain of the second transistor T2 is electrically connected to the display control node NDC.

[0607] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the display control node NDC.

[0608] The first terminal of C1 is electrically connected to the display control node NDC, and the second terminal of C1 is electrically connected to the first initial voltage terminal I1.

[0609] In at least one embodiment shown in Figure 34, T1, T2 and T3 are all p-type transistors.

[0610] In at least one embodiment shown in Figure 34, during operation, in the first stage, RSTT can provide a low voltage signal, T3 is turned on, and I0 provides the display reset voltage Vinit0 to NDC to reset NDC. The purpose is to control T1 to be turned off in the first to third stages, so that the display control circuit is in the off state.

[0611] In the fourth stage, GT provides a low voltage signal, T2 turns on, and DT provides control data voltage Vdata to NC; when DT provides a low voltage signal, T1 turns on; when DT provides a high voltage signal, T1 turns off.

[0612] As shown in Figure 35, based on at least one embodiment of the pixel circuit shown in Figure 16, the on / off control circuit includes a first transistor T1, the display control writing circuit includes a first second transistor M12 and a second second transistor M22, the display control reset circuit includes a third transistor T3, and the first energy storage circuit includes a first capacitor C1.

[0613] The gate of the first transistor T1 is electrically connected to the display control node NDC, the source of the first transistor T1 is electrically connected to the display node ND, and the drain of the first transistor T1 is electrically connected to the write node NW.

[0614] The source of M12 is electrically connected to the control data voltage terminal DT, and the gate and drain of M12 are electrically connected to the source of M22.

[0615] The gate of M22 is electrically connected to the display control scanning terminal GT, and the drain of M22 is electrically connected to the display control node NDC.

[0616] The gate of the third transistor T3 is electrically connected to the display reset control terminal RSTT, the source of the third transistor T3 is electrically connected to the display reset voltage terminal I0, and the drain of the third transistor T3 is electrically connected to the display control node NDC; the display reset voltage terminal I0 is used to provide the display reset voltage Vinit0.

[0617] The first terminal of the first capacitor C1 is electrically connected to the display control node NDC, and the second terminal of the first capacitor C1 is electrically connected to the switch control voltage terminal SW.

[0618] The first light-emitting control circuit includes a seventh transistor T7; the first driving circuit includes a first driving transistor TD1; the light-emitting element is a miniature light-emitting diode M1;

[0619] The gate of the seventh transistor T7 is electrically connected to the first light-emitting control terminal EM1, the source of the seventh transistor T7 is electrically connected to the drain of the first driving transistor TD1, and the drain of the seventh transistor T7 is electrically connected to the anode of M1.

[0620] The second light-emitting control circuit includes an eighth transistor T8, the first data writing circuit includes a ninth transistor T9, the first compensation control circuit includes a tenth transistor T10, the first initialization circuit includes an eleventh transistor T11, and the second energy storage circuit includes a second capacitor C2.

[0621] The gate of the eighth transistor T8 is electrically connected to the first light-emitting control terminal EM1, the source of the eighth transistor T8 is electrically connected to the first power supply voltage terminal VDD1, and the drain of the eighth transistor T8 is electrically connected to the source of the first driving transistor TD1; the first light-emitting control terminal and the second light-emitting control terminal are the same light-emitting control terminal.

[0622] The gate of the ninth transistor T9 is electrically connected to the first scan terminal GTA, the source of the ninth transistor T9 is electrically connected to the first data voltage terminal DTA, and the drain of the ninth transistor T9 is electrically connected to the source of the first driving transistor TD1.

[0623] The gate of the tenth transistor T10 is electrically connected to the first scan terminal GTA, the source of the tenth transistor T10 is electrically connected to the gate of the first driving transistor TD1, and the drain of the tenth transistor T10 is electrically connected to the drain of the first driving transistor TD1.

[0624] The gate of the eleventh transistor T11 is electrically connected to the first reset control terminal RSTA, the source of the eleventh transistor T11 is electrically connected to the second initial voltage terminal I2, and the drain of the eleventh transistor T11 is electrically connected to the gate of the first driving transistor TD1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0625] The first terminal of the second capacitor C2 is electrically connected to the gate of the first driving transistor TD1, and the second terminal of the second capacitor C2 is electrically connected to the first power supply voltage terminal VDD1; the first DC voltage terminal is the first power supply voltage terminal VDD1.

[0626] The second initialization circuit includes a twelfth transistor T12;

[0627] The gate of the twelfth transistor T12 is electrically connected to the second reset control terminal RSTC, the source of the twelfth transistor T12 is electrically connected to the third initial voltage terminal I3, and the drain of the twelfth transistor T12 is electrically connected to the anode of M1; the third initial voltage terminal I3 is used to provide the third initial voltage Vinit3; the cathode of M1 is electrically connected to the low-level terminal VSS; the fourth voltage terminal is the low-level terminal VSS;

[0628] The second driving circuit includes a second driving transistor TD2, the third light-emitting control circuit includes a thirteenth transistor T13, the second data writing circuit includes a fourteenth transistor T14, the second compensation control circuit includes a fifteenth transistor T15, the third initialization circuit includes a sixteenth transistor T16, and the third energy storage circuit includes a third capacitor C3.

[0629] The drain of the second driving transistor TD2 is electrically connected to the write node NW;

[0630] The gate of the thirteenth transistor T13 is electrically connected to the third light-emitting control terminal EM3, the source of the thirteenth transistor T13 is electrically connected to the second power supply voltage terminal VDD2, and the drain of the thirteenth transistor T13 is electrically connected to the source of the second driving transistor TD2.

[0631] The gate of the fourteenth transistor T14 is electrically connected to the second scan terminal GTB, the source of the fourteenth transistor T14 is electrically connected to the second data voltage terminal DTB, and the drain of the fourteenth transistor T14 is electrically connected to the source of the second driving transistor TD2.

[0632] The gate of the fifteenth transistor T15 is electrically connected to the second scan terminal GTB, the source of the fifteenth transistor T15 is electrically connected to the gate of the second driving transistor TD2, and the drain of the fifteenth transistor T15 is electrically connected to the drain of the second driving transistor TD2.

[0633] The gate of the sixteenth transistor T16 is electrically connected to the third reset control terminal RSTB, the source of the sixteenth transistor T16 is electrically connected to the fourth initial voltage terminal I4, and the drain of the sixteenth transistor T16 is electrically connected to the gate of the second driving transistor TD2; the fourth initial voltage terminal I4 is used to provide the fourth initial voltage Vinit4.

[0634] The first terminal of the third capacitor C3 is electrically connected to the gate of the second driving transistor TD2, and the second terminal of the third capacitor C3 is electrically connected to the second power supply voltage terminal VDD2; the second DC voltage terminal is the second power supply voltage terminal VDDD2.

[0635] In at least one embodiment of the pixel circuit shown in Figure 35, all transistors are p-type transistors.

[0636] In Figure 35, node N1 is the first node and node N5 is the fifth node; the gates of N1 and TD1 are electrically connected, and the gates of N5 and TD2 are electrically connected.

[0637] At least one embodiment of the pixel circuit shown in Figure 35 of this disclosure, when in operation,

[0638] When performing high grayscale display, during the light emission stage, T1 can be turned off, and M1 is driven to emit light by TD1. EM1 can be a long pulse width light emission control signal, a single pulse width duration control signal, or a high frequency pulse width control signal. The total pulse width (long duration light emission) within a frame matches the high current to drive the backplane to achieve high grayscale display.

[0639] During low-to-medium grayscale display, in the light-emitting phase, the first data voltage VdataA provided by DTA is adjusted to make the first driving current Id1 generated by TD1 zero; in the reset phase, RSTT provides a low voltage signal, T3 is turned on, and I0 provides the display reset voltage Vinit0 to NDC, where Vinit0 can be high; T1 is turned off; in the data writing phase, the light-emitting time of different pulse widths can be controlled by controlling the voltage value of the control data voltage Vdata provided by DT; GT provides a low voltage signal to write Vdata+Vth0 to NDC, where... Vth0 is the threshold voltage of M12; SW provides a high-level signal SW_Vgh, and T1 is turned off; during the light-emitting stage, both EM1 and EM3 provide low-voltage signals. At the beginning of the light-emitting stage, T1 is turned off. As the potential of the switch control voltage provided by SW decreases, the potential of NDC decreases. When the potential of NDC decreases to the point that T1 can be turned on, the second driving current Id2 generated by TD2 is written into M1 to drive M1 to emit light. The voltage values ​​of the control data voltage written by DT are different, and the turn-on time of T1 is different during the light-emitting stage, thereby realizing different pulse width control for medium and low gray levels.

[0640] Furthermore, the first pixel driving circuit controls high grayscale display. In the current path of the first pixel driving circuit, the channel width-to-length ratios of TD1, T7, and T8, as well as the first power supply voltage Vdd1 provided by VDD1, are matched to the pixel current Id corresponding to the high grayscale. For example, high grayscale uses the current density corresponding to the highest efficiency of M1. Since the current is higher, TD1 needs to meet the current driving capability, so the channel width of TD1 is set to be relatively large, and the channel width-to-length ratio of TD1 is also set to be relatively large. The second pixel driving circuit performs medium-low grayscale display. In the current path of the second pixel driving circuit, the channel width-to-length ratios of T13, TD2, and T1, as well as the voltage value of the second power supply voltage Vdd2 provided by VDD2, are matched to the medium-low grayscale current. For example, to match the pixel current corresponding to the brightness uniformity of the medium-low current density, the channel length of TD2 can be set to be larger. A larger channel length results in a larger subthreshold swing SS, making low grayscale expansion easier and more refined.

[0641] In at least one embodiment shown in Figure 35, the first node N1 is electrically connected to the gate of TD1, and the fifth node N5 is electrically connected to the gate of TD2.

[0642] As shown in FIG36, when at least one embodiment of the pixel circuit shown in FIG35 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0643] In the first stage P1, RSTA, RSTB, and RSTT all provide low voltage signals, as shown in Figure 37A. T11, T16, and T3 are all on, resetting N1, N5, and NDC. I2 provides the second initial voltage Vinit2 to N1, and I4 provides the fourth initial voltage Vinit4 to N5. The voltage value of Vinit2 can be low (it can be the same as the voltage value of the low voltage signal provided by VSS). N1 and N5 are reset. During the reset, TD1 and TD2 are ensured to be on. I0 provides the display reset voltage Vinit0 to NDC. The voltage value of Vinit0 is high, resetting NDC. The purpose is to turn off T1 in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing data voltage writing of the second pixel driving circuit, threshold voltage compensation, and leakage of M1.

[0644] In the second phase P2, both GTA and GTB provide low voltage signals, as shown in Figure 37B. T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA to N1, and DTB provides the second data voltage VdataB to N5. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. At the beginning of the second phase P2, TD1 and TD2 are turned on, changing the potentials of N1 and N5 until the potential of N1 is VdataA + Vth1, at which point TD1 is turned off. Then, TD2 is turned off until the potential of N5 is VdataB + Vth2, at which point, to perform data voltage writing and threshold voltage compensation.

[0645] In the third stage P3, RSTC provides a low voltage signal, as shown in Figure 37C. T12 turns on, and I3 provides a third initial voltage Vinit3 to ND to clear the potential of the anode of M1. Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0646] In the fourth stage P4, GT provides a low voltage signal, DT performs self-compensation through M12, and writes Vdata+Vth12 into NDC. Vdata is the control data voltage provided by DT, and Vth12 is the threshold voltage of M12. DT provides a high voltage signal, as shown in Figure 37D, M12 is turned on, and T1 is turned off.

[0647] During the light-emitting phase, P5, EM1, and EM3 all provide low-voltage signals, as shown in Figure 37E. T8, T7, and T13 are all turned on, T1 is turned off, TD1 and TD2 are turned on, and ND and NW are disconnected. TD1 drives M1 to emit light. TD1 generates the first driving current Id1, and the pixel current of M1 is equal to Id1, matching the light-emitting duration controlled by EM1. M1 emits light for high grayscale display. At this time, the second pixel driving circuit does not drive the light-emitting element, and T1 is turned off. As the voltage value of the switch control voltage provided by SW is pulled down to the switch control low level SW_vgl, the potential of NDC can still control T1 to turn off.

[0648] In at least one embodiment of the pixel circuit shown in Figure 35 of this disclosure, during high grayscale display, T1 can be turned on in the fifth stage, and M1 is driven to emit light by TD1 and TD2 together.

[0649] As shown in FIG38, when at least one embodiment of the pixel circuit shown in FIG35 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0650] In the first stage P1, RSTA, RSTB, and RSTT all provide low voltage signals, and T11, T16, and T3 are all on, resetting N1, N5, and NDC. I2 provides the second initial voltage Vinit2 to N1, and I4 provides the fourth initial voltage Vinit4 to N5. The voltage value of Vinit2 can be low (it can be the same as the voltage value of the low voltage signal provided by VSS), resetting N1 and N5. During the reset, it is ensured that TD1 and TD2 are on. I0 provides the display reset voltage Vinit0 to NDC. The voltage value of Vinit0 is high, resetting NDC. The purpose is to turn off T1 in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing data voltage writing of the second pixel driving circuit, threshold voltage compensation, and leakage of M1.

[0651] In the second phase P2, both GTA and GTB provide low voltage signals, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA to N1, and DTB provides the second data voltage VdataB to N5. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. At the beginning of the second phase P2, TD1 and TD2 are turned on, changing the potentials of N1 and N5 until the potential of N1 is VdataA + Vth1, at which point TD1 is turned off. Then, TD2 is turned off until the potential of N5 is VdataB + Vth2, at which point, to perform data voltage writing and threshold voltage compensation.

[0652] In the third stage P3, RSTC provides a low voltage signal, T12 turns on, and I3 provides a third initial voltage Vinit3 to ND to clear the potential of the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0653] In the fourth stage P4, GT provides a low voltage signal, DT performs self-compensation through M12, writes Vdata+Vth12 into NDC, Vdata is the control data voltage provided by DT, and Vth12 is the threshold voltage of M12; DT provides the matching voltage required for the pulse width, M11 and M12 are turned on, and T1 is turned off.

[0654] In the fifth stage P5 (the fifth stage can be the light-emitting stage), EM1 and EM3 both provide low voltage signals, as shown in Figure 37F. T8, T7 and T13 are all turned on. By controlling VdataA, the first drive current Id1 generated by TD1 is controlled to be 0.

[0655] At the start of the fifth stage P5, the potential of NDC is Vdata + Vth12, T1 is turned off, and M1 does not emit light;

[0656] In the fifth stage P5, as the voltage value of the switch control voltage provided by SW decreases, the potential of NDC decreases accordingly. When the potential of NDC decreases to the point that T1 can be turned on, the second driving current Id2 generated by TD2 drives M1 to emit light through T1 until the voltage value of the switch control voltage provided by SW is pulled up, which pulls up the potential of NDC, causing T1 to turn off and M1 to stop emitting light.

[0657] In the fourth stage P4, the voltage values ​​of the control data voltage written by DT are different. In the fifth stage P5, the light emission time of M1 is different, thus achieving different pulse width modulation. At this time, by adjusting VdataA, Id1 is made equal to 0, the pixel current Id flowing through M1 is made equal to Id2, and M1 is only driven to emit light by TD2 to perform medium and low grayscale display.

[0658] It should be noted that when displaying in low to medium grayscale, the voltage value of Vdata must be set to be greater than the voltage value of Vinit0 in order for Vdata to be written to NDC.

[0659] Furthermore, the channel width-to-length ratio of T1 can be the same as that of M12, and the threshold voltage of M12 can be approximately the same as that of T1, so that the control data voltage Vdata provided by DT can eliminate the difference in pulse width duration caused by the different threshold voltage of T1 through the self-compensation of M12.

[0660] In a preferred embodiment, to reduce eye fatigue, the switching control voltage provided by SW and the first light emission control signal provided by EM1 can be high-frequency pulse signals.

[0661] In Figure 38, the period labeled SE is the emission time period. During the emission time period SE, M1 emits light.

[0662] In Figures 36 and 38, in the fifth stage P5, SW can be a single pulse width control signal.

[0663] As shown in FIG39, when at least one embodiment of the pixel circuit shown in FIG35 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0664] In the first stage P1, RSTA, RSTB, and RSTT all provide low voltage signals, and T11, T16, and T3 are all on, resetting N1, N5, and NDC. I2 provides the second initial voltage Vinit2 to N1, and I4 provides the fourth initial voltage Vinit4 to N5. The voltage value of Vinit2 can be low (it can be the same as the voltage value of the low voltage signal provided by VSS), resetting N1 and N5. During the reset, it is ensured that TD1 and TD2 are on. I0 provides the display reset voltage Vinit0 to NDC. The voltage value of Vinit0 is high, resetting NDC. The purpose is to turn off T1 in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing data voltage writing of the second pixel driving circuit, threshold voltage compensation, and leakage of M1.

[0665] In the second phase P2, both GTA and GTB provide low voltage signals, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA to N1, and DTB provides the second data voltage VdataB to N5. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. At the beginning of the second phase P2, TD1 and TD2 are turned on, changing the potentials of N1 and N5 until the potential of N1 is VdataA + Vth1, at which point TD1 is turned off. Then, TD2 is turned off until the potential of N5 is VdataB + Vth2, at which point, to perform data voltage writing and threshold voltage compensation.

[0666] In the third stage P3, RSTC provides a low voltage signal, T12 turns on, and I3 provides a third initial voltage Vinit3 to ND to clear the potential of the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0667] In the fourth stage P4, GT provides a low voltage signal, DT performs self-compensation through M12, writes Vdata+Vth12 into NDC, Vdata is the control data voltage provided by DT, and Vth12 is the threshold voltage of M12; DT provides the matching voltage required for the pulse width, M11 and M12 are turned on, and T1 is turned off.

[0668] In the fifth stage P5 (the fifth stage can be the light-emitting stage), EM1 and EM3 both provide low voltage signals, T8, T7 and T13 are all turned on, and the first drive current Id1 generated by TD1 is controlled to be 0 by controlling VdataA.

[0669] In the fifth stage P5, the switching control voltage provided by SW is a high-frequency multi-pulse-width signal;

[0670] At the start of the fifth stage P5, the potential of NDC is Vdata + Vth12, T1 is turned off, and M1 does not emit light;

[0671] In the fifth stage P5, as the voltage value of the switch control voltage provided by SW decreases, the potential of NDC decreases accordingly. When the potential of NDC decreases to the point that T1 can be turned on, the second driving current Id2 generated by TD2 drives M1 to emit light through T1 until the voltage value of the switch control voltage provided by SW is pulled up, which pulls up the potential of NDC, causing T1 to turn off and M1 to stop emitting light.

[0672] In the fourth stage P4, the voltage values ​​of the control data voltage written by DT are different. In the fifth stage P5, the light emission time of M1 is different, thus achieving different pulse width modulation. At this time, by adjusting VdataA, Id1 is made equal to 0, the pixel current Id flowing through M1 is made equal to Id2, and M1 is only driven to emit light by TD2 to perform medium and low grayscale display.

[0673] It should be noted that when displaying in low to medium grayscale, the voltage value of Vdata must be set to be greater than the voltage value of Vinit0 in order for Vdata to be written to NDC.

[0674] In Figure 39, SE1 is the first emission period, SE2 is the second emission period, and SE3 is the third emission period. M1 emits light during the first emission period SE1, the second emission period SE2, and the third emission period SE3.

[0675] When SW provides a single pulse width control signal in the fifth stage, the light emission diagram of M1 can be shown in Figure 40A.

[0676] When SW provides a high-frequency multi-pulse-width signal in the fifth stage, the emission diagram of M1 can be shown in Figure 40B.

[0677] In Figures 40A and 40B, the time marked F1 is the first frame time, and the time marked F2 is the second frame time.

[0678] In Figure 40A, SX1 represents the first addressing scan stage, SE1 represents the first emission time period, SX2 represents the second addressing scan stage, and SE2 represents the second emission time period.

[0679] In Figure 40B, SX1 represents the first addressing scan stage, SE1 represents the first emission time period, SE2 represents the second emission time period, SE3 represents the third emission time period, SX2 represents the second addressing scan stage, SE4 represents the fourth emission time period, SE5 represents the fifth emission time period, SE6 represents the sixth emission time period, SE7 represents the seventh emission time period, and SE8 represents the eighth emission time period.

[0680] As shown in FIG41A, when at least one embodiment of the pixel circuit shown in FIG35 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0681] In the first stage P1, RSTA, RSTB, and RSTT all provide low voltage signals, and T11, T16, and T3 are all on, resetting N1, N5, and NDC. I2 provides the second initial voltage Vinit2 to N1, and I4 provides the fourth initial voltage Vinit4 to N5. The voltage value of Vinit2 can be low (it can be the same as the voltage value of the low voltage signal provided by VSS), resetting N1 and N5. During the reset, it is ensured that TD1 and TD2 are on. I0 provides the display reset voltage Vinit0 to NDC. The voltage value of Vinit0 is high, resetting NDC. The purpose is to turn off T1 in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing data voltage writing of the second pixel driving circuit, threshold voltage compensation, and leakage of M1.

[0682] In the second phase P2, both GTA and GTB provide low voltage signals, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA to N1, and DTB provides the second data voltage VdataB to N5. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. At the beginning of the second phase P2, TD1 and TD2 are turned on, changing the potentials of N1 and N5 until the potential of N1 is VdataA + Vth1, at which point TD1 is turned off. Then, TD2 is turned off until the potential of N5 is VdataB + Vth2, at which point, to perform data voltage writing and threshold voltage compensation.

[0683] In the third stage P3, RSTC provides a low voltage signal, T12 turns on, and I3 provides a third initial voltage Vinit3 to ND to clear the potential of the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0684] In the fourth stage P4, GT provides a low voltage signal, DT performs self-compensation through M12, writes Vdata+Vth12 into NDC, Vdata is the control data voltage provided by DT, and Vth12 is the threshold voltage of M12; DT provides the matching voltage required for the pulse width, M11 and M12 are turned on, and T1 is turned off.

[0685] In the fifth stage P5 (the fifth stage can be the light-emitting stage), EM1 and EM3 both provide low voltage signals, T8, T7 and T13 are all turned on, and the first drive current Id1 generated by TD1 is controlled to be 0 by controlling VdataA.

[0686] In the fifth stage P5, the switching control voltage provided by SW is a single-pulse-width triangular wave signal;

[0687] At the start of the fifth stage P5, the potential of NDC is Vdata + Vth12, T1 is turned off, and M1 does not emit light;

[0688] In the fifth stage P5, as the voltage value of the switch control voltage provided by SW decreases, the potential of NDC decreases accordingly. When the potential of NDC decreases to the point that T1 can be turned on, the second driving current Id2 generated by TD2 drives M1 to emit light through T1 until the voltage value of the switch control voltage provided by SW is pulled up, which pulls up the potential of NDC, causing T1 to turn off and M1 to stop emitting light.

[0689] In the fourth stage P4, the voltage values ​​of the control data voltage written by DT are different. In the fifth stage P5, the light emission time of M1 is different, thus achieving different pulse width modulation. At this time, by adjusting VdataA, Id1 is made equal to 0, the pixel current Id flowing through M1 is made equal to Id2, and M1 is only driven to emit light by TD2 to perform medium and low grayscale display.

[0690] It should be noted that when displaying in low to medium grayscale, the voltage value of Vdata must be set to be greater than the voltage value of Vinit0 in order for Vdata to be written to NDC.

[0691] In Figure 41A, in the fifth stage P5, the period labeled SE is the emission time period. During the emission time period SE, M1 emits light.

[0692] As shown in FIG41B, when at least one embodiment of the pixel circuit shown in FIG35 of this disclosure is in operation, a frame time may include a first stage P1, a second stage P2, a third stage P3, a fourth stage P4 and a fifth stage P5 set sequentially.

[0693] In the first stage P1, RSTA, RSTB, and RSTT all provide low voltage signals, and T11, T16, and T3 are all on, resetting N1, N5, and NDC. I2 provides the second initial voltage Vinit2 to N1, and I4 provides the fourth initial voltage Vinit4 to N5. The voltage value of Vinit2 can be low (it can be the same as the voltage value of the low voltage signal provided by VSS), resetting N1 and N5. During the reset, it is ensured that TD1 and TD2 are on. I0 provides the display reset voltage Vinit0 to NDC. The voltage value of Vinit0 is high, resetting NDC. The purpose is to turn off T1 in the first stage P1 to the third stage P3, so that the display control circuit is in the off state, preventing data voltage writing of the second pixel driving circuit, threshold voltage compensation, and leakage of M1.

[0694] In the second phase P2, both GTA and GTB provide low voltage signals, and T9, T10, T14, and T15 are all turned on. DTA provides the first data voltage VdataA to N1, and DTB provides the second data voltage VdataB to N5. The voltage value of Vinit2 is lower than the voltage value of VdataA, and the voltage value of Vinit4 is lower than the voltage value of VdataB. At the beginning of the second phase P2, TD1 and TD2 are turned on, changing the potentials of N1 and N5 until the potential of N1 is VdataA + Vth1, at which point TD1 is turned off. Then, TD2 is turned off until the potential of N5 is VdataB + Vth2, at which point, to perform data voltage writing and threshold voltage compensation.

[0695] In the third stage P3, RSTC provides a low voltage signal, T12 turns on, and I3 provides a third initial voltage Vinit3 to ND to clear the potential of the anode of M1; Vinit3 is preferably a DC voltage to ensure that M1 is off.

[0696] In the fourth stage P4, GT provides a low voltage signal, DT performs self-compensation through M12, writes Vdata+Vth12 into NDC, Vdata is the control data voltage provided by DT, and Vth12 is the threshold voltage of M12; DT provides the matching voltage required for the pulse width, M11 and M12 are turned on, and T1 is turned off.

[0697] In the fifth stage P5 (the fifth stage can be the light-emitting stage), EM1 and EM3 both provide low voltage signals, T8, T7 and T13 are all turned on, and the first drive current Id1 generated by TD1 is controlled to be 0 by controlling VdataA.

[0698] In the fifth stage P5, the switching control voltage provided by SW is a multi-pulse width triangular wave signal;

[0699] At the start of the fifth stage P5, the potential of NDC is Vdata + Vth12, T1 is turned off, and M1 does not emit light;

[0700] In the fifth stage P5, as the voltage value of the switch control voltage provided by SW decreases, the potential of NDC decreases accordingly. When the potential of NDC decreases to the point that T1 can be turned on, the second driving current Id2 generated by TD2 drives M1 to emit light through T1 until the voltage value of the switch control voltage provided by SW is pulled up, which pulls up the potential of NDC, causing T1 to turn off and M1 to stop emitting light.

[0701] In the fourth stage P4, the voltage values ​​of the control data voltage written by DT are different. In the fifth stage P5, the light emission time of M1 is different, thus achieving different pulse width modulation. At this time, by adjusting VdataA, Id1 is made equal to 0, the pixel current Id flowing through M1 is made equal to Id2, and M1 is only driven to emit light by TD2 to perform medium and low grayscale display.

[0702] It should be noted that when displaying in low to medium grayscale, the voltage value of Vdata must be set to be greater than the voltage value of Vinit0 in order for Vdata to be written to NDC.

[0703] In Figure 41B, in the fifth stage P5, the first emission time period is labeled SE1, the second emission time period is labeled SE2, and the third emission time period is labeled SE3. M1 emits light during the first emission time period SE1, the second emission time period SE2, and the third emission time period SE3.

[0704] The differences between at least one embodiment of the pixel circuit shown in Figure 42 and at least one embodiment of the pixel circuit shown in Figure 35 are as follows:

[0705] T9, T10, and T11 are n-type transistors, M22 and T3 are n-type transistors, and T14, T15, and T16 are all n-type transistors.

[0706] In at least one embodiment of this disclosure, by taking advantage of the low leakage current of Oxide TFT, the leakage current of the node electrically connected to the gate of TD1, the node electrically connected to the gate of TD2, and NDC can be reduced, and all or part of M22, T3, T9, T10, T11, T14, T15, and T16 can be changed from PMOS TFT to NMOS TFT.

[0707] Taking advantage of the high mobility of PMOS TFTs, all or some of TD1, T7, T8, TD2, T1, and T13 can be set as PMOS TFTs. This is beneficial for reducing threshold voltage compensation and the compensation time at point N1 during the light emission stage, meeting current drive requirements, reducing capacitor area, and further improving display performance.

[0708] Figure 43 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 42. In Figure 43, the period labeled SE is the light emission time period. During the light emission time period SE, M1 emits light.

[0709] In Figure 43, P1 is the first stage, P2 is the second stage, P3 is the third stage, P4 is the fourth stage, and P5 is the fifth stage.

[0710] In Figure 43, in the fifth stage P5, SW provides a single pulse width control signal, but is not limited to this.

[0711] In practical implementation, at stage P5, SW can also provide high-frequency multi-pulse width signals, single-pulse triangular wave signals, or multi-pulse width triangular wave signals, but is not limited to these. In actual operation, at stage P5, SW can also provide other types of AC voltage signals.

[0712] This disclosure provides a driving method applied to the pixel circuit described above, the driving method comprising:

[0713] The first pixel driving circuit, under the control of the first data voltage, controls whether to provide the first driving current to the display node;

[0714] The second pixel driving circuit, under the control of the second data voltage, controls whether to provide the second driving current to the write node;

[0715] Under the control of the display control scan signal, the display control circuit controls whether to write the second drive current into the write node according to the control data voltage.

[0716] The display device described in this disclosure includes the pixel circuit described above.

[0717] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a first pixel driving circuit, a second pixel driving circuit, and a display control circuit; The first pixel driving circuit is electrically connected to the first data voltage terminal and the display node respectively, and is used to control whether to provide a first driving current to the display node under the control of the first data voltage provided by the first data voltage terminal; The second pixel driving circuit is electrically connected to the second data voltage terminal and the write node respectively, and is used to control whether to provide a second driving current to the write node under the control of the second data voltage provided by the second data voltage terminal; The display control circuit is electrically connected to the display control scanning terminal, the control data voltage terminal, the writing node, and the display node, respectively, and is used to control whether to write the second driving current to the writing node according to the control data voltage provided by the control data voltage terminal under the control of the display control scanning signal provided by the display control scanning terminal.

2. The pixel circuit as described in claim 1, wherein, The display control circuit is also electrically connected to the switch control voltage terminal, and is used to control whether to write the second drive current into the write node under the control of the display control scan signal, based on the control data voltage and the switch control voltage provided by the switch control voltage terminal.

3. The pixel circuit as described in claim 1, wherein, The display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit; The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node; The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal and the display control node respectively, and is used to write the control data voltage into the display control node under the control of the display control scanning signal; The display control reset circuit is electrically connected to the display reset control terminal and the display control node, respectively. The display control reset circuit is also electrically connected to the display reset voltage terminal or the first voltage terminal, and is used to write the display reset voltage provided by the display reset voltage terminal or the first voltage signal provided by the first voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal. The first terminal of the first energy storage circuit is electrically connected to the display control node, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal.

4. The pixel circuit as described in claim 1, wherein, The display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, a first energy storage circuit, and a control circuit. The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node; The control circuit is electrically connected to the control node, the second voltage terminal, the third voltage terminal and the display control node respectively, and is used to control the display control node to connect with the second voltage terminal or the third voltage terminal under the control of the potential of the control node; The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal and the control node respectively, and is used to write the control data voltage into the control node under the control of the display control scanning signal; The display control reset circuit is electrically connected to the display reset control terminal, the display reset voltage terminal, and the display control node, respectively, and is used to write the display reset voltage provided by the display reset voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal; The first terminal of the first energy storage circuit is electrically connected to the control node, and the second terminal of the first energy storage circuit is electrically connected to the first initial voltage terminal.

5. The pixel circuit as described in claim 2, wherein, The display control circuit includes an on / off control circuit, a display control writing circuit, a display control reset circuit, and a first energy storage circuit; The control terminal of the on / off control circuit is electrically connected to the display control node, the display node, and the writing node, and is used to control the connection or disconnection between the display node and the writing node under the control of the potential of the display control node; The display control writing circuit is electrically connected to the display control scanning terminal, the control data voltage terminal, and the display control node, respectively, and is used to control the connection or disconnection between the control data voltage terminal and the display control node under the control of the display control scanning signal; The display control reset circuit is electrically connected to the display reset control terminal, the display reset voltage terminal, and the display control node, respectively, and is used to write the display reset voltage provided by the display reset voltage terminal into the display control node under the control of the display reset control signal provided by the display reset control terminal; The first terminal of the first energy storage circuit is electrically connected to the display control node, and the second terminal of the first energy storage circuit is electrically connected to the switch control voltage terminal.

6. The pixel circuit as described in claim 3, wherein, The on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor. The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node; The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the display control node. The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node. The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal.

7. The pixel circuit as described in claim 4, wherein, The on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor; the control circuit includes a fourth transistor and a fifth transistor. The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node; The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor is electrically connected to the control data voltage terminal, and the second terminal of the second transistor is electrically connected to the control node. The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node. The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the first initial voltage terminal. The gate of the fourth transistor is electrically connected to the control node, the first terminal of the fourth transistor is electrically connected to the second voltage terminal, and the second terminal of the fourth transistor is electrically connected to the display control node. The gate of the fifth transistor is electrically connected to the control node, the first terminal of the fifth transistor is electrically connected to the first voltage terminal, and the second terminal of the fifth transistor is electrically connected to the display control node.

8. The pixel circuit as described in claim 5, wherein, The on / off control circuit includes a first transistor, the display control writing circuit includes a second transistor and a sixth transistor, the display control reset circuit includes a third transistor, and the first energy storage circuit includes a first capacitor; The gate of the first transistor is electrically connected to the display control node, the first electrode of the first transistor is electrically connected to the display node, and the second electrode of the first transistor is electrically connected to the write node; The gate of the second transistor is electrically connected to the display control scanning terminal, the first terminal of the second transistor, the gate of the sixth transistor, and the second terminal of the sixth transistor are electrically connected, and the second terminal of the second transistor is electrically connected to the display control node; The first terminal of the sixth transistor is electrically connected to the control data voltage terminal. The gate of the third transistor is electrically connected to the display reset control terminal, the first terminal of the third transistor is electrically connected to the display reset voltage terminal or the first voltage terminal, and the second terminal of the third transistor is electrically connected to the display control node. The first terminal of the first capacitor is electrically connected to the display control node, and the second terminal of the first capacitor is electrically connected to the switch control voltage terminal.

9. The pixel circuit according to any one of claims 3 to 8, wherein, It also includes a light-emitting element; the first pixel driving circuit includes a first driving circuit; the first driving circuit is used to control whether to generate a first driving current under the control of the first data voltage; the second electrode of the light-emitting element is electrically connected to the fourth voltage terminal; The display node is electrically connected to the first terminal of the light-emitting element; or, the display node is electrically connected to the second terminal of the first driving circuit.

10. The pixel circuit as claimed in claim 9, wherein, The first pixel driving circuit also includes a first light emission control circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

11. The pixel circuit as claimed in claim 10, wherein, The first pixel driving circuit further includes a second light emission control circuit, a first data writing circuit, a first compensation control circuit, a first initialization circuit, and a second energy storage circuit. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first power supply voltage terminal, and the first terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal. The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first terminal of the first driving circuit, respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first terminal of the first driving circuit under the control of the first scanning signal provided by the first scanning terminal. The first compensation control circuit is electrically connected to the first scanning terminal, the control terminal of the first driving circuit, and the second terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the control terminal of the first driving circuit and the second terminal of the first driving circuit under the control of the first scanning signal. The first initialization circuit is electrically connected to the first reset control terminal, the second initial voltage terminal, and the control terminal of the first driving circuit, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the control terminal of the first driving circuit under the control of the first reset control signal provided by the first reset control terminal. The second energy storage circuit is electrically connected to the control terminal of the first drive circuit to maintain the potential of the control terminal of the first drive circuit.

12. The pixel circuit as claimed in claim 11, wherein, The first pixel driving circuit also includes a second initialization circuit; The second initialization circuit is electrically connected to the second reset control terminal, the third initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

13. The pixel circuit as claimed in claim 12, wherein, The second pixel driving circuit includes a second driving circuit, a third light emission control circuit, a second data writing circuit, a second compensation control circuit, a third initialization circuit, and a third energy storage circuit. The second terminal of the second driving circuit is electrically connected to the write node; the second driving circuit is used to control whether to generate a second driving current under the control of the second data voltage; The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal. The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the first terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal into the first terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal; The second compensation control circuit is electrically connected to the second scanning terminal, the control terminal of the second driving circuit, and the second terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the control terminal of the second driving circuit and the second terminal of the second driving circuit under the control of the second scanning signal. The third initialization circuit is electrically connected to the third reset control terminal, the fourth initial voltage terminal, and the control terminal of the second drive circuit, respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the control terminal of the second drive circuit under the control of the third reset control signal provided by the third reset control terminal. The third energy storage circuit is electrically connected to the control terminal of the second drive circuit and is used to maintain the potential of the control terminal of the second drive circuit.

14. The pixel circuit as claimed in claim 13, wherein, At least two of the display reset control terminal, the first reset control terminal, the second reset control terminal, and the third reset control terminal are the same reset control terminal; and / or, The first scanning end and the second scanning end are the same scanning end; and / or, At least two of the first initial voltage terminal, the second initial voltage terminal, the third initial voltage terminal, and the fourth initial voltage terminal are the same initial voltage terminal.

15. The pixel circuit as claimed in claim 13, wherein, The first data voltage terminal, the second data voltage terminal, and the control data voltage terminal are the same data voltage terminal; The first scanning end is the nth level scanning end, the second scanning end is the (n+1)th level scanning end, and the display control scanning end is the (n+2)th level scanning end; n is a positive integer.

16. The pixel circuit as claimed in claim 13, wherein, The transistors included in the first initialization circuit, the first compensation control circuit, the third initialization circuit, the second compensation control circuit, the display control writing circuit, the display control reset circuit, the first data writing circuit, and the second data writing circuit are all of type n transistors. And / or, At least one of the transistors included in the first driving circuit, the transistors included in the second driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the third light-emitting control circuit, and the transistors included in the on / off control circuit is a p-type transistor.

17. The pixel circuit as claimed in claim 9, wherein, The first pixel driving circuit also includes a fourth energy storage circuit, a first data writing circuit, and a switch control circuit; The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the control terminal of the first driving circuit, respectively, and is used to write the first data voltage provided by the first data voltage terminal to the control terminal of the first driving circuit under the control of the first scanning signal provided by the first scanning terminal. The first terminal of the fourth energy storage circuit is electrically connected to the control terminal of the first drive circuit, and the second terminal of the fourth energy storage circuit is electrically connected to the second terminal of the first drive circuit. The switch control circuit is electrically connected to the third scanning terminal, the external compensation sensing line, and the second terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the second terminal of the first driving circuit under the control of the third scanning signal provided by the third scanning terminal.

18. The pixel circuit of claim 17, wherein, The first pixel driving circuit also includes a second light emission control circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the first power supply voltage terminal, and the first terminal of the first driving circuit, respectively, and is used to control the connection or disconnection between the first power supply voltage terminal and the first terminal of the first driving circuit under the control of the second light-emitting control signal provided by the second light-emitting control terminal; or... The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

19. The pixel circuit as claimed in claim 17, wherein, The first pixel driving circuit also includes a first switching circuit and a second switching circuit. The first switching circuit is electrically connected to the first switching control terminal, the external compensation sensing line, and the reference voltage terminal, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the external compensation sensing line under the control of the first switching control signal provided by the first switching control terminal. The second switching circuit is electrically connected to the second switch control terminal, the external compensation sensing line, and the sensing terminal, respectively, and is used to control the connection or disconnection between the external compensation sensing line and the sensing terminal under the control of the second switch control signal provided by the second switch control terminal.

20. The pixel circuit of claim 17, wherein, The second pixel driving circuit includes a second driving circuit, a second data writing circuit, and a third energy storage circuit; The first terminal of the second driving circuit is electrically connected to the second power supply voltage terminal, and the second terminal of the second driving circuit is electrically connected to the write node. The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal, and the control terminal of the second driving circuit, respectively, and is used to write the second data voltage provided by the second data voltage terminal to the control terminal of the second driving circuit under the control of the second scanning signal provided by the second scanning terminal. The first end of the third energy storage circuit is electrically connected to the control end of the second driving circuit, and the second end of the third energy storage circuit is electrically connected to the write node.

21. The pixel circuit as claimed in claim 20, wherein, The second pixel driving circuit also includes a third light emission control circuit; The third light-emitting control circuit is electrically connected to the third light-emitting control terminal, the second power supply voltage terminal, and the first terminal of the second driving circuit, respectively, and is used to control the connection or disconnection between the second power supply voltage terminal and the first terminal of the second driving circuit under the control of the third light-emitting control signal provided by the third light-emitting control terminal.

22. The pixel circuit of claim 20, wherein, The first pixel driving circuit also includes a second light emission control circuit; The first terminal of the first driving circuit is electrically connected to the first power supply voltage terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the first driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The display node is electrically connected to the second terminal of the first driving circuit.

23. The pixel circuit as claimed in claim 12, wherein, The first light-emitting control circuit includes a seventh transistor; the first driving circuit includes a first driving transistor. The gate of the seventh transistor is electrically connected to the first light-emitting control terminal, the first terminal of the seventh transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element. The second light-emitting control circuit includes an eighth transistor, the first data writing circuit includes a ninth transistor, the first compensation control circuit includes a tenth transistor, the first initialization circuit includes an eleventh transistor, and the second energy storage circuit includes a second capacitor. The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor. The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the first terminal of the first driving transistor. The gate of the tenth transistor is electrically connected to the first scan terminal, the first terminal of the tenth transistor is electrically connected to the gate of the first driving transistor, and the second terminal of the tenth transistor is electrically connected to the second terminal of the first driving transistor. The gate of the eleventh transistor is electrically connected to the first reset control terminal, the first terminal of the eleventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the eleventh transistor is electrically connected to the gate of the first driving transistor. The first terminal of the second capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the second capacitor is electrically connected to the first DC voltage terminal. The second initialization circuit includes a twelfth transistor; The gate of the twelfth transistor is electrically connected to the second reset control terminal, the first terminal of the twelfth transistor is electrically connected to the third initial voltage terminal, and the second terminal of the twelfth transistor is electrically connected to the first terminal of the light-emitting element.

24. The pixel circuit as claimed in claim 13, wherein, The second driving circuit includes a second driving transistor, the third light-emitting control circuit includes a thirteenth transistor, the second data writing circuit includes a fourteenth transistor, the second compensation control circuit includes a fifteenth transistor, the third initialization circuit includes a sixteenth transistor, and the third energy storage circuit includes a third capacitor. The second terminal of the second driving transistor is electrically connected to the write node; The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor. The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the first terminal of the second drive transistor. The gate of the fifteenth transistor is electrically connected to the second scan terminal, the first terminal of the fifteenth transistor is electrically connected to the gate of the second driving transistor, and the second terminal of the fifteenth transistor is electrically connected to the second terminal of the second driving transistor. The gate of the sixteenth transistor is electrically connected to the third reset control terminal, the first terminal of the sixteenth transistor is electrically connected to the fourth initial voltage terminal, and the second terminal of the sixteenth transistor is electrically connected to the gate of the second driving transistor. The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the second DC voltage terminal.

25. The pixel circuit as claimed in claim 17, wherein, The first driving circuit includes a first driving transistor; the fourth energy storage circuit includes a fourth capacitor; the first terminal of the fourth capacitor is electrically connected to the gate of the first driving transistor, and the second terminal of the fourth capacitor is electrically connected to the second terminal of the first driving transistor. The first data writing circuit includes a ninth transistor, and the switch control circuit includes a seventeenth transistor; The gate of the ninth transistor is electrically connected to the first scan terminal, the first terminal of the ninth transistor is electrically connected to the first data voltage terminal, and the second terminal of the ninth transistor is electrically connected to the gate of the first driving transistor. The gate of the seventeenth transistor is electrically connected to the third scanning terminal, the first terminal of the seventeenth transistor is electrically connected to the external compensation sensing line, and the second terminal of the seventeenth transistor is electrically connected to the second terminal of the first driving transistor.

26. The pixel circuit as claimed in claim 18, wherein, The second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor; The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the first power supply voltage terminal, and the second terminal of the eighth transistor is electrically connected to the first terminal of the first driving transistor; or... The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal; the gate of the eighth transistor is electrically connected to the second light-emitting control terminal; the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor; and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

27. The pixel circuit as claimed in claim 19, wherein, The first switching circuit includes a first switch, and the second switching circuit includes a second switch; The control terminal of the first switch is electrically connected to the control terminal of the first switch, the first terminal of the first switch is electrically connected to the external compensation sensing line, and the second terminal of the first switch is electrically connected to the reference voltage terminal. The control terminal of the second switch is electrically connected to the control terminal of the second switch, the first terminal of the second switch is electrically connected to the external compensation sensing line, and the second terminal of the second switch is electrically connected to the sensing terminal.

28. The pixel circuit as claimed in claim 20, wherein, The second driving circuit includes a second driving transistor, the second data writing circuit includes a fourteenth transistor, and the third energy storage circuit includes a third capacitor; The first terminal of the second driving transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the second driving transistor is electrically connected to the write node; The gate of the fourteenth transistor is electrically connected to the second scan terminal, the first terminal of the fourteenth transistor is electrically connected to the second data voltage terminal, and the second terminal of the fourteenth transistor is electrically connected to the gate of the second driving transistor. The first terminal of the third capacitor is electrically connected to the gate of the second driving transistor, and the second terminal of the third capacitor is electrically connected to the write node.

29. The pixel circuit as claimed in claim 21, wherein, The third light-emitting control circuit includes a thirteenth transistor; The gate of the thirteenth transistor is electrically connected to the third light-emitting control terminal, the first terminal of the thirteenth transistor is electrically connected to the second power supply voltage terminal, and the second terminal of the thirteenth transistor is electrically connected to the first terminal of the second driving transistor.

30. The pixel circuit of claim 22, wherein, The second light-emitting control circuit includes an eighth transistor; the first driving circuit includes a first driving transistor; The first terminal of the first driving transistor is electrically connected to the first power supply voltage terminal; The gate of the eighth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the eighth transistor is electrically connected to the second terminal of the first driving transistor, and the second terminal of the eighth transistor is electrically connected to the first terminal of the light-emitting element.

31. A driving method applied to a pixel circuit as described in any one of claims 1 to 30, the driving method comprising: The first pixel driving circuit, under the control of the first data voltage, controls whether to provide the first driving current to the display node; The second pixel driving circuit, under the control of the second data voltage, controls whether to provide the second driving current to the write node; Under the control of the display control scan signal, the display control circuit controls whether to write the second drive current into the write node according to the control data voltage.

32. A display device comprising a pixel circuit as described in any one of claims 1 to 30.

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