Array substrate and display device
Patent Information
- Application Number
- PCT/CN2025/079925
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-09-03
Smart Images
Figure CN2025079925_03092026_PF_FP_ABST
Abstract
Description
Array substrate and display device Technical Field
[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate and a display device. Background Technology
[0002] Liquid crystal displays (LCDs) are a common type of display. An LCD uses two polarized materials with a liquid crystal solution between them. When an electric current passes through the liquid, it causes the crystals to rearrange, blocking light from passing through. Therefore, each crystal acts like a Venetian blind, both allowing and blocking light. Currently, LCDs are being developed towards being lighter, thinner, shorter, and smaller. Summary of the Invention
[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0004] This disclosure provides an array substrate and a display device.
[0005] On one hand, embodiments of this disclosure provide an array substrate, including a display area and a border area surrounding the display area; the display area includes:
[0006] Substrate;
[0007] A plurality of sub-pixels located on the substrate, the plurality of sub-pixels including at least red sub-pixels, green sub-pixels, and blue sub-pixels; and,
[0008] A reflective layer and a microlens array are located on the substrate. The microlens array includes multiple microlenses. The orthographic projection of the reflective layer onto the plane of the substrate at least partially overlaps with the orthographic projections of the red sub-pixel and the green sub-pixel onto the plane of the substrate, and the orthographic projection of the reflective layer onto the plane of the substrate does not overlap with the orthographic projection of the blue sub-pixel onto the plane of the substrate. The orthographic projection of the microlens onto the plane of the substrate at least partially overlaps with the orthographic projection of the blue sub-pixel onto the plane of the substrate.
[0009] In some exemplary embodiments, the reflective layer includes a plurality of sub-layers stacked together, the plurality of sub-layers including a first sub-layer having a first refractive index and a second sub-layer having a second refractive index, the first sub-layer and the second sub-layer being alternately disposed, and the first refractive index being greater than the second refractive index.
[0010] In some exemplary embodiments, the orthographic projection of the red sub-pixel onto the plane of the substrate lies within the orthographic projection of the reflective layer onto the plane of the substrate, and the orthographic projection of the green sub-pixel onto the plane of the substrate lies within the orthographic projection of the reflective layer onto the plane of the substrate.
[0011] In some exemplary embodiments, the microlens is made of an inorganic material.
[0012] In some exemplary embodiments, the microlens has an arch height along a direction perpendicular to the plane of the substrate, the arch height being greater than or equal to 0.5 micrometers and less than or equal to 1.0 micrometers.
[0013] In some exemplary embodiments, the microlens array includes a plurality of spaced-apart microlenses; at least a portion of the reflective layer is located between two adjacent microlenses.
[0014] In some exemplary embodiments, at least one of the sub-pixels includes a transistor located on the side of the reflective layer away from the substrate, and the orthographic projection of the transistor onto the plane of the substrate does not overlap with the orthographic projection of the microlens onto the plane of the substrate.
[0015] In some exemplary embodiments, the microlens is made of an organic material.
[0016] In some exemplary embodiments, the microlens array is located on the side of the reflective layer away from the substrate; the orthographic projection of the red sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the microlens onto the plane of the substrate; the orthographic projection of the green sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the microlens onto the plane of the substrate.
[0017] In some exemplary embodiments, the reflective layer has at least one through-slot that extends through the reflective layer along a direction perpendicular to the plane of the substrate;
[0018] The display area also includes a planarization layer located within the through slot, and the orthographic projection of the blue sub-pixel onto the plane of the substrate is located within the orthographic projection of the planarization layer onto the plane of the substrate.
[0019] In some exemplary embodiments, the plurality of sub-pixels and the plurality of microlenses are arranged in pairs, and the orthographic projection of the sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the paired microlenses onto the plane of the substrate.
[0020] In some exemplary embodiments, the display area further includes a source / drain metal layer and a gate metal layer, and both the source / drain metal layer and the gate metal layer are located on the side of the reflective layer away from the substrate, with the source / drain metal layer being closer to the reflective layer than the gate metal layer;
[0021] At least one of the sub-pixels includes a transistor, the transistor including a first electrode, a second electrode, and a gate electrode, the source / drain metal layer including the first electrode and the second electrode, and the gate metal layer including the gate electrode.
[0022] In some exemplary embodiments, the material of the source / drain metal layer includes at least two of MoNiTi, MoNb, Mo, MoTiCu, and Cu.
[0023] In some exemplary embodiments, the reflective layer has at least one through-slot that extends through the reflective layer along a direction perpendicular to the plane of the substrate;
[0024] The display area further includes a planarization layer, at least a portion of which is located within the through slot, and the orthographic projection of the blue sub-pixel onto the plane of the substrate is located within the orthographic projection of the planarization layer onto the plane of the substrate.
[0025] On the other hand, this disclosure provides a display device. The display device includes an array substrate, a counter substrate, and a liquid crystal layer as described in any of the above embodiments; the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.
[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.
[0027] Overview of the attached figures
[0028] Figure 1 is a front view schematic diagram of an array substrate according to an embodiment of the present disclosure;
[0029] Figure 2 is a schematic diagram of the planar structure of the display area of an array substrate according to an embodiment of the present disclosure;
[0030] Figure 3 is a partial cross-sectional schematic diagram of the display area of an array substrate according to an embodiment of the present disclosure;
[0031] Figure 4A is a partial cross-sectional schematic diagram of the display area of an array substrate according to an embodiment of the present disclosure after forming a microlens array;
[0032] Figure 4B is a partial cross-sectional schematic diagram of the display area of an array substrate according to an embodiment of the present disclosure after a reflective film has been formed.
[0033] Figure 4C is a partial cross-sectional view of an array substrate after a photoresist layer has been formed in the display area of the present disclosure.
[0034] Figure 4D is a partial cross-sectional view of an array substrate after a reflective layer has been formed in the display area of an embodiment of the present disclosure;
[0035] Figure 4E is a partial cross-sectional view of an array substrate after transistors have been formed in the display area of an embodiment of the present disclosure;
[0036] Figure 5 is a partial cross-sectional schematic diagram of the display area of an array substrate according to another embodiment of the present disclosure;
[0037] Figure 6A is a partial cross-sectional view of the display area of the array substrate after a reflective film has been formed, according to another embodiment of the present disclosure.
[0038] Figure 6B is a partial cross-sectional schematic diagram of the display area of the array substrate after a reflective layer has been formed, according to another embodiment of the present disclosure.
[0039] Figure 6C is a partial cross-sectional view of the display area of the array substrate after a planarization layer has been formed, according to another embodiment of the present disclosure.
[0040] Figure 6D is a partial cross-sectional view of the display area of the array substrate after the initial pattern of the microlens array is formed in the display area of another embodiment of the present disclosure;
[0041] Figure 6E is a partial cross-sectional schematic diagram of the display area of the array substrate after forming a microlens array according to another embodiment of the present disclosure;
[0042] Figure 7 is a partial cross-sectional schematic diagram of the display area of an array substrate according to another embodiment of the present disclosure;
[0043] Figure 8A is a partial cross-sectional view of the display area of the array substrate after a reflective film has been formed in another embodiment of the present disclosure;
[0044] Figure 8B is a partial cross-sectional schematic diagram of the display area of the array substrate after the source and drain metal layers are formed in another embodiment of the present disclosure;
[0045] Figure 8C is a partial cross-sectional schematic diagram of the display area of the array substrate after a mask layer has been formed in another embodiment of the present disclosure;
[0046] Figure 8D is a partial cross-sectional view of the display area of the array substrate after a reflective layer has been formed, according to another embodiment of the present disclosure.
[0047] Figure 8E is a partial cross-sectional schematic diagram of the display area of the array substrate after forming a microlens array in another embodiment of the present disclosure.
[0048] Figure 9 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure.
[0049] Detailed Explanation
[0050] The embodiments of this disclosure will now be described with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0051] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values shown in the drawings.
[0052] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.
[0053] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.
[0054] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.
[0055] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.
[0056] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0057] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and "drain electrode" can be interchanged.
[0058] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.
[0059] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".
[0060] In this disclosure, "about" or "approximately" means values that are not strictly defined and are within the allowable range of process and measurement errors.
[0061] In this disclosure, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, and chamfers, curved edges, and other deformations are possible.
[0062] This disclosure provides an array substrate. The array substrate includes a display area and a border area surrounding the display area; the display area includes:
[0063] Substrate;
[0064] A plurality of sub-pixels located on the substrate, the plurality of sub-pixels including at least red sub-pixels, green sub-pixels, and blue sub-pixels; and,
[0065] A reflective layer and a microlens array are located on the substrate. The microlens array includes multiple microlenses. The orthographic projection of the reflective layer onto the plane of the substrate at least partially overlaps with the orthographic projections of the red sub-pixel and the green sub-pixel onto the plane of the substrate, and the orthographic projection of the reflective layer onto the plane of the substrate does not overlap with the orthographic projection of the blue sub-pixel onto the plane of the substrate. The orthographic projection of the microlens onto the plane of the substrate at least partially overlaps with the orthographic projection of the blue sub-pixel onto the plane of the substrate.
[0066] In this embodiment of the present disclosure, by setting a reflective layer and a microlens array, and limiting the reflective layer to at least partially overlap with the orthographic projections of the red and green sub-pixels, and the reflective layer to not overlap with the orthographic projections of the blue sub-pixels, and the microlenses to at least partially overlap with the orthographic projections of the blue sub-pixels, the light efficiency of red and green light can be improved, and blue light damage can be avoided while ensuring that the display device does not display distortion.
[0067] Figure 1 is a front view schematic diagram of an array substrate according to an embodiment of the present disclosure. As shown in Figure 1, the array substrate may include a display area AA and a border area BB located around the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top border, left border, and right border of the array substrate.
[0068] In an exemplary embodiment, as shown in FIG1, the display area AA may include: multiple data lines DL and multiple gate lines GL disposed on a substrate. The multiple gate lines GL may extend along a first direction X and be arranged sequentially along a second direction Y different from the first direction X. The multiple data lines DL may extend along the second direction Y and be arranged sequentially along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The multiple data lines DL and the multiple gate lines GL may be located in different film layers; for example, the multiple data lines DL may be located on the side of the multiple gate lines GL closer to the substrate.
[0069] In an exemplary embodiment, as shown in FIG1, multiple data lines DL and multiple gate lines GL can intersect to form multiple sub-pixel regions. The region defined by the intersection of adjacent data lines DL and adjacent gate lines GL can be a sub-pixel region. A sub-pixel can be correspondingly disposed within a sub-pixel region. A sub-pixel region can include an open region and a non-open region surrounding the open region. The non-open region can be a region obscured by the black matrix of the opposing substrate of the array substrate, and the open region can be a region not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL can both be located within the non-open region. The array substrate of this disclosure embodiment can be used to implement a display function, and the open region of each sub-pixel region can be configured for display. The non-open region surrounds the open region and is not displayed. However, this disclosure embodiment is not limited thereto. In some examples, the array substrate can be used to implement other functions.
[0070] In an exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may, for example, be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. As shown in FIG1, at least one sub-pixel may include a first electrode 10 and a common electrode (not shown in FIG1), and the orthographic projections of the first electrode 10 and the common electrode of the sub-pixel onto the plane of the substrate may overlap. For example, the first electrode 10 may be a pixel electrode. The common electrode of the plurality of sub-pixels of the display area AA may be a single structure. For example, the common electrode may be located on the side of the first electrode 10 away from the substrate. The sub-pixel may also include a transistor 20. The transistor 20 may be located near the intersection of the data line DL and the gate line GL. The transistor 20 may include a gate electrode, a first electrode, and a second electrode. The gate electrode can be electrically connected to the gate line GL, the first electrode of the transistor 20 can be electrically connected to the data line DL, and the second electrode can be electrically connected to the first electrode 10 of a sub-pixel. The transistor 20 can be configured to provide the data signal transmitted by the data line DL to the first electrode 10 of the sub-pixel under the control of the gate line GL.
[0071] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In ADS mode, both the first electrode and the common electrode are located on one side of the array substrate. In TN and VA modes, the first electrode and the common electrode are respectively located on opposite sides of the liquid crystal layer, with the first electrode located on one side of the array substrate and the common electrode located on the opposite substrate side.
[0072] Figure 2 is a schematic planar structure diagram of the display area of an array substrate according to an embodiment of the present disclosure. The display area of the array substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. The first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. The shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal. The three sub-pixels may be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.
[0073] In some exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.
[0074] Figure 3 is a partial cross-sectional schematic diagram of the display area of an array substrate according to an embodiment of the present disclosure. As shown in Figure 3, in a plane perpendicular to the plane of the array substrate, i.e., in the thickness direction of the array substrate, the display area of the array substrate may include a substrate 30, a microlens array 40 located on the substrate 30, and a reflective layer 45 located on the substrate 30. The microlens array 40 may include a plurality of spaced microlenses 41. The orthographic projection of the microlens 41 onto the plane of the substrate 30 and the orthographic projection of the reflective layer 45 onto the plane of the substrate 30 may at least partially overlap, and at least a portion of the reflective layer 45 may be located between two adjacent microlenses 41. In this embodiment of the present disclosure, the microlenses 41 may be used to enhance the light emitted from the sub-pixels. In this embodiment of the present disclosure, the plane of the array substrate is parallel to the plane of the substrate, and the plane of the substrate is parallel to the plane formed by the first direction X and the second direction Y.
[0075] The display area AA may further include multiple pixel units disposed on the substrate 30. At least one pixel unit may include a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the microlens 41 onto the plane of the substrate 30, but does not overlap with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. The orthographic projection of the red sub-pixel onto the plane of the substrate 30 does not overlap with the orthographic projection of the microlens 41 onto the plane of the substrate 30, but at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. The orthographic projection of the green sub-pixel onto the plane of the substrate 30 does not overlap with the orthographic projection of the microlens 41 onto the plane of the substrate 30, but at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. In this embodiment of the present disclosure, by using the reflective layer 45 and the microlens array 40, the problem of blue light damage in existing display devices can be solved while ensuring that the display device does not display distortion. Furthermore, the reflective layer 45 enhances light in wavelengths other than the blue light band, thereby improving the display brightness and display quality of the display device.
[0076] In some exemplary embodiments, the reflective layer 45 may have a distributed Bragg reflector (DBR) structure. The DBR structure features adjustable filtering wavelength, simple fabrication process, short fabrication cycle, stable filtering performance, and long service life. In practical applications, by adjusting the film structure of the DBR structure, the reflection of red and green light can be reduced, the transmittance of red and green light can be increased, light loss can be reduced, and luminous efficiency can be improved.
[0077] In some exemplary embodiments, the reflective layer 45 can transmit light in wavelengths other than the blue light band. The reflective layer 45 can employ a λ / 4 film system (λ being the center wavelength). The reflective layer 45 can include a plurality of stacked sublayers, including a first sublayer having a first refractive index and a second sublayer having a second refractive index, wherein the first and second sublayers are alternately arranged, and the first refractive index is greater than the second refractive index. For example, the first and second sublayers are arranged alternately in a direction away from the substrate 30.
[0078] In some exemplary embodiments, the first refractive index may be 1.6 to 2.5 and the second refractive index may be 1.3 to 1.5 in the visible light range.
[0079] In some exemplary embodiments, the material of the first sublayer may include any one or more of the following: oxides and nitrides. The oxides may include any one or more of the following: titanium dioxide, zirconium dioxide, and niobium pentoxide. The nitrides may include silicon nitride.
[0080] In some exemplary embodiments, the material of the second sublayer may include any one or more of the following: silicon dioxide, magnesium fluoride, silane oxide, and aluminum oxide.
[0081] In some exemplary embodiments, as shown in FIG3, the display area of the array substrate may further include a transistor 20 located on the side of the reflective layer 45 away from the substrate 30. The transistor 20 may include an active layer 21, a gate electrode 23, a first electrode 25, and a second electrode 26. The orthographic projection of the transistor 20 onto the plane of the substrate 30 does not overlap with the orthographic projection of the microlens 41 onto the plane of the substrate 30.
[0082] The structure of the array substrate is illustrated below through an example of the fabrication process of the array substrate. The "patterning process" described in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and processes such as organic material coating, mask exposure, and development for organic materials. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; and etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The "A and B co-layer structure" described in this disclosure refers to A and B being formed through the same patterning process.
[0083] The fabrication process of the array substrate may include the following steps:
[0084] (01) Forming a microlens array. Forming a microlens array may include: forming an inorganic thin film on a substrate 30, coating the inorganic thin film with photoresist, then exposing the photoresist with a mask and developing the photoresist, then etching the inorganic thin film, and then stripping off the remaining photoresist to obtain a microlens array 40, as shown in FIG4A.
[0085] As shown in Figure 4A, the microlens array 40 may include a plurality of spaced microlenses 41. Along the thickness direction of the array substrate, the thickness direction is perpendicular to the plane where the substrate 30 is located. The plane where the substrate 30 is located is parallel to the plane formed by the first direction X and the second direction Y. The microlenses 41 may be grouped with a sub-pixel. The orthographic projection of the microlens 41 onto the plane where the substrate 30 is located at least partially overlaps with the orthographic projection of a sub-pixel onto the plane where the substrate 30 is located. For example, the orthographic projection of the microlens 41 onto the plane where the substrate 30 is located may include the orthographic projection of a sub-pixel onto the plane where the substrate 30 is located.
[0086] In some exemplary embodiments, the microlens 41 may be grouped with the blue sub-pixels, and the orthographic projections of the microlens 41 and the blue sub-pixels onto the plane of the substrate 30 at least partially overlap. In embodiments of this disclosure, the microlens 41 can be used to improve the luminous efficacy of blue light.
[0087] In some exemplary embodiments, the microlens 41 has an arch height H along the thickness direction of the array substrate, and the range of H can be greater than or equal to 0.5 micrometers and less than or equal to 1.0 micrometers.
[0088] In some exemplary embodiments, the substrate 30 may be a glass substrate, a transparent plastic substrate, or a flexible substrate, or other light-transmitting substrate.
[0089] (02) Forming a reflective film 42, as shown in FIG4B, the orthogonal projection of the reflective film 42 onto the plane where the substrate 30 is located may include the orthogonal projection of the microlens array 40 onto the plane where the substrate 30 is located.
[0090] In some exemplary embodiments, the reflective film 42 may include an alternately disposed first reflective film and a second reflective film, and the first reflective film and the second reflective film have different refractive indices. For example, the first reflective film may be a silicon dioxide film, and the second reflective film may be a titanium dioxide film.
[0091] (03) Forming a photoresist layer 43, as shown in FIG4C, the orthogonal projection of the photoresist layer 43 on the plane where the substrate 30 is located may include the orthogonal projection of the microlens array 40 on the plane where the substrate 30 is located, and the orthogonal projection of the photoresist layer 43 on the plane where the substrate 30 is located may include the orthogonal projection of the reflective film 42 on the plane where the substrate 30 is located.
[0092] (04) Forming a reflective layer. Forming a reflective layer may include etching the substrate 30 formed by the aforementioned operation to form a plurality of openings 44 in the photoresist layer 43, removing the photoresist within the openings 44 and exposing a portion of the reflective film 42. The plurality of openings 44 and the plurality of microlenses 41 may be arranged in pairs, and the orthographic projection of the openings 44 onto the plane of the substrate 30 may lie within the orthographic projection of the paired microlenses 41 onto the plane of the substrate 30.
[0093] Subsequently, based on the opening 44, the reflective film 42 is etched away to remove the reflective film 42 exposed by the opening 44, so that the reflective film 42 forms a reflective layer 45, as shown in Figure 4D.
[0094] As shown in Figure 4D, the orthographic projection of the reflective layer 45 onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the red sub-pixel onto the plane of the substrate 30, the orthographic projection of the reflective layer 45 onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the green sub-pixel onto the plane of the substrate 30, and the orthographic projection of the reflective layer 45 onto the plane of the substrate 30 does not overlap with the orthographic projection of the blue sub-pixel onto the plane of the substrate 30.
[0095] (05) Forming a transistor. Forming a transistor may include: removing the photoresist layer 43 on the substrate 30 on which the aforementioned structure is formed; subsequently forming an active layer pattern, the active layer pattern including active layers 21 of a plurality of transistors 20; subsequently forming a gate insulating layer 22 and a gate metal layer in sequence, the gate metal layer including at least the gate electrodes 23 of the plurality of transistors 20, the orthographic projection of the gate electrodes 23 onto the plane of the substrate 30 at least partially overlapping the orthographic projection of the active layer 21 onto the plane of the substrate 30; subsequently forming an interlayer insulating layer 24, the interlayer insulating layer 24 serving a planarization function. Subsequently, a patterning process is used on the substrate 30 forming the aforementioned structure to form a plurality of vias K. The gate insulating layer 22 and the interlayer insulating layer 24 located within the vias K are etched away, exposing a portion of the active layer 21. Then, a source drain metal layer is formed. The source drain metal layer may include at least the first electrode 25 and the second electrode 26 of the transistor 20. The first electrode 25 is connected to the active layer 21 via the via K, and the second electrode 26 is connected to the active layer 21 via another via K, as shown in FIG4E.
[0096] In some exemplary embodiments, the orthographic projection of transistor 20 onto the plane of substrate 30 does not overlap with the orthographic projection of microlens 41 onto the plane of substrate 30, which can avoid the adverse effects of transistor 20 on the optical performance of microlens 41 and improve the light extraction efficiency of blue sub-pixels.
[0097] Figure 5 is a partial cross-sectional schematic diagram of the display area of an array substrate according to another embodiment of the present disclosure. As shown in Figure 5, the display area of the array substrate may include a substrate 30, a reflective layer 45 located on the substrate 30, and a microlens array 40 located on the side of the reflective layer 45 away from the substrate 30. The microlens array 40 may include a plurality of microlenses 41. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 does not overlap with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. The orthographic projection of the red sub-pixel onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. For example, the orthographic projection of the red sub-pixel onto the plane of the substrate 30 is located within the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. The orthographic projection of the green sub-pixel onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of the substrate 30. For example, the orthographic projection of the green sub-pixel onto the plane of the substrate 30 is located within the orthographic projection of the reflective layer 45 onto the plane of the substrate 30.
[0098] The reflective layer 45 has multiple through slots 46, which can penetrate the reflective layer 45 along a direction perpendicular to the plane of the substrate 30. The display area of the array substrate may also include a planarization layer 47, which is located within the through slots 46. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 can be located within the orthographic projection of the planarization layer 47 onto the plane of the substrate 30.
[0099] In some exemplary embodiments, multiple sub-pixels and multiple microlenses 41 can be arranged in pairs, and the orthographic projection of the sub-pixel onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the paired microlenses 41 onto the plane of the substrate 30. For example, the orthographic projection of the sub-pixel onto the plane of the substrate 30 may lie within the orthographic projection of the paired microlenses 41 onto the plane of the substrate 30. In embodiments of this disclosure, the microlenses 41 can be used to converge red and green light, thereby improving the luminous efficiency of red and green light.
[0100] The structure of an array substrate is illustrated below through an example of its fabrication process. The fabrication process of an array substrate may include the following steps:
[0101] (01) A reflective thin film 42 is formed on the substrate 30, as shown in FIG6A.
[0102] (02) Forming a reflective layer. Forming a reflective layer may include: patterning the reflective film 42 using a patterning process to form multiple through-grooves 46 to form a reflective layer 45, as shown in FIG6B. The reflective film 42 located within the through-grooves 46 is etched away, exposing a portion of the substrate 30. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 may be located within the orthographic projection of the through-grooves 46 onto the plane of the substrate 30, which can reduce the blue light emitted by the display device.
[0103] In some exemplary embodiments, the orthographic projection of the through-slot 46 onto the plane of the substrate 30 can be a circle, a square, a rectangle, or a regular hexagon, etc.
[0104] (03) A planarization layer is formed. As shown in FIG6C, the planarization layer 47 is located within the through groove 46. The surface of the planarization layer 47 away from the substrate 30 can be substantially flush with the surface of the reflective layer 45 away from the substrate 30. For example, the surface of the planarization layer 47 away from the substrate 30 is flush with the surface of the reflective layer 45 away from the substrate 30. Alternatively, the surface of the planarization layer 47 away from the substrate 30 is not flush with the surface of the reflective layer 45 away from the substrate 30, and the step difference between the surface of the planarization layer 47 away from the substrate 30 and the surface of the reflective layer 45 away from the substrate 30 is within a set range. The orthographic projection of the blue sub-pixel onto the plane where the substrate 30 is located can be located within the orthographic projection of the planarization layer 47 onto the plane where the substrate 30 is located.
[0105] In some exemplary embodiments, the material of the planarization layer 47 may be an organic transparent material.
[0106] In some exemplary embodiments, the planarization layer 47 has a blue light transmittance greater than or equal to 90%, and the blue light refractive index of the planarization layer 47 is less than the blue light refractive index of the microlens, which can improve the luminous brightness of the blue sub-pixel and enhance the display quality.
[0107] In some exemplary embodiments, the planarization layer 47 has a transmittance of white light greater than or equal to 90%, and the refractive index of the planarization layer 47 for white light is less than the refractive index of the microlens for white light, which can improve the luminous brightness of the blue sub-pixel and enhance the display quality.
[0108] (04) Forming an initial pattern for the microlens array. Forming an initial pattern for the microlens array may include forming an organic thin film on the substrate 30 on which the aforementioned structure is formed. The orthographic projection of the organic thin film onto the plane of the substrate 30 includes the orthographic projection of the planarization layer 47 onto the plane of the substrate 30, and includes the orthographic projection of the reflective layer 45 onto the plane of the substrate 30.
[0109] Subsequently, the organic thin film is patterned using a patterning process to form an initial pattern for the microlens array, as shown in Figure 6D. The initial pattern for the microlens array includes a plurality of spaced pillars 48, which, for example, can be cylinders.
[0110] In some exemplary embodiments, the material of the organic thin film can be organic photoresist, etc.
[0111] (05) Forming a microlens array. Forming a microlens array may include: using photoresist thermal reflow technology to form a microlens array 40 from the initial pattern of the microlens array obtained by the aforementioned operations. The microlens array 40 may include multiple microlenses 41, as shown in FIG6E. In the embodiments of this disclosure, the microlenses 41 are made of organic materials, and can be prepared using photoresist thermal reflow technology during the preparation process, which has the advantages of simple process, low cost, and strong plasticity.
[0112] Figure 7 is a partial cross-sectional schematic diagram of the display area of an array substrate according to another embodiment of the present disclosure. As shown in Figure 7, the display area of the array substrate may include a substrate 30, a reflective layer 45 located on the substrate 30, and a source / drain metal layer 49 located on the side of the reflective layer 45 away from the substrate 30. The source / drain metal layer 49 may include data lines, a first electrode, and a second electrode, etc. The surface of the source / drain metal layer 49 near the substrate 30 can contact the surface of the reflective layer 45 away from the substrate 30, which can avoid metal residue during the fabrication of the source / drain metal layer wiring and solve problems such as light leakage through vias.
[0113] The orthographic projection of the blue sub-pixel onto the plane of substrate 30 does not overlap with the orthographic projection of the reflective layer 45 onto the plane of substrate 30. The orthographic projection of the red sub-pixel onto the plane of substrate 30 at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of substrate 30; for example, the orthographic projection of the red sub-pixel onto the plane of substrate 30 lies within the orthographic projection of the reflective layer 45 onto the plane of substrate 30. The orthographic projection of the green sub-pixel onto the plane of substrate 30 at least partially overlaps with the orthographic projection of the reflective layer 45 onto the plane of substrate 30; for example, the orthographic projection of the green sub-pixel onto the plane of substrate 30 lies within the orthographic projection of the reflective layer 45 onto the plane of substrate 30.
[0114] The reflective layer 45 may have multiple through slots 46, which may extend through the reflective layer 45 along a direction perpendicular to the plane of the substrate 30. The display area of the array substrate may also include a planarization layer 47, a portion of which is located within the through slots 46. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 may be located within the orthographic projection of the planarization layer 47 onto the plane of the substrate 30.
[0115] In some exemplary embodiments, the display area of the array substrate may further include a microlens array 40, which is located on the side of the source / drain metal layer 49 away from the substrate 30. The microlens array 40 may include a plurality of microlenses 41. A plurality of sub-pixels and a plurality of microlenses 41 may be paired, and the orthographic projection of the sub-pixel onto the plane of the substrate 30 at least partially overlaps with the orthographic projection of the paired microlenses 41 onto the plane of the substrate 30. For example, the orthographic projection of the sub-pixel onto the plane of the substrate 30 may lie within the orthographic projection of the paired microlenses 41 onto the plane of the substrate 30. In embodiments of this disclosure, the microlenses 41 can be used to converge red and green light, thereby improving the luminous efficiency of the red and green light.
[0116] In some exemplary embodiments, the source / drain metal layer 49 can be a single layer, a multilayer, or a composite layer structure.
[0117] In some exemplary embodiments, the display area of the array substrate further includes a gate metal layer, and both the source / drain metal layer 49 and the gate metal layer are located on the side of the reflective layer 45 away from the substrate 30, with the source / drain metal layer 49 being closer to the reflective layer 45 than the gate metal layer. At least one sub-pixel includes a transistor, the transistor including a first electrode, a second electrode, and a gate electrode, the source / drain metal layer 49 including a first electrode and a second electrode, and the gate metal layer including a gate electrode.
[0118] In some exemplary embodiments, the gate metal layer can be a single layer, multiple layers, or a composite layer structure.
[0119] The structure of an array substrate is illustrated below through an example of its fabrication process. The fabrication process of an array substrate may include the following steps:
[0120] (01) A reflective thin film 42 is formed on the substrate 30, as shown in FIG8A.
[0121] (02) A source / drain metal layer 49 is formed on the side of the reflective film 42 away from the substrate 30, as shown in FIG8B.
[0122] In some exemplary embodiments, the material of the source / drain metal layer 49 may be TiN / Mo, or may include at least two of MoNiTi, MoNb, Mo, MoTiCu, and Cu.
[0123] (03) A mask layer 50 is formed on the side of the source / drain metal layer 49 away from the substrate 30, as shown in FIG8C. The orthogonal projection of the mask layer 50 onto the plane where the substrate 30 is located may include the orthogonal projection of the source / drain metal layer 49 onto the plane where the substrate 30 is located.
[0124] In some exemplary embodiments, the material of the mask layer 50 can be an organic material, an inorganic material, or a metallic material, etc. For example, the material of the mask layer 50 can be an organic photoresist. For example, the material of the mask layer 50 can be SiN. For example, the material of the mask layer 50 can be Ti.
[0125] (04) Forming a reflective layer. Forming a reflective layer may include: using a mask layer 50, patterning a reflective film 42 to form multiple through-slots 46 to form a reflective layer 45, as shown in FIG8D. The reflective film 42 located within the through-slots 46 is etched away, exposing a portion of the substrate 30. The orthographic projection of the blue sub-pixel onto the plane of the substrate 30 may be located within the orthographic projection of the through-slots 46 onto the plane of the substrate 30, which can reduce the blue light emitted by the display device.
[0126] (05) Forming a microlens array. Forming a microlens array may include: forming a planarization layer 47 within the through slot 46, wherein the surface of the planarization layer 47 away from the substrate 30 is substantially flush with the surface of the source / drain metal layer 49 away from the substrate 30. For example, the surface of the planarization layer 47 away from the substrate 30 is flush with the surface of the source / drain metal layer 49 away from the substrate 30, or the step difference between the surface of the planarization layer 47 away from the substrate 30 and the surface of the source / drain metal layer 49 away from the substrate 30 is within a set range.
[0127] Subsequently, an organic thin film is formed on the substrate 30 on which the aforementioned structure is formed. The orthographic projection of the organic thin film onto the plane of the substrate 30 includes the orthographic projection of the planarization layer 47 onto the plane of the substrate 30, and also includes the orthographic projection of the source / drain metal layer 49 onto the plane of the substrate 30.
[0128] Subsequently, the organic thin film is patterned using a patterning process to form an initial pattern for the microlens array, as shown in Figure 6D above. The initial pattern for the microlens array includes a plurality of spaced pillars 48, for example, the pillars 48 can be cylinders.
[0129] Subsequently, the initial pattern of the microlens array obtained by the aforementioned operation is subjected to photoresist thermal reflow technology to form a microlens array 40, which may include multiple microlenses 41, as shown in Figure 8E.
[0130] In some exemplary embodiments, the material of the microlens 41 may be an inorganic material.
[0131] Figure 9 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 9, the display device may further include a counter substrate 1 and a liquid crystal layer 2 disposed between an array substrate 5 and the counter substrate 1. The array substrate 5 includes a first electrode and a common electrode, which can be configured to generate an electric field to control the deflection of liquid crystal molecules in the liquid crystal layer 2. The liquid crystal molecules in the liquid crystal layer 2 can be horizontally arranged on the array substrate 5, and in this embodiment of the present disclosure, the horizontal direction is parallel to the plane on which the array substrate 5 is located. The array substrate 5 may be the array substrate provided in any of the foregoing embodiments. The counter substrate 1 may include a substrate substrate, and a black matrix 3 and a color filter layer 4 disposed on the substrate substrate. However, the embodiments of the present disclosure are not limited in this respect.
[0132] This disclosure also provides a display device. The display device includes the array substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure is not limited in this respect.
[0133] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.
Claims
1. An array substrate, comprising a display area and a border area surrounding the display area; the display area comprising: Substrate; A plurality of sub-pixels located on the substrate, the plurality of sub-pixels including at least red sub-pixels, green sub-pixels and blue sub-pixels; as well as, A reflective layer and a microlens array are located on the substrate. The microlens array includes multiple microlenses. The orthographic projection of the reflective layer onto the plane of the substrate at least partially overlaps with the orthographic projections of the red sub-pixel and the green sub-pixel onto the plane of the substrate, and the orthographic projection of the reflective layer onto the plane of the substrate does not overlap with the orthographic projection of the blue sub-pixel onto the plane of the substrate. The orthographic projection of the microlens onto the plane of the substrate at least partially overlaps with the orthographic projection of the blue sub-pixel onto the plane of the substrate.
2. The array substrate as claimed in claim 1, wherein, The reflective layer includes multiple sub-layers stacked together. The multiple sub-layers include a first sub-layer having a first refractive index and a second sub-layer having a second refractive index. The first sub-layer and the second sub-layer are alternately arranged in the multiple sub-layers, and the first refractive index is greater than the second refractive index.
3. The array substrate as claimed in claim 1, wherein, The orthographic projection of the red sub-pixel onto the plane of the substrate lies within the orthographic projection of the reflective layer onto the plane of the substrate, and the orthographic projection of the green sub-pixel onto the plane of the substrate lies within the orthographic projection of the reflective layer onto the plane of the substrate.
4. The array substrate according to any one of claims 1 to 3, wherein, The microlens is made of inorganic material.
5. The array substrate as claimed in claim 4, wherein, Along a direction perpendicular to the plane of the substrate, the microlens has an arch height that is greater than or equal to 0.5 micrometers and less than or equal to 1.0 micrometers.
6. The array substrate as claimed in claim 4, wherein, The microlens array includes a plurality of spaced-apart microlenses; at least a portion of the reflective layer is located between two adjacent microlenses.
7. The array substrate as claimed in claim 4, wherein, At least one of the sub-pixels includes a transistor located on the side of the reflective layer away from the substrate, and the orthographic projection of the transistor onto the plane of the substrate does not overlap with the orthographic projection of the microlens onto the plane of the substrate.
8. The array substrate according to any one of claims 1 to 3, wherein, The microlens is made of organic material.
9. The array substrate as claimed in claim 8, wherein, The microlens array is located on the side of the reflective layer away from the substrate; the orthographic projection of the red sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the microlens onto the plane of the substrate; the orthographic projection of the green sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the microlens onto the plane of the substrate.
10. The array substrate as claimed in claim 9, wherein, The reflective layer has at least one through-slot that extends through the reflective layer along a direction perpendicular to the plane of the substrate; The display area also includes a planarization layer located within the through slot, and the orthographic projection of the blue sub-pixel onto the plane of the substrate is located within the orthographic projection of the planarization layer onto the plane of the substrate.
11. The array substrate as claimed in claim 9, wherein, The plurality of sub-pixels and the plurality of microlenses are arranged in pairs, and the orthographic projection of the sub-pixel onto the plane of the substrate at least partially overlaps with the orthographic projection of the paired microlenses onto the plane of the substrate.
12. The array substrate according to any one of claims 1 to 3, wherein, The display area further includes a source / drain metal layer and a gate metal layer, and both the source / drain metal layer and the gate metal layer are located on the side of the reflective layer away from the substrate, with the source / drain metal layer being closer to the reflective layer than the gate metal layer; At least one of the sub-pixels includes a transistor, the transistor including a first electrode, a second electrode, and a gate electrode, the source / drain metal layer including the first electrode and the second electrode, and the gate metal layer including the gate electrode.
13. The array substrate as claimed in claim 12, wherein, The source / drain metal layer is made of at least two of the following materials: MoNiTi, MoNb, Mo, MoTiCu, and Cu.
14. The array substrate as claimed in claim 12, wherein, The reflective layer has at least one through-slot that extends through the reflective layer along a direction perpendicular to the plane of the substrate; The display area further includes a planarization layer, at least a portion of which is located within the through slot, and the orthographic projection of the blue sub-pixel onto the plane of the substrate is located within the orthographic projection of the planarization layer onto the plane of the substrate.
15. A display device comprising an array substrate, an opposing substrate, and a liquid crystal layer as described in any one of claims 1 to 14; wherein the array substrate and the opposing substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.