Package substrate and manufacturing method therefor, and functional substrate and manufacturing method therefor

Abstract

The present disclosure belongs to the technical field of display. Provided are a package substrate and a manufacturing method therefor, and a functional substrate and a manufacturing method therefor. The package substrate comprises: a carrier plate, which comprises a first surface and a second surface arranged opposite each other in the thickness direction thereof; and a first circuit structure, which is located on the first surface, and comprises a capacitor and a wiring structure located on the side of the capacitor away from the carrier plate, the wiring structure comprising at least two wiring layers and a first insulation layer adjacent to the wiring layers. The present embodiment can optimize the manufacturing process for a package substrate, reduce process steps, and reduce manufacturing costs.

Description

Packaging substrate and its fabrication method, functional substrate and its fabrication method Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a packaging substrate and its manufacturing method, and a functional substrate and its manufacturing method. Background Technology

[0002] Packaging involves placing an integrated circuit die on a substrate that serves as a support, and then securing the substrate and the die together to form a package. Pins are then led out from the package. The package serves functions such as chip protection, electrical interconnection, and heat dissipation.

[0003] With the development of communication technology, the frequencies used in mobile communication are also increasing, from 2G technology with only a few hundred megahertz to 5G technology with 3.5 GHz. Correspondingly, the requirements for integrated passive components are also becoming more stringent. Passive components include capacitors, inductors, and resistors. Based on different integration substrates, integrated passive component technologies can be divided into different technical routes, such as silicon-based, glass-based, and low-temperature co-fired ceramic (LTCC)-based. In related technologies, after the passive components are fabricated, they need to be packaged onto a carrier board to transmit signals and perform their functions together with other chips. Summary of the Invention

[0004] The technical problem to be solved by this disclosure is to provide a packaging substrate and its manufacturing method, and a functional substrate and its manufacturing method, which can optimize the manufacturing process of the packaging substrate, reduce process steps, and reduce manufacturing costs.

[0005] To address the aforementioned technical problems, the embodiments of this disclosure provide the following technical solutions:

[0006] On one hand, a packaging substrate is provided, comprising:

[0007] A carrier plate, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction;

[0008] A first circuit structure located on the first surface, the first circuit structure including a capacitor and a trace structure located on the side of the capacitor away from the carrier board, the trace structure including at least two trace layers and a first insulating layer adjacent to the trace layers.

[0009] In some embodiments, the first circuit structure further includes:

[0010] Multiple connection terminals are located on the side of the wiring structure away from the carrier board. The connection terminals are connected to the outermost wiring of the wiring structure through vias penetrating the first insulating layer.

[0011] In some embodiments, the packaging substrate further includes:

[0012] Electronic components soldered to the connection terminals.

[0013] In some embodiments, from the direction near the carrier to the direction away from the carrier, each trace of the previous layer is connected to at least one trace of the next layer through a via through the first insulating layer, and each trace of the last layer is connected to at least one of the connection terminals.

[0014] In some embodiments, all first insulating layers are made of a thin-film interlayer insulating material (ABF).

[0015] In some embodiments, a portion of the first insulating layer is made of a thin-film interlayer insulating material (ABF) layer, while other portions of the first insulating layer are made of a polyimide layer.

[0016] In some embodiments, the polyimide layer in the first insulating layer is located on the side of the ABF layer away from the carrier plate.

[0017] In some embodiments, the ABF layer is made of a magnetic ABF material.

[0018] In some embodiments, it also includes:

[0019] The second circuit structure located on the second surface.

[0020] In some embodiments, the first circuit structure and the second circuit structure are connected by a through-hole penetrating the carrier plate.

[0021] In some embodiments, the second circuit structure includes the wiring structure, and the first circuit structure includes the wiring structure and the capacitor.

[0022] In some embodiments, the trace structure includes an inductor, and in the first circuit structure and the second circuit structure, the inductor is located on the outermost side of the trace structure.

[0023] In some embodiments, the capacitor includes a first electrode, a second insulating layer, and a second electrode stacked sequentially.

[0024] In some embodiments, grooves are formed on the surface of the carrier plate.

[0025] The first electrode plate is located within the groove, and the surface of the first electrode plate is flush with the surface of the carrier plate;

[0026] or

[0027] The capacitor is located within the groove, and the surface of the second electrode plate is flush with the surface of the carrier plate.

[0028] Embodiments of this disclosure also provide a functional substrate, including the above-described packaging substrate.

[0029] Embodiments of this disclosure also provide a method for manufacturing a packaging substrate, comprising:

[0030] A carrier plate is provided, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction;

[0031] A first circuit structure is formed on the first surface. The first circuit structure includes a capacitor and a trace structure located on the side of the capacitor away from the carrier board. The trace structure includes at least two trace layers and a first insulating layer adjacent to the trace layers. Forming at least a portion of the first insulating layer includes:

[0032] A thin-film interlayer insulating material (ABF) layer is formed by hot pressing.

[0033] In some embodiments, forming the first circuit structure further includes:

[0034] Multiple connection terminals are formed on the side of the wiring structure away from the carrier board, and the connection terminals are connected to the outermost wiring of the wiring structure through through-holes penetrating the first insulating layer.

[0035] In some embodiments, the manufacturing method further includes:

[0036] Provide another carrier board;

[0037] Bond the second surface of the other carrier plate to the second surface of the carrier plate;

[0038] While the first circuit structure is formed on the first surface of the carrier plate, the first circuit structure is also formed on the first surface of the other carrier plate.

[0039] The second surface of the other carrier plate is debonded to the second surface of the carrier plate.

[0040] In some embodiments, the manufacturing method further includes:

[0041] Forming a through hole penetrating the carrier plate;

[0042] While the first circuit structure is formed on the first surface, a second circuit structure is formed on the second surface, and the first circuit structure and the second circuit structure are connected by a through hole through the carrier plate.

[0043] In some embodiments, the traces are formed using electroplating or electroless plating processes.

[0044] The embodiments of this disclosure also provide a method for preparing a functional substrate, including the above-described method for preparing a packaging substrate. Attached Figure Description

[0045] Figure 1 is a schematic diagram of the structure of the packaging substrate in the related technology;

[0046] Figures 2 and 3 are schematic diagrams of the structure of the packaging substrate according to an embodiment of the present disclosure;

[0047] Figures 4 and 5 are schematic diagrams showing that the first insulating layer in some embodiments of this disclosure uses a polyimide layer;

[0048] Figures 6-9 are schematic diagrams of circuit structures fabricated on two surfaces of a carrier board according to an embodiment of the present disclosure. Figures 10-11 are schematic diagrams of the fabrication of a packaging substrate according to an embodiment of the present disclosure.

[0049] Figure 12 is a schematic diagram of bonding two carrier plates according to an embodiment of this disclosure;

[0050] Figure 13 is a schematic diagram of the circuit structure fabricated simultaneously on two carrier boards according to an embodiment of the present disclosure;

[0051] Figure 14 is a schematic diagram of debonding two carrier plates according to an embodiment of this disclosure.

[0052] Figure reference numerals: 01 Carrier board; 02 Capacitor; 021 First electrode plate; 022 Second insulating layer; 023 Second electrode plate; 03 Trace structure: 0311 First layer trace; 0312 Second layer trace; 0321 First polyimide layer; 0322 Second polyimide layer; 0323 Third polyimide layer; 0331 Polyimide layer; 0332 First ABF layer; 0333 Second ABF layer; 0333 Third ABF layer; 04 Connecting terminal; 041 Copper pillar; 042 Solder cap; 05 Seed layer; 06 Via; 07 Bonding layer. Detailed Implementation

[0053] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0055] Figure 1 is a schematic diagram of the packaging substrate in the related technology. As shown in Figure 1, the packaging substrate includes a carrier plate 01 and a capacitor 02, a wiring structure 03, and a connection terminal 04 located on the carrier plate 01. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022, and a second electrode plate 023 stacked sequentially. The wiring structure includes a first layer of wiring 0311 and a second layer of wiring 0312, and also includes an insulating layer adjacent to the two wiring layers: a first polyimide layer 0321, a second polyimide layer 0322, and a third polyimide layer 0323. In the related technology, because the polyimide layer pattern needs to be created through a patterning process, integrated passive devices often need to be fabricated separately. After the integrated passive device is fabricated, it needs to be packaged onto the carrier plate. The transfer and packaging of the integrated passive device results in high yield loss and numerous process steps, leading to high process costs.

[0056] This disclosure provides a packaging substrate and its manufacturing method, as well as a functional substrate and its manufacturing method, which can optimize the manufacturing process of the packaging substrate, reduce process steps, and lower manufacturing costs.

[0057] Embodiments of this disclosure provide a packaging substrate, comprising:

[0058] A carrier plate, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction;

[0059] A first circuit structure located on the first surface, the first circuit structure including a capacitor and a trace structure located on the side of the capacitor away from the carrier board, the trace structure including at least two trace layers and a first insulating layer adjacent to the trace layers, wherein at least a portion of the first insulating layer is a thin film interlayer insulating material ABF layer.

[0060] In this embodiment, the first insulating layer of the first circuit structure can be an ABF layer. The ABF layer can be fabricated using a thermo-pressing process, allowing the traces and the first insulating layer that make up the passive device to be fabricated directly on the carrier board. That is, the passive device can be fabricated directly on the carrier board, eliminating the need to fabricate the passive device first and then package it onto the carrier board. This reduces the number of process steps and avoids yield loss during the transfer and packaging of passive devices, thereby improving product yield and reducing process costs. In addition, the ABF layer is fabricated using a thermo-pressing process, which has better flatness and bonding strength, further improving product yield.

[0061] In this embodiment, the carrier board can be a glass substrate, a silicon substrate, or an LTCC substrate, and there is no limitation on the type. The packaging substrate in this embodiment can serve as an IC packaging substrate for connecting the chip to the printed circuit board (PCB). The packaging substrate in this embodiment includes various products such as Flip Chip Ball Grid Array (FCBGA) and Flip Chip Chip Scale Package (FCCSP). The wiring structure can form inductors, resistors, and other devices, and together with capacitors, form passive devices such as filters. In some embodiments, the carrier board can be a glass substrate, which has low dielectric loss and good application prospects in high-frequency fields.

[0062] As shown in Figure 2, the packaging substrate of this embodiment includes a carrier plate 01, a capacitor 02 and a wiring structure 03 located on the carrier plate 01. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022 and a second electrode plate 023 stacked sequentially. The wiring structure includes a first layer wiring 0311 and a second layer wiring 0312. The first layer wiring 0311 and the second layer wiring 0312 can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The wiring structure 03 also includes: a first ABF layer 0331 located between the capacitor 02 and the first layer wiring 0311; a second ABF layer 0332 located between the first layer wiring 0311 and the second layer wiring 0312; and a third ABF layer 0333 located on the side of the second layer wiring 0312 away from the carrier plate 01. This embodiment uses a packaging substrate with two layers of traces as an example for illustration. However, the packaging substrate in this embodiment is not limited to having two layers of traces. It may also include more layers of traces. Along the direction away from the carrier board, each layer of trace can be connected to the previous layer of trace. In order to prevent short circuits between adjacent layers of traces, a first insulating layer is provided between adjacent layers of traces to isolate conductive materials and protect the device.

[0063] In this embodiment, the wiring structure 03 forms the coil of the inductor. It can be that the wiring of different layers forms the coil of the inductor in the direction perpendicular to the carrier plate 01, or it can be that the wiring of the same layer forms the coil of the inductor in the direction parallel to the carrier plate 01.

[0064] In this embodiment, at least a portion of the first insulating layer is made of ABF layer. This can be either a portion of the first insulating layer or all of the first insulating layers are made of ABF layer. ABF layer has good insulation performance and can replace polyimide layer. Furthermore, ABF layer is manufactured using a hot-pressing process, resulting in better flatness and adhesion. This not only improves the flatness of each film layer and enhances the adhesion between film layers, but also allows for matching with board-level processes, reducing process steps and lowering manufacturing costs.

[0065] In some embodiments, as shown in FIG2, the first circuit structure includes, in addition to the wiring structure 03, the following:

[0066] Multiple connection terminals 04 are located on the side of the wiring structure 03 away from the carrier board 01. The connection terminals 04 are connected to the outermost layer of the wiring structure 03 through vias penetrating the first insulating layer, as shown in Figure 2. The connection terminals 04 are connected to the second layer wiring 0312 through vias penetrating the third ABF layer 0333.

[0067] In this embodiment, to facilitate the input and output of signals from passive devices, connection terminals 04 are also fabricated on the packaging substrate. Connection terminals 04 include copper pillars 041 and solder caps 042. The solder caps 042 can be made of a tin-silver alloy, which has good conductivity and can be soldered to external devices. In this embodiment, from the direction near the carrier plate 01 to the direction away from the carrier plate 01, each trace of the previous layer is connected to at least one trace of the next layer through a via penetrating the first insulating layer. Each trace of the last layer is connected to at least one of the connection terminals 04. As shown in Figure 2, the trace structure 03 is connected to the first electrode plate 021 of the capacitor 02 and also to the connection terminals 04.

[0068] In some embodiments, the packaging substrate may further include electronic components soldered to the connection terminal 04, specifically, the electronic components may be chips.

[0069] In this embodiment, as shown in FIG3, the connection terminal 04 may not be fabricated on the packaging substrate, which simplifies the manufacturing process of the packaging substrate and reduces the production cost of the packaging substrate. As shown in FIG3, the packaging substrate of this embodiment includes a carrier plate 01 and a capacitor 02 and a wiring structure 03 located on the carrier plate 01. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022 and a second electrode plate 023 stacked sequentially. The wiring structure includes a first layer wiring 0311 and a second layer wiring 0312. The first layer wiring 0311 and the second layer wiring 0312 can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The wiring structure 03 also includes a first ABF layer 0331 located between the capacitor 02 and the first layer wiring 0311, a second ABF layer 0332 located between the first layer wiring 0311 and the second layer wiring 0312, and a third ABF layer 0333 covering the second layer wiring 0312. When the connection terminal 04 is not made, the input and output of passive device signals can be realized by using the first layer trace 0311 and the second layer trace 0312.

[0070] In this embodiment, a portion of the first insulating layer may be made of the ABF layer, while the remaining portion may be made of a polyimide layer. Due to material properties, the thickness of the ABF layer is typically 25-35 micrometers, while the thickness of the cured polyimide layer is typically 10-15 micrometers. Using a polyimide layer for a portion of the first insulating layer helps reduce the overall thickness of the packaging substrate. Furthermore, when the first insulating layer is an ABF layer, laser-based vias are needed to create holes in the ABF layer to connect adjacent traces. Laser-based vias result in larger via sizes, which restricts the trace width and spacing, typically requiring a minimum of 9 micrometers for both. When a polyimide layer is used as the first insulating layer, photolithography can be used to form vias penetrating the polyimide layer, resulting in smaller via sizes and reducing the trace width and spacing to approximately 4 micrometers. Therefore, to reduce trace width and spacing and increase wiring density, a portion of the first insulating layer may be made of a polyimide layer.

[0071] In one embodiment, as shown in FIG4, the packaging substrate includes a carrier plate 01 and a capacitor 02 and a wiring structure 03 located on the carrier plate 01. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022 and a second electrode plate 023 stacked sequentially. The wiring structure includes a first layer wiring 0311 and a second layer wiring 0312. The first layer wiring 0311 and the second layer wiring 0312 can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The wiring structure 03 further includes: a first ABF layer 0331 located between the capacitor 02 and the first layer wiring 0311; a polyimide layer 032 located between the first layer wiring 0311 and the second layer wiring 0312; and a third ABF layer 0333 covering the second layer wiring 0312. In this embodiment, compared to the embodiment shown in FIG2, the second ABF layer 0332 between the first layer trace 0311 and the second layer trace 0312 is replaced with a polyimide layer 032, which is beneficial to reduce the overall thickness of the packaging substrate. In addition, it can reduce the line width and spacing of the second layer trace 0312 and increase the wiring density of the second layer trace 0312.

[0072] In another embodiment, as shown in FIG5, the packaging substrate includes a carrier plate 01 and a capacitor 02 and a wiring structure 03 located on the carrier plate 01. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022 and a second electrode plate 023 stacked sequentially. The wiring structure 03 includes a first layer wiring 0311 and a second layer wiring 0312. The first layer wiring 0311 and the second layer wiring 0312 can be metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and alloys of these metals. The wiring structure 03 also includes a first ABF layer 0331 located between the capacitor 02 and the first layer wiring 0311, a second ABF layer 0332 located between the first layer wiring 0311 and the second layer wiring 0312, and a polyimide layer 032 located between the second layer wiring 0312 and the connection terminal 04. In this embodiment, compared to the embodiment shown in FIG2, the third ABF layer 0333 between the second layer trace 0312 and the connection terminal 04 is replaced with a polyimide layer 032, which helps to reduce the overall thickness of the packaging substrate. In addition, it can reduce the line width and spacing of the connection terminal 04 and increase the arrangement density of the connection terminal 04.

[0073] In some embodiments, the polyimide layer 032 in the first insulating layer may be located on the side of the ABF layer away from the carrier plate 01, which can reduce the line width and spacing of the outermost traces of the packaging substrate.

[0074] Crosstalk occurs when signals are transmitted between adjacent layers, leading to transmission loss. The thickness of the ABF layer is greater than that of the polyimide layer, which reduces crosstalk between adjacent layers and lowers transmission loss. Therefore, to reduce transmission loss, the number of ABF layers in the first insulating layer can be greater than the number of polyimide layers. For example, if the first insulating layer has three layers, it can consist of two ABF layers and one polyimide layer; or if the first insulating layer has four layers, it can consist of three ABF layers and one polyimide layer.

[0075] In some embodiments, the ABF layer may be made of a magnetic ABF material. Magnetic ABF material can improve the quality factor of the inductor. When the wiring structure includes an inductor, several ABF layers near the inductor can be replaced with magnetic ABF material to improve the quality factor of the inductor.

[0076] In some embodiments, to improve the integration density of the integrated passive devices, a second circuit structure can also be formed on the second surface of the carrier board 01. As shown in FIG6, a first circuit structure is fabricated on the first surface of the carrier board 01. The first circuit structure includes: a capacitor 02, a wiring structure 03, and a connection terminal 04. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022, and a second electrode plate 023 stacked sequentially. The wiring structure 03 includes a first layer of wiring 0311 and a second layer of wiring 0312, and further includes: a first ABF layer 0331 located between the capacitor 02 and the first layer of wiring 0311, a polyimide layer 032 located between the first layer of wiring 0311 and the second layer of wiring 0312, and a third ABF layer 0333 located between the second layer of wiring 0312 and the connection terminal 04. The connection terminal 04 includes a copper pillar 041 and a solder cap 042. The structure of the second circuit structure can be the same as that of the first circuit structure. The first circuit structure and the second circuit structure can be connected through a through hole through the carrier plate 01, as shown in Figure 6. The first electrode plate 021 of the first circuit structure is connected to the first electrode plate 021 of the second circuit structure through the through hole through the carrier plate 01.

[0077] In the embodiment shown in Figure 6, the structure of the second circuit structure is the same as that of the first circuit structure; in some embodiments, the structure of the second circuit structure may also be different from that of the first circuit structure, as shown in Figure 7, where the area of ​​the first electrode plate 021 of the second circuit structure is larger than the area of ​​the first electrode plate 021 of the first circuit structure.

[0078] In some embodiments, capacitor 02 may be formed only on the first surface of carrier board 01, as shown in FIG8. The first circuit structure includes the wiring structure 03 and capacitor 02; the second circuit structure does not include capacitor 02. Specifically, the first circuit structure includes: capacitor 02, wiring structure 03 and connection terminal 04, wherein capacitor 02 includes a first electrode plate 021, a second insulating layer 022 and a second electrode plate 023 stacked sequentially; wiring structure 03 includes a first layer of wiring 0311 and a second layer of wiring 0312, wiring structure 03 also includes a first ABF layer 0331 located between capacitor 02 and first layer of wiring 0311, a second ABF layer 0332 located between first layer of wiring 0311 and second layer of wiring 0312, and a polyimide layer 032 located between second layer of wiring 0312 and connection terminal 04; connection terminal 04 includes copper pillar 041 and solder cap 042. The second circuit structure includes: a first electrode plate 021, a first ABF layer 0331, a first layer trace 0311, a second ABF layer 0332, a second layer trace 0312, a polyimide layer 032, and a connecting terminal 04. The connecting terminal 04 includes a copper pillar 041 and a solder cap 042. The first ABF layer 0331, the first layer trace 0311, the second ABF layer 0332, the second layer trace 0312, and the polyimide layer 032 form a trace structure. The first electrode plate 021 of the second circuit structure no longer serves as the electrode plate of the capacitor. It can be part of the trace structure or a connecting electrode connecting the first circuit structure and the second circuit structure.

[0079] In some embodiments, in the first circuit structure and the second circuit structure, the inductor can be located on the outermost side of the trace structure, that is, the position in the trace structure that is farthest from the carrier board. This can help dissipate heat from the inductor itself, improve the performance of the inductor, and thus improve the performance of the carrier board.

[0080] In some embodiments, as shown in FIG9, a groove is formed on the surface of the carrier plate 01, and the first electrode plate 021 is located within the groove, with the surface of the first electrode plate 021 flush with the surface of the carrier plate 01. This significantly improves the flatness of the surface of the first electrode plate 021. For capacitors, the flatness of the upper and lower electrodes has a significant impact on the capacitance value fluctuation. A flat surface of the first electrode plate can improve the stability of the capacitance value, thereby improving the stability of the carrier plate performance. In some embodiments, the entire capacitor may be located within the groove, with the surface of the second electrode plate flush with the surface of the carrier plate. This improves the flatness of the second electrode plate surface, which in turn improves the stability of the capacitance value, thereby improving the stability of the carrier plate performance.

[0081] Embodiments of this disclosure also provide a functional substrate, including the aforementioned packaging substrate. The functional substrate further includes a printed circuit board, through which the chip and the printed circuit board can be connected.

[0082] Embodiments of this disclosure also provide a method for manufacturing a packaging substrate, comprising:

[0083] A carrier plate is provided, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction;

[0084] A first circuit structure is formed on the first surface. The first circuit structure includes a capacitor and a trace structure located on the side of the capacitor away from the carrier board. The trace structure includes at least two trace layers and a first insulating layer adjacent to the trace layers. Forming at least a portion of the first insulating layer includes:

[0085] A thin-film interlayer insulating material (ABF) layer is formed by hot pressing.

[0086] In this embodiment, the first insulating layer of the first circuit structure is an ABF layer. The ABF layer can be fabricated using a thermo-pressing process, allowing the traces and the first insulating layer that make up the passive device to be fabricated directly on the carrier board. That is, the passive device is fabricated directly on the carrier board, eliminating the need to fabricate the passive device first and then package it onto the carrier board. This reduces the number of process steps and avoids yield loss during the transfer of passive devices, thereby improving product yield and reducing process costs. In addition, the ABF layer is fabricated using a thermo-pressing process, which has better flatness and bonding strength, further improving product yield.

[0087] In this embodiment, the carrier board can be a glass substrate, a silicon substrate, or an LTCC substrate, and there is no limitation on the type. The packaging substrate in this embodiment can serve as an IC packaging substrate for connecting the chip to the printed circuit board (PCB). The packaging substrate in this embodiment includes various products such as Flip Chip Ball Grid Array (FCBGA) and Flip Chip Chip Scale Package (FCCSP). The wiring structure can form inductors, resistors, and other devices, and together with capacitors, form passive devices such as filters. In some embodiments, the carrier board can be a glass substrate, which has low dielectric loss and good application prospects in high-frequency fields.

[0088] In one embodiment, the method for manufacturing the packaging substrate includes the following steps:

[0089] A carrier plate is provided and cleaned, as shown in Figure 10. After cleaning the carrier plate 01, a metal layer is formed on the carrier plate 01. The metal layer is patterned using photolithography to form a first electrode plate 021. Then, a second insulating layer 022 can be formed using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The second insulating layer 022 is patterned to form vias penetrating the second insulating layer 022, and a seed layer 05 is formed in the vias. Then, a metal layer is formed on the second insulating layer 022, and the metal layer is patterned using photolithography to form a second electrode plate 023. The first electrode plate 021, the second insulating layer 022, and the second electrode plate 023 constitute a capacitor 02.

[0090] After capacitor 02 is formed, as shown in Figure 11, a first ABF layer 0331 can be formed directly on the carrier plate 01 on which capacitor 02 is formed using a hot pressing process. A laser is used to open the first ABF layer 0331. After opening the first ABF layer 0331, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the first layer of trace 0311 can be formed using electroplating or electroless plating.

[0091] A second ABF layer 0332 is formed on a carrier board 01 with a first layer of traces 0311 using a hot-pressing process. A hole is made in the second ABF layer 0332 using a laser. After the hole is made in the second ABF layer 0332, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the second layer of traces 0312 can be formed using electroplating or electroless plating.

[0092] A third ABF layer 0333 is formed on a carrier board 01 with a second layer of traces 0312 using a hot-pressing process. A hole is made in the third ABF layer 0333 using a laser. After making the hole in the third ABF layer 0333, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, copper pillars 041 can be formed using electroplating or electroless plating. After forming the copper pillars 041, in order to prevent oxidation of the copper pillars 041 and to facilitate soldering with electronic components, a tin cap 042 can be formed on the copper pillars 041 using a tin-silver alloy. After forming the tin cap 042, to facilitate soldering, a round cap-shaped tin cap 042 can be formed by hot reflow. The copper pillars 041 and the tin cap 042 form a connection terminal 04. The connection terminal 04 is connected to the trace structure 03 through a via penetrating the third ABF layer 0333, resulting in the packaging substrate shown in Figure 2.

[0093] In another embodiment, the connection terminal 04 may not be fabricated on the packaging substrate, which simplifies the manufacturing process of the packaging substrate and reduces its production cost. The method for fabricating the packaging substrate includes the following steps:

[0094] A carrier plate is provided and cleaned, as shown in Figure 10. After cleaning the carrier plate 01, a metal layer is formed on the carrier plate 01. The metal layer is patterned using photolithography to form a first electrode plate 021. Then, a second insulating layer 022 can be formed using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The second insulating layer 022 is patterned to form vias penetrating the second insulating layer 022, and a seed layer 05 is formed in the vias. Then, a metal layer is formed on the second insulating layer 022, and the metal layer is patterned using photolithography to form a second electrode plate 023. The first electrode plate 021, the second insulating layer 022, and the second electrode plate 023 constitute a capacitor 02.

[0095] After capacitor 02 is formed, as shown in Figure 11, a first ABF layer 0331 can be formed directly on the carrier plate 01 on which capacitor 02 is formed using a hot pressing process. A laser is used to open the first ABF layer 0331. After opening the first ABF layer 0331, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the first layer of trace 0311 can be formed using electroplating or electroless plating.

[0096] A second ABF layer 0332 is formed on a carrier board 01 with a first layer of traces 0311 using a hot-pressing process. A hole is made in the second ABF layer 0332 using a laser. After the hole is made in the second ABF layer 0332, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the second layer of traces 0312 can be formed using electroplating or electroless plating.

[0097] A third ABF layer 0333 is formed on the carrier board 01 with the second layer of traces 0312 using a thermo-pressing process, resulting in the packaging substrate shown in Figure 3. In this embodiment, no connection terminals 04 are fabricated on the packaging substrate, and the input and output of passive device signals can be realized using the first layer of traces 0311 and the second layer of traces 0312.

[0098] In another embodiment, two packaging substrates can be fabricated simultaneously. Before fabricating the packaging substrate, another carrier board is provided; the second surface of the other carrier board is bonded to the second surface of the carrier board; while the first circuit structure is formed on the first surface of the carrier board, the first circuit structure is formed on the first surface of the other carrier board; the second surface of the other carrier board is debonded to the second surface of the carrier board.

[0099] As shown in Figure 12, two substrates 01 can be bonded together, where 07 is the bonding layer. Then, capacitor 02 is fabricated simultaneously on the first surfaces of both substrates 01. The steps for fabricating capacitor 02 include: forming a metal layer on substrate 01; patterning the metal layer using photolithography to form a first electrode 021; then forming a second insulating layer 022 using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), and patterning the second insulating layer 022 to form vias penetrating the second insulating layer 022; finally, forming a metal layer on the second insulating layer 022, and patterning the metal layer using photolithography to form a second electrode 023. The first electrode 021, the second insulating layer 022, and the second electrode 023 constitute capacitor 02.

[0100] As shown in Figure 13, after forming capacitor 02, a first ABF layer 0331 can be directly formed on the carrier plate 01 on which capacitor 02 is formed using a hot pressing process. A laser is used to open the first ABF layer 0331. After opening the first ABF layer 0331, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the first layer of trace 0311 can be formed using electroplating or electroless plating.

[0101] Subsequently, a second ABF layer 0332 can be formed on the carrier board 01 with the first layer of traces 0311 using a hot-pressing process. A hole is then made in the second ABF layer 0332 using a laser. After making the hole in the second ABF layer 0332, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the second layer of traces 0312 can be formed using electroplating or electroless plating.

[0102] A third ABF layer 0333 is formed on a carrier board 01 with a second layer of traces 0312 using a hot-pressing process. A hole is made in the third ABF layer 0333 using a laser. After making the hole in the third ABF layer 0333, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, copper pillars 041 can be formed using electroplating or electroless plating. After forming the copper pillars 041, in order to prevent oxidation of the copper pillars 041 and to facilitate soldering with electronic components, a tin cap 042 can be formed on the copper pillars 041 using a tin-silver alloy. After forming the tin cap 042, in order to facilitate soldering, a round cap-shaped tin cap 042 can be formed by hot reflow. The copper pillars 041 and the tin cap 042 form a connection terminal 04. The connection terminal 04 is connected to the trace structure 03 through a via penetrating the third ABF layer 0333, resulting in the packaging substrate shown in Figure 13.

[0103] Of course, in this embodiment, the connection terminal 04 can be omitted, and the input and output of passive device signals can be achieved directly using the first layer trace 0311 and the second layer trace 0312.

[0104] After the first circuit structure is fabricated on the two carrier boards 01, as shown in Figure 14, the carrier boards on both sides are debonded to obtain two packaging substrates, which can improve the production efficiency of the packaging carrier boards.

[0105] In this embodiment, a portion of the first insulating layer may be made of the ABF layer, while the remaining portion may be made of a polyimide layer. Due to material properties, the thickness of the ABF layer is typically 25-35 micrometers, while the thickness of the cured polyimide layer is typically 10-15 micrometers. Using a polyimide layer for a portion of the first insulating layer helps reduce the overall thickness of the packaging substrate. Furthermore, when the first insulating layer is an ABF layer, laser-based vias are needed to create holes in the ABF layer to connect adjacent traces. Laser-based vias result in larger via sizes, which restricts the trace width and spacing, typically requiring a minimum of 9 micrometers for both. When a polyimide layer is used as the first insulating layer, photolithography can be used to form vias penetrating the polyimide layer, resulting in smaller via sizes and reducing the trace width and spacing to approximately 4 micrometers. Therefore, to reduce trace width and spacing and increase wiring density, a portion of the first insulating layer may be made of a polyimide layer.

[0106] Additionally, the ABF layer can be made of magnetic ABF material. Magnetic ABF material can improve the quality factor of the inductor. When the wiring structure includes an inductor, the ABF layers near the inductor can be replaced with magnetic ABF material to improve the inductor's quality factor.

[0107] In another embodiment, the method for manufacturing the packaging substrate includes:

[0108] A carrier plate is provided, and a through hole is formed through the carrier plate; while the first circuit structure is formed on the first surface, a second circuit structure is formed on the second surface, and the first circuit structure and the second circuit structure are connected through the through hole through the carrier plate.

[0109] As shown in Figure 6, forming the first circuit structure may include: forming a capacitor 02, a wiring structure 03, and a connection terminal 04. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022, and a second electrode plate 023 stacked sequentially. The wiring structure 03 includes a first layer of wiring 0311 and a second layer of wiring 0312, and further includes: a first ABF layer 0331 located between the capacitor 02 and the first layer of wiring 0311, a polyimide layer 032 located between the first layer of wiring 0311 and the second layer of wiring 0312, and a third ABF layer 0333 located between the second layer of wiring 0312 and the connection terminal 04. The connection terminal 04 includes a copper pillar 041 and a solder cap 042. The structure of the second circuit structure can be the same as that of the first circuit structure. The second circuit structure can be formed on the second surface of the carrier plate 01 using the same process. The first circuit structure and the second circuit structure are connected through a through hole through the carrier plate 01, as shown in Figure 6. The first electrode plate 021 of the first circuit structure is connected to the first electrode plate 021 of the second circuit structure through the through hole through the carrier plate 01.

[0110] In the embodiment shown in Figure 6, the structure of the second circuit structure is the same as that of the first circuit structure; in some embodiments, the structure of the second circuit structure may also be different from that of the first circuit structure, as shown in Figure 7, where the area of ​​the first electrode plate 021 of the second circuit structure is larger than the area of ​​the first electrode plate 021 of the first circuit structure.

[0111] Alternatively, a capacitor 02 can be formed only on the first surface of the carrier board 01, as shown in FIG8. The formation of the first circuit structure includes: forming a capacitor 02, a wiring structure 03, and a connection terminal 04. The capacitor 02 includes a first electrode plate 021, a second insulating layer 022, and a second electrode plate 023 stacked sequentially. The wiring structure 03 includes a first layer of wiring 0311 and a second layer of wiring 0312. The wiring structure 03 also includes a first ABF layer 0331 located between the capacitor 02 and the first layer of wiring 0311, a second ABF layer 0332 located between the first layer of wiring 0311 and the second layer of wiring 0312, and a polyimide layer 032 located between the second layer of wiring 0312 and the connection terminal 04. The connection terminal 04 includes a copper pillar 041 and a solder cap 042. The formation of the second circuit structure includes: sequentially forming a first electrode plate 021, a first ABF layer 0331, a first layer trace 0311, a second ABF layer 0332, a second layer trace 0312, a polyimide layer 032, and a connection terminal 04. The connection terminal 04 includes a copper pillar 041 and a solder cap 042. The first ABF layer 0331, the first layer trace 0311, the second ABF layer 0332, the second layer trace 0312, and the polyimide layer 032 form a trace structure. The first electrode plate 021 of the second circuit structure no longer serves as the electrode plate of a capacitor, but can serve as part of the trace structure or as a connection electrode connecting the first circuit structure and the second circuit structure.

[0112] In another embodiment, slots may be cut into the carrier plate to house part or all of the capacitor within the carrier plate. The method for fabricating the packaging substrate includes the following steps:

[0113] A carrier plate 01 is provided and cleaned. After cleaning, a groove is cut into the carrier plate 01 to form a recess. The shape of the recess is the same as the shape of the first electrode plate 021 of the capacitor 02 to be formed. A layer of copper can be grown in the recess by electroplating. The copper on the surface of the carrier plate 01 is removed by chemical mechanical polishing (CMP) to form the first electrode plate 021. Then, a second insulating layer 022 can be formed by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The second insulating layer 022 is patterned to form vias penetrating the second insulating layer 022. A metal layer is then formed on the second insulating layer 022. The metal layer is patterned by photolithography to form the second electrode plate 023. The first electrode plate 021, the second insulating layer 022, and the second electrode plate 023 constitute the capacitor 02.

[0114] After capacitor 02 is formed, a first ABF layer 0331 can be formed directly on the carrier board 01 on which capacitor 02 is formed using a hot pressing process. A laser is used to open the first ABF layer 0331. After opening the first ABF layer 0331, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the first layer of trace 0311 can be formed using electroplating or electroless plating.

[0115] A polyimide layer 032 is formed on a carrier board 01 on which the first layer of traces 0311 is formed. A hole is made in the polyimide layer 032 using a photolithography process. After the hole is made in the polyimide layer 032, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, the second layer of traces 0312 can be formed using electroplating or electroless plating.

[0116] A third ABF layer 0333 is formed on a carrier board 01 with a second layer of traces 0312 using a hot-pressing process. A hole is made in the third ABF layer 0333 using a laser. After making the hole in the third ABF layer 0333, a seed layer can be formed in the via using chemical vapor deposition (PVD) or electroless plating. Then, copper pillars 041 can be formed using electroplating or electroless plating. After forming the copper pillars 041, in order to prevent oxidation of the copper pillars 041 and to facilitate soldering with electronic components, a tin cap 042 can be formed on the copper pillars 041 using a tin-silver alloy. After forming the tin cap 042, to facilitate soldering, a round cap-shaped tin cap 042 can be formed by hot reflow. The copper pillars 041 and the tin cap 042 form a connection terminal 04. The connection terminal 04 is connected to the trace structure 03 through a via penetrating the third ABF layer 0333, resulting in the packaging substrate shown in Figure 9.

[0117] This embodiment can significantly improve the flatness of the surface of the first electrode plate 021. For capacitors, the flatness of the upper and lower electrodes has a significant impact on the fluctuation of the capacitance value. A flat surface of the first electrode plate can improve the stability of the capacitance value, thereby improving the stability of the carrier plate performance.

[0118] In other embodiments, the entire capacitor may be located within the groove, and the surface of the second electrode plate may be flush with the surface of the carrier plate. This can improve the flatness of the second electrode plate surface, and a flat second electrode plate surface can improve the stability of the capacitance value, thereby improving the stability of the carrier plate performance.

[0119] The embodiments of this disclosure also provide a method for preparing a functional substrate, including the above-described method for preparing a packaging substrate.

[0120] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0121] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0122] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0123] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. 。

Claims

1. A packaging substrate, characterized in that, include: A carrier plate, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction; A first circuit structure located on the first surface, the first circuit structure including a capacitor and a trace structure located on the side of the capacitor away from the carrier board, the trace structure including at least two trace layers and a first insulating layer adjacent to the trace layers.

2. The packaging substrate according to claim 1, characterized in that, The first circuit structure further includes: Multiple connection terminals are located on the side of the wiring structure away from the carrier board. The connection terminals are connected to the outermost wiring of the wiring structure through vias penetrating the first insulating layer.

3. The packaging substrate according to claim 2, characterized in that, The packaging substrate further includes: Electronic components soldered to the connection terminals.

4. The packaging substrate according to claim 2, characterized in that, From the direction closest to the carrier plate to the direction furthest from the carrier plate, each trace of the preceding layer is connected to at least one trace of the following layer through a via penetrating the first insulating layer, and each trace of the last layer is connected to at least one of the connection terminals.

5. The packaging substrate according to claim 1, characterized in that, All of the first insulating layers are made of thin-film interlayer insulating material ABF layer.

6. The packaging substrate according to claim 1, characterized in that, Some of the first insulating layers are made of a thin-film interlayer insulating material ABF layer, while others are made of a polyimide layer.

7. The packaging substrate according to claim 6, characterized in that, In the first insulating layer, the polyimide layer is located on the side of the ABF layer away from the carrier plate.

8. The packaging substrate according to claim 5 or 6, characterized in that, The ABF layer is made of magnetic ABF material.

9. The packaging substrate according to claim 1, characterized in that, Also includes: The second circuit structure located on the second surface.

10. The packaging substrate according to claim 9, characterized in that, The first circuit structure and the second circuit structure are connected by a through hole penetrating the carrier plate.

11. The packaging substrate according to claim 9, characterized in that, The second circuit structure includes the wiring structure, and the first circuit structure includes the wiring structure and the capacitor.

12. The packaging substrate according to claim 11, characterized in that, The trace structure includes an inductor, and in the first circuit structure and the second circuit structure, the inductor is located on the outermost side of the trace structure.

13. The packaging substrate according to any one of claims 1-12, characterized in that, The capacitor comprises a first electrode plate, a second insulating layer, and a second electrode plate stacked in sequence.

14. The packaging substrate according to claim 13, characterized in that, The surface of the carrier plate has grooves formed. The first electrode plate is located within the groove, and the surface of the first electrode plate is flush with the surface of the carrier plate; or The capacitor is located within the groove, and the surface of the second electrode plate is flush with the surface of the carrier plate.

15. A functional substrate, characterized in that, The packaging substrate includes any one of claims 1-14.

16. A method for manufacturing a packaging substrate, characterized in that, include: A carrier plate is provided, the carrier plate including a first surface and a second surface disposed opposite to each other along its thickness direction; A first circuit structure is formed on the first surface. The first circuit structure includes a capacitor and a trace structure located on the side of the capacitor away from the carrier board. The trace structure includes at least two trace layers and a first insulating layer adjacent to the trace layers. Forming at least a portion of the first insulating layer includes: A thin-film interlayer insulating material (ABF) layer is formed by hot pressing.

17. The method for manufacturing a packaging substrate according to claim 16, characterized in that, The first circuit structure also includes: Multiple connection terminals are formed on the side of the wiring structure away from the carrier board, and the connection terminals are connected to the outermost wiring of the wiring structure through through-holes penetrating the first insulating layer.

18. The method for manufacturing a packaging substrate according to claim 16, characterized in that, The manufacturing method further includes: Provide another carrier board; Bond the second surface of the other carrier plate to the second surface of the carrier plate; While the first circuit structure is formed on the first surface of the carrier plate, the first circuit structure is also formed on the first surface of the other carrier plate. The second surface of the other carrier plate is debonded to the second surface of the carrier plate.

19. The method for manufacturing a packaging substrate according to claim 16, characterized in that, The manufacturing method further includes: A through hole is formed through the carrier plate; While the first circuit structure is formed on the first surface, a second circuit structure is formed on the second surface, and the first circuit structure and the second circuit structure are connected by a through hole through the carrier plate.

20. The method for manufacturing a packaging substrate according to claim 16, characterized in that, The wiring is formed using electroplating or chemical plating processes.

21. A method for preparing a functional substrate, characterized in that, The method for preparing the packaging substrate according to any one of claims 16-20.

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