Instruction execution method and apparatus, and electronic device

Abstract

An instruction execution method and apparatus, and an electronic device, relating to the technical field of computers, and used for solving the problem of low computing performance of a single general-purpose instruction. The instruction execution method is applied to the instruction execution apparatus. The method comprises: acquiring a target instruction, the target instruction comprising instruction information, and the instruction information being used for indicating at least two computational operations, a first register and a second register, wherein the first register is used for storing at least one operand; acquiring the at least one operand from the first register; and on the basis of the at least one operand, executing the at least two computational operations corresponding to the target instruction, and storing obtained first target data in the second register, wherein the at least two computational operations include a data precision conversion operation and at least one computational operation, and the bit width of each operand among the at least one operand is different from the bit width of the first target data. The at least two computational operations are implemented by executing the target instruction, thereby shortening the time for executing the instruction.

Description

A method, apparatus and electronic device for executing instructions

[0001] This application claims priority to Chinese Patent Application No. 202510245958.5, filed with the State Intellectual Property Office of China on February 28, 2025, entitled “An Instruction Execution Method, Apparatus and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to an instruction execution method, apparatus and electronic device. Background Technology

[0003] Transformer models are deep learning models based on attention mechanisms. Common examples of Transformer models include large language models (LLM) and chat generative pre-trained transformers (chatGPT).

[0004] Currently, general-purpose processors perform attention mechanism calculations using general-purpose instructions, such as calculating the softmax function within the attention mechanism. General-purpose processors can include central processing units (CPUs), graphics processing units (GPUs), and neural network processing units (NPUs); general-purpose instructions can include sub, cast, exp, mul, and add instructions. A single general-purpose instruction can also be called a single instruction.

[0005] However, a single general instruction can only perform the calculation of a single function, resulting in low computational performance. This leads to high computational time for the attention mechanism, which cannot meet the needs of high-performance scenarios, such as artificial intelligence (AI) scenarios. Summary of the Invention

[0006] This application provides an instruction execution method, apparatus, and electronic device to solve the problem of low computational performance of a single general-purpose instruction.

[0007] In a first aspect, an instruction execution method is provided, applied in an instruction execution device. The method includes: acquiring a target instruction, the target instruction including instruction information, the instruction information indicating: at least two arithmetic operations, a first register, and a second register; wherein the first register is used to store at least one operand; acquiring at least one operand from the first register; executing at least two arithmetic operations corresponding to the target instruction according to the at least one operand, and storing the obtained first target data in the second register; wherein the at least two arithmetic operations include a data precision conversion operation and at least one arithmetic operation, and the bit width of each operand in the at least one operand is different from the bit width of the first target data.

[0008] In the above technical solution, the target instruction includes a data precision conversion operation and at least one arithmetic operation. The processor executes at least two arithmetic operations corresponding to the target instruction based on at least one operand. That is, the processor calculates attention weights on at least one operand by executing the target instruction. The performance of the target instruction is equivalent to the performance of multiple general instructions. For example, the performance of the target instruction is equivalent to the performance of 2-4 general instructions. By executing the target instruction, the performance of multiple general instructions can be achieved. Compared with executing multiple general instructions, executing the target instruction shortens the instruction execution time and improves computational efficiency. For example, it can improve computational efficiency by 25%, thereby improving the performance of the Transformer model. For example, it can improve the performance gain of the Transformer model by 25%, enabling the Transformer model to be applied to high-performance scenarios.

[0009] In any possible implementation of the first aspect, each operand in the at least one operand has a first bit width, and the first target data has a second bit width, wherein the first bit width is greater than the second bit width; at least two arithmetic operations corresponding to the target instruction are executed based on the at least one operand, including: performing a first arithmetic operation of the first bit width on the at least one operand, and performing a data precision conversion operation on the obtained arithmetic result to obtain first converted data; performing a second arithmetic operation of the second bit width on the first converted data to obtain the first target data. The above possible implementations can execute at least two arithmetic operations corresponding to the target instruction on at least one operand with a high bit width, outputting the first target data with a low bit width, shortening the instruction execution time, improving computational efficiency, and enhancing the versatility of the target instruction.

[0010] In any possible implementation of the first aspect, each operand in the at least one operand has a first bit width, and the first target data has a second bit width, where the first bit width is smaller than the second bit width. At least two arithmetic operations corresponding to the target instruction are executed based on the at least one operand, including: performing a data precision conversion operation on the at least one operand, and performing a second arithmetic operation of the second bit width on the converted at least one operand to obtain the first target data. The above possible implementations can execute at least two arithmetic operations corresponding to the target instruction on at least one operand with a lower bit width, outputting the first target data with a higher bit width. Compared with executing multiple general instructions, executing the target instruction shortens the instruction execution time and improves computational efficiency.

[0011] In any possible implementation of the first aspect, each operand in the at least one operand is of first bit width, and the first target data is of second bit width, wherein the first bit width is smaller than the second bit width; at least two arithmetic operations corresponding to the target instruction are executed based on the at least one operand, including: performing a first arithmetic operation of the first bit width on the at least one operand, and performing a data precision conversion operation on the obtained arithmetic result to obtain second converted data; performing a second arithmetic operation of the second bit width on the second converted data to obtain the first target data. The above possible implementations can execute at least two arithmetic operations corresponding to the target instruction on at least one operand of low bit width, outputting the first target data of high bit width, shortening the instruction execution time, improving computational efficiency, and enhancing the versatility of the target instruction.

[0012] In any possible implementation of the first aspect, the method further includes: performing a data precision conversion operation on the first target data to obtain second target data; storing the obtained first target data in a second register, including: storing the second target data in a second register. The above possible implementations enable the target instruction to process operands of different bit widths and to output operands of different bit widths as needed, thereby increasing the applicability and versatility of the target instruction.

[0013] In any possible implementation of the first aspect, at least one operand is an integer or floating-point type. These possible implementations allow the target instruction to process different types of data, making the target instruction more flexible and efficient.

[0014] In any possible implementation of the first aspect, at least one operand includes a first operand and a second operand, where the first operand is a vector and the second operand is either a vector or a scalar. In the above possible implementations, vector registers support parallel processing of multiple data items, improving computational efficiency. Furthermore, retrieving different operands from different vector registers reduces processor memory access, lowering power consumption and latency. Scalar registers can provide higher data throughput and lower latency when processing large amounts of data, thereby improving the execution efficiency of the target instruction.

[0015] In any possible implementation of the first aspect, the first register includes a first vector register and a second vector register, and the storage location of the first operand in the first vector register and the storage location of the second operand in the second vector register are the same. The above possible implementations improve the processor's efficiency in reading at least one operand during subsequent calculations while reducing the complexity of executing the target instruction.

[0016] In any of the possible implementations of the first aspect, the target instruction is applicable to both Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT) computation scenarios. These possible implementations increase the application scenarios of the target instruction and improve its versatility.

[0017] In any possible implementation of the first aspect, at least one arithmetic operation includes at least one of the following: subtraction, exponentiation, multiplication, addition, or data type conversion. The above possible implementations make the performance of the target instruction consistent with that of multiple general-purpose instructions, thereby shortening the execution time of the target instruction and improving computational efficiency.

[0018] In a second aspect, an instruction execution apparatus is provided, comprising: an acquisition unit for acquiring a target instruction, the target instruction including instruction information, the instruction information indicating: at least two arithmetic operations, a first register, and a second register; wherein the first register is used to store at least one operand; the acquisition unit is further configured to acquire at least one operand from the first register; and an execution unit for executing at least two arithmetic operations corresponding to the target instruction according to the at least one operand, and storing the obtained first target data in the second register; wherein the at least two arithmetic operations include a data precision conversion operation and at least one arithmetic operation, and the bit width of each operand in the at least one operand is different from the bit width of the first target data.

[0019] In any possible implementation of the second aspect, each operand in at least one operand is a first bit width, the first target data is a second bit width, and the first bit width is greater than the second bit width; the execution unit is further configured to: perform a first operation on the first bit width of the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain first converted data; and perform a second operation on the first converted data with a second bit width to obtain the first target data.

[0020] In any possible implementation of the second aspect, each operand in at least one operand is of first bit width, the first target data is of second bit width, and the first bit width is smaller than the second bit width; the execution unit is further configured to: perform data precision conversion operations on at least one operand respectively, and perform a second operation operation of second bit width on the at least one operand after conversion to obtain the first target data.

[0021] In any possible implementation of the second aspect, each operand in at least one operand is a first bit width, the first target data is a second bit width, and the first bit width is less than the second bit width; the execution unit is further configured to: perform a first operation on the first bit width of the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain second converted data; and perform a second operation on the second converted data with the second bit width to obtain the first target data.

[0022] In any possible implementation of the second aspect, the execution unit is further configured to: perform a data precision conversion operation on the first target data to obtain the second target data; and store the second target data in the second register.

[0023] In any possible implementation of the second aspect, at least one operand is an integer type or a floating-point type.

[0024] In any possible implementation of the second aspect, at least one operand includes a first operand and a second operand, wherein the first operand is a vector and the second operand is either a vector or a scalar.

[0025] In any possible implementation of the second aspect, the first register includes a first vector register and a second vector register, wherein the storage location of the first operand in the first vector register and the storage location of the second operand in the second vector register are the same.

[0026] In any possible implementation of the second aspect, the target instruction is applicable to computational scenarios of Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT).

[0027] In any possible implementation of the second aspect, at least one arithmetic operation includes at least one of the following: subtraction, exponentiation, multiplication, addition, or data type conversion.

[0028] Thirdly, an electronic device is provided, comprising a processor and a memory, the memory for storing data, and the processor for executing instruction execution methods as provided in the first aspect or any possible implementation thereof.

[0029] Fourthly, a computer-readable storage medium is provided, wherein a computer program or instructions are stored therein, and when the computer program or instructions are executed, implement the instruction execution method provided by the first aspect or any possible implementation thereof.

[0030] Fifthly, a computer program product is provided, comprising: a computer program, also known as code or instructions, which, when run, causes a computer to execute the instruction execution method provided by the first aspect or any possible implementation thereof.

[0031] Understandably, the beneficial effects that can be achieved by the second to fifth aspects mentioned above can be referred to in the context of the first aspect or any possible implementation of the first aspect, and will not be repeated here. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0033] Figure 2 is a flowchart illustrating an instruction execution method provided in an embodiment of this application;

[0034] Figure 3 is a functional schematic diagram of a target instruction provided in an embodiment of this application;

[0035] Figure 4 is a functional schematic diagram of another target instruction provided in an embodiment of this application;

[0036] Figure 5 is a functional schematic diagram of another target instruction provided in an embodiment of this application;

[0037] Figure 6 is a functional schematic diagram of another target instruction provided in an embodiment of this application;

[0038] Figure 7 is a data processing flowchart provided in an embodiment of this application;

[0039] Figure 8 is another data processing flowchart provided in an embodiment of this application;

[0040] Figure 9 is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application. Detailed Implementation

[0041] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this application and technology, and do not limit the scope of this application.

[0042] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0043] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0044] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0045] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or roles. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order.

[0046] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0047] Before introducing the embodiments of this application, we will first introduce and explain the relevant knowledge of deep learning models.

[0048] A Transformer model is a deep learning model based on an attention mechanism. Examples of Transformer models include large language models (LLMs) and chat generative pre-trained transformers (chatGPT). As the length of the user input sequence increases, the computational cost of the attention mechanism becomes increasingly high; for instance, the softmax function in the attention mechanism is computationally expensive. The sequence comprises multiple data points, and the length of the sequence can also be referred to as the length of these multiple data points.

[0049] In one possible embodiment, the computational and data storage requirements of the attention mechanism are reduced by decreasing the bit width (i.e., precision) of the data. For example, the input and output data of the softmax function are typically converted from 32-bit half-precision floating-point (HPFP32) data to 16-bit half-precision floating-point (HPFP16) data or 16-bit brain floating-point (BFP16) data to reduce the computational and data storage requirements of the softmax function, thereby reducing the computational and data storage requirements of the attention mechanism.

[0050] However, general-purpose processors perform the calculations for the attention mechanism using general-purpose instructions. For example, they calculate the softmax function in the attention mechanism, which is used to calculate the attention weight for each data point in the sequence. General-purpose processors can include central processing units (CPUs), graphics processing units (GPUs), and neural-network processing units (NPUs), etc.; general-purpose instructions can include subtraction instructions, cast instructions, exp instructions, mul instructions, and add instructions, etc. A single general-purpose instruction can also be called a single instruction.

[0051] For example, if the input and output data of the softmax function are both FP16 data, the instructions executed by the softmax function during the calculation process include the sub instruction, cast instruction, exp instruction, cast instruction, and mul instruction, etc.; if the input data of the softmax function is FP32 data and the output data is FP16 data or BF16 data, the instructions executed by the softmax function during the calculation process include the sub instruction, exp instruction, cast instruction, and mul instruction, etc.

[0052] However, a single general instruction can only perform the calculation of a single function, resulting in low computational performance. This leads to high computational time for the attention mechanism, which cannot meet the needs of high-performance scenarios, such as artificial intelligence (AI) scenarios.

[0053] Based on this, embodiments of this application provide an instruction execution method to solve the problem of high computation time of the attention mechanism, thereby shortening the computation time of the attention mechanism and improving the performance of the Transformer model.

[0054] The method provided in this application can be applied to various electronic devices. Optionally, the electronic device may include, but is not limited to: mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), camera, wearable device (e.g., smartwatch, smart bracelet, pedometer, etc.), audio equipment, audio and video player, set-top box, game console, printer, mouse, keyboard, in-vehicle equipment (e.g., equipment on vehicles such as cars, airplanes, ships, trains and high-speed trains), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (e.g., refrigerator, television, air conditioner, electricity meter, etc.), smart robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flying equipment (e.g., smart robot, hot air balloon, drone, airplane), etc.

[0055] The following example uses a mobile phone as an example to illustrate the structure of the electronic device. As shown in Figure 1, the electronic device may include components such as a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display unit 140, a sensor 150, an audio circuit 160, a processor 170, and a power supply 180.

[0056] RF circuit 110 can be used to send and receive information, or to receive or send signals during a call. Specifically, it receives downlink information from the base station and processes it in processor 170; additionally, it sends uplink data to the base station. Typically, RF circuit 110 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, RF circuit 110 can also communicate wirelessly with networks and other devices.

[0057] The memory 120 can be used to store data, software programs, and modules; it mainly includes a program storage area and a data storage area. The program storage area can store the operating system and application programs required for at least one function, such as sound playback and image playback functions. The data storage area can store data created based on the use of the electronic device, such as audio data, image data, and a phone book. Furthermore, the electronic device may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0058] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the electronic device. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch screen), and drive the corresponding connected devices according to a pre-set program. Optionally, other input devices 132 may include, but are not limited to, one or more of the following: a physical keyboard, function keys (such as volume control buttons, power switch buttons, etc.), a trackball, a mouse, a joystick, etc.

[0059] Display unit 140 can be used to display information input by the user or information provided to the user, as well as various menus of the electronic device. In one example, display unit 140 may include display screen 141, which may be configured as a liquid crystal display (LCD), organic light-emitting diode (OLED), or similar device. Furthermore, touchscreen 131 may cover display screen 141. When touchscreen 131 detects a touch operation on or near it, it transmits the information to processor 170 to determine the type of touch event. Subsequently, processor 170 provides corresponding visual output on display screen 141 based on the type of touch event. Although in the figures, touchscreen 131 and display screen 141 are shown as two separate components to implement the input and output functions of the electronic device, in some embodiments, touchscreen 131 and display screen 141 can be integrated to achieve the input and output functions of the electronic device.

[0060] Sensor 150 may include one or more sensors for providing status assessments of various aspects of the electronic device. Sensor 150 may include a light sensor, which can be used in imaging applications, i.e., as a component of a camera or video camera. Furthermore, sensor 150 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor 150 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the electronic device.

[0061] Audio circuitry 160, a speaker, and a microphone provide an audio interface between the user and the electronic device. Audio circuitry 160 converts received audio data into electrical signals and transmits them to the speaker, where the speaker converts them into sound signals for output. On the other hand, the microphone converts collected sound signals into electrical signals, which are then received by audio circuitry 160, converted into audio data, and output to RF circuitry 110 for transmission to, for example, another mobile phone, or to memory 120 for further processing.

[0062] The processor 170 is the control center of the electronic device, connecting various parts of the device through various interfaces and lines. It executes software programs and / or modules stored in the memory 120, and calls data stored in the memory 120, to perform various functions and process data, thereby providing overall monitoring of the electronic device. Optionally, the processor 170 may include one or more processing units, which may include, but are not limited to: a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), an image signal processor (ISP), a tensor processing unit (TPU), a data processing unit (DPU), a digital signal processor (DSP), a microcontroller, or a microprocessor. Furthermore, the processor 170 may also include other hardware circuits or accelerators, such as application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Optionally, the processor 170 may also be a combination of functions that implement computing, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0063] The electronic device may also include a power supply 180 (e.g., a battery) to power various components. The power supply 180 can be logically connected to the processor 170 via a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. Optionally, the power management system can simultaneously support fast charging and non-fast charging technologies. In practical applications, the power management system can charge the battery in the power supply 180 using either fast charging or non-fast charging technologies.

[0064] Although not shown, the electronic device may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described in detail in the embodiments of this application. Those skilled in the art will understand that the structure of the electronic device shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0065] Figure 2 is a schematic flowchart of an instruction execution method provided in an embodiment of this application. This method can be applied to a processor, which can be the processor 170 shown in Figure 1 above. The method includes the following steps.

[0066] S201: The processor fetches the target instruction, which includes instruction information indicating at least two arithmetic operations, a first register, and a second register; wherein the first register is used to store at least one operand.

[0067] When it is necessary to calculate attention weights, i.e., to perform calculations related to the softmax function in the attention mechanism, the processor can retrieve the target instruction from memory, cache, or buffer. For example, if the target instruction is stored in memory, the processor retrieves the target instruction from memory; if the target instruction is stored in cache, the processor retrieves the target instruction from cache; if the target instruction is stored in buffer, the processor retrieves the target instruction from buffer.

[0068] In addition, at least two arithmetic operations include data precision conversion operations and at least one arithmetic operation, which includes at least one of the following: subtraction, exponentiation, multiplication, addition, or data type conversion.

[0069] Furthermore, at least one operand may include only one operand or multiple operands. This application does not specifically limit this. In one possible embodiment, at least one operand includes a first operand. In another possible embodiment, at least one operand includes both a first operand and a second operand. The following embodiments illustrate this using the example of at least one operand including both a first operand and a second operand.

[0070] Secondly, at least one operand type can be either an integer or a floating-point number. Integer types can include unsigned integers (uint), such as uint8, uint16, uint32, or uint64. Floating-point data types include FP8, FP16, FP32, FP64, BF16, float16, float8, FP4, MXFP4, and HiFloat8.

[0071] Furthermore, the at least two computational operations are at least some of the computational operations in the softmax function. In one possible embodiment, the at least two computational operations can be the computationally intensive parts of the softmax function, meaning the target instruction can perform the computationally intensive parts of the softmax function. In another possible embodiment, the at least two computational operations can be all the computational operations in the softmax function, meaning the target instruction can perform all the calculations in the softmax function. The embodiments in this application are not specifically limited. The target instruction can also be called a mixed-precision fusion instruction. The following embodiments use the example of the target instruction performing the computationally intensive parts of the softmax function for illustration.

[0072] In one possible embodiment, when at least one operand includes a first operand and a second operand, the first operand is a vector and the second operand is a scalar. When the first register includes a first vector register and a scalar register, the first vector register is used to store the first operand, and the scalar register is used to store the second operand.

[0073] In another possible embodiment, when at least one operand includes a first operand and a second operand, both the first operand and the second operand are vectors. When the first register includes a first vector register and a second vector register, the first vector register is used to store the first operand, and the second vector register is used to store the second operand. Optionally, the storage location of the first operand in the first vector register and the storage location of the second operand in the second register can be the same. For example, if the first operand is stored in bits 0-15 of the first vector register, then the second operand is also stored in bits 0-15 of the second vector register.

[0074] In practical applications, the processor receives data to be processed from the user (e.g., one or more types of image data, text data, video data, and signal data). The processor converts the data into a sequence, which is an m-row, n-column matrix. Based on a linear transformation matrix (including a query matrix Wq and a key matrix Wk), the processor determines the corresponding query matrix qi and key matrix ki for the sequence; that is, the processor converts the sequence into a linear matrix. The query matrix qi is an m-row, k-column matrix, and the key matrix ki is an n-row, k-column matrix. The processor calculates the product of the query matrix qi and the transposed key matrix kt to obtain a first matrix. The transposed key matrix kt is a k-row, n-column matrix. The first matrix is ​​an m-row, n-column matrix, and the m×n data in the first matrix are the first operands. Each row of the first matrix contains m data points representing one piece of data to be processed. In one possible embodiment, the processor determines the maximum data point in each row of the first matrix to obtain a second matrix. The second matrix is ​​a row matrix with m rows, and the m data points in the second matrix are the second operands. The processor stores the first and second operands in memory. Both m and m' are integers greater than 1.

[0075] In one possible embodiment, when attention mechanism computation is required, the processor reads a first operand and a second operand from memory and stores the first operand and the second operand in a first register. The memory may include caches and registers, which can also be called local caches or buffers.

[0076] S202: The processor obtains the first operand and the second operand from the first register.

[0077] When attention weights need to be calculated, i.e., when the softmax function in the attention mechanism is being calculated, the processor obtains the first operand and the second operand from the first register. Since the first register can include different registers, the two cases will be explained separately below.

[0078] In one possible embodiment, the first register includes a first vector register and a scalar register, wherein the processor obtains a first operand from the first vector register and a second operand from the scalar register.

[0079] In one possible embodiment, the first register includes a first vector register and a second vector register, wherein the processor obtains a first operand from the first vector register and a second operand from the second vector register.

[0080] S203: The processor executes at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand, and stores the obtained first target data in the second register; wherein the at least two arithmetic operations include a data precision conversion operation and at least one arithmetic operation, the bit width of the first operand and the bit width of the second operand are the same, and the bit width of the first target data is different.

[0081] The processor executes at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand. These at least two arithmetic operations are part of the arithmetic operations in the softmax function, which satisfies formula (1):

[0082] Among them, X ij X represents the j-th data in the i-th row of the first matrix. imax Let m represent the largest data in the i-th row of the first matrix, and let m represent the total number of data in the i-th row of the first matrix, where 1 ≤ i ≤ m and 1 ≤ j ≤ n.

[0083] Specifically, the processor executes at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand. That is, the processor executes the target instruction to perform at least two arithmetic operations on the first operand and the second operand. In other words, the processor executes the target instruction to perform attention calculation on the first matrix with m rows and n columns and the second matrix with m rows to obtain a third matrix with m rows and n columns. The third matrix includes multiple data that are the first target data.

[0084] Furthermore, the processor stores the first target data in a second register, which can also be a target prediction register.

[0085] Secondly, the bit width of the first operand is the same as the bit width of the second operand, but different from the bit width of the first target data. For example, the bit width of both the first and second operands is the first bit width, and the bit width of the first target data is the second bit width; the first bit width and the second bit width are different. Optionally, the bit width of the first operand is the sum of the bit widths of the multiple data included in the first matrix, the bit width of the second operand is the sum of the bit widths of the multiple data included in the second matrix, and the bit width of the first target data is the sum of the bit widths of the multiple data included in the third matrix.

[0086] Since data precision is positively correlated with data bit width—for example, the larger the data bit width, the higher the data precision; conversely, the smaller the data bit width, the lower the data precision—the precision of the first operand and the second operand are the same, but different from the precision of the first target data. For example, the precision of both the first and second operands is the first precision, while the precision of the first target data is the second precision; the first precision and the second precision are different.

[0087] Assuming that the bit width of the first operand and the bit width of the second operand are both the first bit width, and the bit width of the first target data is the second bit width, the following describes several possible implementations of processing the first operand and the second operand when the first bit width and the second bit width are different.

[0088] In a first possible embodiment, the bit width of the first operand is the same as the bit width of the second operand and is greater than the bit width of the first target data, that is, the first bit width is greater than the second bit width.

[0089] In this embodiment, the first bit width is a high bit width relative to the bit width of the first target data (i.e., the second bit width), and the second bit width is a low bit width relative to the bit width of the first operand and the bit width of the second operand (i.e., the first bit width). That is, both the first operand and the second operand are high bit width data, and the first target data is low bit width data. In other words, both the first operand and the second operand are high precision data, and the first target data is low precision data. For example, both the first operand and the second operand are FP32 data or FP64 data, and the first target data is FP16 data, BF16 data, or FP8 data, etc.

[0090] At this point, both the first and second operands in the target instruction are high-bit-width (i.e., high-precision) data, and the first target data output by the processor after executing the target instruction is low-bit-width (i.e., low-precision) data. The following explanation, with reference to Figure 3, illustrates the process of the processor executing the target instruction for calculation when the first bit width is greater than the second bit width.

[0091] For example, as shown in Figure 3, in step S203, the processor executes at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand. These operations include: the processor performing a first arithmetic operation (i.e., high-bit-width calculation) on the high-bit-width first operand and the high-bit-width second operand, and performing a data precision conversion operation on the obtained result to obtain first converted data, i.e., converting the result from the first bit-width (i.e., high-bit-width) to the second bit-width (i.e., low-bit-width); and performing a second arithmetic operation (i.e., low-bit-width calculation) on the first converted data to obtain the low-bit-width first target data. The data precision conversion operation can also be called a data bit-width conversion operation.

[0092] The at least one arithmetic operation includes a first arithmetic operation and a second arithmetic operation. That is, the first arithmetic operation is any one of the at least one arithmetic operation, and the second arithmetic operation is any one of the at least one arithmetic operation. The first arithmetic operation and the second arithmetic operation can be the same or different. For example, both the first arithmetic operation and the second arithmetic operation can be multiplication, or the first arithmetic operation can be multiplication and the second arithmetic operation can be addition. This application does not specifically limit this aspect.

[0093] In a second possible embodiment, the bit width of the first operand is the same as the bit width of the second operand, and is smaller than the bit width of the first target data, that is, the first bit width is smaller than the second bit width.

[0094] In this embodiment, the first bit width is a low bit width relative to the bit width of the first target data (i.e., the second bit width), and the second bit width is a high bit width relative to the bit width of the first operand and the bit width of the second operand (i.e., the first bit width). That is, both the first operand and the second operand are low bit width data, and the first target data is high bit width data. In other words, both the first operand and the second operand are low precision data, and the first target data is high precision data. For example, both the first operand and the second operand are FP16 data, BF16 data, or 8-bit half-precision floating-point (HPFP8) (abbreviated as FP8) data, etc., and the first target data is FP32 data or 64-bit half-precision floating-point (HPFP64) (abbreviated as FP64) data, etc.

[0095] At this point, both the first and second operands in the target instruction are low-width (i.e., low-precision) data, and the first target data output by the processor after executing the target instruction is high-width (i.e., high-precision) data. The following explanation, in conjunction with Figures 4 and 5, illustrates the process of the processor executing the target instruction for calculation when the first bit width is smaller than the second bit width.

[0096] In one possible embodiment, exemplarily as shown in FIG4, in step S203, the processor performs at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand, including: the processor performs a first arithmetic operation (i.e., low-bit-width calculation) on the low-bit-width first operand and the low-bit-width second operand, and performs a data precision conversion operation on the obtained arithmetic result to obtain second converted data, that is, the arithmetic result is converted from the first bit width (i.e., low bit width) to the second bit width (i.e., high bit width); the processor performs a second arithmetic operation (i.e., high bit width calculation) on the high-bit-width second converted data to obtain the high-bit-width first target data.

[0097] In one possible embodiment, for example as shown in FIG5, in step S203, the processor executes at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand, including: the processor performs data precision conversion operations on the low-bit-width first operand and the low-bit-width second operand respectively, that is, converts the first operand from the first bit width to the second bit width, converts the second operand from the first bit width to the second bit width, and performs a second arithmetic operation (i.e., high-bit-width calculation) on the converted high-bit-width first operand and the high-bit-width second operand to obtain the high-bit-width first target data.

[0098] In one possible embodiment, the bit width of the first operand is the same as the bit width of the second operand and the same as the bit width of the first target data, that is, the first bit width is equal to the second bit width.

[0099] In this embodiment, the first bit width can be either a low bit width or a high bit width. The low bit width is relative to the high bit width, and vice versa. For example, in practical applications, a bit width greater than or equal to 32 bits can be called a high bit width, and a bit width less than 32 bits can be called a low bit width. This embodiment does not specifically limit this. The two cases will be described below.

[0100] The first scenario: Both the first and second bit widths are low bit widths.

[0101] Among them, the first operand, the second operand, and the first target data are low-bit-width data, that is, the first operand, the second operand, and the first target data are low-precision data, such as FP16 data, BF16 data, or FP8 data.

[0102] At this time, both the first and second operands in the target instruction are low-bit-width (i.e., low-precision) data, and the first target data output by the processor after executing the target instruction is also low-bit-width (i.e., low-precision) data. For example, referring to Figures 5 and 6, the method provided in this embodiment further includes: the processor performing a data precision conversion operation on the high-bit-width first target data to obtain the low-bit-width second target data.

[0103] Furthermore, in step S203, storing the obtained first target data in the second register includes storing the second target data in the second register.

[0104] The second scenario: Both the first and second bit widths are high bit widths.

[0105] Among them, the first operand, the second operand, and the first target data are high-bit-width data, that is, the first operand, the second operand, and the first target data are high-precision data, such as FP32 data or FP64 data, etc.

[0106] At this point, both the first and second operands in the target instruction are high-bit-width (i.e., high-precision) data, and the first target data output by the processor after executing the target instruction is also high-bit-width (i.e., high-precision) data.

[0107] In the above possible embodiments, the target instruction can support input data (including the first operand and the second operand) and output data (including the first target data) with different bit widths (i.e. precision), thus expanding the scope of application of the target instruction; and the target instruction supports data precision conversion operations and at least one arithmetic operation, thereby improving computational efficiency without changing the hardware.

[0108] In one possible embodiment, the target instruction is adapted to single instruction multiple data (SIMD) and single instruction multiple threads (SIMT) computing scenarios.

[0109] Since the first register may include the first vector register and the second vector register, the following describes the specific process by which the processor processes the first operand and the second operand when the first register includes the first vector register and the second vector register, with reference to Figure 7.

[0110] For example, as shown in Figure 7, the processor includes a register set and multiple arithmetic and logic units (ALUs). The register set includes multiple first registers and multiple second registers. Any two registers in the register set have the same bit width; for example, any register in the register set can be a 32-bit register or a 64-bit register. The multiple arithmetic and logic units can include four ALUs, which can be represented as ALU1 to ALU4. Figure 7 illustrates only a portion of the processor's structure, using an example of multiple first registers comprising eight registers, which can be represented as R1 to R8, and multiple second registers comprising four registers, which can be represented as R9 to R12, with any register in the register set being a 32-bit register.

[0111] The first vector register can be any one of registers R1 to R8, for example, register R1; the second vector register can be any one of registers R1 to R8 except register R1, for example, register R5; the second register can be any one of registers R9 to R12, for example, register R9. The following explanation uses register R1 as the first vector register, register R5 as the second vector register, and register R9 as the second vector register as an example.

[0112] Assuming both the first and second operands are FP16 data, and the first target data is FP32 data (i.e., the first and second operands are low-bit-width (i.e., low-precision) data, and the first target data is high-bit-width (i.e., high-precision) data), the processor's control unit retrieves the first and second operands from memory during attention mechanism calculations and stores them in the first vector register (i.e., register R1) and the second vector register (i.e., register R5), respectively. Further, during attention weight calculations, the control unit retrieves the target instruction, obtains the first and second operands from the first vector register (i.e., register R1) and the second vector register (i.e., register R5), and sends them to ALU1 through ALU4. ALU1 through ALU4 execute at least two arithmetic operations corresponding to the target instruction based on the first and second operands. Specifically, ALU1 through ALU4 calculates the attention weights on the first and second operands to obtain the first target data and stores it in the second register (i.e., register R9).

[0113] Optionally, the control unit can store the first operand in bits 0 to 15 (the lower 1 / 2 bits) of the first vector register (i.e., register R1), or it can store the first operand in bits 16 to 31 (the higher 1 / 2 bits) of the first vector register (i.e., register R1). When the first operand is stored in bits 0 to 15 of the first vector register (i.e., register R1), the control unit stores the second operand in bits 0 to 15 of the second vector register (i.e., register R5); when the first operand is stored in bits 16 to 31 of the first vector register (i.e., register R1), the control unit stores the second operand in bits 16 to 31 of the second vector register (i.e., register R5). This ensures that the storage location of the first operand in the first vector register (i.e., register R1) and the storage location of the second operand in register R5 are the same, reducing the design complexity of the target instruction and improving execution efficiency.

[0114] In one possible embodiment, when both the first operand and the second operand are FP8 data, the control unit can be used to store the first operand at any 1 / 4 bit location in the first vector register (i.e., register R1). Similarly, the control unit can be used to store the second operand at any 1 / 4 bit location in the second vector register (i.e., register R5), where the storage location of the first operand in the first vector register (i.e., register R1) is the same as the storage location of the second operand in the second vector register (i.e., register R5).

[0115] In one possible embodiment, referring to Figure 7 and Figure 8, Figure 8 uses FP32 data for both the first operand and the second operand, and FP16 data for the first target data. That is, the first operand and the second operand are high-bit-width (i.e., high-precision) data, and the first target data is low-bit-width (i.e., low-precision) data.

[0116] In one possible embodiment, when at least one operand includes a first operand, the process by which the processor performs at least two arithmetic operations corresponding to the target instruction based on the first operand is similar to the process described above of the processor performing at least two arithmetic operations corresponding to the target instruction based on the first operand and the second operand, and will not be repeated here.

[0117] In one possible embodiment, the first register includes a first vector register and a second vector register, which are collectively referred to as vector registers. When the first operand is src0 and the second operand is src1, the first vector register can be represented as Vsrc0, the second vector register can be represented as Vsrc1, and the second register can be represented as Vdst0. The target instruction format is as follows:

[0118] First format: >VOP.dtype,Vdst0,Vsrc0,Vsrc1,p,#part / / Vdst0,Vsrc0 and Vsrc1 are vector registers, p is the prediction register>vexpdif.f32,V2,V0,V1,p,#0 -v2=exp(v0–v1) / / v0,v1,v2 are all FP32 data types>vexpdif.f16,V2,V0,V1,p,#0 -v2=exp((float)(v0–v1)) / / v0,v1 are FP16 data types, v2 is FP32 data type

[0119] The pre-stored register is used to store first indication information and second indication information. The first indication information is used to indicate whether the first operand stored in the first vector register is used for calculation, and the second indication information is used to indicate whether the data stored in the second vector register is used for calculation.

[0120] In this embodiment, the first operand and the second operand are FP16 data, and the first target data is FP32 data, as an example.

[0121] In one possible embodiment, the first register includes a first vector register (referred to as the vector register) and a scalar register. When the first operand is src0 and the second operand is src1, the first vector register can be represented as Vsrc0, the scalar register can be represented as Sreg, and the second register can be represented as Vdst0. The target instruction format is as follows:

[0122] >VOP.dtype,Vdst0,Vsrc0,Sreg,p,#part / / Vdst0 and Vsrc0 are vector registers, Sreg is a scalar register, and p is a prediction register

[0123] >vmulscvt v2,v0,s0,p,#0

[0124] -v2 = (float16)v0 * s0 / / v0 and s0 are FP32 data types, v2 is a float16 data type

[0125] In this embodiment, the first operand and the second operand are FP32 data, and the first target data is float16 data, as an example.

[0126] In this embodiment, the target instruction includes a data precision conversion operation and at least one arithmetic operation. The processor executes at least two arithmetic operations corresponding to the target instruction based on at least one operand. That is, the processor calculates attention weights for at least one operand by executing the target instruction. The performance of the target instruction is equivalent to the performance of multiple general instructions. For example, the performance of the target instruction is equivalent to the performance of 2-4 general instructions. By executing the target instruction, the performance of multiple general instructions can be achieved. Compared with executing multiple general instructions, executing the target instruction shortens the instruction execution time and improves computational efficiency. For example, it can improve computational efficiency by 25%, thereby improving the performance of the Transformer model. For example, it can improve the performance gain of the Transformer model by 25%, enabling the Transformer model to be applied to high-performance scenarios, such as the AI ​​transformer model, for hardware acceleration of training and inference of the AI ​​transformer model.

[0127] The foregoing mainly describes the solutions provided by the embodiments of this application from the perspective of an instruction execution device. It is understood that, in order to achieve the above functions, the instruction execution device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0128] This application embodiment can divide the instruction execution device into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0129] In the case of using integrated units, Figure 9 shows a schematic diagram of the structure of an instruction execution device involved in the above embodiments. This instruction execution device may include: an acquisition unit 901 and an execution unit 902. The acquisition unit 901 is used to support the device in executing S201 and S202 in the above method embodiments, and / or other steps in the embodiments of this application; the execution unit 902 is used to support the device in executing S203 in the above method embodiments, and / or other steps in the embodiments of this application. All relevant content of each step involved in the above method embodiments can be referred to in the functional description of the corresponding functional module, and will not be repeated here.

[0130] In another embodiment of this application, an electronic device is also provided, which includes a processor and a memory; wherein the processor is used to perform the steps in the method embodiments provided above.

[0131] It is understood that all relevant content of each step involved in the above method embodiments can be referenced in the embodiments of the electronic device, and the embodiments of this application will not be repeated here.

[0132] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0133] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0135] In another embodiment of this application, a readable storage medium is also provided, which stores computer-executable instructions. When a device (which may be a microcontroller, chip, etc.) or a processor executes the computer-executable instructions, the device performs the steps in the above method embodiments.

[0136] In another embodiment of this application, a computer program product is also provided, the computer program product including computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and the at least one processor executes the computer instructions to cause the device to perform the steps in the above method embodiments.

[0137] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for executing instructions, characterized in that, Applied in an instruction execution device, the method includes: Obtain a target instruction, the target instruction including instruction information, the instruction information being used to indicate: at least two arithmetic operations, a first register and a second register; wherein, the first register is used to store at least one operand; Obtain the at least one operand from the first register; The at least two arithmetic operations corresponding to the target instruction are executed according to the at least one operand, and the resulting first target data is stored in the second register; wherein the at least two arithmetic operations include a data precision conversion operation and at least one arithmetic operation, and the bit width of each operand in the at least one operand is different from the bit width of the first target data.

2. The method according to claim 1, characterized in that, Each of the at least one operands is a first bit width, the first target data is a second bit width, and the first bit width is greater than the second bit width; The step of performing the at least two arithmetic operations corresponding to the target instruction based on the at least one operand includes: Perform a first operation with a first bit width on the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain first converted data; The first converted data is subjected to a second operation with the second bit width to obtain the first target data.

3. The method according to claim 1, characterized in that, Each of the at least one operands is a first bit width, the first target data is a second bit width, and the first bit width is smaller than the second bit width; The step of performing the at least two arithmetic operations corresponding to the target instruction based on the at least one operand includes: Perform a data precision conversion operation on the at least one operand, and then perform a second operation with a second bit width on the converted at least one operand to obtain the first target data.

4. The method according to claim 1, characterized in that, Each of the at least one operands is a first bit width, the first target data is a second bit width, and the first bit width is smaller than the second bit width; The step of performing the at least two arithmetic operations corresponding to the target instruction based on the at least one operand includes: Perform a first operation with a first bit width on the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain second converted data; The second converted data is subjected to a second operation with a second bit width to obtain the first target data.

5. The method according to claim 3, characterized in that, The method further includes: The first target data is converted to a higher precision to obtain the second target data; The step of storing the obtained first target data in the second register includes: storing the second target data in the second register.

6. The method according to any one of claims 1-5, characterized in that, The at least one operand is an integer type or a floating-point type.

7. The method according to any one of claims 1-6, characterized in that, The at least one operand includes a first operand and a second operand, wherein the first operand is a vector and the second operand is a vector or a scalar.

8. The method according to claim 7, characterized in that, The first register includes a first vector register and a second vector register, and the storage location of the first operand in the first vector register is the same as the storage location of the second operand in the second vector register.

9. The method according to any one of claims 1-8, characterized in that, The target instruction is applicable to computational scenarios of Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT).

10. The method according to any one of claims 1-9, characterized in that, The at least one arithmetic operation includes at least one of the following: subtraction, exponentiation, multiplication, addition, or data type conversion.

11. An instruction execution device, characterized in that, The device includes: An acquisition unit is used to acquire a target instruction, the target instruction including instruction information, the instruction information indicating: at least two arithmetic operations, a first register and a second register; wherein, the first register is used to store a first operand and a second operand; The acquisition unit is further configured to acquire the at least one operand from the first register; An execution unit is configured to execute at least two arithmetic operations corresponding to the target instruction according to the at least one operand, and store the resulting first target data in the second register; wherein the at least two arithmetic operations include a data precision conversion operation and at least one arithmetic operation, and the bit width of each operand in the at least one operand is different from the bit width of the first target data.

12. The apparatus according to claim 11, characterized in that, Each of the at least one operand is a first bit width, the first target data is a second bit width, and the first bit width is greater than the second bit width; the execution unit is further configured to: Perform a first operation with a first bit width on the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain first converted data; The first converted data is subjected to a second operation with the second bit width to obtain the first target data.

13. The apparatus according to claim 11, characterized in that, Each of the at least one operand is a first bit width, the first target data is a second bit width, and the first bit width is smaller than the second bit width; the execution unit is further configured to: Perform a data precision conversion operation on the at least one operand, and then perform a second operation with a second bit width on the converted at least one operand to obtain the first target data.

14. The apparatus according to claim 11, characterized in that, Each of the at least one operand is a first bit width, the first target data is a second bit width, and the first bit width is smaller than the second bit width; the execution unit is further configured to: Perform a first operation with a first bit width on the at least one operand, and perform a data precision conversion operation on the obtained operation result to obtain second converted data; The second converted data is subjected to a second operation with a second bit width to obtain the first target data.

15. The apparatus according to claim 13, characterized in that, The execution unit is also used for: The first target data is converted to a higher precision to obtain the second target data; The second target data is stored in the second register.

16. The apparatus according to any one of claims 11-15, characterized in that, The at least one operand is an integer type or a floating-point type.

17. The apparatus according to any one of claims 11-16, characterized in that, The at least one operand includes a first operand and a second operand, wherein the first operand is a vector and the second operand is a vector or a scalar.

18. The apparatus according to claim 17, characterized in that, The first register includes a first vector register and a second vector register, wherein the storage location of the first operand in the first vector register is the same as the storage location of the second operand in the second vector register.

19. The apparatus according to any one of claims 11-18, characterized in that, The target instruction is applicable to computational scenarios of Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Thread (SIMT).

20. The apparatus according to any one of claims 11-19, characterized in that, The at least one arithmetic operation includes at least one of the following: subtraction, exponentiation, multiplication, addition, or data type conversion.

21. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory being used to store data, and the processor being used to execute the instruction execution method as described in any one of claims 1-10.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on the device, cause the device to perform the instruction execution method as described in any one of claims 1-10.

23. A computer program product, characterized in that, The computer program product includes a computer program that, when run on a device, causes the device to perform the instruction execution method as described in any one of claims 1-10.

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