Cell, module, and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of photovoltaics. Provided are a cell, a module, and a photovoltaic system. The cell comprises: a silicon substrate, which comprises a first region and a second region, wherein a P-type polycrystalline silicon layer comprising several P-type grains is disposed in the first region, and an N-type polycrystalline silicon layer comprising several N-type grains is disposed in the second region. Separation and collection of holes and electrons are facilitated, and the transport efficiency of the cell is improved.

Description

Batteries, modules and photovoltaic systems

[0001] Priority information

[0002] This disclosure claims priority to Chinese patent application No. 202510238735.6, filed on February 28, 2025, with the China National Intellectual Property Administration, entitled “A Solar Cell, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure pertains to the field of photovoltaic technology, and particularly relates to a solar cell, a solar module, and a photovoltaic system. Background Technology

[0004] Solar energy, as one of the most abundant renewable energy sources, has enormous development potential and application prospects. Solar cells are the core components that directly convert solar energy into electrical energy and are a key technology for achieving efficient solar energy utilization. Photovoltaic conversion efficiency (PDE) refers to the proportion of incident light energy converted into electrical energy by a solar cell, and is a core indicator for measuring solar cell performance. Improving PEE can increase the electrical output per unit area and reduce power generation costs.

[0005] Currently, the photoelectric conversion efficiency (PCE) of commercial silicon-based solar cells is approximately 20%–25%. Improving the PCE is a crucial aspect of solar cell research and development. Increasing PCE can increase the energy output per unit area, reduce power generation costs, shorten the investment payback period, enhance market competitiveness, and drive the rapid development of the photovoltaic industry. Therefore, improving the PCE of solar cells is not only of significant economic, environmental, and technological importance, but also key to promoting the sustainable development of the photovoltaic industry. Summary of the Invention

[0006] This disclosure provides a solar cell designed to improve the photoelectric conversion efficiency of solar cells and solve the problem of low photoelectric conversion efficiency.

[0007] This disclosure is implemented as follows: a solar cell includes:

[0008] A silicon substrate, comprising a first region and a second region, wherein a P-type polycrystalline silicon layer is disposed in the first region and an N-type polycrystalline silicon layer is disposed in the second region;

[0009] The P-type polycrystalline silicon layer includes a number of P-type grains, and the N-type polycrystalline silicon layer includes a number of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region.

[0010] Optionally, the silicon substrate has a light-facing surface and a back-light-facing surface disposed opposite to each other, with both the first region and the second region located on the back-light-facing surface.

[0011] Optionally, the total perimeter of P-type grains per unit area is greater than the total perimeter of N-type grains per unit area.

[0012] Optionally, at least one area in the first and second regions is velvet.

[0013] Optionally, both the first and second areas can be made of velvet.

[0014] Optionally, both the first and second regions are polished surfaces.

[0015] Optionally, the roughness of the P-type polycrystalline silicon layer is less than that of the N-type polycrystalline silicon layer.

[0016] This disclosure also provides a battery assembly including the solar cell described above.

[0017] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0018] The beneficial effects achieved by this disclosure are due to the presence of a first region and a second region on a silicon substrate. The first region contains a P-type polycrystalline silicon layer comprising a plurality of P-type grains; the second region contains an N-type polycrystalline silicon layer comprising a plurality of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region. This facilitates the separation and collection of holes and electrons, improves the solar cell's transport efficiency, reduces carrier recombination, increases the short-circuit current of the solar cell, optimizes the cell's response to the entire solar spectrum, and thus enhances the solar cell's photoelectric conversion efficiency. Attached Figure Description

[0019] Figure 1 is a magnified schematic diagram of a textured P-type polycrystalline silicon layer with a 200K surface provided in an embodiment of this disclosure from a first-view perspective.

[0020] Figure 2 is a magnified schematic diagram of a textured N-type polycrystalline silicon layer with a surface of 200K provided in an embodiment of this disclosure from a first-view perspective.

[0021] Figure 3 is a magnified first-view schematic diagram of the 200K P-type polysilicon layer on the polished surface provided in the embodiment of this disclosure;

[0022] Figure 4 is a magnified first-view schematic diagram of the polished surface of the 200K N-type polysilicon layer on the present disclosure embodiment;

[0023] Figure 5 is a magnified schematic diagram of the 200K P-type polysilicon layer on the polished surface provided in the embodiments of this disclosure from a second viewing angle.

[0024] Figure 6 is a magnified schematic diagram of the polished surface of the N-type polysilicon layer 200K from a second viewing angle according to an embodiment of the present disclosure.

[0025] Explanation of reference numerals in the attached figures: 101, P-type grain; 102, first grain boundary; 201, N-type grain; 202, second grain boundary; 30, protrusion; 40, depression. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0027] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0030] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0031] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0032] This disclosure involves forming a first region and a second region on a silicon substrate. The first region contains a P-type polycrystalline silicon layer comprising a plurality of P-type grains; the second region contains an N-type polycrystalline silicon layer comprising a plurality of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region. This facilitates the separation and collection of holes and electrons, improving the solar cell's transport efficiency, reducing carrier recombination, increasing the short-circuit current of the solar cell, optimizing the cell's response to the entire solar spectrum, and ultimately enhancing the solar cell's photoelectric conversion efficiency.

[0033] Example

[0034] As shown in Figures 1 to 4, this embodiment provides a solar cell, including:

[0035] A silicon substrate, comprising a first region and a second region, wherein a P-type polycrystalline silicon layer is disposed in the first region and an N-type polycrystalline silicon layer is disposed in the second region;

[0036] The P-type polysilicon layer includes a number of P-type grains 101, and the N-type polysilicon layer includes a number of N-type grains 201. The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region.

[0037] Two distinct regions, a first region and a second region, are arranged on a silicon substrate. The first and second regions can be located on the same surface of the silicon substrate or on two opposite surfaces; this is not a limitation. A P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region. The P-type and N-type polysilicon layers form regions with different electrical characteristics, supporting the formation of a PN junction and the separation of charge carriers.

[0038] The P-type polycrystalline silicon layer can cover the entire first region or only a portion of it. P-type polycrystalline silicon is a polycrystalline silicon material that has undergone specific doping treatment. The doping elements are usually elements that can provide holes (equivalent to positive charge carriers), such as boron (B).

[0039] The P-type polycrystalline silicon layer is composed of several P-type grains 101. A grain is the basic unit in the microstructure of polycrystalline silicon. The atomic arrangement within each P-type grain 101 follows a certain regularity, but the orientations of different grains may differ, resulting in different shapes and sizes for each P-type grain 101. The shape of the P-type grain 101 can be approximately square, triangular, trapezoidal, other polygonal, or irregular, and is not limited here. In the first region, these P-type grains 101 are distributed throughout the entire P-type polycrystalline silicon layer.

[0040] The N-type polysilicon layer can cover the entire second region or only a portion of it. N-type polysilicon is formed by doping with elements that can donate electrons (negative charge carriers), such as phosphorus (P).

[0041] The N-type polysilicon layer is also composed of several N-type grains 201. Similar to the P-type grains 101, the atoms inside the N-type grains 201 are arranged in a regular pattern, but the orientation between grains differs, resulting in each N-type grain 201 having a different shape and size. The shape of the N-type grains 201 can be approximately square, triangular, trapezoidal, other polygonal, or irregular, and is not limited here. In the second region, these N-type grains 201 are distributed throughout the entire N-type polysilicon layer.

[0042] The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. The unit area is a predefined specific region, the side length, area and shape of which are fixed. The specific shape of the specific region can be square, circular or other shapes, which are not limited here.

[0043] When the specific region is set in the first region, the specific region can be set at any position in the first region, and the number of P-type grains 101 falling into the specific region is a; when the specific region is set in the second region, the specific region can be set at any position in the second region, and the number of N-type grains 201 falling into the specific region is b, where a > b.

[0044] The number of P-type grains 101 per unit area is greater than the number of N-type grains 201, which means that the average area of ​​the P-type grains 101 is smaller than the average area of ​​the N-type grains 201. This is because, within the same area, if the number of a certain type of grain is small, then the area occupied by each grain is relatively large. For example, if there are more P-type grains 101 in a unit area, then the average area occupied by each P-type grain 101 will be smaller than the average area of ​​the smaller number of N-type grains 201.

[0045] Understandably, although the average area of ​​P-type grains 101 is smaller than the average area of ​​N-type grains 201, this does not preclude the possibility that one or more P-type grains 101 in the first region have an area larger than any N-type grain 201 in the second region. These larger P-type grains 101 may be due to local conditions during material growth, inhomogeneity of doping distribution, or other factors. The average area is a statistical value that reflects an overall trend, not the specific situation of each individual grain. In actual materials, grain size may have a certain distribution range; some P-type grains 101 may be larger, while some N-type grains 201 may be smaller.

[0046] On one hand, when a solar cell is exposed to sunlight, the silicon substrate absorbs photon energy, generating electron-hole pairs. In this structure of polycrystalline silicon layers with different doping types, the P-type polycrystalline silicon layer is rich in holes, while the N-type polycrystalline silicon layer is rich in electrons. The main function of the P-type polycrystalline silicon layer is to transport holes. More P-type grains can provide more transport channels, allowing holes to move more efficiently to the corresponding electrodes of the cell. Because hole migration within each grain is relatively smooth, the network structure formed by numerous grains can reduce obstacles in the hole transport process, lower the probability of hole recombination, and improve hole collection efficiency. Since the P-type region generates more photogenerated carriers, these carriers diffuse into the N-type region under the influence of the PN junction. At this point, although the number of grains per unit area in the N-type region is relatively small, it can form a good match with the carriers generated in the P-type region. The N-type region has sufficient space and capacity to receive electrons diffused from the P-type region. Its synergistic effect with the N-type region avoids the increase in recombination caused by excessive concentration of charge carriers, thus ensuring the effective separation and transport of charge carriers.

[0047] On the other hand, the greater number of P-type grains in the P-type polycrystalline silicon layer means there are more grain interfaces. These interfaces can serve as effective areas for light absorption. When light shines on the solar cell, more P-type grains can interact with the light, increasing the probability of light absorption. Absorbed light excites more electron-hole pairs, i.e., photogenerated carriers, thereby improving the efficiency of photogenerated carrier generation. The numerous P-type grains form a complex microstructure, and light undergoes multiple scatterings between these grains. The scattered light has a longer propagation path inside the cell, increasing its chances of absorption and further enhancing the amount of light absorbed, thus increasing the generation of photogenerated carriers.

[0048] On the other hand, P-type and N-type polycrystalline silicon layers exhibit different absorption and response characteristics to different wavelengths of light due to their different doping types and microstructures. The varying number of grains per unit area in the first and second regions allows solar cells to achieve effective light absorption and carrier generation over a wider spectral range. For example, P-type polycrystalline silicon layers may have an advantage in absorbing certain specific wavelengths of light, while N-type polycrystalline silicon layers perform better in absorbing other wavelengths. By rationally setting the number of grains per unit area, the cell's response to the entire solar spectrum can be optimized, improving the cell's power generation capacity under different illumination conditions.

[0049] In this embodiment, a first region and a second region are respectively formed on a silicon substrate. A P-type polycrystalline silicon layer, comprising a plurality of P-type grains 101, is formed in the first region. An N-type polycrystalline silicon layer, comprising a plurality of N-type grains 201, is formed in the second region. The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. This facilitates the separation and collection of holes and electrons, improves the solar cell's transmission efficiency, reduces carrier recombination, increases the short-circuit current of the solar cell, optimizes the cell's response to the entire solar spectrum, and thus improves the solar cell's photoelectric conversion efficiency.

[0050] In some embodiments, the silicon substrate has a light-facing surface and a back-light-facing surface disposed opposite to each other, with both the first region and the second region located on the back-light-facing surface.

[0051] The silicon substrate has two main surfaces: a light-facing surface and a back-lighting surface. The light-facing surface faces the sunlight directly and is directly exposed to light, while the back-lighting surface is on the other side, and the two surfaces are arranged opposite each other.

[0052] Both the first and second regions are disposed on the backlight surface, meaning that both the P-type and N-type polycrystalline silicon layers are disposed on the backlight surface, and the first and second regions are typically arranged alternately. Specifically, a plurality of first regions and a plurality of second regions can be arranged alternately along a first direction, and both the first and second regions extend along a second direction, which intersects the first direction. The first and second regions can be arranged alternately along the lateral direction of the silicon substrate and both extend along the longitudinal direction; that is, the first direction can be the lateral direction of the back contact cell, and the second direction can be the longitudinal direction of the back contact cell, and the two are perpendicular to each other. Of course, in other embodiments, the first and second directions can also be other directions, for example, they can be the diagonal directions of the silicon substrate, and no specific limitation is made here.

[0053] In this embodiment, a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer are disposed on the backlight surface. The polycrystalline silicon layer on the backlight surface can effectively collect and transport charge carriers, while reducing the reflection loss of photons on the backlight surface. This can optimize the collection and transport of charge carriers and improve the photoelectric conversion efficiency of the solar cell.

[0054] In some embodiments, the total perimeter of P-type grains 101 per unit area is greater than the total perimeter of N-type grains 201 per unit area.

[0055] Perimeter refers to the total length of the boundary lines of a geometric shape. For a grain, perimeter refers to the total length of the grain boundary. Total perimeter is the sum of the perimeters of all individual grains within a unit area.

[0056] The total perimeter of a grain per unit area is mainly affected by two factors: the number of grains, the more grains per unit area, the larger the total perimeter is usually; and the ruggedness of the grain boundaries, the more rugged the grain boundaries (i.e. the more complex the shape), the larger the perimeter of a single grain, and thus the larger the total perimeter.

[0057] Specific examples illustrate the impact of grain number and grain boundary roughness on the total perimeter of grains per unit area:

[0058] Example 1: Assume a unit area of ​​1 square centimeter, with 20 first grains set within the unit area, each grain having a smooth and flat boundary, and a perimeter of 0.1 centimeters for each grain. Then the total perimeter is: 20 × 0.1 = 2 centimeters.

[0059] Ten second grains are set within a unit area. The boundaries of each grain are very rugged. The perimeter of a single grain is 0.2 cm. Therefore, the total perimeter is: 10 × 0.2 = 2 cm.

[0060] The second grain is fewer in number but has rugged boundaries, with a total perimeter of 2 cm. The first grain is more numerous but has smooth boundaries, with a total perimeter of 2 cm as well. In this example, although the second grain is fewer in number than the first grain, the rugged boundaries of the second grain result in a larger perimeter for each individual grain, ultimately making their total perimeters equal.

[0061] Second example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 centimeters. Then the total perimeter is: 20 × 0.1 = 2 centimeters.

[0062] Ten second grains are set within a unit area. The boundaries of each grain are very rugged. The perimeter of a single grain is 0.3 cm. Therefore, the total perimeter is: 10 × 0.3 = 3 cm.

[0063] The second grain is fewer in number but has rugged boundaries, with a total perimeter of 3 cm. The first grain is more numerous but has smooth boundaries, with a total perimeter of 2 cm, which is greater than the total perimeter of the second grain per unit area. In this example, the total perimeter of the second grain is greater than that of the first grain. Although the second grain is fewer in number, the ruggedness of its boundaries significantly increases the perimeter of each individual grain, resulting in a larger total perimeter.

[0064] Third example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 centimeters. Then the total perimeter is: 20 × 0.1 = 2 centimeters.

[0065] Ten second grains are set within a unit area. The boundaries of each grain are rugged, and the perimeter of a single grain is 0.15 cm. Therefore, the total perimeter is: 10 × 0.15 = 1.5 cm.

[0066] The second grain is fewer in number but has rugged boundaries, with a total perimeter of 1.5 cm. The first grain is more numerous but has smooth boundaries, with a total perimeter of 2 cm. The second grain is fewer in number than the first grain, and the ruggedness of the second grain's boundaries is greater than that of the first grain. However, the impact of the ruggedness of the second grain on the increase in total perimeter is less than the impact of the number of first grains on the increase in total perimeter, resulting in the total perimeter of the second grain being smaller than that of the first grain. In other words, the total perimeter of the first grain is greater than that of the second grain.

[0067] Fourth example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The roughness of the boundary of each grain is similar to that of the second grain. The perimeter of a single grain is also 0.2 centimeters. Then the total perimeter is: 20 × 0.2 = 4 centimeters.

[0068] If 10 second grains are set within a unit area, and the perimeter of a single grain is 0.2 cm, then the total perimeter is: 10 × 0.2 = 2 cm.

[0069] The number of second grains is less than that of the first grains, and the roughness of the boundaries of the second grains is similar to that of the first grains. Each individual grain has the same perimeter, resulting in the total perimeter of the second grains being less than that of the first grains. It is understandable that when the roughness of the second grains is less than that of the first grains, the total perimeter of the second grains is also less than that of the first grains; that is, the total perimeter of the first grains is greater than that of the second grains.

[0070] In this embodiment, the total perimeter of the P-type grains 101 per unit area is greater than the total perimeter of the second grains per unit area. This can be similar to the third example or the fourth example. A smaller total perimeter indicates that the P-type grains 101 have more boundaries, that is, the N-type grains 201 have fewer boundaries. This can reduce carrier recombination at grain boundaries, which is beneficial to improving carrier transport efficiency and thus improving the photoelectric conversion efficiency of the solar cell.

[0071] As shown in Figures 5 and 6, in some embodiments, the number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region.

[0072] A protrusion is a portion of a P-type grain 101 or N-type grain 201 that is higher in height than the reference plane relative to the reference plane. For a P-type polysilicon layer, the reference plane usually refers to the plane in which most of the P-type polysilicon layer is located in the first region; for an N-type polysilicon layer, the reference plane usually refers to the plane in which most of the N-type polysilicon layer is located in the second region.

[0073] In the first region, P-type grains 101 protrude from the reference surface of the first region at multiple locations. Specifically, one P-type grain 101 may be set at each of the multiple locations, multiple adjacent P-type grains 101 may be set at each of the multiple locations, or one P-type grain 101 may be set at some of the multiple locations, and multiple adjacent P-type grains 101 may be set at other locations.

[0074] Similarly, in the second region, N-type grains 201 protrude from the reference surface of the second region at multiple locations. Specifically, one N-type grain 201 protruding from the reference surface of the second region can be set at each of the multiple locations, multiple adjacent N-type grains 201 protruding from the reference surface of the second region can be set at each of the multiple locations, or one N-type grain 201 protruding from the reference surface of the second region can be set at some of the multiple locations, while multiple adjacent N-type grains 201 protruding from the reference surface of the second region can be set at other locations.

[0075] The number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region. The unit area is a pre-defined specific region, the side length, area and shape of which are fixed. The specific shape of the specific region can be square, circular or other shapes, which are not limited here.

[0076] When the specific region is set in the first region, the specific region can be set at any position in the first region, and the number of P-type grains 101 protruding in the specific region is a; when the specific region is set in the second region, the specific region can be set at any position in the second region, and the number of N-type grains 201 protruding in the specific region is b, where a < b.

[0077] The P-type polysilicon layer is primarily responsible for hole transport, while the N-type polysilicon layer is primarily responsible for electron transport. Protruding grains increase the effective surface area, thus affecting carrier transport and recombination. In the first region, the P-type grains 101 have fewer protrusions, which reduces surface defects and carrier recombination, improving hole transport efficiency. Protruding grains can also increase light scattering and absorption, reducing light reflection losses.

[0078] In this embodiment, a first region and a second region are respectively formed on a silicon substrate. A P-type polycrystalline silicon layer is formed in the first region, and the P-type polycrystalline silicon layer includes a plurality of P-type grains 101. An N-type polycrystalline silicon layer is formed in the second region, and the N-type polycrystalline silicon layer includes a plurality of N-type grains 201. The number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region. This ensures that the hole transport efficiency is higher in the first region and the electron collection efficiency is higher in the second region. By increasing light absorption and reducing carrier recombination, the photoelectric conversion efficiency of the solar cell is significantly improved.

[0079] In some embodiments, the height of the P-type grain 101 protrusion is less than the height of the N-type grain 201 protrusion.

[0080] The fact that the protrusion height of P-type grain 101 is less than that of N-type grain 201 describes the average state; that is, the average protrusion height of P-type grain 101 per unit area is less than the average protrusion height of N-type grain 201 per unit area. There may be individual P-type grains 101 with a protrusion height greater than that of N-type grains 201, but their impact on the average trend is weak and will not be discussed separately.

[0081] Understandably, the protrusion height of the P-type grain 101 refers to the distance between the highest point of the protrusion of the P-type grain 101 and the reference plane of the first region. The protrusion height of the N-type grain 201 refers to the distance between the highest point of the protrusion of the N-type grain 201 and the reference plane of the second region.

[0082] On one hand, the higher protrusion of the N-type grain 201 allows for better light scattering. When light shines on the battery surface, the higher N-type grain 201 causes multiple scatterings of the light on its surface, lengthening the light's propagation path inside the battery. This increases the chance of light being absorbed by the P-type semiconductor, which is primarily responsible for absorbing photons and generating electron-hole pairs. The lower protrusion of the P-type grain 101, however, does not excessively obstruct light propagation, ensuring that light can effectively reach the P-type region for photoelectric conversion. The higher N-type grain 201 can also change the incident angle of light, allowing more light to enter the battery instead of being reflected, thereby improving light utilization.

[0083] On the other hand, electrons and holes generated under illumination need to be effectively separated and collected. A taller N-type grain 201 provides a larger surface area, which is beneficial for rapid electron collection. As the majority carrier in an N-type semiconductor, electrons can reach the electrode more quickly through the N-type grain 201. A lower P-type grain 101 reduces the probability of hole recombination during transport, because holes are easily lost due to recombination with electrons if they pass through too many interfaces and obstacles during transport in a P-type semiconductor. A lower P-type grain 101 allows holes to transport more smoothly to the electrode, thereby improving carrier collection efficiency.

[0084] In this embodiment, the height of the P-type grain 101 protrusion is smaller than the height of the N-type grain 201, which can optimize the carrier transport and collection efficiency.

[0085] In some embodiments, the height of the P-type grain 101 protrusion is 1-10 nm.

[0086] The specific height value can precisely control the carrier transport path and recombination rate, further optimizing battery performance. For example, P-type grains 101 with a height of 1-10 nm can reduce surface recombination and improve carrier lifetime.

[0087] In some embodiments, the height of the protrusion of the N-type grain 201 is 1-15 nm.

[0088] The specific height value can precisely control the electron collection efficiency, further optimizing battery performance. For example, N-type 201 with a height of 1-15nm can enhance electron collection and increase the battery's short-circuit current.

[0089] In some embodiments, the thickness of the grain is at least one of the following: the thickness of a single P-type grain 101 is not uniform, and the thickness of a single N-type grain 201 is not uniform.

[0090] Specifically, it could be that at least one P-type grain 101 has a non-uniform thickness while all N-type grains 201 have a uniform thickness; or it could be that at least one N-type grain 201 has a non-uniform thickness while all P-type grains 101 have a uniform thickness; or it could be that at least one P-type grain 101 has a non-uniform thickness and at least one N-type grain 201 has a non-uniform thickness.

[0091] Non-uniform thickness of a single grain refers to the difference in thickness at different locations within the area occupied by each grain. Specifically, the grain thickness refers to the vertical distance between the top surface of the grain and the reference plane (i.e., the plane in which most of the P-type or N-type polysilicon layer is located).

[0092] Within a single grain, the thickness may be greater in one region and thinner in another. This thickness inhomogeneity can be a continuous gradual change or an abrupt, step-like variation.

[0093] Non-uniform grain thickness can optimize carrier transport paths and recombination rates. Thicker regions enhance carrier collection efficiency, while thinner regions reduce carrier recombination, thereby improving overall cell performance. Simultaneously, non-uniform grain thickness can increase light scattering and absorption, reducing light reflection losses. Thicker regions can utilize incident light more effectively, improving photoelectric conversion efficiency.

[0094] In this embodiment, the grain thickness is at least one of the following: the thickness of a single P-type grain 101 is non-uniform, and the thickness of a single N-type grain 201 is non-uniform. This is beneficial for improving carrier collection efficiency and reducing carrier recombination.

[0095] As shown in Figures 1 to 4, in some embodiments, the undulation of the P-type grain 101 is greater than that of the N-type grain 201.

[0096] The surface morphologies of P-type grain 101 and N-type grain 201 are different, with the undulation of P-type grain 101 being greater than that of N-type grain 201.

[0097] Undulation refers to the degree of elevation difference of a material surface relative to a reference plane, reflecting the complexity and irregularity of the material's surface morphology. Specifically, unevenness can be quantified by measuring the height difference between various points on the surface relative to the reference plane. The reference plane is a pre-defined reference plane, which can be an idealized, perfectly flat reference plane, or a plane approximated by most of the material surface. Undulation is measured relative to the reference plane, and the choice of the reference plane directly affects the calculation results. Choosing a reference plane that approximates most of the material surface means that the unevenness measurement will primarily reflect the elevation difference of the surface relative to this plane; this method is more intuitive and allows for judgment based on observation of the surface morphology.

[0098] The undulation can be calculated by measuring the height of each point on the surface relative to the reference plane. The undulation of the P-type grain 101 is greater than that of the N-type grain 201, which means that the surface morphology of the P-type grain 101 is more complex than that of the N-type grain 201, with more protrusions 30 and depressions 40.

[0099] The fact that the undulation of the P-type grain 101 is greater than that of the N-type grain 201 means that the surface of the P-type grain 101 has at least more protrusions 30 and depressions 40 than the surface of the N-type grain 201 (in Figures 1 to 4, protrusions 30 are in white and depressions 40 are in black). Specifically, the surface of the P-type grain 101 may have more protrusions 30 than the surface of the N-type grain 201, while the number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; the number of protrusions 30 on the surface of the P-type grain 101 may be greater than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is a), while the number of depressions 40 on the surface of the P-type grain 101 may be less than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is b), and a > b; or the surface of the P-type grain 101 may have more protrusions 30 than the surface of the N-type grain 201, while the number of depressions 40 on the surface of the P-type grain 101 is less than the number of depressions 40 on the surface of the N-type grain 201, and a > b. The number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; or, the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is c), and the number of protrusions 30 on the surface of the P-type grain 101 is less than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is d), and c > d; or, the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201, and the number of protrusions 30 on the surface of the P-type grain 101 is greater than the number of protrusions 30 on the surface of the N-type grain 201.

[0100] Understandably, the statement that the undulation of P-type grain 101 is greater than that of N-type grain 201 is a description of the average state; that is, the average undulation of P-type grain 101 is greater than that of N-type grain 201. Since grain growth is influenced by many factors, there may be some P-type grains 101 with less undulation than some N-type grains 201, but this does not affect the overall trend of the average undulation of the grains.

[0101] The surface roughness of a material is related not only to the number of at least one of the depressions 40 and protrusions 30 on the material surface, but also to the depth of the depressions 40 and the depth of the protrusions 30. The deeper the depressions 40 and the higher the protrusions 30, the greater the surface roughness of the material. However, on the surface of a grain, since the grain size itself is small, the size of at least one of the depressions 40 and protrusions 30 on the grain is even smaller. The number of at least one of the depressions 40 and protrusions 30 has a much greater impact on the roughness than the depth of the depressions 40 and the depth of the protrusions 30. Therefore, in this embodiment, the influence of the depth of the depressions 40 and the depth of the protrusions 30 on the roughness is ignored and not discussed in detail.

[0102] Understandably, the surface of P-type grain 101 has at least more protrusions 30 and depressions 40 than the surface of N-type grain 201. This greater undulation may increase the surface area of ​​the grain, thus affecting light absorption and carrier generation and transport. Greater undulation means more light scattering and reflection. The larger surface undulation of P-type grain 101 causes light to be reflected and scattered multiple times on the grain surface, increasing the path length of photons within the P-type region and their residence time, thereby improving light absorption. In contrast, N-type grain 201 has less undulation, meaning its surface is relatively flat. Smaller undulation helps reduce surface defects and improve carrier transport efficiency. The combined effect contributes to improving the overall photoelectric conversion efficiency of the solar cell.

[0103] In this embodiment, a first region and a second region are respectively formed on a silicon substrate. A P-type polycrystalline silicon layer, comprising a plurality of P-type grains 101, is formed in the first region; an N-type polycrystalline silicon layer, comprising a plurality of N-type grains 201, is formed in the second region. The undulation of the P-type grains 101 is greater than that of the N-type grains 201. This increases the photon absorption efficiency in the first region and improves the carrier transport efficiency in the second region, thereby enhancing the overall photoelectric conversion efficiency of the solar cell.

[0104] In some embodiments, the number of recesses 40 on the P-type grain 101 is greater than the number of recesses 40 on the N-type grain 201.

[0105] The term "recess 40" refers to a tiny recessed region on the grain surface. The fact that the number of recesses 40 on P-type grain 101 is greater than the number of recesses 40 on N-type grain 201 describes the average state; that is, the average number of recesses 40 on P-type grain 101 is greater than the average number of recesses 40 on N-type grain 201. There may be individual P-type grains 101 with fewer recesses 40 than N-type grains 201, but their impact on the average trend is weak and will not be discussed separately.

[0106] The location of the depression 40 affects light scattering and absorption. More depressions 40 increase the light scattering capability of the P-type grain 101 surface, allowing incident light to be captured and absorbed more effectively in the P-type region. This helps improve the photoelectric conversion efficiency of the P-type region, thereby enhancing the overall performance of the solar cell.

[0107] In this embodiment, the number of recesses 40 on the P-type grain 101 is greater than the number of recesses 40 on the N-type grain 201. The presence of recesses 40 causes light to be reflected and scattered multiple times on the grain surface, increasing the path length of photons in the P-type region, thereby improving the light absorption efficiency.

[0108] In some embodiments, the number of protrusions 30 on the P-type die 101 is greater than the number of protrusions 30 on the N-type die 201.

[0109] Protrusion 30 refers to a tiny upward-convex region on the grain surface. Similar to depression 40, the fact that the number of protrusions 30 on P-type grains 101 is greater than the number of protrusions 30 on N-type grains 201 describes the average state; that is, the average number of protrusions 30 on P-type grains 101 is greater than the average number of protrusions 30 on N-type grains 201. There may be individual P-type grains 101 with fewer protrusions 30 than N-type grains 201, but their impact on the average trend is weak and will not be discussed separately.

[0110] The protrusions at position 30 also affect light scattering and absorption. A greater number of protrusions at position 30 further enhances the light scattering effect on the surface of the P-type grain 101, increasing the residence time of photons in the P-type region and improving light absorption efficiency. This helps to improve the overall performance of the solar cell.

[0111] In this embodiment, the number of protrusions 30 on the P-type grain 101 is greater than the number of protrusions 30 on the N-type grain 201. The presence of protrusions 30 causes light to be reflected and scattered multiple times on the grain surface, increasing the path length of photons in the P-type region, thereby improving the light absorption efficiency.

[0112] In some embodiments, the difference between the highest and lowest positions on the P-type grain 101 is 1-15 nm.

[0113] Tests were conducted on multiple different samples, and the experimental results showed that when the difference between the highest and lowest positions on the P-type grain 101 was 1-15 nm, the light absorption efficiency improved rapidly.

[0114] In some embodiments, the difference between the highest and lowest positions on the N-type grain 201 is 1-20 nm.

[0115] Tests were conducted on multiple different samples, and the experimental results showed that when the difference between the highest and lowest positions on the N-type grain 201 was 1-20 nm, the light absorption efficiency improved rapidly.

[0116] In some embodiments, a plurality of P-type grains 101 cover the entire surface of the first region.

[0117] A number of P-type grains 101 are distributed throughout the entire first region, arranged in a non-overlapping manner on the plane of the first region to ensure that the entire first region is completely covered. It is not excluded that there are gaps between adjacent grains (grain boundaries formed due to the repulsive force between adjacent grains).

[0118] The fully covered P-type grain 101 ensures that there are no unused areas in the first region, maximizing light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0119] In this embodiment, a plurality of P-type grains 101 cover the entire surface of the first region. The full coverage of the P-type grains 101 enables each part of the first region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0120] In some embodiments, a plurality of N-type grains 201 cover the entire surface of the second region.

[0121] A number of N-type grains 201 cover the entire first region and are arranged in a non-overlapping manner on the plane of the second region, ensuring that the entire second region is completely covered. Gaps (grain boundaries formed due to repulsive forces between adjacent grains) are not excluded.

[0122] The fully covered N-type grain 201 ensures that there are no unused areas in the second region, maximizing light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0123] In this embodiment, a plurality of N-type grains 201 cover the entire surface of the second region. The full coverage of the N-type grains 201 enables each part of the second region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0124] As shown in Figures 1 to 4, in some embodiments, there is a first grain boundary 102 between adjacent P-type grains 101 and a second grain boundary 202 between adjacent N-type grains 201, and the width of the first grain boundary 102 is smaller than the width of the second grain boundary 202.

[0125] Grain boundaries are the interfaces between adjacent grains in polycrystalline materials. In polycrystalline materials, grain boundaries form between adjacent grains due to differences in grain growth direction and crystal structure. Grain boundaries are recombination centers for charge carriers (electrons or holes), affecting the material's conductivity and carrier lifetime. Grain boundaries can hinder dislocation movement, increasing the material's strength and hardness; however, excessive grain boundaries can also lead to increased brittleness.

[0126] The statement that the width of the first grain boundary 102 is less than the width of the second grain boundary 202 describes the average state; that is, the average width of the first grain boundary 102 is on average less than the average width of the second grain boundary 202. The average width can be determined using the mean method. This involves arbitrarily selecting the same number of grain boundaries in both the first and second regions, summing the widths of the grain boundaries in each region, and then dividing by the number of grain boundaries to calculate the average width. Understandably, the number of grain boundaries selected should not be too small, as this can easily lead to a large deviation in the result. Theoretically, the more grain boundaries selected, the more accurate the calculation result. The specific number of grain boundaries can be chosen based on the actual situation.

[0127] There may be individual P-type grains 101 with a grain boundary width greater than that of N-type grains 201, but the impact on the average trend is weak and will not be discussed separately.

[0128] Grain boundaries contain numerous lattice defects and impurities, which can form energy traps. When electrons move through silicon, they may be captured by these traps upon encountering a grain boundary, thus hindering their normal transport path. Electrons need to spend more time and energy to bypass these traps or escape from them, which slows down their migration speed and reduces transport efficiency.

[0129] For example, electrons can normally move quickly from one location to another along a relatively smooth path, but as the grain boundaries widen, electrons frequently interact with defects and impurities at the grain boundaries, constantly changing their direction of movement, resulting in a longer actual transport time and a decrease in overall transport efficiency.

[0130] On the one hand, the P-type grains 101 are doped with P-type impurities (such as boron), exhibiting hole conductivity. Silicon materials contain a large number of free electrons, which become the majority carriers. Although the widening of the second grain boundary 202 reduces electron transport efficiency, the sheer number of electrons in N-type silicon means that even if some electrons are hindered at the grain boundary, a large number can still successfully complete the transport process and participate in the photoelectric conversion of the battery. In other words, the overall electron supply is sufficient, and the loss of a few electrons at the second grain boundary 202 has a relatively small impact on the total electron transport volume in the entire N-region.

[0131] From a macroscopic perspective, the overall efficiency of a solar cell mainly depends on the number of charge carriers that can effectively participate in photoelectric conversion and their transport efficiency. In the N-region, due to the abundance of electrons, the reduction in electron transport efficiency caused by the widening of the second grain boundary 202 does not significantly affect the number of electrons that can ultimately reach the cell electrodes, and therefore has little impact on the overall efficiency of the solar cell.

[0132] P-type grain 101 is doped with P-type impurities (such as boron) and exhibits hole conductivity. In P-type silicon, holes are the majority carriers, while electrons are the minority carriers. For the overall carrier balance in the P-region, holes can be considered, to some extent, as key "minority participants" in the photoelectric conversion process (the number of holes participating in the effective photoelectric conversion process is limited relative to the large hole generation mechanism in the P-region). When the first grain boundary 102 widens, the situation differs significantly from that in the N-region. Since holes are relatively few in number in the P-region, they are the key minority carriers participating in the effective photoelectric conversion process. The increased defects and impurities at the grain boundary caused by the widening of the first grain boundary 102 greatly increase the probability of hole trapping and recombination.

[0133] Holes are easily recombine when they encounter traps at grain boundaries during transport, preventing them from reaching the electrodes and participating in photoelectric conversion. Furthermore, due to the limited number of holes, the loss of even one hole has a significant impact on carrier transport and photoelectric conversion in the entire P-region. Compared to the abundant electrons in the N-region, the P-region has fewer holes. The hole loss caused by the widening of the first grain boundary 102 significantly reduces the number of holes capable of participating in photoelectric conversion, thus severely affecting the overall efficiency of the solar cell. Therefore, a narrower first grain boundary 102 can reduce hole recombination at the grain boundary, thereby improving hole lifetime and cell efficiency.

[0134] On the other hand, the P-region is typically slightly larger than the N-region. This is because in solar cell design, the P-region is primarily responsible for absorbing photons and generating photogenerated carriers (electron-hole pairs). A larger P-region area increases the light absorption area, thereby increasing the number of photogenerated carriers and improving the photoelectric conversion efficiency of the solar cell. Grain boundaries exhibit lattice distortion and impurity enrichment, generating stress. Since the P-region is slightly larger than the N-region, and the width of the first grain boundary is smaller than the width of the second grain boundary, this results in a more balanced stress distribution across the entire silicon wafer.

[0135] In larger P-regions, the narrower first grain boundary generates relatively less stress. While the N-region has wider grain boundaries, its relatively smaller area allows it to balance the stress generated by the N-region. When the internal stress distribution of a silicon wafer is uneven, an internal stress gradient is generated, which can cause the wafer to bend and deform. This bending of the silicon wafer can severely impact subsequent cell manufacturing processes (such as photolithography and film deposition), potentially leading to decreased process precision, pattern alignment deviations, and uneven film thickness, thereby reducing the performance and yield of solar cells.

[0136] When the grain boundaries in the P-region are smaller than those in the N-region, resulting in a more balanced overall stress, the likelihood of silicon wafer bending is greatly reduced. Maintaining a flat silicon wafer facilitates the precise implementation of subsequent processes, reduces process defects caused by wafer bending, thereby improving the manufacturing yield of solar cells, lowering production costs, and enhancing product quality and reliability.

[0137] In this embodiment, a first region and a second region are respectively formed on the silicon substrate. A P-type polycrystalline silicon layer, comprising a plurality of P-type grains 101, is formed in the first region. An N-type polycrystalline silicon layer, comprising a plurality of N-type grains 201, is formed in the second region. A first grain boundary 102 is formed between adjacent P-type grains 101, and a second grain boundary 202 is formed between adjacent N-type grains 201. The width of the first grain boundary 102 is smaller than the width of the second grain boundary 202. This reduces hole recombination at the grain boundaries, enhances electron transport efficiency, and improves the photoelectric conversion efficiency of the solar cell. Simultaneously, it enables a more balanced overall stress on the silicon wafer, reducing the possibility of wafer bending and ultimately improving the manufacturing yield of the solar cell.

[0138] In some embodiments, the width of the first grain boundary 102 is less than 10 nm.

[0139] Tests were conducted on multiple samples with different first grain boundary 102 widths. Experimental results show that when the first grain boundary 102 width is less than 10 nm, the carrier lifetime is significantly improved. For example, when the first grain boundary 102 width is 7 nm, the carrier lifetime is 200 μs; while when the first grain boundary 102 width is 12 nm, the carrier lifetime is only 100 μs. Statistical analysis of the experimental data confirms that a first grain boundary 102 width of less than 10 nm can effectively reduce carrier recombination at the grain boundary, thereby improving the carrier lifetime.

[0140] Furthermore, the width of the first grain boundary 102 is in the range of 7-8 nm, which can further optimize the carrier transport and recombination rate, significantly reduce carrier recombination at the grain boundary, and improve carrier lifetime.

[0141] In some embodiments, the width of the second grain boundary 202 is greater than 10 nm.

[0142] In N-type semiconductors, due to the doping of pentavalent impurities (such as phosphorus), there are differences in size and electronic structure between the impurity atoms and silicon atoms. When the width of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will be stretched or compressed, and the cumulative effect of this distortion is more obvious in the grain boundary region, thus generating greater stress.

[0143] Tests were conducted on multiple samples with different widths of the first grain boundary 102. Experimental results show that when the width of the second grain boundary 202 is greater than 10, a good balance with the stress in the P-region can be achieved, alleviating stress concentration within the silicon wafer. This is beneficial for improving the stability of the silicon wafer in subsequent processing, such as reducing pattern deformation and dimensional deviations caused by stress in photolithography and etching processes. Simultaneously, it also helps improve the long-term stability and reliability of solar cells, reducing material fatigue and performance degradation caused by stress.

[0144] Furthermore, the width of the second grain boundary 202 is in the range of 10–22 nm. If the width of the second grain boundary is too large, exceeding the stress balance range that the silicon wafer can withstand, it may also lead to stress imbalance inside the silicon wafer, increasing the risk of silicon wafer breakage and reducing the manufacturing yield of solar cells. Setting the width of the second grain boundary 202 in the range of 10–22 nm can better achieve stress balance, reduce material fatigue and performance degradation caused by stress, and improve the overall performance of the cell.

[0145] In some embodiments, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202.

[0146] Grain boundaries have both width and depth. Grain boundary depth refers to the vertical distance a grain boundary extends within a material, typically measured from the surface inwards. Grain boundary depth can be measured by cross-sectional observation of a sample using a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0147] Grain boundary depth affects the transport path of charge carriers in materials. Deeper grain boundaries may form more complex transport channels, affecting the flow efficiency of charge carriers. Grain boundary depth is also closely related to the defect distribution at the grain boundary; deeper grain boundaries may contain more defects, increasing the probability of charge carrier recombination. Simultaneously, grain boundary depth affects the distribution of the local electric field; deeper grain boundaries may form a stronger local electric field, affecting the separation and collection of charge carriers.

[0148] The depth of the first grain boundary 102 is less than the depth of the second grain boundary 202. In the P-type grain 101, holes are the main charge carriers, and they easily recombine with electrons at the grain boundaries. The shallower depth of the first grain boundary 102 can reduce the residence time of holes at the grain boundary and lower the recombination rate. In contrast, in the N-type grain 201, electrons are the main charge carriers, and electrons require a longer transport path at the grain boundaries. The greater depth of the second grain boundary 202 can enhance the electron transport efficiency and reduce losses during transport.

[0149] Grain boundaries are the interface regions between different grains. Their atomic arrangement is irregular, and they contain a large number of lattice defects, such as dislocations and vacancies, and may also be enriched with impurity atoms. As grain boundaries deepen, it means that the area containing these defects and impurities expands in the direction perpendicular to the grain surface.

[0150] When electrons travel through an N-type semiconductor, they need to move freely within the crystal lattice. As grain boundaries deepen, electrons encounter more defects and impurities during their movement. These defects and impurities can form energy traps, which may trap electrons, causing them to deviate from their original paths or even become trapped. This leads to a decrease in electron mobility; electrons that could previously move rapidly and directionally to form an electric current now need to spend more time and energy overcoming these obstacles, thus reducing electron transport efficiency.

[0151] In the second region, the number of free electrons far exceeds the number of holes, making electrons the majority carriers. Even though the deepening of the second grain boundary 202 hinders the transport of some electrons, the affected electrons are only a small fraction of the vast electron population, so the impact on overall efficiency is minimal.

[0152] In the first region, holes are the majority carriers, while electrons are the minority carriers. However, this discussion focuses on holes that participate in electrical conduction and energy conversion during interactions with the second region. These holes are relatively few in number and are minority carriers.

[0153] As the first grain boundary 102 deepens, the number of defects and impurities at the first grain boundary 102 increases, making it easier for holes to be captured and recombine during transport. Since the number of holes is already small, the loss of each hole has a significant impact on the overall carrier transport. In solar cells, the smooth transport of holes is crucial for converting light energy into electrical energy. The deepening of the first grain boundary 102 leads to a significant reduction in hole transport efficiency, resulting in a substantial decrease in the number of holes reaching the electrode. This severely affects the cell's current output and photoelectric conversion efficiency, thus significantly impacting the overall efficiency.

[0154] In this embodiment, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202, which can reduce recombination, improve transmission efficiency, and thus improve the photoelectric conversion efficiency of the cell.

[0155] In some embodiments, the depth of the first grain boundary 102 is less than 15 nm.

[0156] The shallow depth of the first grain boundary 102 can reduce the defect density at the grain boundary. The shallow grain boundary can limit the formation and expansion of defects, reduce the number of hole recombination centers, thereby reducing the recombination rate of holes at the grain boundary and thus improving the hole lifetime.

[0157] Multiple samples with different first grain boundary (102) depths were tested. Experimental results show that when the first grain boundary (102) depth is less than 15 nm, the hole lifetime is significantly improved. For example, when the first grain boundary (102) depth is 10 nm, the hole lifetime is 250 μs; while when the first grain boundary (102) depth is 18 nm, the hole lifetime is only 120 μs. Statistical analysis of the experimental data confirms that a longer hole lifetime occurs when the first grain boundary (102) depth is less than 15 nm.

[0158] Furthermore, the depth of the first grain boundary 102 is in the range of 8–14 nm, and the hole lifetime reaches the optimal value, thereby improving the overall performance of the device.

[0159] In some embodiments, the depth of the second grain boundary 202 is greater than 10 nm.

[0160] In N-type semiconductors, due to the doping of pentavalent impurities (such as phosphorus), there are differences in size and electronic structure between the impurity atoms and silicon atoms. When the depth of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will be stretched or compressed, and the cumulative effect of this distortion is more obvious in the grain boundary region, thus generating greater stress.

[0161] Tests were conducted on multiple samples with different second grain boundary (202) depths. Experimental results show that when the second grain boundary (202) depth is greater than 10 nm, a good balance with the stress in the P-region can be achieved, alleviating stress concentration within the silicon wafer. This is beneficial for improving the stability of the silicon wafer in subsequent processing, such as reducing pattern deformation and dimensional deviations caused by stress in photolithography and etching processes. Simultaneously, it also helps improve the long-term stability and reliability of solar cells, reducing material fatigue and performance degradation caused by stress.

[0162] Furthermore, the depth of the second grain boundary 202 is in the range of 15–24 nm. If the depth of the second grain boundary is too large, exceeding the stress balance range that the silicon wafer can withstand, it may also lead to stress imbalance inside the silicon wafer, increasing the risk of silicon wafer breakage and reducing the manufacturing yield of solar cells. Setting the depth of the second grain boundary 202 in the range of 15–24 nm can better achieve stress balance, reduce material fatigue and performance degradation caused by stress, and improve the overall performance of the cell.

[0163] In some embodiments, at least one area in the first region and the second region is a velvet surface.

[0164] Textured surfaces are a surface treatment technique that increases light scattering and absorption by creating tiny bumps and depressions on the surface of a material. Textured surfaces are typically created using methods such as chemical etching or mechanical polishing. Chemical etching uses specific etchants to create tiny bumps and depressions on the material surface, while mechanical polishing uses mechanical force to create similar bumps and depressions.

[0165] Specifically, both the first and second regions can be textured, meaning both the P-type and N-type polysilicon layers are textured. Alternatively, the first region can be textured, and the second region can be polished, meaning the P-type polysilicon layer is textured and the N-type polysilicon layer is polished. Another option is that the first region is polished, and the second region is textured, meaning the P-type polysilicon layer is polished and the N-type polysilicon layer is textured.

[0166] Textured surfaces can increase light scattering and reflection, and lengthen the light path within the material, thereby improving light absorption efficiency. Setting at least one region in the first and second regions to a textured surface can improve the photoelectric conversion efficiency of solar cells.

[0167] In some embodiments, both the first region and the second region are velvety.

[0168] Specifically, both the P-type and N-type polycrystalline silicon layers are textured layers. The double-textured structure can simultaneously increase light scattering and absorption in both the P-type and N-type polycrystalline silicon layers, optimizing light absorption efficiency and thus improving the photoelectric conversion efficiency of the solar cell.

[0169] In some embodiments, both the first region and the second region are acid-faceted.

[0170] Acid etching is a type of texturing, which is a microstructure formed on the surface of a silicon wafer through acid etching technology. Specifically, the etching depth and surface morphology can be controlled by adjusting the acid concentration, temperature, and time to meet different application requirements.

[0171] The acid faceting creates an irregular uneven structure. This uneven structure causes light to be reflected and scattered multiple times on the surface, which lengthens the path length of photons within the silicon wafer, thereby improving light absorption efficiency. The irregular structure can also effectively reduce light reflection loss, allowing more light energy to enter the silicon wafer.

[0172] Acid etching also increases the surface area of ​​the silicon wafer, providing more carrier transport channels, improving charge separation and collection efficiency, and the microstructure of the acid-etched surface can capture carriers and reduce their recombination loss on the surface, thereby improving photoelectric conversion efficiency.

[0173] In this embodiment, both the first and second regions are acid-faceted to ensure uniform light absorption and carrier transport performance across the entire battery surface, thus avoiding local performance differences.

[0174] In some embodiments, both the first region and the second region are polished surfaces.

[0175] Polishing is a surface treatment technique that uses mechanical or chemical methods to make a material surface extremely smooth. Polishing typically uses polishing compounds and polishing pads, applying mechanical force to make the material surface very smooth. Chemical polishing, on the other hand, uses specific chemical reagents to create a smooth surface on the material.

[0176] In this embodiment, both the first and second regions are polished surfaces; that is, both the P-type and N-type polycrystalline silicon layers are polished surfaces. Polishing reduces surface defects and impurities, improving carrier transport efficiency. By making both the first and second regions polished, the carrier transport efficiency of the solar cell can be improved, carrier recombination reduced, and thus the photoelectric conversion efficiency improved.

[0177] In some embodiments, the roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer.

[0178] Roughness is a parameter that measures the smoothness of a material surface. The higher the roughness, the lower the smoothness of the material surface, and vice versa.

[0179] P-type polycrystalline silicon is typically formed by doping with acceptor impurities such as boron (B). Boron atoms are small, causing less disruption to the crystal structure during doping and making it easier to form a smooth surface. Furthermore, P-type polycrystalline silicon is more likely to form a uniform grain structure during deposition and annealing. N-type polycrystalline silicon, on the other hand, is typically formed by doping with donor impurities such as phosphorus (P) or arsenic (As). Phosphorus and arsenic atoms are larger, easily causing lattice distortion during doping. Additionally, the grain growth of N-type polycrystalline silicon may be uneven due to the influence of the doped atoms, leading to increased surface roughness. The roughness of P-type polycrystalline silicon layers is lower than that of N-type polycrystalline silicon layers, making it easier to achieve in processing and reducing processing difficulty.

[0180] In terms of performance, the smoother surface of the P-type polysilicon layer with lower roughness reduces surface defects and trapped states at grain boundaries, thereby lowering the recombination probability of charge carriers (electrons and holes) at the surface and grain boundaries. A lower carrier recombination rate can improve the carrier lifetime and efficiency of the device. Meanwhile, the interface quality between the P-type and N-type polysilicon layers is crucial to device performance. A rougher P-type polysilicon layer than an N-type polysilicon layer can form a more uniform and stable interface, reducing the interface state density and thus improving the electrical characteristics of the device.

[0181] Specifically, the root mean square roughness (RMS) of a material surface can be measured using atomic force microscopy (AFM). AFM utilizes a tiny probe (tip) that interacts with the sample surface. As the probe approaches the sample surface, it is subjected to various forces, such as van der Waals forces and electrostatic forces. By detecting changes in the forces between the probe and the sample surface, AFM can accurately measure the height change of the probe as it scans the sample surface. During the scan, the probe moves point by point along the sample surface, recording the height value of each point relative to a reference plane. Statistical analysis of these height values ​​allows for the calculation of the RMS roughness.

[0182] The higher the RMS value, the higher the surface roughness of the material; the lower the RMS value, the lower the surface roughness of the material.

[0183] For example, the RMS value of the surface of the detected P-type polycrystalline silicon layer sample was 1.736 nm, and the RMS value of the surface of the detected N-type polycrystalline silicon layer sample was 6.928 nm. 1.736 nm < 6.928 nm, indicating that the roughness of the P-type polycrystalline silicon layer is less than that of the N-type polycrystalline silicon layer.

[0184] In this embodiment, based on the differences in processing and physical properties of P-type and N-type polysilicon, the roughness of the P-type polysilicon layer is smaller than that of the N-type polysilicon layer, which can significantly reduce carrier recombination, improve carrier mobility, optimize interface properties, reduce leakage current, and improve device consistency and yield.

[0185] In some embodiments, the surface of the N-type grain 201 has dense micropores.

[0186] Pinholes refer to tiny pores on the surface of grains. The pinholes on the surface of N-type grain 201 are blind pinholes, and they are densely distributed on the surface of N-type grain 201. Pinholes and depressions 40 are two different surface structural features:

[0187] Orifices are typically small in size, with diameters ranging from nanometers to micrometers (e.g., 0.1 micrometers to 1 micrometer), and are very densely distributed, with a large number of pores per unit area (e.g., hundreds of pores per square micrometer). In contrast, recesses are typically larger in size, with diameters ranging from micrometers to millimeters (e.g., 1 micrometer to 100 micrometers), and are relatively sparsely distributed, with fewer recesses per unit area (e.g., tens of recesses per square micrometer).

[0188] The orifice is shallower, usually equal to or slightly smaller than its diameter (e.g., 0.1 micrometers to 1 micrometer), and its depth is more uniform, resulting in a relatively smooth surface. In contrast, the depression 40 is much deeper, potentially much larger than its diameter (e.g., 1 micrometer to 10 micrometers), and its depth is uneven, possibly exhibiting noticeable undulations.

[0189] The small holes are typically regular or irregular circles or ovals, giving the surface a porous structure, similar to a sponge or honeycomb. The depressions, on the other hand, are usually irregular in shape, possibly elongated, circular, or irregular polygons. The depressions give the surface an uneven, undulating appearance, similar to grooves or pits.

[0190] The presence of the aperture causes light to be reflected and scattered multiple times on the surface of the grain, increasing the path length of photons in the N-type region and the light scattering ability of the N-type grain surface. This increases the residence time of photons in the N-type region, improves light absorption efficiency, and helps to enhance the overall performance of the solar cell.

[0191] In this embodiment, the surface of the N-type grain 201 has dense small holes, which increases the surface area and enhances light scattering, thereby improving light absorption efficiency.

[0192] Furthermore, the aperture of the pore is 0.1-2 nm.

[0193] This embodiment also provides a battery assembly, including the solar cell described in the above embodiment.

[0194] The beneficial effects of battery modules are similar to those of solar cells, and will not be elaborated upon here.

[0195] A battery module may include multiple back-contact solar cells. These multiple back-contact solar cells in the battery module can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between the individual cells can be achieved by welding solder strips, or the connection between the individual battery strings can be achieved by busbars.

[0196] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film (not shown in the figures). The encapsulating film can be filled between the light-facing side of the solar cell and the photovoltaic glass, the back-facing side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film can be EVA film or POE film, and the specific choice can be made according to the actual situation. There are no restrictions here.

[0197] Photovoltaic glass can be applied to the photosensitive surface of solar cells using an encapsulating film. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cells while minimizing impact on their efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and solar cells together, providing sealing, insulation, and waterproofing / moisture protection for the solar cells.

[0198] The backsheet can be attached to the film on the back side of the solar cell. The backsheet protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell, film, and photovoltaic glass together can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire solar module, providing stable support and installation. For example, the solar module can be installed at the desired location using the metal frame.

[0199] This embodiment also provides a photovoltaic system, including the battery module in the above embodiment.

[0200] The beneficial effects of photovoltaic systems are similar to those of battery modules, and will not be elaborated upon here.

[0201] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0202] It is understood that those skilled in the art can combine various implementation methods in the above embodiments under the guidance of the above examples to obtain technical solutions with multiple implementation methods.

[0203] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A solar cell, wherein, include: A silicon substrate, comprising a first region and a second region, wherein a P-type polycrystalline silicon layer is disposed in the first region and an N-type polycrystalline silicon layer is disposed in the second region; The P-type polycrystalline silicon layer includes a plurality of P-type grains, and the N-type polycrystalline silicon layer includes a plurality of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region.

2. The solar cell as described in claim 1, wherein, The silicon substrate has a light-facing surface and a back-light-facing surface arranged opposite to each other, with both the first region and the second region located on the back-light-facing surface.

3. The solar cell as described in claim 1, wherein, The total perimeter of the P-type grains per unit area is greater than the total perimeter of the N-type grains per unit area.

4. The solar cell as described in claim 1, wherein, At least one area in the first region and the second region is velvety.

5. The solar cell as described in claim 4, wherein, Both the first and second regions have a velvety surface.

6. The solar cell as claimed in claim 1, wherein, Both the first region and the second region are polished surfaces.

7. The solar cell as claimed in claim 1, wherein, The roughness of the P-type polycrystalline silicon layer is less than that of the N-type polycrystalline silicon layer.

8. The solar cell as claimed in claim 1, wherein, The undulation of the P-type grain is greater than that of the N-type grain.

9. A battery assembly, wherein, Includes the solar cell described in any one of claims 1 to 8.

10. A photovoltaic system, wherein, Includes the battery assembly as described in claim 9.

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