Solar cell

Abstract

The present application provides a solar cell, comprising: a silicon substrate; a first tunneling layer, the first tunneling layer having a plurality of first openings; a first crystalline conductive layer, the first crystalline conductive layer extending into at least one first opening and contacting the silicon substrate; a second tunneling layer, the second tunneling layer having a plurality of second openings; and a second crystalline conductive layer, the first crystalline conductive layer and / or the second crystalline conductive layer extending into at least one second opening, such that the second crystalline conductive layer contacts the first crystalline conductive layer. The degree of concentration of the second openings in the second tunneling layer is greater than the degree of concentration of the first openings in the first tunneling layer. The design of the solar cell not only effectively reduces carrier recombination in the solar cell, improving the passivation effect of the cell, but also increases carrier transmission channels, improving the carrier transmission efficiency of the cell, thereby improving the efficiency of the solar cell.

Description

A solar cell Technical Field

[0001] This application belongs to the field of solar energy technology and relates to a solar cell. Background Technology

[0002] In the prior art, the back side of a solar cell uses a tunneling oxide layer and a doped polycrystalline silicon layer to form a passivation contact. For example, CN115863452A discloses a solar cell and its fabrication method, as well as a photovoltaic module. This solar cell includes a silicon substrate; a first oxide layer, a semiconductor layer, a second oxide layer, a polycrystalline silicon layer, and a first passivation layer are stacked on the silicon substrate. Both the first oxide layer and the second oxide layer have through holes, and the through hole density in the first oxide layer is greater than that in the second oxide layer. A first electrode penetrates the first passivation layer and is electrically connected to the polycrystalline silicon layer, or the first electrode sequentially penetrates the first passivation layer, the polycrystalline silicon layer, and the second oxide layer and is electrically connected to the semiconductor layer. The silicon substrate includes a base region and an emitter; a second passivation layer is provided on the side of the emitter away from the base region; a second electrode penetrates the second passivation layer and is electrically connected to the emitter. This patent utilizes the vias in different oxide layers to increase the resonant state density and improve the probability of resonant tunneling. However, it still relies on pore tunneling rather than contact transport. Furthermore, the via density of the first oxide layer near the silicon substrate surface is greater than that of the second oxide layer, which is detrimental to passivation at the silicon substrate interface. Additionally, the distance between the first and second oxide layers in the quantum well structure must be very close (i.e., the semiconductor layer thickness is less than 3 nm) to achieve the resonant tunneling effect, which can easily lead to excessive diffusion of dopants from the polycrystalline silicon layer into the silicon substrate. CN118299432A discloses a back-side structure of a solar cell and its fabrication method, relating to the field of photovoltaic technology. It includes: a monocrystalline silicon substrate, a stacked polycrystalline silicon passivation layer structure, and a metal electrode body located on the side of the stacked polycrystalline silicon passivation layer away from the monocrystalline silicon substrate. Two different types of silver particles, type I and type II, are precipitated on the side of the metal electrode body facing the stacked polycrystalline silicon passivation layer. Silver particle type II penetrates the second tunneling oxide layer and contacts the first doped polycrystalline silicon layer. The carrier transport efficiency at the tunneling layer interface of the above-mentioned battery structure is low, hindering the improvement of battery efficiency.

[0003] Therefore, improving the carrier transport efficiency at the tunneling layer interface in the battery structure, thereby enhancing the efficiency of solar cells, is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a solar cell. In the solar cell structure provided by this application, both the first tunneling layer and the second tunneling layer have notches. A first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate. The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one second notch, such that the second crystalline conductive layer contacts the first crystalline conductive layer. Furthermore, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces carrier recombination in the solar cell and improves the passivation effect, but also increases the carrier transport channels, improving carrier transport efficiency, thereby increasing the efficiency of the solar cell.

[0005] In a first aspect, this application provides a solar cell, comprising:

[0006] Silicon substrate;

[0007] The back side of the silicon substrate is provided with a first tunneling layer, a first crystalline conductive layer, a second tunneling layer, and a second crystalline conductive layer.

[0008] The first tunnel layer has multiple first gaps;

[0009] The first crystalline conductive layer extends into at least one of the first notches and contacts the silicon substrate;

[0010] The second tunneling layer has multiple second gaps;

[0011] The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer contacts the first crystalline conductive layer;

[0012] The density of the second gap in the second tunnel layer is greater than the density of the first gap in the first tunnel layer.

[0013] In the solar cell structure provided in this application, both the first tunneling layer and the second tunneling layer have notches. A first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate. The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one second notch, such that the second crystalline conductive layer contacts the first crystalline conductive layer. Furthermore, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces carrier recombination in the solar cell and improves the passivation effect, but also increases the carrier transport channels, improving the carrier transport efficiency of the cell, thereby increasing the efficiency of the solar cell.

[0014] Preferably, the density of the first gap is 5×10. 5 -5×10 10 cm -2 .

[0015] Preferably, the density of the second gap is 1×10. 8 -1×10 13 cm -2 .

[0016] Preferably, the width of the first notch and / or the width of the second notch is less than 200 nm.

[0017] Preferably, both the first crystalline conductive layer and the second crystalline conductive layer include a plurality of grains; wherein at least one of the grains penetrates at least one second notch and extends into the at least one first notch, such that the second crystalline conductive layer contacts the silicon substrate.

[0018] Preferably, the thickness of the first crystalline conductive layer is denoted as d3, the thickness of the second crystalline conductive layer is denoted as d4, and d3 < d4.

[0019] Preferably, the ratio of d3 to d4 is (1-7):10.

[0020] Preferably, the value of d3 is in the range of 10-50 nm.

[0021] Preferably, the value of d4 is in the range of 20-90nm.

[0022] Preferably, the value of d3 is in the range of 15-40nm.

[0023] Preferably, the value of d4 is in the range of 30-80nm.

[0024] Preferably, the first crystalline conductive layer and the second crystalline conductive layer each independently comprise a polycrystalline silicon layer or a silicon carbide layer.

[0025] Preferably, the silicon substrate has a first conductivity type.

[0026] Preferably, the conductivity type of both the first crystalline conductive layer and the second crystalline conductive layer is either the first conductivity type or the second conductivity type.

[0027] Preferably, both the first crystalline conductive layer and the second crystalline conductive layer contain a first conductivity type dopant or a second conductivity type dopant, and the doping concentration of the dopant in the first crystalline conductive layer is less than the doping concentration of the dopant in the second crystalline conductive layer.

[0028] Preferably, the doping concentration of the doped element in the first crystalline conductive layer is 1×10⁻⁶. 18 -5×10 20 cm -3 .

[0029] Preferably, the doping concentration of the doped element in the second crystalline conductive layer is 3 × 10⁻⁶. 19 -1×10 22 cm -3 .

[0030] Preferably, the first tunneling layer and the second tunneling layer each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide layer.

[0031] Preferably, the thickness of the first tunneling layer is denoted as d1, the thickness of the second tunneling layer is denoted as d2, and d2≤d1.

[0032] Preferably, the values ​​of d1 and d2 are each independently within the range of 1-10 nm.

[0033] Preferably, the values ​​of d1 and d2 are each independently within the range of 2-5 nm.

[0034] Preferably, the values ​​of d1 and d2 are each independently within the range of 2.5-5nm.

[0035] Preferably, the solar cell further includes a first passivation layer, which is disposed on the side surface of the second crystalline conductive layer away from the back side of the silicon substrate, and a first anti-reflection layer is disposed on the first passivation layer.

[0036] Preferably, the first passivation layer includes at least one of a silicon oxynitride layer, a silicon nitride layer, or a silicon oxide layer.

[0037] Preferably, the first antireflective layer comprises a hydrogenated silicon nitride layer and / or a silicon oxynitride layer.

[0038] Preferably, the first passivation layer is a silicon oxynitride passivation layer.

[0039] Preferably, the first antireflective layer comprises a silicon hydrogen nitride layer and a silicon oxynitride layer stacked sequentially along the direction away from the back side of the silicon substrate.

[0040] Preferably, the solar cell further includes an emitter located on the front side of the silicon substrate and having a conductivity type opposite to that of the silicon substrate; or, the solar cell further includes a front surface field located on the front side of the silicon substrate and having the same conductivity type as that of the silicon substrate.

[0041] Preferably, the emitter or the front surface field is located inside or outside the front surface of the silicon substrate.

[0042] Preferably, the solar cell further includes a second passivation layer located on the emitter or the front surface field.

[0043] Preferably, the second passivation layer comprises at least one of an aluminum oxide layer, a silicon oxide layer, or a silicon nitride layer.

[0044] Preferably, a second anti-reflective layer is provided on the second passivation layer.

[0045] Preferably, the second antireflective layer comprises at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a magnesium fluoride layer.

[0046] Preferably, the solar cell further includes:

[0047] A back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer.

[0048] A front electrode that passes through the second passivation layer and makes contact with the emitter or front surface field.

[0049] Preferably, both the first crystalline conductive layer and the second crystalline conductive layer include a polycrystalline conductive layer formed by heat treatment and crystallization of an amorphous conductive layer.

[0050] Preferably, the back side of the silicon substrate is provided with a plurality of first conductivity type regions and a plurality of second conductivity type regions, and the plurality of first conductivity type regions and the plurality of second conductivity type regions are arranged at intervals along the horizontal direction of the back side of the silicon substrate.

[0051] The first tunneling layer, the first crystalline conductive layer, the second tunneling layer, and the second crystalline conductive layer are disposed in the first conductivity type region or the second conductivity type region.

[0052] Preferably, the solar cell further includes a back passivation layer disposed on the second conductivity type region and the first conductivity type region. A first electrode is disposed on the back passivation layer located in the first conductivity type region, and the first electrode passes through the back passivation layer and contacts at least the second crystalline conductive layer.

[0053] Preferably, a second electrode is provided on the back passivation layer located in the second conductivity type region, the second electrode passes through the back passivation layer into the silicon substrate, and the second electrode has a second conductivity type contact portion in the silicon substrate.

[0054] Preferably, the second electrode is an aluminum electrode, and the second conductive contact is an aluminum-silicon alloy contact.

[0055] Preferably, the front side of the silicon substrate is provided with a doped passivation layer, and a front passivation layer and / or a front anti-reflection layer are stacked on the doped passivation layer along the direction away from the silicon substrate.

[0056] The numerical range described in this application includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this application will not exhaustively list the specific point values ​​included in the range.

[0057] Compared with the prior art, the beneficial effects of this application are as follows:

[0058] In the solar cell structure provided in this application, both the first tunneling layer and the second tunneling layer are provided with notches. The first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate. The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. This design not only effectively reduces carrier recombination in the solar cell and improves the passivation effect of the cell, but also increases the carrier transport channels and improves the carrier transport efficiency of the cell, thereby improving the efficiency of the solar cell. Attached Figure Description

[0059] Figure 1 is a schematic diagram of the structure of the solar cell provided in Embodiment 1 of this application.

[0060] Figure 2 is a TEM scan of the back side of the solar cell provided in Embodiment 1 of this application.

[0061] Figure 3 is a partial structural schematic diagram of the solar cell provided in Embodiment 3 of this application.

[0062] Figure 4 is a schematic diagram of the first tunneling layer in the solar cells provided in Embodiments 1, 2 and 3 of this application.

[0063] Figure 5 is a schematic diagram of the second tunneling layer in the solar cells provided in Embodiments 1, 2 and 3 of this application.

[0064] Figure 6 is a schematic diagram of the structure of the solar cell provided in Embodiment 4 of this application.

[0065] Figure 7 is a schematic diagram of the structure of the solar cell provided in Embodiment 5 of this application.

[0066] Among them, 100-n type silicon wafer; 101-first tunneling layer; 102-first crystalline conductive layer; 103-second tunneling layer; 104-second crystalline conductive layer; 105-first passivation layer; 106-silicon nitride layer; 107-silicon oxynitride layer; 108-back electrode; 109-p-type emitter; 110-second passivation layer; 111-second anti-reflection layer; 112-front electrode; 113-first notch; 114-second notch; 102A-n region first crystalline conductive layer; 102B-p region first crystalline conductive layer; 103A-n region second tunneling layer; 103B-p region second tunneling layer; 104A-n region second crystalline conductive layer; 104B-p region second crystalline conductive layer; 105 106'-Back passivation layer; 107'-Back hydrogenated silicon nitride layer; 109'-Back silicon oxynitride layer; 110'-Doped passivation layer; 111'-Front passivation layer; 115'-Front antireflection layer; 116'-Metal negative electrode; 600-Metal positive electrode; 601-First tunneling oxide layer; 602a-First n-type phosphorus-doped polycrystalline silicon layer; 602b-Second n-type phosphorus-doped polycrystalline silicon layer; 603-Second tunneling oxide layer; 604-Interface passivation layer; 605-Hydrogenated silicon nitride film; 606-Silicon oxynitride film; 607-Second electrode; 608-First electrode; 609-Boron-doped layer; 610-Front passivation layer; 611-Front reflective layer; 612-P-type contact. Detailed Implementation

[0067] It should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0068] It should be noted that, in the description of this application, unless otherwise expressly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0069] The technical solution of this application will be further described below with reference to the accompanying drawings and specific embodiments.

[0070] In one specific embodiment, this application provides a solar cell, the structural schematic diagram and back-side TEM scan image of which are shown in Figures 1 and 2, including:

[0071] Silicon substrate (exemplarily, for example, it may be an n-type silicon wafer 100);

[0072] A first tunneling layer 101 is located on the back side of the silicon substrate, and the first tunneling layer 101 has a plurality of first notches;

[0073] A first crystalline conductive layer 102 is disposed on the first tunneling layer 101, and the first crystalline conductive layer 102 extends into at least one of the first notches and contacts the silicon substrate.

[0074] The second tunneling layer 103 is disposed on the first crystalline conductive layer 102, and the second tunneling layer 103 has a plurality of second notches;

[0075] A second crystalline conductive layer 104 is disposed on the second tunneling layer 103, and the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one second notch, such that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102.

[0076] The density of the second gap in the second tunnel layer 103 is greater than the density of the first gap in the first tunnel layer 101.

[0077] In the solar cell structure provided in this application, both the first tunneling layer 101 and the second tunneling layer 103 have notches. A first crystalline conductive layer 102 extends into at least one first notch and contacts the silicon substrate. The first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one second notch, such that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102. Furthermore, the density of the second notches is greater than the density of the first notches. This design not only effectively reduces carrier recombination in the solar cell and improves the passivation effect, but also increases the carrier transport channels, improving the carrier transport efficiency of the cell, thereby increasing the efficiency of the solar cell.

[0078] In this application, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are in direct contact through a gap on the second tunneling layer 103, which reduces the grain boundary density of polycrystalline silicon and reduces carrier scattering and recombination losses. The second tunneling layer 103 acts as a buffer layer, which buffers the diffusion of dopants in the polycrystalline silicon layer. This achieves a stepped doping distribution with low doping concentration in the first crystalline conductive layer 102 and high doping concentration in the second crystalline conductive layer 104, while reducing the carrier transport blocking effect of the second tunneling layer 103.

[0079] It should be noted that "density of gaps" refers to the number of gaps per unit area, such as the number of gaps per square centimeter. Essentially, it is an indicator used to quantify the density of defect distribution in a layered structure, and the same applies below.

[0080] It should be noted that, in this application, the first crystalline conductive layer 102, the second crystalline conductive layer 104, the first tunneling layer 101 and the second tunneling layer 103 can be disposed on the substantially entire back side of the silicon substrate, or they can be disposed on a portion of the back side of the silicon substrate, such as in Figures 6 and 7, or other partial designs, which are also within the scope of protection of this application.

[0081] In this application, to avoid affecting carrier transport, and because the surface passivation of the first tunneling layer 101 plays an important role, and the second crystalline conductive layer 104 requires high conductivity, the density of the second notch in the second tunneling layer 103 is greater than the density of the first notch in the first tunneling layer 101. That is, the density of the second tunneling layer 103 is less than that of the first tunneling layer 101. Therefore, the second notch with a higher density in the second tunneling layer 103 can reduce carrier transport loss. At the same time, the second notch increases the diffusion channels of high-concentration phosphorus dopant in the second crystalline conductive layer 104, reduces the accumulation of phosphorus on the surface of the second tunneling layer 103, and improves the doping concentration distribution.

[0082] In this application, the first crystalline conductive layer 102 and / or the second crystalline conductive layer 104 extend into at least one second notch, such that the second crystalline conductive layer 104 contacts the first crystalline conductive layer 102. The following are possible scenarios:

[0083] The first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend together into the same second notch; the first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend into different second notches; a portion of the first crystalline conductive layer 102 and the second crystalline conductive layer 104 extend together into the same second notch, while the other portions extend into different second notches.

[0084] Furthermore, the density of the first gap is 5×10. 5 -5×10 10 cm -2 For example, it could be 5×10 5 cm -2 5×10 6 cm -2 5×10 7 cm -2 5×10 8 cm -2 5×10 9 cm -2 Or 5×10 10 cm -2 Etc., preferably 5×10 6 -5×10 8 cm -2 .

[0085] In this application, if the density of the first gap is less than 5×10 5 cm -2 If the junction resistance is too high, the carrier transport efficiency is low, and the passivation effect does not change much; if the density of the first notch is greater than 5×10 10 cm -2 This leads to excessive recombination loss of interface carriers and a decrease in passivation effect.

[0086] Furthermore, the density of the second gap is 1×10. 8 -1×10 13 cm -2 For example, it could be 1×10 8 cm -2 1×10 9 cm -2 1×10 10 cm -2 1×10 11 cm -2 1×10 12 cm-2 Or 1×10 13 cm -2 Etc., preferably 1×10 9 -1×10 11 cm -2 .

[0087] In this application, if the density of the second gap is less than 1×10 8 cm -2 If the junction resistance is too high, it will severely obstruct the carriers in the first crystalline conductive layer 102, resulting in low carrier transport efficiency; if the density of the second notch is greater than 1×10 13 cm -2 If the density is insufficient to buffer the diffusion of high-concentration dopants in the second crystalline conductive layer 104, the dopants will diffuse excessively within the silicon substrate, resulting in excessive loss of interfacial carrier recombination and a decrease in passivation effect.

[0088] Furthermore, the width of the first notch and / or the width of the second notch is less than 200nm, for example, it can be 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0089] It should be noted that in the first tunnel layer 101, since the widths of the multiple gaps are not completely consistent, the selection of the width parameters of the multiple gaps needs to be limited to the condition of satisfying the above-mentioned gap density range, so as to avoid including technical features that cannot be achieved.

[0090] It should be noted that in the second tunnel layer 103, since the widths of the multiple gaps are not completely consistent, the selection of the width parameters of the multiple gaps needs to be limited to the condition of satisfying the above-mentioned gap density range, so as to avoid including technical features that cannot be achieved.

[0091] Furthermore, the first and second notches can be prepared using the following methods:

[0092] A first tunneling layer, a first amorphous conductive layer, a second tunneling layer, and a second amorphous conductive layer are sequentially deposited on the back side of a silicon substrate. Then, a heat treatment is performed to crystallize the first and second amorphous conductive layers to form a first crystalline conductive layer and a second crystalline conductive layer, with multiple notches formed in the first and second tunneling layers. The amorphous conductive layer may include amorphous silicon, and the first and second crystalline conductive layers formed after heat treatment crystallization may include polycrystalline silicon. During the deposition of the second tunneling layer, excess hydrogen is introduced, causing the hydrogen in the second tunneling layer to be released in subsequent processes, thereby introducing more notches into the second tunneling layer.

[0093] It should be noted that by adjusting the temperature and atmosphere of the heat treatment, the crystallization of the first and second amorphous silicon layers can be controlled, making the density of the first notch less than that of the second notch. For example, the heat treatment temperature is 800-1200℃, such as 800℃, 850℃, 950℃, 1050℃, 1100℃, 1150℃, or 1200℃.

[0094] Specifically, the step of cooling after heat treatment, which employs rapid cooling or gradient cooling, aims to introduce more second gaps in the second tunneling layer.

[0095] Furthermore, the methods for forming multiple notches include any one of plasma etching, wet etching, or laser etching.

[0096] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are prepared by in-situ doping process. The purpose of this process is to control the doping concentration distribution of the first crystalline conductive layer 102 and the second crystalline conductive layer 104. Moreover, this process can be prepared in the same chamber, simplifying the preparation process.

[0097] Furthermore, both the first crystalline conductive layer 102 and the second crystalline conductive layer 104 include a plurality of grains; wherein at least one of the grains penetrates at least one second notch and extends into the at least one first notch, such that the second crystalline conductive layer 104 contacts the silicon substrate.

[0098] In this application, at least one grain in the second crystalline conductive layer 104 penetrates at least one second notch and extends into at least one first notch. That is, there is a complete grain between the notches of the upper and lower tunneling layers, and there are no grain boundaries between the notches of the upper and lower tunneling layers along the thickness direction of the silicon substrate (e.g., grains that are induced to grow vertically, or grain boundaries that are moved by high-temperature treatment, and the grains of the first crystalline conductive layer and the second crystalline conductive layer merge with each other to form grains larger than the thickness of the first crystalline conductive layer). This can reduce the grain boundary density and further improve the carrier transport efficiency.

[0099] Furthermore, the deposition methods for the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are each independently vapor phase deposition methods.

[0100] Furthermore, the thickness of the first crystalline conductive layer 102 is denoted as d3, and the thickness of the second crystalline conductive layer 104 is denoted as d4, where d3 < d4.

[0101] Furthermore, the ratio of d3 to d4 is (1-7):10, for example, it can be 1:10, 2:10, 3:10, 4:10, 5:10, 6:10 or 7:10, etc.

[0102] In this application, the ratio of d3 to d4 is limited to (1-7):10, which is beneficial to the diffusion of the concentration gradient of the doped elements in the second crystalline conductive layer 104, forming a high-low junction, reducing the diffusion of impurities on the silicon substrate, and improving the passivation effect.

[0103] Furthermore, the value of d3 is in the range of 10-50nm, for example, it can be 10nm, 20nm, 30nm, 40nm or 50nm, etc.

[0104] In this application, if the thickness of the first crystalline conductive layer 102 is greater than 50 nm, it is not conducive to the gradient diffusion of doped elements in the second crystalline conductive layer 104; if the thickness of the first crystalline conductive layer 102 is less than 10 nm, the buffering effect is poor, resulting in excessive diffusion of doped elements into the silicon substrate.

[0105] Furthermore, the value of d4 is in the range of 20-90nm, for example, it can be 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, etc.

[0106] Furthermore, the value of d3 ranges from 15 to 40 nm.

[0107] Furthermore, the value of d4 ranges from 30 to 80 nm.

[0108] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 each independently include a polycrystalline silicon layer or a silicon carbide layer.

[0109] Furthermore, the silicon substrate has a first conductivity type. Exemplarily, for example, it may be an n-type silicon wafer 100.

[0110] Furthermore, the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are both of the first conductive type or the second conductive type.

[0111] It should be noted that semiconductors have two types of conductivity: N-type and P-type. In N-type semiconductors, electrons are the majority carriers and holes are the minority carriers; their conductivity mainly relies on the movement of electrons. In P-type semiconductors, holes are the majority carriers and electrons are the minority carriers; the movement of holes dominates current conduction. For ease of study, this application defines either N-type or P-type as the "first conductivity type," and the other as the "second conductivity type." For example, if the first conductivity type is N-type and the second conductivity type is P-type, then the silicon substrate is N-type silicon, the first and second crystalline conductive layers are N-type semiconductors, and the emitter is P-type. The same principle applies below.

[0112] Furthermore, both the first crystalline conductive layer 102 and the second crystalline conductive layer 104 have a first conductivity type dopant element or a second conductivity type dopant element, and the doping concentration of the dopant element in the first crystalline conductive layer 102 is less than the doping concentration of the dopant element in the second crystalline conductive layer 104.

[0113] In this application, the doping concentration of the dopant element in the first crystalline conductive layer 102 is limited to be lower than that in the second crystalline conductive layer 104. This is beneficial for maintaining a higher doping concentration in the second crystalline conductive layer 104, thereby improving carrier transport efficiency. The lower doping concentration in the first crystalline conductive layer 102 helps reduce excessive diffusion of phosphorus dopant into the silicon substrate. Furthermore, the density of the first notch in the first tunneling layer 101 is lower than that in the second tunneling layer 103, further reducing the doping concentration between the first crystalline conductive layer 102 and the silicon substrate, thus reducing interfacial carrier recombination. The second crystalline conductive layer 104 requires a high concentration of phosphorus doping. When the phosphorus dopant in the second crystalline conductive layer 104 diffuses inward, it tends to accumulate on the surface of the second tunneling layer 103, introducing undesirable band bending. When the notch density in the second tunneling layer 103 is greater than that in the first tunneling layer 101, it reduces carrier transport losses while increasing the diffusion channels for the high-concentration phosphorus dopant in the second crystalline conductive layer 104, thereby improving the doping concentration distribution of the first crystalline conductive layer 102 and the second crystalline conductive layer 104.

[0114] Furthermore, the doping elements in the first crystalline conductive layer 102 and the second crystalline conductive layer 104 are both phosphorus.

[0115] Furthermore, the phosphorus doping concentration in the first crystalline conductive layer 102 is 1×10⁻⁶. 18 cm -3 -5×10 20 cm -3 For example, it could be 1×10 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 Or 5×10 20 cm -3 wait.

[0116] Furthermore, the phosphorus doping concentration in the second crystalline conductive layer 104 is 3 × 10⁻⁶. 19 cm -3 -1×10 22 cm-3 For example, it could be 3×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 5×10 20 cm -3 1×10 21 cm -3 Or 1×10 22 cm -3 wait.

[0117] Furthermore, the first tunneling layer 101 and the second tunneling layer 103 each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer.

[0118] In this application, the silicon oxide layer facilitates selective carrier tunneling.

[0119] It should be noted that the material of the silicon oxynitride layer is silicon oxynitride.

[0120] Furthermore, the preparation methods of the first tunneling layer 101 and the second tunneling layer 103 each independently include any one of thermal oxidation, chemical oxidation, or vapor deposition.

[0121] Further, the thickness of the first tunneling layer 101 is denoted as d1, and the thickness of the second tunneling layer 103 is denoted as d2, where d2≤d1.

[0122] In this application, d2≤d1 can avoid excessive suppression of the diffusion of dopants in the second crystalline conductive layer 104 during annealing and reduce obstruction of carrier transport.

[0123] Furthermore, the values ​​of d1 and d2 are each independently 1-10nm, for example, they can be 1nm, 3nm, 5nm, 7nm, 9nm or 10nm, etc.

[0124] In this application, if d1 is less than 1nm, the interface passivation effect is poor; if d1 is greater than 10nm, it severely obstructs carrier transport and the efficiency decreases significantly.

[0125] In this application, if d2 is less than 1nm, the interface passivation effect is poor; if d2 is greater than 10nm, it severely obstructs carrier transport and the efficiency decreases significantly.

[0126] Furthermore, the values ​​of d1 and d2 are each independently within the range of 2-5nm.

[0127] Furthermore, the values ​​of d1 and d2 are each independently within the range of 2.5-5nm.

[0128] Even slight variations in the thickness of the tunneling layer have a significant impact on the junction resistance. Generally, the tunneling layer thickness needs to be less than 2 nm, but an excessively thin tunneling layer leads to poor passivation. In this application, the thickness of the first tunneling layer 101 is greater than 2 nm, and further allows for a thickness greater than 2.5 nm, significantly improving the surface passivation effect and reducing the inward diffusion effect of the first crystalline conductive layer 102 on the silicon substrate. Simultaneously, since the first crystalline conductive layer 102 and the silicon substrate are in local contact through a notch, the carrier transport channel is increased, effectively suppressing the problem of increased junction resistance caused by a thicker tunneling layer.

[0129] Furthermore, the solar cell also includes a first passivation layer 105, which is disposed on the side surface of the second crystalline conductive layer 104 away from the back side of the silicon substrate, and a first anti-reflection layer is disposed on the first passivation layer 105.

[0130] In this application, the first anti-reflective layer has a passivation effect.

[0131] Furthermore, the first passivation layer 105 includes at least one of a silicon oxynitride passivation layer, a silicon nitride layer, or a silicon oxide layer.

[0132] Furthermore, the first antireflective layer comprises a silicon nitride layer and / or a silicon oxynitride layer.

[0133] Furthermore, the first passivation layer 105 is a silicon oxynitride passivation layer.

[0134] In this application, the silicon oxynitride passivation layer has a fixed positive charge. In addition, due to the presence of oxygen atoms, the electrical properties of the first passivation layer 105 can be adjusted, the n-type surface state density can be reduced, and carrier recombination can be reduced.

[0135] Furthermore, the first antireflective layer comprises a silicon hydrogen nitride layer 106 and a silicon oxynitride layer 107 stacked sequentially.

[0136] In this application, after heat treatment, hydrogen diffuses into the first passivation layer 105 and the silicon substrate in the hydrogenated silicon nitride layer 106, which is beneficial for passivating surface defects.

[0137] Furthermore, both the first passivation layer 105 and the first anti-reflection layer are prepared by vapor deposition.

[0138] Furthermore, the thickness of the first passivation layer 105 is less than 10 nm, for example, it can be 8 nm, 6 nm, 4 nm or 2 nm, etc.

[0139] In this application, the thickness of the first passivation layer 105 is less than 10 nm, which is beneficial to the diffusion of hydrogen atoms in the first anti-reflection layer and further improves the passivation effect.

[0140] Furthermore, the thickness of the hydrogenated silicon nitride layer 106 is 30-70nm, for example, it can be 30nm, 40nm, 50nm, 60nm or 70nm.

[0141] In this application, if the thickness of the silicon hydrogen nitride layer 106 is less than 30 nm, the passivation effect is poor; if the thickness of the silicon hydrogen nitride layer 106 is greater than 70 nm, it leads to a decrease in optical performance.

[0142] Furthermore, the thickness of the silicon oxynitride layer 107 is 20-60 nm, for example, it can be 20 nm, 30 nm, 40 nm, 50 nm or 60 nm.

[0143] In this application, if the thickness of the silicon oxynitride layer 107 is less than 20 nm, the passivation effect is poor; if the thickness of the silicon oxynitride layer 107 is greater than 60 nm, it leads to a decrease in optical performance.

[0144] Furthermore, the solar cell further includes an emitter located on the front side of the silicon substrate and having a conductivity type opposite to that of the silicon substrate (e.g., a p-type emitter 109); or, the solar cell further includes a front surface field located on the front side of the silicon substrate and having the same conductivity type as the silicon substrate.

[0145] Furthermore, the emitter or the front surface field is located inside or outside the front surface of the silicon substrate.

[0146] In this application, the emitter is formed by diffusion of an n-type dopant or a p-type dopant into the front side of the silicon substrate. The p-type dopant can be, for example, a boron dopant.

[0147] Furthermore, the method for preparing the emitter includes thermal diffusion or ion implantation.

[0148] Furthermore, the solar cell also includes a second passivation layer 110, which is located on the emitter or the front surface field.

[0149] Furthermore, the second passivation layer 110 includes at least one of an aluminum oxide layer, a silicon oxide layer, or a silicon nitride layer.

[0150] In this application, the alumina layer has a high density of fixed negative charges, which has a good passivation effect on the p-type surface.

[0151] Furthermore, a second anti-reflection layer 111 is provided on the second passivation layer 110.

[0152] Furthermore, the second antireflective layer 111 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a magnesium fluoride layer.

[0153] Furthermore, the second passivation layer 110 and the second anti-reflection layer 111 are both prepared by vapor deposition.

[0154] Furthermore, the solar cell also includes:

[0155] The back electrode 108 passes through the first passivation layer 105 and is in contact with at least the second crystalline conductive layer 104.

[0156] The front electrode 112 passes through the second passivation layer 110 and contacts the emitter or front surface field.

[0157] It should be noted that "at least in contact with the second crystalline conductive layer 104" means that the back electrode 108 can be in contact with the second crystalline conductive layer 104 or the first crystalline conductive layer 102.

[0158] It should be noted that when the back electrode 108 penetrates the second tunneling layer 103, the gap in the second tunneling layer 103 refers to the location other than the penetration opening of the back electrode 108.

[0159] Furthermore, the back electrode 108 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode.

[0160] Furthermore, the front electrode 112 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, a palladium electrode, or a silver-aluminum electrode, preferably a silver-aluminum electrode.

[0161] Furthermore, both the first crystalline conductive layer and the second crystalline conductive layer include a polycrystalline conductive layer formed by heat treatment and crystallization of the amorphous conductive layer.

[0162] In another specific embodiment, this application provides a solar cell, which differs from the solar cell described above in that the silicon substrate has a first conductivity type, the first crystalline conductive layer and the second crystalline conductive layer have a second conductivity type, and the front side of the silicon substrate has a front surface field with the same conductivity type as the silicon substrate.

[0163] In the solar cell structure provided in this application, the first crystalline conductive layer and the second crystalline conductive layer are set as the emitter layers on the back side of the silicon substrate. The density of the first notch in the first tunneling layer is greater than the density of the second notch in the second tunneling layer. This structure can effectively suppress the excessive diffusion of dopants into the silicon substrate and reduce carrier recombination near the back PN junction, thus having a relatively high open-circuit voltage.

[0164] In another specific embodiment, the structural schematic diagram of the solar cell provided in this application is shown in Figure 7, including:

[0165] A silicon substrate having a first conductivity type or a second conductivity type (exemplarily, for example, a P-type silicon wafer 600);

[0166] The back side of the silicon substrate is provided with a plurality of first conductivity type regions and a plurality of second conductivity type regions, and the plurality of first conductivity type regions and the plurality of second conductivity type regions are arranged at intervals from each other along the horizontal direction of the back side of the silicon substrate;

[0167] The first conductive type region is provided with a first tunneling layer (exemplarily, for example, a first tunneling oxide layer 601), and the first tunneling layer has a plurality of first notches;

[0168] And a first crystalline conductive layer (exemplarily, for example, a first n-type phosphorus-doped polycrystalline silicon layer 602a), the first crystalline conductive layer being disposed on the first tunneling layer and having a first conductivity type, the first crystalline conductive layer extending into at least one of the first notches and contacting the silicon substrate.

[0169] And a second tunneling layer (exemplarily, for example, a second tunneling oxide layer 603), the second tunneling layer being disposed on the first crystalline conductive layer, the second tunneling layer having a plurality of second gaps, the density of the second gaps being greater than the density of the first gaps;

[0170] And a second crystalline conductive layer (exemplarily, for example, a second n-type phosphorus-doped polycrystalline silicon layer 602b), the second crystalline conductive layer being disposed on the second tunneling layer and having a first conductivity type, the first crystalline conductive layer and / or the second crystalline conductive layer extending into at least one of the second notches, such that the second crystalline conductive layer is in contact with the first crystalline conductive layer.

[0171] In this solar cell structure, both the first tunneling layer and the second tunneling layer have notches. The first crystalline conductive layer extends into at least one first notch and contacts the silicon substrate. The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one second notch, so that the second crystalline conductive layer contacts the first crystalline conductive layer. This design not only effectively reduces carrier recombination in the solar cell and improves the passivation effect of the cell, but also increases the carrier transport channels and improves the carrier transport efficiency at the interface of the first tunneling layer in the cell structure, thereby improving the efficiency of the solar cell.

[0172] Furthermore, the solar cell also includes a back passivation layer (i.e., an interface passivation layer 604), which is disposed on the second conductivity type region and the first conductivity type region. A first electrode 608 is disposed on the back passivation layer located in the first conductivity type region, and the first electrode 608 passes through the back passivation layer and contacts at least the second crystalline conductive layer.

[0173] It should be noted that "at least in contact with the second crystalline conductive layer" means that the first electrode 608 can be in contact with either the second crystalline conductive layer or the first crystalline conductive layer.

[0174] Furthermore, the solar cell also includes a back antireflection layer disposed on the back passivation layer.

[0175] Furthermore, a second electrode 607 is provided on the back passivation layer located in the second conductivity type region. The second electrode 607 passes through the back passivation layer and enters the silicon substrate. The second electrode 607 has a second conductivity type contact portion in the silicon substrate.

[0176] Furthermore, the first electrode 608 includes any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode.

[0177] Furthermore, the second electrode 607 is an aluminum electrode, and the second conductive contact is an aluminum-silicon alloy contact.

[0178] Furthermore, the back antireflection layer comprises a stacked silicon hydrogen nitride film 605 and a silicon oxynitride film 606 along a direction away from the silicon substrate.

[0179] Furthermore, the front side of the silicon substrate is provided with a doped passivation layer (exemplarily, for example, a boron doped layer 609), and a front passivation layer (i.e., front passivation layer 610) and / or a front anti-reflection layer (i.e., front reflection layer 611) are stacked on the doped passivation layer along a direction away from the silicon substrate.

[0180] In this application, the doping type of the passivation layer can be n-type or p-type, which is beneficial to reduce carrier recombination on this surface of the silicon substrate.

[0181] Furthermore, a front passivation layer 610 and a front reflection layer 611 are sequentially stacked on the doped passivation layer along the direction away from the silicon substrate.

[0182] Furthermore, the silicon substrate is an n-type silicon wafer or a p-type silicon wafer.

[0183] Example 1

[0184] This embodiment provides a solar cell, the structural schematic of which is shown in Figure 1. It includes an n-type silicon wafer 100. On its front side (i.e., the light-receiving surface), along the direction away from the n-type silicon wafer 100, a p-type emitter 109, a second passivation layer 110, and a second anti-reflection layer 111 are sequentially stacked. On its back side, along the direction away from the n-type silicon wafer 100, a first tunneling layer 101, a first crystalline conductive layer 102, a second tunneling layer 103, a second crystalline conductive layer 104, a first passivation layer 105, and a second anti-reflection layer are sequentially stacked. The first tunneling layer 101 is a silicon oxide layer with a thickness d1 equal to 3 nm; the second tunneling layer 103 is a silicon oxide layer with a thickness d2 equal to 2 nm; and the first crystalline conductive layer 102 is an n-type phosphorus-doped polycrystalline silicon layer with a thickness d3 equal to 30 nm and a doping concentration of 5 × 10⁻⁶. 19 cm -3 The second crystalline conductive layer 104 is an n-type phosphorus-doped polycrystalline silicon layer with a thickness d4 of 50 nm and a doping concentration of 5 × 10⁻⁶. 20 cm -3 The ratio of d3 to d4 is 6:10; the second passivation layer 110 is an aluminum oxide layer with a thickness of 5 nm, the first passivation layer 105 is a silicon oxynitride layer with a thickness of 5 nm, the second antireflection layer 111 is a silicon nitride layer with a thickness of 70 nm, and the first antireflection layer includes a silicon oxynitride layer 106 with a thickness of 50 nm and a silicon oxynitride layer 107 with a thickness of 40 nm stacked sequentially; the p-type emitter 109 is doped with boron with a doping concentration of 3 × 10⁻⁶. 20 cm -3 .

[0185] Referring to Figure 2, the first tunneling layer 101 has multiple first gaps, and the second tunneling layer 103 has multiple second gaps. The density of the second gaps is greater than that of the first gaps, as shown in the red circle. The first crystalline conductive layer 102 extends into at least one first gap and contacts the n-type silicon wafer 100. The second crystalline conductive layer 104 extends into at least one second gap, making contact between the second crystalline conductive layer 104 and the first crystalline conductive layer 102. The density of the first gaps is 5 × 10⁻⁶. 5 -5×10 10 cm -2 (Optionally, the density can be 5×10) 5 cm -2 5×10 6 cm -2 5×10 7 cm -2 5×10 8 cm -2 5×10 9 cm -2 Or 5×10 10 cm -2(etc.), the density of the second gap is 1×10 8 -1×10 13 cm -2 (Optionally, the density can be 1×10) 8 cm -2 1×10 9 cm -2 1×10 10 cm -2 1×10 11 cm -2 1×10 12 cm -2 Or 1×10 13 cm -2 (etc.); the width of the first notch is 1-50nm, and the width of the second notch is 1-200nm.

[0186] A back electrode 108 is provided on the second anti-reflection layer. The back electrode 108 passes through the first anti-reflection layer, the first passivation layer 105, the second crystalline conductive layer 104, and the second tunneling layer 103 and contacts the first crystalline conductive layer 102. The back electrode 108 is an Ag electrode.

[0187] A front electrode 112 is provided on the second anti-reflection layer 111. The front electrode 112 passes through the second anti-reflection layer 111 and the second passivation layer 110 and contacts the p-type emitter 109 of the n-type silicon wafer 100. The front electrode 112 is a silver-aluminum electrode. The silver-aluminum electrode contacts the p-type emitter 109 to form a p+ doped region.

[0188] The emitter is located on the front surface of the silicon substrate.

[0189] Example 2

[0190] The difference between this embodiment and Embodiment 1 is that the first crystalline conductive layer is a p-type boron-doped polycrystalline silicon layer, and the second crystalline conductive layer is also a p-type boron-doped polycrystalline silicon layer. The p-type emitter is replaced with an n-type phosphorus-doped front surface field.

[0191] The rest of the structure remains the same as in Example 1.

[0192] Example 3

[0193] The difference between this embodiment and Embodiment 1 is that the thickness d1 of the first tunneling layer is equal to 3 nm, the thickness d2 of the second tunneling layer is equal to 2.2 nm, and d2 < d1; the density of the second notch is greater than the density of the first notch, while the density of the first notch is 5 × 10⁻⁶. 5 -5×10 10 cm -2 The density of the second gap is 1×10. 8 -1×10 13cm -2 .

[0194] The second crystalline conductive layer includes a plurality of grains, at least one grain penetrating at least one second notch and extending into at least one first notch, such that the second crystalline conductive layer contacts the n-type silicon wafer.

[0195] The remaining structure and parameters are consistent with those of Example 1.

[0196] Figure 3 shows a partial structural schematic diagram of the solar cell provided in this embodiment, wherein 100 is an n-type silicon wafer, 101 is a first tunneling layer, 102 is a first crystalline conductive layer, 103 is a second tunneling layer, 104 is a second crystalline conductive layer, 113 is a first notch, and 114 is a second notch. At the second notch 114, the grains of the second crystalline conductive layer 104 penetrate the second notch and extend into the first notch of the first tunneling layer 101. That is, there are complete grains (such as grains induced to grow vertically) between the notches of the upper and lower tunneling layers. This reduces the grain boundary density and further improves the carrier transport efficiency. The arrow indicates the direction of carrier flow at the first notch.

[0197] Figures 4 and 5 show schematic diagrams of the first tunneling layer and the second tunneling layer in the solar cells provided in Embodiments 1, 2 and 3, respectively. By comparison, it can be seen that the first tunneling layer is denser than the second tunneling layer, that is, the gap density of the second tunneling layer is greater than that of the first tunneling layer.

[0198] Example 4

[0199] This embodiment provides a solar cell, the structural schematic of which is shown in Figure 6, including:

[0200] N-type silicon wafer 100.

[0201] The N-type silicon wafer 100 has a first tunneling layer 101 with a thickness of 3 nm on its back side. The material is silicon oxide. The first tunneling layer 101 has multiple first notches with a density of 5 × 10⁻⁶. 5 -5×10 10 cm -2 (Optionally, the density can be 5×10) 5 cm -2 5×10 6 cm -2 5×10 7 cm -2 5×10 8 cm -2 5×10 9 cm -2 Or 5×10 10 cm -2(etc.); The first tunneling layer 101 is provided with a plurality of n-type regions and a plurality of p-type regions, the plurality of n-type regions and the plurality of p-type regions are arranged at intervals along the horizontal direction of the back side of the N-type silicon wafer 100, and a partition region is provided between adjacent n-type regions and p-type regions.

[0202] The n-type region, along the direction away from the first tunneling layer 101, includes a stacked n-region first crystalline conductive layer 102A, an n-region second tunneling layer 103A, and an n-region second crystalline conductive layer 104A. The p-type region, along the direction away from the first tunneling layer 101, includes a stacked p-region first crystalline conductive layer 102B, a p-region second tunneling layer 103B, and a p-region second crystalline conductive layer 104B. The thickness of both the n-region first crystalline conductive layer 102A and the p-region first crystalline conductive layer 102B is 30 nm. The n-region first crystalline conductive layer 102A is an n-type phosphorus-doped polycrystalline conductive layer. The silicon layer consists of two layers: the first crystalline conductive layer 102B in the p-region is a p-type boron-doped polycrystalline silicon layer; the second tunneling layer 103A in the n-region and the second tunneling layer 103B in the p-region are both 2 nm thick and made of silicon oxide; the second crystalline conductive layer 104A in the n-region and the second crystalline conductive layer 104B in the p-region are both 50 nm thick, with the n-type second crystalline conductive layer 104A being an n-type phosphorus-doped polycrystalline silicon layer and the p-type second crystalline conductive layer 104B being a p-type boron-doped polycrystalline silicon layer; both the n-type second tunneling layer 103A and the p-type second tunneling layer 103B have multiple second notches, each with a notch density of 1 × 10⁻⁶. 8 -1×10 13 cm -2 (Optionally, the density can be 1×10) 8 cm -2 1×10 9 cm -2 1×10 10 cm -2 1×10 11 cm -2 1×10 12 cm -2 Or 1×10 13 cm -2 wait).

[0203] The back passivation layer 105' is disposed on the outer surface of the n-type region, p-type region and the partition region, with a thickness of 5nm and made of silicon oxynitride.

[0204] The back antireflection layer is disposed on the outer surface of the back passivation layer 105', and includes a back hydrogenated silicon nitride layer 106' with a thickness of 50 nm and a back silicon oxynitride layer 107' with a thickness of 40 nm, which are stacked sequentially.

[0205] A doped passivation layer 109' is disposed on the front surface of an n-type silicon wafer 100, and the doping element is boron with a doping concentration of 3 × 10⁻⁶. 20 cm -3 The doped passivation layer 109' is provided with a front passivation layer 110' with a thickness of 5 nm and a front anti-reflection layer 111' with a thickness of 70 nm, which are stacked sequentially on the doped passivation layer 109'. The front passivation layer 110' is an aluminum oxide layer and the front anti-reflection layer 111' is a silicon nitride layer.

[0206] The metal negative electrode 115 is located in the n-type region and passes through the back anti-reflection layer, the back passivation layer 105', the second crystalline conductive layer 104A and the second tunneling layer 103A of the n-region to contact the first crystalline conductive layer 102A of the n-region. The material is silver.

[0207] The metal positive electrode 116 is located in the p-type region and passes through the back anti-reflection layer, the back passivation layer 105', the p-region second crystalline conductive layer 104B and the p-region second tunneling layer 103B to contact the p-region first crystalline conductive layer 102B. The material is silver.

[0208] Example 6

[0209] This embodiment provides a solar cell, the structural schematic of which is shown in Figure 7, including:

[0210] P-type silicon wafer 600.

[0211] The back side of the P-type silicon wafer 600 is provided with a plurality of n-type regions and p-type regions, which are spaced apart from each other along the horizontal direction of the back side of the P-type silicon wafer 600.

[0212] The n-type region is provided with a first tunneling layer, which is a first tunneling oxide layer 601 with multiple first notches, a thickness of 3 nm, and is made of silicon oxide. The density of the first notches is 5 × 10⁻⁶. 5 -5×10 10 cm -2 (Optionally, the density can be 5×10) 5 cm -2 5×10 6 cm -2 5×10 7 cm -2 5×10 8 cm -2 5×10 9 cm -2 Or 5×10 10 cm -2 wait).

[0213] And a first crystalline conductive layer, which is a first n-type phosphorus-doped polycrystalline silicon layer 602a with a thickness of 30 nm, disposed on the first tunneling oxide layer 601, with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The first n-type phosphorus-doped polycrystalline silicon layer 602a extends into at least one of the first notches and contacts the p-type silicon wafer 600.

[0214] And a second tunneling layer, which is a second tunneling oxide layer 603, disposed on the first n-type phosphorus-doped polycrystalline silicon layer 602a, with a thickness of 2 nm, made of silicon oxide, and having multiple second notches. The density of the second notches is greater than that of the first notches, and the density of the second notches is 1 × 10⁻⁶. 8 -1×10 13 cm -2 (Optionally, the density can be 1×10) 8 cm -2 1×10 9 cm -2 1×10 10 cm -2 1×10 11 cm -2 1×10 12 cm -2 Or 1×10 13 cm -2 wait).

[0215] And a second crystalline conductive layer, which is a second n-type phosphorus-doped polysilicon layer 602b, disposed on the second tunneling oxide layer 603, with a thickness of 50nm. The second n-type phosphorus-doped polysilicon layer 602b extends into at least one of the second gaps, so that the second n-type phosphorus-doped polysilicon layer 602b is in contact with the first n-type phosphorus-doped polysilicon layer 602a.

[0216] The method for preparing the p-type and n-type regions includes: firstly, depositing a complete first tunneling layer, a first n-type phosphorus-doped polysilicon layer, a second tunneling layer, and a second n-type phosphorus-doped polysilicon layer sequentially on the back side of a p-type silicon wafer; then, using laser or mask etching, partially removing the aforementioned functional layers deposited on the back side of the p-type silicon wafer, thereby forming multiple spaced openings on the aforementioned functional layers, exposing the p-type silicon wafer through the multiple openings to form the p-type region, and the aforementioned functional layer regions retained outside the openings being the n-type regions.

[0217] The solar cell also includes a back passivation layer, which is an interface passivation layer 604 disposed on the n-type region and the p-type region. The interface passivation layer 604 is a silicon oxynitride layer with a thickness of 5 nm.

[0218] The solar cell also includes a back antireflection layer, which is an interface antireflection layer disposed on the interface passivation layer 604. The interface antireflection layer includes a 50 nm thick silicon nitride film 605 and a 40 nm thick silicon oxynitride film 606 stacked sequentially.

[0219] A first electrode 608 is provided on the interface antireflection layer located in the n-type region. The first electrode 608 passes through the interface antireflection layer and the interface passivation layer 604 and is in contact with the second n-type phosphorus-doped polysilicon layer 602b at least. The first electrode 608 is an Ag electrode.

[0220] A second electrode 607 is provided on the interface antireflection layer located in the p-type region. The second electrode 607 passes through the interface antireflection layer and the interface passivation layer 604 (the opening through the interface antireflection layer and the interface passivation layer 604 can be a laser opening or an opening formed by aluminum paste sintering) and enters into the p-type silicon wafer 600. The second electrode 607 has a p-type contact portion 612 in the p-type silicon wafer 600. The second electrode 607 is an aluminum electrode, and the p-type contact portion 612 is an aluminum-silicon alloy contact portion. It is formed by the aluminum electrode sintering into the p-type silicon wafer 600 and reacting with the p-type silicon wafer 600 to form an Al-Si alloy p+ layer, thereby achieving ohmic contact.

[0221] The front side of the P-type silicon wafer 600 is provided with a doped passivation layer, which is a boron doped layer 609 with a doping concentration of 3×10⁻⁶. 20 cm -3 The boron-doped layer 609 has a front passivation layer 610 and a front antireflection layer 611 stacked sequentially along the direction away from the P-type silicon wafer 600. The front passivation layer 610 is an aluminum oxide layer with a thickness of 5 nm, and the front antireflection layer 611 is a silicon nitride layer with a thickness of 70 nm.

[0222] In this embodiment, the p-type region does not have a first tunneling layer, a first crystalline conductive layer, a second tunneling layer, and a second crystalline conductive layer. Instead, a back passivation layer and a back antireflection layer are directly formed, and ohmic contact is achieved by direct sintering of the aluminum electrode. This reduces the number of isolation process steps and is beneficial for industrial manufacturing. Furthermore, the aluminum electrode is less expensive, and the p+ layer of the Al-Si alloy forms an ohmic contact, improving carrier transport efficiency.

[0223] The applicant declares that the above description is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application fall within the protection and disclosure scope of this application.

Claims

1. A solar cell, comprising: Silicon substrate; The back side of the silicon substrate is provided with a first tunneling layer, a first crystalline conductive layer, a second tunneling layer, and a second crystalline conductive layer. The first tunnel layer has multiple first gaps; The first crystalline conductive layer extends into at least one of the first notches and contacts the silicon substrate; The second tunneling layer has multiple second gaps; The first crystalline conductive layer and / or the second crystalline conductive layer extend into at least one of the second notches, such that the second crystalline conductive layer contacts the first crystalline conductive layer; The density of the second gap in the second tunnel layer is greater than the density of the first gap in the first tunnel layer.

2. The solar cell according to claim 1, wherein, The density of the first gap in the first tunnel layer is 5×10. 5 -5×10 10 cm -2 The density of the second gap in the second tunnel layer is 1×10. 8 -1×10 13 cm -2 .

3. The solar cell according to claim 1, wherein, The width of the first notch and / or the width of the second notch is less than 200 nm.

4. The solar cell according to claim 1, wherein, Both the first crystalline conductive layer and the second crystalline conductive layer include a plurality of grains; wherein at least one of the grains penetrates at least one second notch and extends into at least one first notch, such that the second crystalline conductive layer contacts the silicon substrate.

5. The solar cell according to claim 1, wherein, The thickness of the first crystalline conductive layer is denoted as d3, and the thickness of the second crystalline conductive layer is denoted as d4, where d3 < d4.

6. The solar cell according to claim 5, wherein, The ratio of d3 to d4 is (1-7):

10.

7. The solar cell according to claim 5, wherein, The value range of d3 is 10-50nm; the value range of d4 is 20-90nm.

8. The solar cell according to claim 7, wherein, The value of d3 is in the range of 15-40nm, and the value of d4 is in the range of 30-80nm.

9. The solar cell according to claim 1, wherein, The first crystalline conductive layer and the second crystalline conductive layer each independently comprise a polycrystalline silicon layer or a silicon carbide layer.

10. The solar cell according to claim 1, wherein, The silicon substrate has a first conductivity type; the first crystalline conductive layer and the second crystalline conductive layer both have either the first conductivity type or the second conductivity type.

11. The solar cell according to claim 10, wherein, Both the first crystalline conductive layer and the second crystalline conductive layer contain a first conductivity type dopant or a second conductivity type dopant, and the doping concentration of the dopant in the first crystalline conductive layer is less than the doping concentration of the dopant in the second crystalline conductive layer.

12. The solar cell according to claim 11, wherein, The doping concentration of the doped element in the first crystalline conductive layer is 1×10⁻⁶. 18 -5×10 20 cm -3 The doping concentration of the doped elements in the second crystalline conductive layer is 3 × 10⁻⁶. 19 -1×10 22 cm -3 .

13. The solar cell according to claim 1, wherein, The first tunneling layer and the second tunneling layer each independently include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer.

14. The solar cell according to claim 1, wherein, The thickness of the first tunneling layer is denoted as d1, and the thickness of the second tunneling layer is denoted as d2, where d2 ≤ d1.

15. The solar cell according to claim 14, wherein, The values ​​of d1 and d2 are each independently within the range of 1-10 nm.

16. The solar cell according to claim 15, wherein, The values ​​of d1 and d2 are each independently within the range of 2-5nm.

17. The solar cell according to claim 16, wherein, The values ​​of d1 and d2 are each independently within the range of 2.5-5nm.

18. The solar cell according to claim 10, wherein, The solar cell further includes a first passivation layer, which is disposed on the side surface of the second crystalline conductive layer away from the back side of the silicon substrate, and a first anti-reflection layer is disposed on the first passivation layer.

19. The solar cell according to claim 18, wherein, The first passivation layer includes at least one of a silicon oxynitride layer, a silicon nitride layer, or a silicon oxide layer; the first antireflection layer includes a hydrogenated silicon nitride layer and / or a silicon oxynitride layer.

20. The solar cell according to claim 19, wherein, The first passivation layer is a silicon oxynitride layer; the first antireflection layer includes a silicon hydrogen nitride layer and a silicon oxynitride layer stacked sequentially along the direction away from the back side of the silicon substrate.

21. The solar cell according to claim 18, wherein, The solar cell further includes an emitter located on the front side of the silicon substrate and having a conductivity type opposite to that of the silicon substrate; or, the solar cell further includes a front surface field located on the front side of the silicon substrate and having the same conductivity type as that of the silicon substrate.

22. The solar cell according to claim 21, wherein, The emitter or the front surface field is located inside or outside the front surface of the silicon substrate.

23. The solar cell according to claim 21, wherein, The solar cell further includes a second passivation layer located on the emitter or the front surface field.

24. The solar cell according to claim 23, wherein, The second passivation layer includes at least one of an aluminum oxide layer, a silicon oxide layer, or a silicon nitride layer.

25. The solar cell according to claim 23, wherein, A second anti-reflection layer is provided on the second passivation layer.

26. The solar cell according to claim 25, wherein, The second antireflective layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a magnesium fluoride layer.

27. The solar cell according to claim 23, wherein, The solar cell also includes: A back electrode that passes through the first passivation layer and is in contact with at least the second crystalline conductive layer; A front electrode that passes through the second passivation layer and makes contact with the emitter or front surface field.

28. The solar cell according to claim 1, wherein, Both the first crystalline conductive layer and the second crystalline conductive layer include a polycrystalline conductive layer formed by heat treatment and crystallization of an amorphous conductive layer.

29. The solar cell according to claim 1, wherein, The back side of the silicon substrate is provided with a plurality of first conductivity type regions and a plurality of second conductivity type regions, and the plurality of first conductivity type regions and the plurality of second conductivity type regions are arranged at intervals with each other along the horizontal direction of the back side of the silicon substrate; The first tunneling layer, the first crystalline conductive layer, the second tunneling layer, and the second crystalline conductive layer are disposed in the first conductivity type region or the second conductivity type region.

30. The solar cell according to claim 29, wherein, The solar cell further includes a back passivation layer disposed on the second conductivity type region and the first conductivity type region. A first electrode is disposed on the back passivation layer located in the first conductivity type region. The first electrode passes through the back passivation layer and contacts at least the second crystalline conductive layer.

31. The solar cell according to claim 30, wherein, A second electrode is provided on the back passivation layer located in the second conductivity type region. The second electrode passes through the back passivation layer and enters the silicon substrate. The second electrode has a second conductivity type contact portion in the silicon substrate.

32. The solar cell according to claim 31, wherein, The second electrode is an aluminum electrode, and the second conductive contact is an aluminum-silicon alloy contact.

33. The solar cell according to claim 29, wherein, The silicon substrate has a doped passivation layer on its front side, and a front passivation layer and / or a front anti-reflection layer are stacked on the doped passivation layer along a direction away from the silicon substrate.

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