Transistor, semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

A transistor, a semiconductor device and a manufacturing method therefor, and an electronic apparatus. The transistor comprises: a first electrode (P1), a second electrode (P2), a first semiconductor layer (C1), a first gate electrode (G1) and a second gate electrode (G2) located on a substrate (10); the first electrode (P1) and the second electrode (P2) are spaced apart along a direction perpendicular to the substrate (10); the first gate electrode (G1) and the second gate electrode (G2) are distributed along a column direction parallel to the substrate (10) on sidewalls on two sides of the first semiconductor layer (C1), and a gate insulating layer (13) is provided between the first gate electrode (G1) and the first semiconductor layer (C1), and between the first semiconductor layer (C1) and the second gate electrode (G2); the first gate electrode (G1) and the first semiconductor layer (C1) are located between the first electrode (P1) and the second electrode (P2), and the second gate electrode (G2) is located on one side of the first electrode (P1) and the second electrode (P2) along the column direction; and the first semiconductor layer (C1) and the second gate electrode (G2) both extend along the direction perpendicular to the substrate (10).

Description

Transistors, semiconductor devices and their manufacturing methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510238522.3, filed on February 28, 2025, entitled "Transistor, Semiconductor Device and Method of Manufacturing Thereof, Electronic Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] The embodiments of this application relate to, but are not limited to, the field of semiconductor technology, and particularly to a transistor, a semiconductor device, a method for manufacturing the same, and an electronic device. Background Technology

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0004] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] This application provides a transistor, a semiconductor device and a method for manufacturing the same, and an electronic device. The transistor adopts a vertical channel structure, which can reduce the area of ​​the memory cell and increase the integration density of the device.

[0007] According to a first aspect of this application, a transistor is provided, the transistor comprising: a first electrode, a second electrode, a first semiconductor layer, a first gate electrode, and a second gate electrode located on a substrate;

[0008] The first electrode and the second electrode are spaced apart along a direction perpendicular to the substrate;

[0009] The first gate electrode and the second gate electrode are distributed on both sidewalls of the first semiconductor layer along a column direction parallel to the substrate. A gate insulating layer is provided between the first gate electrode and the first semiconductor layer, and between the first semiconductor layer and the second gate electrode. The first gate electrode and the first semiconductor layer are located between the first electrode and the second electrode, and the second gate electrode is located on the side of the first electrode and the second electrode that are distributed along the column direction. Both the first semiconductor layer and the second gate electrode extend in a direction perpendicular to the substrate.

[0010] In some embodiments of the first aspect, the first gate electrode extends in a row direction parallel to the substrate, and the circumferential sidewalls of the first gate electrode are partially surrounded by the gate insulating layer.

[0011] In some embodiments of the first aspect, the first gate electrode has sidewalls extending along the row direction; the gate insulating layer surrounds two sidewalls of the first gate electrode distributed in a direction perpendicular to the substrate and one sidewall of the first gate electrode distributed in the column direction.

[0012] In some embodiments of the first aspect, both the first electrode and the second electrode have a first end and a second end that are spaced apart along the column direction;

[0013] The gate insulating layer surrounding the first gate electrode extends to the end faces of the first electrode and the second electrode at the first ends, to the side surface of the first electrode away from the substrate, and to the side surface of the second electrode close to the substrate.

[0014] In some embodiments of the first aspect, the gate insulating layer surrounds the circumferential sidewall of the second gate electrode and an end face near one end of the substrate;

[0015] The gate insulating layer surrounding the second gate electrode extends to the end faces of the second ends of the first electrode and the second electrode.

[0016] In some embodiments of the first aspect, the material of the first semiconductor layer is single-crystal silicon.

[0017] According to a second aspect of this application, a semiconductor device is provided, the semiconductor device comprising: a plurality of memory cells located on a substrate; the plurality of memory cells being spaced apart along a column direction and a row direction parallel to the substrate;

[0018] The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate; the read transistors are transistors as described above.

[0019] In some embodiments of the second aspect, the write transistor includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, and a third gate electrode;

[0020] The third electrode and the fourth electrode are spaced apart along a direction perpendicular to the substrate; the third electrode is connected to the second gate electrode located in the same memory cell; and / or, the third electrode and the second gate electrode are connected by a lead.

[0021] The second semiconductor layer and the third gate electrode both extend in a direction perpendicular to the substrate; the second semiconductor layer at least partially surrounds the third gate electrode.

[0022] In some embodiments of the second aspect, the storage unit further includes a storage node;

[0023] The storage node is connected to the second gate electrode and the third electrode respectively; and / or, the storage node and at least one of the second gate electrode and the third electrode are integrally formed.

[0024] In some embodiments of the second aspect, the semiconductor device further includes: read word lines, write word lines, and bit lines;

[0025] The read line extends along the row direction and is connected to the first gate electrode of a row of memory cells spaced apart along the row direction; and / or,

[0026] The write lines extend along the row direction and are connected to the third gate electrode of a row of memory cells spaced apart along the row direction; and / or,

[0027] The bit line extends along the column direction and is connected to the second and fourth electrodes of a column of memory cells spaced apart along the column direction; and / or,

[0028] The reading line and the first gate electrode are an integral structure; and / or,

[0029] The bit line and the fourth electrode are integrally integrated; and / or

[0030] The second electrode contains metal silicide.

[0031] According to a third aspect of this application, a method for manufacturing a semiconductor device is provided, the method comprising:

[0032] A first electrode layer, a first sacrificial layer, and a second electrode layer are sequentially formed on a substrate to obtain a stacked structure.

[0033] A first trench is formed in the stacked structure, extending through the stacked structure in a direction toward the substrate and in a row direction parallel to the substrate, and the first trench has first lateral grooves on both sides extending into the first sacrificial layer and extending in the row direction.

[0034] A first initial semiconductor layer is formed in the first transverse groove, and a second sacrificial layer is formed in the first trench;

[0035] A second trench is formed on the same side of each second sacrificial layer, extending through the stacked structure in a direction toward the substrate and along the row direction; one side of the second trench exposes the second sacrificial layer, and the other side has a second lateral groove located between the first electrode layer and the second electrode layer, the second lateral groove exposing the first initial semiconductor layer;

[0036] A gate insulating layer is formed on the inner wall of the second trench and the second lateral groove, a read line is formed in the second lateral groove, and an isolation layer is formed in the second trench;

[0037] Remove the second sacrificial layer, and sequentially form a gate insulating layer and a first gate electrode layer in the first trench;

[0038] The first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer are disconnected in the row direction to obtain a plurality of first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes that are spaced apart.

[0039] In some embodiments of the third aspect, forming a first trench in the stacked structure extending through the stacked structure in a direction toward the substrate and in a row direction parallel to the substrate, the first trench having first lateral grooves on both sides extending into the first sacrificial layer and extending in the row direction, includes:

[0040] The stacked structure is etched along the direction toward the substrate to form a plurality of first trenches that penetrate the stacked structure. The plurality of first trenches extend along the row direction and are spaced apart in the column direction parallel to the substrate.

[0041] The first sacrificial layer on both sides is laterally etched within the first trench to form a first lateral groove on both sides of the first trench that extends into the first sacrificial layer and extends along the row direction.

[0042] In some embodiments of the third aspect, the formation of a second trench on the same side of each of the second sacrificial layers, extending through the stacked structure in a direction toward the substrate and along the row direction; one side of the second trench exposes the second sacrificial layer, and the other side has a second lateral groove located between the first electrode layer and the second electrode layer, the second lateral groove exposing the first initial semiconductor layer, including:

[0043] The stacked structure and a first initial semiconductor layer located on the same side of each second sacrificial layer are etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the row direction; the width of the second trench in the column direction parallel to the substrate is greater than or equal to the width of a first initial semiconductor layer in the column direction, such that the second sacrificial layer is exposed on one side of the second trench located on the first sacrificial layer, and the first sacrificial layer is exposed on the other side.

[0044] The exposed first sacrificial layer is etched in the second trench to remove the first sacrificial layer, thereby obtaining a second lateral groove located between the first electrode layer and the second electrode layer. The second lateral groove extends along the row direction and exposes the first initial semiconductor layer.

[0045] In some embodiments of the third aspect, forming a gate insulating layer on the inner walls of the second trench and the second lateral recess, forming a read word line in the second lateral recess, and forming an isolation layer in the second trench includes:

[0046] A gate insulating layer and a second gate electrode layer are sequentially formed in the second trench and the second lateral groove;

[0047] Remove the second gate electrode layer in the second trench and retain the second gate electrode layer in the second transverse groove as the read line;

[0048] The isolation layer is formed within the second trench.

[0049] In some embodiments of the third aspect, the step of breaking the first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer in the row direction to obtain a plurality of spaced-apart first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes includes:

[0050] The first electrode layer, the first initial semiconductor layer, the second electrode layer, the first gate electrode layer, and the isolation layer are etched along the direction toward the substrate to form a third trench extending in a column direction parallel to the substrate.

[0051] The third trench has different depths in different regions along its extension direction:

[0052] In the region where the first gate electrode layer, the isolation layer, and the first initial semiconductor layer are located, the third trench penetrates the first gate electrode layer, the isolation layer, the first initial semiconductor layer, and the first electrode layers and the second electrode layers on both sides of the first initial semiconductor layer, and exposes the substrate.

[0053] In the area where the reading line is located, the third trench only penetrates the second electrode layer on one side of the reading line and exposes the reading line;

[0054] The third trench is filled with insulating material.

[0055] In some embodiments of the third aspect, the sequential formation of a first electrode layer, a first sacrificial layer, and a second electrode layer on the substrate includes:

[0056] A first electrode layer, a first sacrificial layer, and a second electrode layer, formed of crystalline materials, are sequentially grown on the substrate using an epitaxial growth method.

[0057] The formation of the first initial semiconductor layer within the first transverse groove includes:

[0058] Using the first sacrificial layer exposed by the first transverse groove as a template, an epitaxial growth method is used to form the first initial semiconductor layer on the sidewall of the first sacrificial layer;

[0059] The material of the first sacrificial layer is crystalline silicon germanium, and the material of the first initial semiconductor layer is crystalline silicon.

[0060] In some embodiments of the third aspect, the manufacturing method further includes: after forming a plurality of spaced-apart second gate electrodes,

[0061] A bit line connected to the second electrode is formed on the side of the second electrode away from the substrate; and

[0062] A write transistor connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate, and the write transistor is connected to the bit line.

[0063] In some embodiments of the third aspect, forming a bit line connected to the second electrode on the side of the second electrode away from the substrate includes:

[0064] An insulating layer is formed on a surface away from the substrate, covering the second electrode and the second gate electrode;

[0065] A first via is etched in the insulating layer above each of the second electrodes, and each first via exposes a second electrode;

[0066] A connection signal line is formed in the first through hole;

[0067] A bit line layer covering the connection signal lines is formed on a surface away from the substrate;

[0068] The bit line layer is patterned and etched to form multiple bit lines that extend in a column direction parallel to the substrate and are spaced apart in the row direction. Each bit line is connected to multiple connection signal lines that are spaced apart in the column direction.

[0069] The insulating layer is formed to cover the bit line.

[0070] In some embodiments of the third aspect, before forming a connection signal line in the first through-hole, the method further includes: filling the bottom of the first through-hole with a metal material and annealing it, wherein the metal material reacts with silicon in the second electrode to form a metal silicide, and removing unreacted metal material.

[0071] In some embodiments of the third aspect, forming a write transistor connected to the second gate electrode on the side of the second gate electrode away from the substrate and connecting the write transistor to the bit line includes:

[0072] Before forming an insulating layer covering the second electrode and the second gate electrode on the substrate surface, a lead wire connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate;

[0073] After forming the insulating layer covering the bit line on the substrate surface, the bit line and the insulating layer on both sides are etched along the direction toward the substrate to form a plurality of fourth trenches penetrating the bit line and the insulating layer on both sides, the fourth trenches extending along the row direction and each of the fourth trenches exposing a row of leads spaced apart along the row direction;

[0074] A second initial semiconductor layer, a gate insulating layer, and a third gate electrode layer are sequentially formed in the fourth trench;

[0075] The second initial semiconductor layer and the third gate electrode layer are disconnected in the row direction to obtain a plurality of second semiconductor layers and a plurality of third gate electrodes spaced apart; the second semiconductor layers are connected to the bit lines;

[0076] A writing line layer is formed on a surface away from the substrate;

[0077] The writing line layer is patterned and etched to form a plurality of writing lines that extend along the row direction and are spaced apart in the column direction; each writing line is connected to a plurality of third gate electrodes that are spaced apart along the row direction.

[0078] According to a fourth aspect of this application, an electronic device is provided, the electronic device comprising the transistor described in the first aspect of this application or the semiconductor device described in the second aspect of this application, or comprising a semiconductor device obtained by the manufacturing method described in the third aspect of this application.

[0079] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0080] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0081] Overview of the attached figures

[0082] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0083] Figure 1A is a schematic diagram of the longitudinal cross-sectional structure of a transistor in an exemplary embodiment of this application on a cross-section AA perpendicular to the substrate (the position of the cross-section AA is shown in Figure 1B);

[0084] Figure 1B is a schematic diagram of the cross-sectional structure of the transistor shown in Figure 1A on a section parallel to the substrate;

[0085] Figure 2A is a schematic cross-sectional view of a semiconductor device in an exemplary embodiment of this application, on a section parallel to the substrate.

[0086] Figure 2B is a schematic diagram of the cross-sectional structure of the semiconductor device shown in Figure 2A on another section parallel to the substrate;

[0087] Figure 2C is a schematic diagram of the longitudinal section structure of the semiconductor device shown in Figure 2A on section AA perpendicular to the substrate;

[0088] Figure 2D is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in Figure 2A on the BB section perpendicular to the substrate;

[0089] Figure 2E is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in Figure 2A on the CC section perpendicular to the substrate;

[0090] Figure 2F is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor device shown in Figure 2A on the DD section perpendicular to the substrate;

[0091] Figure 3 is a logic circuit diagram of a semiconductor device according to an embodiment of this application;

[0092] Figure 4 is a process flow diagram of a semiconductor device manufacturing method according to an exemplary embodiment of this application;

[0093] Figure 5A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming a covered stack structure;

[0094] Figure 5B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 5A on section AA perpendicular to the substrate;

[0095] Figure 6A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming a covered stacked structure;

[0096] Figure 6B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 6A on section AA perpendicular to the substrate;

[0097] Figure 7A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a first lateral groove, on a section parallel to the substrate.

[0098] Figure 7B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 7A on section AA perpendicular to the substrate;

[0099] Figure 8A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the first semiconductor layer, on a section parallel to the substrate.

[0100] Figure 8B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 8A on section AA perpendicular to the substrate.

[0101] Figure 9A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the second lateral groove, on a section parallel to the substrate.

[0102] Figure 9B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 9A on section AA perpendicular to the substrate;

[0103] Figure 10A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after a second gate electrode layer is formed in a second trench and a second lateral groove, on a section parallel to the substrate.

[0104] Figure 10B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 10A on section AA perpendicular to the substrate.

[0105] Figure 11A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of an isolation layer, on a section parallel to the substrate.

[0106] Figure 11B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 11A on section AA perpendicular to the substrate;

[0107] Figure 12A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after a first gate electrode layer is formed in a first trench, on a section parallel to the substrate.

[0108] Figure 12B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 12A on section AA perpendicular to the substrate;

[0109] Figure 13A is a top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, after filling the third trench with insulating material;

[0110] Figure 13B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 13A on the BB section perpendicular to the substrate;

[0111] Figure 13C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 13A on the CC section perpendicular to the substrate;

[0112] Figure 14A is a top view of a semiconductor device manufacturing method according to an exemplary embodiment of this application after bit lines have been formed;

[0113] Figure 14B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 14A on section AA perpendicular to the substrate;

[0114] Figure 14C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 14A on the BB section perpendicular to the substrate;

[0115] Figure 15A is a schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the third gate electrode, on a section parallel to the substrate.

[0116] Figure 15B is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 15A on section AA perpendicular to the substrate.

[0117] Figure 15C is a schematic diagram of the longitudinal section of the semiconductor structure shown in Figure 15A on the DD section perpendicular to the substrate.

[0118] Detailed Explanation

[0119] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0120] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0121] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0122] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0123] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0124] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0125] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0126] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0127] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that they are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0128] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0129] The embodiments of this application are not necessarily limited to the dimensions shown in the accompanying drawings. The shapes and sizes of the components in the drawings are preferred embodiments, and other shapes and sizes are also possible. Furthermore, the accompanying drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the accompanying drawings.

[0130] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0131] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0132] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this application, unless otherwise specified, the "source electrode" and the "drain electrode" can be interchanged.

[0133] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (e.g., a coupled-to connection) or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0134] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more but less than 10°, and therefore also includes angles of -5° or more but less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more but less than 100°, and therefore also includes angles of 85° or more but less than 95°.

[0135] In this application, "film" and "layer" can be interchanged. For example, sometimes "semiconductor layer" can be replaced with "semiconductor film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0136] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0137] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.

[0138] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0139] This application provides a transistor. Figure 1A is a schematic diagram of the longitudinal section structure of a transistor in an exemplary embodiment of this application on a section AA perpendicular to the substrate; Figure 1B is a schematic diagram of the cross-sectional structure of the transistor shown in Figure 1A on a section parallel to the substrate.

[0140] As shown in Figures 1A and 1B, the transistor includes: a first electrode P1, a second electrode P2, a first semiconductor layer C1, a first gate electrode G1, and a second gate electrode G2 located on the substrate 10.

[0141] The first electrode P1 and the second electrode P2 are distributed at intervals along a direction perpendicular to the substrate 10;

[0142] The first gate electrode G1 and the second gate electrode G2 are distributed on the two sidewalls of the first semiconductor layer C1 along a column direction parallel to the substrate 10. A gate insulating layer 13 is provided between the first gate electrode G1 and the first semiconductor layer C1, and between the first semiconductor layer C1 and the second gate electrode G2. The first gate electrode G1 and the first semiconductor layer C1 are located between the first electrode P1 and the second electrode P2. The second gate electrode G2 is located on the side of the first electrode P1 and the second electrode P2 that are distributed along the column direction. The first semiconductor layer C1 and the second gate electrode G2 both extend in a direction perpendicular to the substrate 10.

[0143] In some embodiments of this application, as shown in FIG1B, the first gate electrode G1 extends along a row direction parallel to the substrate 10; as shown in FIG1A, the circumferential sidewall of the first gate electrode G1 is partially surrounded by the gate insulating layer 13.

[0144] In this application, the column direction intersects the row direction; for example, the column direction and the row direction can be perpendicular to each other. For example, the column direction can be the AA direction as shown in Figure 1B; the row direction can be the BB direction as shown in Figure 1B.

[0145] In some embodiments of this application, as shown in Figures 1A and 1B, the first gate electrode G1 has a sidewall extending along the row direction;

[0146] The gate insulating layer 13 surrounds the two sidewalls of the first gate electrode G1 distributed in a direction perpendicular to the substrate 10 and the one sidewall of the first gate electrode G1 distributed in the column direction.

[0147] In some embodiments of this application, as shown in FIG1A, the first electrode P1 and the second electrode P2 both have a first end P11 and a second end P22 that are spaced apart along the column direction.

[0148] The gate insulating layer 13 surrounding the first gate electrode G1 extends to the end face of the first end P11 of the first electrode P1 and the second electrode P2, the side surface of the first electrode P1 away from the substrate 10, and the side surface of the second electrode P2 close to the substrate 10.

[0149] In some embodiments of this application, as shown in FIG1A, the gate insulating layer 13 surrounds the circumferential sidewall of the second gate electrode G2 and the end face near one end of the substrate 10.

[0150] As shown in Figure 1A, the gate insulating layer 13 surrounding the second gate electrode G2 extends to the end face of the second end P22 of the first electrode P1 and the second electrode P2.

[0151] In some embodiments of this application, the first semiconductor layer C1 may be made of monocrystalline silicon. Using a monocrystalline silicon channel is beneficial for improving the performance consistency of the readout transistor.

[0152] This application also provides a semiconductor device. Figure 2A is a schematic cross-sectional view of a semiconductor device in an exemplary embodiment of this application, on a section parallel to the substrate; Figure 2B is a schematic cross-sectional view of the semiconductor device shown in Figure 2A, on another section parallel to the substrate; Figure 2C is a schematic longitudinal section of the semiconductor device shown in Figure 2A, on a section AA perpendicular to the substrate; Figure 2D is a schematic longitudinal section of the semiconductor device shown in Figure 2A, on a section BB perpendicular to the substrate; Figure 2E is a schematic longitudinal section of the semiconductor device shown in Figure 2A, on a section CC perpendicular to the substrate; Figure 2F is a schematic longitudinal section of the semiconductor device shown in Figure 2A, on a section DD perpendicular to the substrate; wherein, the cross-section in Figure 2A passes through the bit line; the cross-section in Figure 2B passes through the read word line; Figure 3 is a logic circuit diagram of the semiconductor device in an embodiment of this application.

[0153] As shown in Figures 2A to 2F, the semiconductor device includes: a plurality of memory cells located on a substrate 10; the plurality of memory cells are spaced apart along column and row directions parallel to the substrate 10;

[0154] The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate 10; the read transistors are transistors as described above.

[0155] In some embodiments of this application, as shown in FIG2A and FIG2C, the write transistor includes a third electrode P3, a fourth electrode P4, a second semiconductor layer C2 located between the third electrode P3 and the fourth electrode P4, and a third gate electrode G3, wherein a gate insulating layer 13 is provided between the second semiconductor layer C2 and the third gate electrode G3.

[0156] The third electrode P3 and the fourth electrode P4 are spaced apart along a direction perpendicular to the substrate 10; the third electrode P3 is connected to the second gate electrode G2 located in the same memory cell; and / or, the third electrode P3 and the second gate electrode G2 are connected by leads.

[0157] The second semiconductor layer C2 and the third gate electrode G3 both extend in a direction perpendicular to the substrate 10; the second semiconductor layer C2 at least partially surrounds the third gate electrode G3.

[0158] In this application, the column direction intersects the row direction; for example, the column direction and the row direction can be perpendicular to each other. For example, the column direction can be the AA direction as shown in Figures 2A to 2C; the row direction can be the BB, CC, or DD direction as shown in Figures 2A to 2C.

[0159] In this application, multiple components distributed along the row direction can be referred to as a row component, for example, a row of storage cells. Multiple components distributed along the column direction can be referred to as a column component, for example, a column of storage cells.

[0160] In some embodiments of this application, as shown in FIG2A, the second semiconductor layer C2 can completely surround the third gate electrode G3, that is, the second semiconductor layer C2 is annular and surrounds the entire circumferential sidewall of the third gate electrode G3.

[0161] In some embodiments of this application, as shown in Figures 2B, 2C and 3, the storage unit further includes a storage node SN;

[0162] The storage node SN is connected to the second gate electrode G2 and the third electrode P3 respectively; and / or, the storage node SN and at least one of the second gate electrode G2 and the third electrode P3 are integrally integrated.

[0163] In some embodiments of this application, as shown in Figures 2A to 3, the semiconductor device further includes: a read word line RWL, a write word line WWL, and a bit line BL;

[0164] The read word line RWL extends along the row direction and is connected to the first gate electrode G1 of a row of memory cells spaced apart along the row direction; and / or,

[0165] The write line WWL extends along the row direction and is connected to the third gate electrode G3 of a row of memory cells spaced apart along the row direction; and / or,

[0166] Bit line BL extends along the column direction and is connected to the second electrode P2 and the fourth electrode P4 of a column of memory cells spaced apart along the column direction; and / or,

[0167] The read line RWL and the first gate electrode G1 are an integral structure; and / or,

[0168] The bit line BL and the fourth electrode P4 are integrated into one structure; and / or

[0169] The second electrode contains metal silicide.

[0170] The read transistor and write transistor of the semiconductor device in this application embodiment adopt a vertical stacking structure, and both the read transistor and write transistor adopt a vertical channel structure, which can reduce the area of ​​the memory cell and improve the integration density of the device.

[0171] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.

[0172] For example, the materials of the first semiconductor layer and the second semiconductor layer can each be independently silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or wide band gap materials, such as metal oxide materials with a band gap of greater than 1.65 eV.

[0173] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain other elements, such as nitrogen, silicon, etc.; and may also contain other small amounts of doping elements.

[0174] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InGaZnO), etc. Materials such as InWO, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0175] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0176] The above-mentioned metal oxide semiconductor layer or channel material only emphasizes the element type of the material, and does not emphasize the atomic ratio of the material or the film quality of the material.

[0177] For example, the material of the first semiconductor layer can be single-crystal silicon, and the material of the second semiconductor layer can be a metal oxide semiconductor material such as IGZO.

[0178] In some embodiments of this application, the material of the bit line can be selected from any one or more of other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The bit line can be a single-layer or multi-layer structure, for example, it can be a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0179] In some embodiments of this application, the materials of the first gate electrode, the second gate electrode, the third gate electrode, the read line, and the write line can be any one or more of the following different types of materials:

[0180] For example, materials containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or metal alloys containing the aforementioned metals.

[0181] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); and metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0182] Of course, it can also be polycrystalline silicon; it can also be conductive material doped with semiconductor material, such as conductive material doped silicon, conductive material doped germanium, conductive material doped silicon germanium, etc.; as well as other materials that exhibit conductivity, etc.

[0183] In some embodiments of this application, the gate insulating layer may comprise one or more low-K and / or high-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.

[0184] Low-K materials, such as silicon oxide.

[0185] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, high-K materials may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0186] This application also provides a method for manufacturing a semiconductor device. Figure 4 is a process flow diagram of a method for manufacturing a semiconductor device according to an exemplary embodiment of this application. As shown in Figure 4, the manufacturing method includes:

[0187] A first electrode layer, a first sacrificial layer, and a second electrode layer are sequentially formed on a substrate to obtain a stacked structure.

[0188] A first trench is formed in the stacked structure, extending through the stacked structure in a direction toward the substrate and in a row direction parallel to the substrate, and the first trench has first lateral grooves on both sides extending into the first sacrificial layer and extending in the row direction.

[0189] A first initial semiconductor layer is formed in the first transverse groove, and a second sacrificial layer is formed in the first trench;

[0190] A second trench is formed on the same side of each second sacrificial layer, extending through the stacked structure in a direction toward the substrate and along the row direction; one side of the second trench exposes the second sacrificial layer, and the other side has a second lateral groove located between the first electrode layer and the second electrode layer, the second lateral groove exposing the first initial semiconductor layer;

[0191] A gate insulating layer is formed on the inner wall of the second trench and the second lateral groove, a read line is formed in the second lateral groove, and an isolation layer is formed in the second trench;

[0192] Remove the second sacrificial layer, and sequentially form a gate insulating layer and a first gate electrode layer in the first trench;

[0193] The first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer are disconnected in the row direction to obtain a plurality of first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes that are spaced apart.

[0194] In some embodiments of this application, forming a first trench in the stacked structure that extends through the stacked structure along a direction toward the substrate and along a row direction parallel to the substrate, the first trench having first lateral grooves on both sides extending into the first sacrificial layer and extending along the row direction, includes:

[0195] The stacked structure is etched along the direction toward the substrate to form a plurality of first trenches that penetrate the stacked structure. The plurality of first trenches extend along the row direction and are spaced apart in the column direction parallel to the substrate.

[0196] The first sacrificial layer on both sides is laterally etched within the first trench to form a first lateral groove on both sides of the first trench that extends into the first sacrificial layer and extends along the row direction.

[0197] In some embodiments of this application, a second trench is formed on the same side of each of the second sacrificial layers, extending through the stacked structure in a direction toward the substrate and along the row direction; one side of the second trench exposes the second sacrificial layer, and the other side has a second lateral groove located between the first electrode layer and the second electrode layer, the second lateral groove exposing the first initial semiconductor layer, including:

[0198] The stacked structure and a first initial semiconductor layer located on the same side of each second sacrificial layer are etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the row direction; the width of the second trench in the column direction parallel to the substrate is greater than or equal to the width of a first initial semiconductor layer in the column direction, such that the second sacrificial layer is exposed on one side of the second trench located on the first sacrificial layer, and the first sacrificial layer is exposed on the other side.

[0199] The exposed first sacrificial layer is etched in the second trench to remove the first sacrificial layer, thereby obtaining a second lateral groove located between the first electrode layer and the second electrode layer. The second lateral groove extends along the row direction and exposes the first initial semiconductor layer.

[0200] In some embodiments of this application, forming a gate insulating layer on the inner wall of the second trench and the second lateral groove, forming a read word line in the second lateral groove, and forming an isolation layer in the second trench includes:

[0201] A gate insulating layer and a second gate electrode layer are sequentially formed in the second trench and the second lateral groove;

[0202] Remove the second gate electrode layer in the second trench and retain the second gate electrode layer in the second transverse groove as the read line;

[0203] The isolation layer is formed within the second trench.

[0204] In some embodiments of this application, the step of breaking the first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer in the row direction to obtain a plurality of spaced-apart first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes includes:

[0205] The first electrode layer, the first initial semiconductor layer, the second electrode layer, the first gate electrode layer, and the isolation layer are etched along the direction toward the substrate to form a third trench extending in a column direction parallel to the substrate.

[0206] The third trench has different depths in different regions along its extension direction:

[0207] In the region where the first gate electrode layer, the isolation layer, and the first initial semiconductor layer are located, the third trench penetrates the first gate electrode layer, the isolation layer, the first initial semiconductor layer, and the first electrode layers and the second electrode layers on both sides of the first initial semiconductor layer, and exposes the substrate.

[0208] In the area where the reading line is located, the third trench only penetrates the second electrode layer on one side of the reading line and exposes the reading line;

[0209] The third trench is filled with insulating material.

[0210] In some embodiments of this application, the sequential formation of a first electrode layer, a first sacrificial layer, and a second electrode layer on the substrate includes:

[0211] A first electrode layer, a first sacrificial layer, and a second electrode layer, formed of crystalline materials, are sequentially grown on the substrate using an epitaxial growth method.

[0212] The formation of the first initial semiconductor layer within the first transverse groove includes:

[0213] Using the first sacrificial layer exposed by the first transverse groove as a template, an epitaxial growth method is used to form the first initial semiconductor layer on the sidewall of the first sacrificial layer;

[0214] The material of the first sacrificial layer is crystalline silicon germanium, and the material of the first initial semiconductor layer is crystalline silicon.

[0215] In some embodiments of this application, the manufacturing method further includes: after forming a plurality of spaced second gate electrodes,

[0216] A bit line connected to the second electrode is formed on the side of the second electrode away from the substrate; and

[0217] A write transistor connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate, and the write transistor is connected to the bit line.

[0218] In some embodiments of this application, forming a bit line connected to the second electrode on the side of the second electrode away from the substrate includes:

[0219] An insulating layer is formed on a surface away from the substrate, covering the second electrode and the second gate electrode;

[0220] A first via is etched in the insulating layer above each of the second electrodes, and each first via exposes a second electrode;

[0221] A connection signal line is formed in the first through hole;

[0222] A bit line layer covering the connection signal lines is formed on the substrate surface;

[0223] The bit line layer is patterned and etched to form multiple bit lines that extend in a column direction parallel to the substrate and are spaced apart in the row direction. Each bit line is connected to multiple connection signal lines that are spaced apart in the column direction.

[0224] An insulating layer covering the bit lines is formed on the substrate surface.

[0225] In some embodiments of this application, before forming the connection signal line in the first through hole, the method further includes:

[0226] A metal material is filled at the bottom of the first through hole and annealed. The metal material reacts with silicon in the second electrode to form a metal silicide, and the unreacted metal material is removed.

[0227] In some embodiments of this application, forming a write transistor connected to the second gate electrode on the side of the second gate electrode away from the substrate, and connecting the write transistor to the bit line includes:

[0228] Before forming an insulating layer covering the second electrode and the second gate electrode on a surface away from the substrate, a lead connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate;

[0229] After forming the insulating layer covering the bit line on the substrate surface, the bit line and the insulating layer on both sides are etched along the direction toward the substrate to form a plurality of fourth trenches penetrating the bit line and the insulating layer on both sides, the fourth trenches extending along the row direction and each of the fourth trenches exposing a row of leads spaced apart along the row direction;

[0230] A second initial semiconductor layer, a gate insulating layer, and a third gate electrode layer are sequentially formed in the fourth trench;

[0231] The second initial semiconductor layer and the third gate electrode layer are disconnected in the row direction to obtain a plurality of second semiconductor layers and a plurality of third gate electrodes spaced apart; the second semiconductor layers are connected to the bit lines;

[0232] A writing line layer is formed on a surface away from the substrate;

[0233] The writing line layer is patterned and etched to form a plurality of writing lines that extend along the row direction and are spaced apart in the column direction; each writing line is connected to a plurality of third gate electrodes that are spaced apart along the row direction.

[0234] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0235] As shown in Figures 5A to 15C and Figures 2A to 2F, in an exemplary embodiment, the method of manufacturing the semiconductor device may include the following processes.

[0236] S10: A first electrode layer P1', a first sacrificial layer 11, a second electrode layer P2' and a hard mask layer HM are sequentially formed on the substrate 10 to obtain a stacked structure, as shown in Figures 5A and 5B.

[0237] For example, step S10 may include:

[0238] S11: The first electrode layer P1', the first sacrificial layer 11, and the second electrode layer P2', formed of crystalline material, are sequentially grown on one side surface of the substrate 10 using an epitaxial growth method.

[0239] S12: A hard mask layer HM is formed on the surface of the second electrode layer P2' away from the substrate 10 to obtain a stacked structure.

[0240] For example, the materials of the first electrode layer P1' and the second electrode layer P2' can be the same, for example, both can be N-type doped single crystal silicon, or both can be P-type doped single crystal silicon; the material of the first sacrificial layer 11 can be single crystal silicon germanium.

[0241] For example, the substrate 10 can be an N-well silicon substrate, which is widely used in complementary metal-oxide-semiconductor (CMOS) processes. It can serve as a carrier for PMOS transistors and form a reverse-biased well-substrate structure with the PMOS transistors to achieve electrical isolation and avoid parasitic leakage current.

[0242] S20: A first trench T1 is formed in the stacked structure, extending through the stacked structure in a direction toward the substrate 10 and in a row direction parallel to the substrate 10. The first trench T1 has first transverse grooves H1 on both sides extending into the first sacrificial layer 11 and extending in the row direction.

[0243] For example, step S20 may include the following steps S21 and S22.

[0244] S21: The stacked structure is etched along the direction toward the substrate 10 to form a plurality of first trenches T1 that penetrate the stacked structure in the direction toward the substrate 10. The plurality of first trenches T1 extend along the row direction and are spaced apart in the column direction parallel to the substrate 10, as shown in Figures 6A and 6B.

[0245] As shown in Figures 6A and 6B, the first trench T1 can extend into the substrate 10 and is perpendicular to the substrate 10.

[0246] In this application, the column direction intersects the row direction; for example, the column direction and the row direction can be perpendicular to each other. For example, the column direction can be the AA direction as shown in Figure 5A; the row direction can be the BB direction as shown in Figure 5A.

[0247] In this application, multiple components distributed along the row direction can be referred to as a row component, for example, a row of storage cells. Multiple components distributed along the column direction can be referred to as a column component, for example, a column of storage cells.

[0248] S22: Laterally etch the first sacrificial layer 11 on both sides within the first trench T1 to form a first lateral groove H1 extending into the first sacrificial layer 11 and along the row direction on both sides of the first trench T1, as shown in Figures 7A and 7B. The cross-section in Figure 7A passes through the first lateral groove H1.

[0249] S30: A first initial semiconductor layer C1' is formed in the first transverse groove H1, and a second sacrificial layer 12 is formed in the first trench T1, as shown in Figures 8A and 8B. The cross-section in Figure 8A passes through the first initial semiconductor layer C1'.

[0250] For example, step S30 may include:

[0251] S31: Using the first sacrificial layer 11 exposed by the first transverse groove H1 as a template, a first initial semiconductor layer C1' is formed in the first transverse groove H1 and the first trench T1 by epitaxial growth of crystalline material;

[0252] S32: Etching to remove the first initial semiconductor layer C1' within the first trench T1;

[0253] S33: A second sacrificial layer 12 is formed within the first trench T1.

[0254] S40: A second trench T2 is formed on the same side of each second sacrificial layer 12, extending through the stacked structure in the direction toward the substrate 10 and along the row direction; one side of the second trench T2 exposes the second sacrificial layer 12, and the other side has a second lateral groove H2 located between the first electrode layer P1' and the second electrode layer P2', and the second lateral groove H2 exposes the first initial semiconductor layer C1'.

[0255] For example, step S40 may include:

[0256] S41: The stacked structure located on the same side of each second sacrificial layer 12 (e.g., the right side shown in FIG. 9B) and a first initial semiconductor layer C1' (e.g., a first initial semiconductor layer C1' on the right sidewall of the second sacrificial layer 12 shown in FIG. 9B) are etched along the direction toward the substrate 10 to form a second trench T2 that penetrates the stacked structure and extends along the row direction; the width of the second trench T2 in the column direction parallel to the substrate 10 is greater than or equal to the width of a first initial semiconductor layer C1' in the column direction, so that a first initial semiconductor layer C1' is removed during the etching of the second trench T2, so that the second sacrificial layer 12 is exposed on one side of the second trench T2 located on the first sacrificial layer 11 and the first sacrificial layer 11 is exposed on the other side;

[0257] S42: The exposed first sacrificial layer 11 is etched within the second trench T2 to remove it, resulting in a second lateral groove H2 located between the first electrode layer P1' and the second electrode layer P2'. The second lateral groove H2 extends along the row direction and exposes the first initial semiconductor layer C1', as shown in Figures 9A and 9B. In Figure 9A, the cross-section passes through the first initial semiconductor layer C1'.

[0258] S50: A gate insulating layer 13 is formed on the inner wall of the second trench T2 and the second transverse groove H2, a read word line RWL is formed in the second transverse groove H2, and an isolation layer 14 is formed in the second trench T2.

[0259] For example, step S50 may include:

[0260] S51: A gate insulating layer 13 and a second gate electrode layer G2' are sequentially formed in the second trench T2 and the second transverse groove H2, as shown in Figures 10A and 10B, wherein the cross section in Figure 10A passes through the first initial semiconductor layer C1'.

[0261] S52: Remove the second gate electrode layer G2' in the second trench T2, and retain the second gate electrode layer G2' in the second transverse groove H2 as the read line RWL. The read line RWL includes a plurality of first gate electrodes G1 integrally connected.

[0262] S53: An isolation layer 14 is formed in the second trench T2, as shown in Figures 11A and 11B. In Figure 11A, the cross-section passes through the first initial semiconductor layer C1'.

[0263] S60: Remove the second sacrificial layer 12, and sequentially form a gate insulating layer 13 and a first gate electrode layer G1' within the first trench T1, as shown in Figures 12A and 12B. The cross-section in Figure 12A passes through the first initial semiconductor layer C1'.

[0264] S70: The first initial semiconductor layer C1', the first electrode layer P1', the second electrode layer P2' and the first gate electrode layer G1' are disconnected in the row direction to obtain a plurality of first semiconductor layers C1, a plurality of first electrodes P1, a plurality of second electrodes P2 and a plurality of second gate electrodes G2 that are spaced apart.

[0265] For example, step S70 may include:

[0266] S71: The first electrode layer P1', the first initial semiconductor layer C1', the second electrode layer P2', the first gate electrode layer G1' and the isolation layer 14 are etched along the direction toward the substrate 10 to form a third trench T3 extending in a column direction parallel to the substrate 10;

[0267] Among them, the third trench T3 has different depths in different regions along its extension direction:

[0268] In the region where the first gate electrode layer G1', the isolation layer 14 and the first initial semiconductor layer C1' are located, the third trench T3 penetrates the first gate electrode layer G1', the isolation layer 14, the first initial semiconductor layer C1' and the first electrode layer P1' and the second electrode layer P2' on both sides of the first initial semiconductor layer C1' and exposes the substrate 10.

[0269] In the region where the reading line RWL is located, the third trench T3 only penetrates the second electrode layer P2' on one side of the reading line RWL and exposes the reading line RWL;

[0270] S72: An insulating layer 15 is filled in the third trench T3. The insulating layer 15 in the third trench T3 breaks the first initial semiconductor layer C1', the first electrode layer P1', the second electrode layer P2', and the first gate electrode layer G1' in the row direction, respectively obtaining a plurality of first semiconductor layers C1, a plurality of first electrodes P1, a plurality of second electrodes P2, and a plurality of second gate electrodes G2 spaced apart, as shown in Figures 13A to 13C. Among them, the longitudinal section in Figure 13B passes through the first semiconductor layer C1.

[0271] S80: A lead L1 connected to the second gate electrode G2 is formed on the side of the second gate electrode G2 away from the substrate 10.

[0272] The function of lead L1 is to bring out the second gate electrode G2 so that the second gate electrode G2 can be connected to the write transistor. In some embodiments, lead L1 may not be provided, and the second gate electrode G2 can be directly connected to the write transistor.

[0273] For example, the lead L1 and the second gate electrode G2 can be made of the same material. The lead L1 can extend to the surface of the isolation layer 14 and be spaced apart in rows and columns parallel to the substrate, corresponding to the second gate electrode G2.

[0274] S90: A bit line BL connected to the second electrode P2 is formed on the side of the second electrode P2 away from the substrate 10, as shown in Figures 14A to 14C.

[0275] For example, step S90 may include:

[0276] S91: An insulating layer 15 is formed on a surface away from the substrate 10, covering the second electrode P2 and the second gate electrode G2;

[0277] S92: A first through hole is etched in the insulating layer 15 above each second electrode P2, and each first through hole exposes a second electrode P2.

[0278] For example, if the second electrode P2 contains silicon, step S92 may further include: filling the bottom of the first through hole with metal material and annealing it to react the metal material with the silicon in the second electrode P2 to form a metal silicide, and removing the unreacted metal material; the formation of the metal silicide can reduce the contact resistance between the second electrode P2 and the subsequent connection signal line L2.

[0279] S93: A connection signal line L2 is formed in the first through hole;

[0280] S94: A bit line layer covering the connection signal line L2 is formed on the surface away from the substrate 10;

[0281] S95: The bit line layer is patterned and etched to form multiple bit lines BL extending in a column direction parallel to the substrate 10 and spaced apart in the row direction. Each bit line BL is connected to multiple connection signal lines L2 spaced apart in the column direction.

[0282] S100: A write transistor connected to the second gate electrode G2 is formed on the side of the second gate electrode G2 away from the substrate 10, and the write transistor is connected to the bit line.

[0283] For example, step S100 may include:

[0284] S101: An insulating layer 15 covering the bit line BL is formed on the surface away from the substrate 10;

[0285] S102: Etch the bit line BL and the insulating layer 15 on both sides in the direction toward the substrate 10 to form a plurality of fourth trenches that penetrate the bit line BL and the insulating layer 15 on both sides. The fourth trenches extend along the row direction and each of the fourth trenches exposes a row of leads L1 that are spaced apart along the row direction.

[0286] S103: A second initial semiconductor layer C2', a gate insulating layer 13 and a third gate electrode layer are sequentially formed in the fourth trench;

[0287] S104: The second initial semiconductor layer C2', the gate insulating layer 13, and the third gate electrode layer are disconnected in the row direction using a photolithography etching process, resulting in a plurality of spaced-apart second semiconductor layers C2 and a plurality of third gate electrodes G3. A column of spaced-apart second semiconductor layers C2 is connected to the bit line BL, as shown in Figures 15A to 15C. The cross-section in Figure 15A passes through the second semiconductor layer C2.

[0288] S110: A write line WWL connected to the third gate electrode G3 is formed on the side of the write transistor away from the substrate 10.

[0289] For example, step S110 may include:

[0290] S111: A writing line layer is formed on the surface away from the substrate 10;

[0291] S112: The writing line layer is patterned and etched to form a plurality of writing lines WWL extending along the row direction and spaced apart in the column direction; each writing line WWL is connected to a plurality of third gate electrodes G3 spaced apart along the row direction to obtain a semiconductor device as shown in Figures 2A to 2F.

[0292] This application also provides an electronic device, which includes the transistor or semiconductor device described above, or a semiconductor device obtained by the manufacturing method described above.

[0293] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0294] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A transistor, comprising: A first electrode, a second electrode, a first semiconductor layer, a first gate electrode, and a second gate electrode are located on a substrate; The first electrode and the second electrode are spaced apart along a direction perpendicular to the substrate; The first gate electrode and the second gate electrode are distributed on both sidewalls of the first semiconductor layer along a column direction parallel to the substrate. A gate insulating layer is provided between the first gate electrode and the first semiconductor layer, and between the first semiconductor layer and the second gate electrode. The first gate electrode and the first semiconductor layer are located between the first electrode and the second electrode, and the second gate electrode is located on the side of the first electrode and the second electrode that are distributed along the column direction. Both the first semiconductor layer and the second gate electrode extend in a direction perpendicular to the substrate.

2. The transistor according to claim 1, wherein, The first gate electrode extends in a row direction parallel to the substrate, and the circumferential sidewalls of the first gate electrode are partially surrounded by the gate insulating layer.

3. The transistor according to claim 2, wherein, The first gate electrode has sidewalls extending along the row direction; the gate insulating layer surrounds the two sidewalls of the first gate electrode distributed in a direction perpendicular to the substrate and the one sidewall of the first gate electrode distributed in the column direction.

4. The transistor according to claim 2 or 3, wherein, Both the first electrode and the second electrode have a first end and a second end that are spaced apart along the column direction; The gate insulating layer surrounding the first gate electrode extends to the end faces of the first electrode and the second electrode at the first ends, to the side surface of the first electrode away from the substrate, and to the side surface of the second electrode close to the substrate.

5. The transistor according to any one of claims 1 to 4, wherein, The gate insulating layer surrounds the circumferential sidewall of the second gate electrode and the end face near one end of the substrate; The gate insulating layer surrounding the second gate electrode extends to the end faces of the second ends of the first electrode and the second electrode.

6. The transistor according to any one of claims 1 to 5, wherein, The material of the first semiconductor layer is single-crystal silicon.

7. A semiconductor device, comprising: Multiple memory cells located on the substrate; The plurality of memory cells are distributed at intervals along column and row directions parallel to the substrate; The storage cell includes read transistors and write transistors stacked along a direction perpendicular to the substrate; the read transistors are transistors according to any one of claims 1 to 6.

8. The semiconductor device according to claim 7, wherein, The write transistor includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, and a third gate electrode; The third electrode and the fourth electrode are spaced apart along a direction perpendicular to the substrate; the third electrode is connected to the second gate electrode located in the same memory cell; and / or, the third electrode and the second gate electrode are connected by a lead. The second semiconductor layer and the third gate electrode both extend in a direction perpendicular to the substrate; the second semiconductor layer at least partially surrounds the third gate electrode.

9. The semiconductor device according to claim 8, wherein, The storage unit also includes a storage node; The storage node is connected to the second gate electrode and the third electrode respectively; and / or, the storage node and at least one of the second gate electrode and the third electrode are integrally formed.

10. The semiconductor device according to claim 8 or 9, further comprising: Reading lines, writing lines, and position lines; The word line extends along the row direction and is connected to the first gate electrode of a row of memory cells spaced apart along the row direction; And / or, The write lines extend along the row direction and are connected to the third gate electrode of a row of memory cells spaced apart along the row direction; and / or, The bit line extends along the column direction and is connected to the second and fourth electrodes of a column of memory cells spaced apart along the column direction; and / or, The reading line and the first gate electrode are an integral structure; and / or, The bit line and the fourth electrode are integrally integrated; and / or The second electrode contains metal silicide.

11. A method for manufacturing a semiconductor device, comprising: A first electrode layer, a first sacrificial layer, and a second electrode layer are sequentially formed on a substrate to obtain a stacked structure. A first trench is formed in the stacked structure, extending through the stacked structure in a direction toward the substrate and in a row direction parallel to the substrate, and the first trench has first lateral grooves on both sides extending into the first sacrificial layer and extending in the row direction. A first initial semiconductor layer is formed in the first transverse groove, and a second sacrificial layer is formed in the first trench; A second trench is formed on the same side of each of the second sacrificial layers, extending through the stacked structure in a direction toward the substrate and along the row direction; The second trench exposes the second sacrificial layer on one side and has a second lateral groove located between the first electrode layer and the second electrode layer on the other side, with the second lateral groove exposing the first initial semiconductor layer. A gate insulating layer is formed on the inner wall of the second trench and the second lateral groove, a read line is formed in the second lateral groove, and an isolation layer is formed in the second trench; Remove the second sacrificial layer, and sequentially form a gate insulating layer and a first gate electrode layer in the first trench; The first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer are disconnected in the row direction to obtain a plurality of first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes that are spaced apart.

12. The manufacturing method according to claim 11, wherein, The first trench formed in the stacked structure extends through the stacked structure in a direction toward the substrate and in a row direction parallel to the substrate, the first trench having first lateral grooves on both sides extending into the first sacrificial layer and extending in the row direction, including: The stacked structure is etched along the direction toward the substrate to form a plurality of first trenches that penetrate the stacked structure. The plurality of first trenches extend along the row direction and are spaced apart in the column direction parallel to the substrate. The first sacrificial layer on both sides is laterally etched within the first trench to form a first lateral groove on both sides of the first trench that extends into the first sacrificial layer and extends along the row direction.

13. The manufacturing method according to claim 11 or 12, wherein, A second trench is formed on the same side of each of the second sacrificial layers, extending through the stacked structure in a direction toward the substrate and along the row direction; The second trench exposes the second sacrificial layer on one side and has a second lateral groove located between the first electrode layer and the second electrode layer on the other side. The second lateral groove exposes the first initial semiconductor layer, including: The stacked structure and a first initial semiconductor layer located on the same side of each of the second sacrificial layers are etched along the direction toward the substrate to form a second trench that penetrates the stacked structure and extends along the row direction; The width of the second trench in the column direction parallel to the substrate is greater than or equal to the width of the first initial semiconductor layer in the column direction, such that the second trench located on one side of the first sacrificial layer exposes the second sacrificial layer, and the first sacrificial layer exposes the other side. The exposed first sacrificial layer is etched in the second trench to remove the first sacrificial layer, thereby obtaining a second lateral groove located between the first electrode layer and the second electrode layer. The second lateral groove extends along the row direction and exposes the first initial semiconductor layer.

14. The manufacturing method according to any one of claims 11 to 13, wherein, The step of forming a gate insulating layer on the inner wall of the second trench and the second lateral groove, forming a read word line in the second lateral groove, and forming an isolation layer in the second trench includes: A gate insulating layer and a second gate electrode layer are sequentially formed in the second trench and the second lateral groove; Remove the second gate electrode layer in the second trench and retain the second gate electrode layer in the second transverse groove as the read line; The isolation layer is formed within the second trench.

15. The manufacturing method according to any one of claims 11 to 14, wherein, The step of breaking the first initial semiconductor layer, the first electrode layer, the second electrode layer, and the first gate electrode layer in the row direction to obtain a plurality of first semiconductor layers, a plurality of first electrodes, a plurality of second electrodes, and a plurality of second gate electrodes spaced apart includes: The first electrode layer, the first initial semiconductor layer, the second electrode layer, the first gate electrode layer, and the isolation layer are etched along the direction toward the substrate to form a third trench extending in a column direction parallel to the substrate. The third trench has different depths in different regions along its extension direction: In the region where the first gate electrode layer, the isolation layer, and the first initial semiconductor layer are located, the third trench penetrates the first gate electrode layer, the isolation layer, the first initial semiconductor layer, and the first electrode layers and the second electrode layers on both sides of the first initial semiconductor layer, and exposes the substrate. In the area where the reading line is located, the third trench only penetrates the second electrode layer on one side of the reading line and exposes the reading line; The third trench is filled with insulating material.

16. The manufacturing method according to any one of claims 11 to 15, wherein, The step of sequentially forming a first electrode layer, a first sacrificial layer, and a second electrode layer on a substrate includes: A first electrode layer, a first sacrificial layer, and a second electrode layer, formed of crystalline materials, are sequentially grown on the substrate using an epitaxial growth method. The formation of the first initial semiconductor layer within the first transverse groove includes: Using the first sacrificial layer exposed by the first transverse groove as a template, an epitaxial growth method is used to form the first initial semiconductor layer on the sidewall of the first sacrificial layer; The material of the first sacrificial layer is crystalline silicon germanium, and the material of the first initial semiconductor layer is crystalline silicon.

17. The manufacturing method according to any one of claims 11 to 16, further comprising: After forming multiple spaced second gate electrodes, A bit line connected to the second electrode is formed on the side of the second electrode away from the substrate; as well as A write transistor connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate, and the write transistor is connected to the bit line.

18. The manufacturing method according to claim 17, wherein, The step of forming a bit line connected to the second electrode on the side of the second electrode away from the substrate includes: An insulating layer is formed on a surface away from the substrate, covering the second electrode and the second gate electrode; A first via is etched in the insulating layer above each of the second electrodes, and each first via exposes a second electrode; A connection signal line is formed in the first through hole; A bit line layer covering the connection signal lines is formed on a surface away from the substrate; The bit line layer is patterned and etched to form multiple bit lines that extend in a column direction parallel to the substrate and are spaced apart in the row direction. Each bit line is connected to multiple connection signal lines that are spaced apart in the column direction. The insulating layer is formed to cover the bit line.

19. The manufacturing method according to claim 18, wherein, Before forming the connection signal line in the first through hole, the method further includes: A metal material is filled at the bottom of the first through hole and annealed. The metal material reacts with silicon in the second electrode to form a metal silicide, and the unreacted metal material is removed.

20. The manufacturing method according to claim 18 or 19, wherein, The step of forming a write transistor connected to the second gate electrode on the side of the second gate electrode away from the substrate and connecting the write transistor to the bit line includes: Before forming an insulating layer covering the second electrode and the second gate electrode on the substrate surface, a lead wire connected to the second gate electrode is formed on the side of the second gate electrode away from the substrate; After forming the insulating layer covering the bit line on the substrate surface, the bit line and the insulating layer on both sides are etched along the direction toward the substrate to form a plurality of fourth trenches penetrating the bit line and the insulating layer on both sides, the fourth trenches extending along the row direction and each of the fourth trenches exposing a row of leads spaced apart along the row direction; A second initial semiconductor layer, a gate insulating layer, and a third gate electrode layer are sequentially formed in the fourth trench; The second initial semiconductor layer and the third gate electrode layer are disconnected in the row direction to obtain a plurality of second semiconductor layers and a plurality of third gate electrodes spaced apart; the second semiconductor layers are connected to the bit lines; A writing line layer is formed on a surface away from the substrate; The writing line layer is patterned and etched to form a plurality of writing lines that extend along the row direction and are spaced apart in the column direction; each writing line is connected to a plurality of third gate electrodes that are spaced apart along the row direction.

21. An electronic device comprising a transistor according to any one of claims 1 to 6, or comprising a semiconductor device according to any one of claims 7 to 10, or comprising a semiconductor device obtained by a manufacturing method according to any one of claims 11 to 20.

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