Server, system, data processing method, device, medium and product

Abstract

A server, a system, a data processing method, a device, a medium and a product. The server comprises at least two accelerator boards (10), a host board (6) and a connection board (7), wherein the at least two accelerator boards (10) are arranged in a direction perpendicular to the surface of the host board (6), the accelerator boards (10) are configured to connect to a plurality of accelerators (3), and each accelerator board (10) comprises switching elements, a plurality of switching elements being in signal connection so as to realize communication between the plurality of accelerators connected to the accelerator board (10); and the connection board (7) is in signal connection with the accelerator boards (10) and the host board (6), such that the host board (10) can be in signal connection with the accelerators, and the accelerators respectively corresponding to the at least two accelerator boards (10) are in signal connection with each other. On the basis of a stacked structure formed by the at least two accelerator boards (10) and the host board (6) and the interconnection between the plurality of switching elements, a multi-board server capable of having a high computing capability is formed.

Description

A server, system, data processing method, device, medium, and product

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510232901.1, filed on February 28, 2025, entitled "A server, system, data processing method, device, medium and product", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of server technology, and more specifically, to servers, server systems, data processing methods, devices, non-volatile storage media, and computer program products. Background Technology

[0004] In recent years, with the rapid development of large models, the computational load of models has shown an exponential growth trend, and the demand for AI (Artificial Intelligence) acceleration computing power is also growing rapidly. The training and inference of a single large model requires multiple AI accelerators to work together.

[0005] In related technologies, when configuring more accelerators, the design of multi-card servers mainly focuses on the design of racks based on multiple accelerators, while the design of single servers based on multiple accelerators is less common, which is not conducive to the later optimization and development of multi-card servers.

[0006] In summary, how to provide a server architecture design based on multiple accelerators is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a server, based on a stacked structure formed by at least two accelerator boards and a motherboard, interconnection between multiple conversion elements, and a connecting board, forming a multi-card server capable of high computing power, so as to facilitate subsequent optimization and development of multi-card servers. Another purpose of this application is to provide a server system, data processing method, device, non-volatile storage medium, and computer program product.

[0008] To achieve the above objectives, this application provides the following technical solution:

[0009] A server, comprising:

[0010] Motherboard, including at least two central processing units;

[0011] Accelerator boards, at least two accelerator boards are stacked in a direction perpendicular to the surface of the host board, and the accelerator boards can be used to connect multiple accelerators;

[0012] The accelerator board includes conversion elements, and multiple conversion elements are signal-connected to the central processing unit. The multiple conversion elements are also signal-connected to each other to enable communication between multiple accelerators connected to the accelerator board.

[0013] The connection board is set perpendicular to the accelerator board and the host board. Both the accelerator board and the host board are connected to the connection board for signal connection. The connection board enables signal connection between the host board and the corresponding accelerators of the accelerator board, and enables signal connection between the accelerators corresponding to at least two accelerator boards.

[0014] On the other hand, the multiple conversion elements corresponding to the accelerator board are connected based on an interconnection protocol. Each conversion element is provided with multiple first interfaces, and at least one first interface corresponding to any two conversion elements is connected.

[0015] On the other hand, the conversion element is provided with multiple second interfaces, which are used to connect multiple accelerators and at least one first network card;

[0016] Alternatively, multiple second interfaces can be used to connect multiple accelerators.

[0017] On the other hand, the conversion element is provided with a third interface, and the corresponding third interface of the conversion element is connected to the central processing unit.

[0018] On the other hand, the conversion element has multiple data channels. The data channel corresponding to the first interface is in Fabric mode, the data channel corresponding to the second interface is in Device mode, and the data channel corresponding to the third interface is in Host mode.

[0019] On the other hand, the connection board includes a cable backplane, and the accelerator board and the main board are all connected to the cable backplane;

[0020] The cable backplane is provided with multiple connector assemblies, which are arranged sequentially along a first direction of the cable backplane. The first direction is consistent with the stacking direction of at least two accelerator boards.

[0021] Multiple connector assemblies are connected to at least two accelerator boards and a host board to enable signal connections between the host board and the accelerator boards, as well as between at least two accelerator boards.

[0022] On the other hand, the connector assembly includes multiple high-density connectors, which are arranged sequentially along a second direction of the cable backplane. The second direction is perpendicular to the first direction, and the plane formed by the second direction and the first direction is perpendicular to the surface of the motherboard.

[0023] The high-density connector has a first end close to the motherboard and accelerator board, and a second end away from the motherboard and accelerator board. The first end is used to plug into the motherboard or accelerator board, and the second end is connected to the transmission cable. The second ends of the two high-density connectors corresponding to any two connector assemblies are connected by a transmission cable.

[0024] On the other hand, multiple conversion elements located on at least two accelerator boards are connected by multiple transmission cables and multiple high-density connectors to form a mesh topology.

[0025] Alternatively, multiple conversion elements located on at least two accelerator boards are connected by multiple transmission cables and multiple high-density connectors to form a ring topology;

[0026] Alternatively, multiple conversion elements located on at least two accelerator boards are connected via multiple transmission cables and multiple high-density connectors to form a dual-ring topology.

[0027] On the other hand, the connection board also includes a power supply backplane, and the accelerator board and the main board are electrically connected to the power supply backplane.

[0028] On the other hand, the server also includes:

[0029] Chassis;

[0030] The power supply unit, the main board, and at least two layers of accelerator boards are stacked sequentially along a direction parallel to the surface of the connecting plate. The power supply unit is electrically connected to the power supply board. The main board and the accelerator boards are both connected to the power supply board through the connecting plate.

[0031] The heat dissipation module, located in the chassis, is used to dissipate heat from the motherboard and accelerator board, and is electrically connected to the power supply board.

[0032] On the other hand, the heat dissipation module includes multiple sets of fans arranged in a direction perpendicular to the surface of the power supply board, with at least one set of fans used for heat dissipation of the host board and at least two sets of fans used for heat dissipation of the accelerator board.

[0033] On the other hand, the motherboard includes:

[0034] The motherboard has a first central processing unit and a second central processing unit;

[0035] A power adapter board connects the motherboard and the connector board, and is used to convert the power supply to a power supply usable by the motherboard.

[0036] The front window input / output module has its mainboard located between the power adapter board and the front window input / output module.

[0037] On the other hand, the motherboard is connected to a management controller, which is set perpendicular to the surface of the motherboard;

[0038] The management controller signals are connected to the first central processing unit, the second central processing unit, the accelerometer board, and the front window input / output module.

[0039] On the other hand, the motherboard is equipped with a logic processing element, which is connected to the accelerator board, the host board, and the power supply board to control the power-on and power-off timing of the accelerator board, the host board, and the power supply board.

[0040] On the other hand, a first signal connector is provided at one end of the power adapter board near the connection board. The socket of the first signal connector is arranged parallel to the surface of the power adapter board, and the socket of the first signal connector is connected to the connector assembly of the cable backplane closest to the motherboard.

[0041] On the other hand, the power adapter board is also provided with a first power connector at one end near the connection board. The socket of the first power connector is arranged parallel to the surface of the power adapter board, and the socket of the first power connector is connected to the second power connector of the power supply backplane that is closest to the motherboard.

[0042] On the other hand, the accelerator board includes a conversion base plate, a slot structure connected to the conversion base plate, multiple conversion elements are disposed on the conversion base plate, and the slot structure is used to connect the accelerator and the first network card.

[0043] The conversion base plate is equipped with a second signal connector, which is set parallel to the surface of the conversion base plate and can be plugged into the cable backplane to realize the signal connection between the accelerator board and the connection board.

[0044] On the other hand, a first connector, a second connector, a third connector, a fourth connector, and a fifth connector are provided on the conversion base plate along the outer periphery of the conversion element;

[0045] Alternatively, a second connector, a third connector, a fourth connector, and a fifth connector may be provided on the base plate along the outer periphery of the conversion element;

[0046] The first connector is used to connect the first network card, the second connector is used to connect the accelerator; the third connector is used to connect the motherboard, the fourth connector is used for interconnection between at least two accelerator boards, and the fifth connector is used for interconnection between conversion elements located on the conversion base plate.

[0047] On the other hand, the accelerator board also includes a power supply board, which is equipped with a third power connector. The third power connector is connected to the power supply backplane of the connection board so that the power supply board can supply power to the conversion base plate and the accelerator.

[0048] On the other hand, the chassis has an installation area, and the slot structure is located in the installation area. There is a gap between the end of the power supply board away from the connection board and the installation area, so as to provide installation space for the accelerator and the first network card to be connected to the slot structure.

[0049] On the other hand, this application also provides a server system, including:

[0050] The server is any of the servers mentioned above;

[0051] An accelerator is a server accelerator board that connects multiple accelerators, which are then connected to each other via a bridge.

[0052] On the other hand, this application also provides a data processing method applied to the aforementioned server system, the data processing method comprising:

[0053] Based on a universal interconnection protocol, at least two accelerator boards' corresponding conversion elements can obtain the data to be processed.

[0054] The data to be processed is processed in parallel using the accelerators connected to each of the conversion elements.

[0055] On the other hand, this application also provides an apparatus comprising:

[0056] Storage elements used to store computer programs;

[0057] A processor is used to execute computer programs to implement the steps of the data processing method described above.

[0058] On the other hand, this application also provides a non-volatile storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data processing method described above.

[0059] On the other hand, this application also provides a computer program product, including a computer program / instructions, characterized in that the computer program / instructions, when executed by a processor, implement the steps of the above-described data processing method.

[0060] The server provided in this application includes at least two accelerator boards, a host board, and a connection board. The at least two accelerator boards are stacked in a direction perpendicular to the surface of the host board. The accelerator boards can connect to multiple accelerators, and each accelerator board includes multiple conversion connections. The multiple conversion elements are all signal-connected to the central processing unit, and the multiple conversion elements are signal-connected to each other to realize communication connections between the multiple accelerators connected to the accelerator boards. The connection board is set perpendicular to the accelerator boards and the host board to enable signal connections between the host board and the accelerators. The connection board enables signal connections between the accelerators corresponding to the at least two accelerator boards, allowing the accelerators connected to the at least two accelerator boards to process calculations in parallel, improving the server's computing power and forming a high-computing-power server structure.

[0061] The beneficial effects of this application are: based on the stacked structure formed by at least two accelerator boards and a host board, the interconnection between multiple conversion elements and the connecting board, a multi-card server with high computing power is formed, so as to facilitate subsequent optimization and development of multi-card servers. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0063] Figure 1 is a schematic diagram of the first topology provided in this application.

[0064] Figure 2 is a schematic diagram of the connection between the first topology provided in this application and the accelerator.

[0065] Figure 3 is a schematic diagram of another connection between the first topology provided in this application and the accelerator.

[0066] Figure 4 is a schematic diagram of the server architecture provided in this application.

[0067] Figure 5 is a schematic diagram of the server structure provided in this application.

[0068] Figure 6 is a schematic diagram of the internal structure of the server provided in this application.

[0069] Figure 7 is a schematic diagram of the front window of the server provided in this application.

[0070] Figure 8 is a schematic diagram of the back window of the server provided in this application.

[0071] Figure 9 is a schematic diagram of the motherboard provided in this application.

[0072] Figure 10 is a schematic diagram of the PCIE resource allocation method of the motherboard provided in this application.

[0073] Figure 11 is a logic block diagram of the motherboard provided in this application.

[0074] Figure 12 is a power-on timing logic diagram of the server provided in this application.

[0075] Figure 13 is a schematic diagram of the accelerator board provided in this application.

[0076] Figure 14 is a schematic diagram of the internal structure of the accelerator board provided in this application.

[0077] Figure 15 is a structural schematic diagram of the first type of conversion base plate provided in this application.

[0078] Figure 16 is a schematic diagram of the power supply board provided in this application.

[0079] Figure 17 is a logic block diagram of the accelerator board provided in this application.

[0080] Figure 18 is a structural schematic diagram of the connecting plate provided in this application.

[0081] Figure 19 is another structural schematic diagram of the connecting plate provided in this application.

[0082] Figure 20 is a schematic diagram of the first connection relationship of the transmission cable on the connection board provided in this application.

[0083] Figure 21 is a schematic diagram of the structure of the device provided in this application.

[0084] Figure 22 is a schematic diagram of the second topology provided in this application.

[0085] Figure 23 is a schematic diagram of the connection between the second topology provided in this application and the accelerator.

[0086] Figure 24 is a schematic diagram of the second connection relationship of the transmission cable on the connection board provided in this application.

[0087] Figure 25 is a structural schematic diagram of the second type of conversion base plate provided in this application.

[0088] Figure 26 is a schematic diagram of the third topology provided in this application.

[0089] Figure 27 is a schematic diagram of the connection between the third topology provided in this application and the accelerator.

[0090] Figure 28 is a schematic diagram of the third connection relationship of the transmission cable on the connection board provided in this application.

[0091] Figure 29 is a structural schematic diagram of the third type of conversion base plate provided in this application.

[0092] In Figures 1-29, the reference numerals include:

[0093] 1-Conversion element; 101-First interface; 102-Second interface; 103-Third interface;

[0094] 2-First Central Processing Unit; 3-Accelerator; 4-First Network Interface Card (NIC); 5-Second Central Processing Unit (CPU); 6-Mainboard; 7-Connection Board; 8-Heat Dissipation Module; 9-Power Supply Board; 10-Accelerator Board; 11-Management Controller; 12-USB Controller; 13-M.2 (Computer Internal Expansion Card Standard) Hard Drive; 14-Second NIC; 15-Clock; 16-Memory; 17-User Interface Board; 18-Multiplexer; 19-BMC (Baseboard Management Controller) Firmware; 20-Dynamic Memory; 21-Embedded Multimedia Card; 22-Port Physical Layer; 23-Front Window RJ45 (Registered Jack 45) Port; 24-Converter; 25-Front Window VGA (Video Graphics Array) Port; 26-Front Window Type-C (USB) Port Type-C (Universal Serial Bus Type-C) socket; 27-Logic processing element; 28-MISC (Miscellaneous); 29-FRU (Field Replaceable Unit); 30-Temperature sensor; 31-Fan assembly; 32-Power supply unit; 33-Solid-state drive; 34-Chassis; 35-Processor; 36-Display; 37-Power supply; 38-Communication interface; 39-Input / output interface; 40-Communication bus; 41-Storage element; 411-Computer program; 412-Operating system; 413-Data;

[0095] 603 - Front window I / O module; 604 - Mainboard; 605 - Power adapter board; 6032 - Front window I / O (Input / Output) panel; 6041 - MCIO (Multi-Gigabit Channelized I / O) connector; 6042 - Voltage regulation module; 6043 - DIMM (Dual In-line Memory Module)

[0096] Connectors; 6051 - Adapter module; 6052 - First power connector; 6053 - First signal connector;

[0097] 701 - Transmission cable; 702 - Power supply backplane; 703 - Cable backplane; 7021 - Second power connector; 7031 - High-density connector;

[0098] 801 - Fan; 901 - Power connector;

[0099] 1001 - Converter baseboard; 1002 - Power supply board; 10011 - Second signal connector; 10012 - First connector; 10013 - Second connector; 10014 - Third connector; 10015 - Fourth connector; 10016 - Fifth connector; 10017 - Slot power connector; 10018 - Slot structure; 10021 - Third power connector; 10022 - Power converter; 10023 - Accelerator card power connector; 10024 - Baseboard power connector. Detailed Implementation

[0100] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0101] The core of this application is to provide a server that, through a stacked structure formed by at least two accelerator boards and a motherboard, interconnection between multiple conversion elements, and a connecting board, can form a multi-card server with high computing power, facilitating subsequent optimization and development of multi-card servers. Another core aspect of this application is to provide a server system, data processing method, device, non-volatile storage medium, and computer program product.

[0102] The server provided in this application includes at least two accelerator boards 10, a host board 6, and a connection board 7, as shown in Figures 5 and 6.

[0103] Motherboard 6 includes at least two central processing units, corresponding to a server configuration of at least a dual-processor server.

[0104] At least two accelerator boards 10 are stacked along a direction perpendicular to the surface of the host board 6. The at least two accelerator boards 10 and the host board 6 can form at least a three-layer server architecture. The host board 6 is the main control board of the server, while the accelerator boards 10 are the computing power part of the server.

[0105] Accelerator board 10 is used to connect multiple accelerators 3, and the computing efficiency of the server is improved by configuring accelerators 3 to meet higher computing power requirements. Specifically, each accelerator board 10 can be configured with two, three, four or more accelerators 3.

[0106] The accelerator board 10 includes a conversion element 1, which is signal-connected to the central processing unit. Multiple conversion elements 1 are signal-connected to each other; specifically, multiple conversion elements 1 within the same accelerator board 10 can be interconnected. The communication protocol for interconnection is not limited here, as long as it meets the usage requirements.

[0107] Please refer to Figures 1, 2, 3, 22, 23, 26, and 27. Through the interconnection between multiple conversion elements 1, multiple accelerators 3 connected to the accelerator board 10 can communicate with each other. When the central processing unit of the host board 6 sends data to be processed to the accelerators 3 through the conversion elements 1, multiple accelerators 3 can perform parallel processing to improve computing power.

[0108] Taking one specific implementation as an example, if each accelerator board 10 is provided with two conversion elements 1, then at least two accelerator boards 10 can be provided with at least four conversion elements 1, and the at least four conversion elements 1 are interconnected. Based on the premise that each conversion element 1 can connect to multiple accelerators 3, for example, a common scenario where one conversion element 1 connects to four x16 interface accelerators 3, then at least two accelerator boards 10 can connect to at least 16 accelerators 3, corresponding to a 16-card server. Alternatively, if a common scenario is that one conversion element 1 connects to eight x8 interface accelerators 3, then at least two accelerator boards 10 can connect to at least 32 accelerators 3, corresponding to a 32-card server.

[0109] Specifically, accelerator 3 can be any of, but is not limited to, FPGA (Field-Programmable Gate Array), GPU (Graphics Processing Unit), or ASIC (Application-Specific Integrated Circuit).

[0110] The main board 6 and at least two accelerator boards 10 are arranged perpendicular to the connecting board 7 so that the connecting board 7 can establish a signal connection with the main board 6 and each accelerator board 10.

[0111] The main board 6 and at least two accelerator boards 10 are all connected to the connection board 7, which enables signal connection between the main board 6 and the accelerator boards 10. In other words, it enables signal connection between the main board 6 and the corresponding accelerator 3 of the accelerator boards 10. Essentially, the central processing unit can be connected to the accelerator 3 through the conversion element 1, and the central processing unit can send the data to be processed to each accelerator 3.

[0112] At least two accelerator boards 10 are signal connected to the connection board 7, so that the signal connection between the at least two accelerator boards 10 can be realized through the connection board 7. Then, the accelerators 3 corresponding to the at least two accelerator boards 10 can form a signal connection, so that the multiple accelerators 3 corresponding to each other can process data in parallel, thereby having better parallel computing capabilities, improving server computing efficiency, and meeting higher computing power requirements.

[0113] In the above process, without considering the inter-card interconnection protocol supported by the accelerators 3, the number of accelerators 3 configured in the server can be effectively increased through a stacked architecture, achieving extreme computing power density, high inter-card communication bandwidth, and low communication latency. Specifically, the server includes, but is not limited to, servers capable of supporting 16 and 32 cards, effectively improving the server's computing efficiency.

[0114] Furthermore, the layered architecture allows each layer to be relatively independent and isolated from the others, enabling simple interconnection between boards and convenient maintenance of each board. It can be widely used in AI scenarios such as inference and training, improving training and inference performance and enhancing product competitiveness.

[0115] In a preferred embodiment, if the accelerators 3 can support the card interconnection protocol themselves, then in addition to increasing the number of accelerators 3, it is possible to further increase the communication bandwidth, improve the parallel computing capability, and improve the computing efficiency of the server.

[0116] The aforementioned server, through at least two accelerator boards 10 and a host board 6, can form at least a three-layer server architecture. The use of interconnecting conversion elements 1 and connection boards 7 enables communication between the corresponding accelerators 3, allowing for parallel data processing and enhancing the server's computing power. Specifically, this architecture forms a server with high computing power, providing a foundation for design and development.

[0117] Based on the above embodiments, the multiple conversion elements 1 corresponding to the accelerator board 10 are connected based on an interconnection protocol.

[0118] The interconnection protocols include, but are not limited to, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) and CXL (Compute Express Link, a new type of high-speed interconnection technology). This universal interconnection protocol enables the accelerator 3 configured on the accelerator board 10 to have good compatibility, allowing the accelerator board 10 to be adapted to accelerators 3 from different manufacturers.

[0119] The conversion element 1 is provided with multiple first interfaces 101, and at least two first interfaces 101 corresponding to any two conversion elements 1 are connected. Here, any two conversion elements 1 refer to two conversion elements 1 located on the same accelerator board 10 or two conversion elements 1 located on different accelerator boards 10. Through the configuration of the first interfaces 101, an interconnection topology can be formed between the conversion elements 1 corresponding to at least two accelerator boards 10, forming a fully interconnected network, so as to realize the communication connection between all accelerators 3 corresponding to at least two accelerator boards 10 through the interconnection between the conversion elements 1.

[0120] In one specific embodiment, referring to Figure 1, the conversion element 1 is provided with three first interfaces 101. Two conversion elements 1 are connected through two corresponding first interfaces 101, that is, any two conversion elements 1 are connected through one corresponding first interface 101. Referring to Figure 4, if the accelerator board 10 includes two interconnected conversion elements 1, and assuming two accelerator boards 10 are provided, then as shown in Figure 1, a 2×2 fully interconnected topology can be formed through four conversion elements 1. Specifically, each of the four conversion elements 1 can be connected to the other conversion elements 1 to form a fully interconnected network. As shown in Figure 2, the four conversion elements 1 are named SW-0, SW-1, SW-2, and SW-3 respectively. The three first interfaces 101 on SW-0 are connected to SW-1, SW-2, and SW-3 respectively; the three first interfaces 101 on SW-1 are connected to SW-0, SW-2, and SW-3 respectively; the three first interfaces 101 on SW-2 are connected to SW-0, SW-1, and SW-3 respectively; and the three first interfaces 101 on SW-3 are connected to SW-0, SW-1, and SW-2 respectively. As shown in Figures 2 and 3, each conversion element 1 has three buses leading out to connect to the other three conversion elements 1.

[0121] In this specific implementation, communication interconnection is achieved between all accelerators 3 corresponding to the four conversion elements 1 through interconnection. This eliminates the need for accelerators 3 to support interconnection protocols; scale-up interconnection between accelerators 3 is directly achieved through the interconnection of the four conversion elements 1. Furthermore, based on an open-source interconnection protocol between conversion elements 1, this implementation enables a scale-up full interconnection scheme for 16 double-width (x16 interface) or 32 single-width (x8 interface) accelerators 3. If the interface of the conversion element 1 is a PCIe 5.0 interface, the corresponding bandwidth is 128GB / s, and the inter-card interconnection bandwidth can reach 384GB / s. The inter-card communication latency is in the tens of nanoseconds (ns). Due to the ecosystem compatibility of the interconnection protocol, it can be applied to accelerators 3 from different manufacturers, improving compatibility.

[0122] In another specific implementation, please refer to Figures 22 and 23. Two conversion elements 1 are connected to a first interface 101 corresponding to each other. As shown in Figure 23, the four conversion elements 1 are named SW-0, SW-1, SW-2, and SW-3 respectively. One of the two first interfaces 101 on SW-0 connects to SW-1 and the other to SW-2. One of the two first interfaces 101 on SW-1 connects to SW-0 and the other to SW-3. One of the two first interfaces 101 on SW-2 connects to SW-0 and the other to SW-3. One of the two first interfaces 101 on SW-3 connects to SW-1 and the other to SW-2. As shown in Figures 22 and 23, each conversion element 1 has two buses leading out to connect to the other two conversion elements 1. In this case, if the interface of the conversion element 1 is a PCIe 5.0 interface, the corresponding bandwidth is 128GB / s. Therefore, the inter-card interconnect bandwidth under this interconnect topology can reach 256GB / s.

[0123] In another specific implementation, referring to Figures 26 and 27, the two conversion elements 1 are connected through four corresponding first interfaces 101, that is, the two first interfaces 101 corresponding to the two conversion elements 1 are connected respectively. As shown in Figure 25, the four conversion elements 1 are named SW-0, SW-1, SW-2, and SW-3 respectively. Two of the four first interfaces 101 on SW-0 are connected to SW-1, and two are connected to SW-2. Two of the four first interfaces 101 on SW-1 are connected to SW-0, and two are connected to SW-3. Two of the four first interfaces 101 on SW-2 are connected to SW-0, and two are connected to SW-3. Two of the four first interfaces 101 on SW-3 are connected to SW-1, and two are connected to SW-2. As shown in Figures 26 and 27, each conversion element 1 leads out four buses to connect to the other three conversion elements 1. In this case, if the interface of the conversion element 1 is a PCIe 5.0 interface, the corresponding bandwidth is 128GB / s. Therefore, the inter-card interconnection bandwidth under this interconnection topology can reach 512GB / s.

[0124] Based on any of the above embodiments, referring to Figures 1 and 2, the conversion element 1 is provided with multiple second interfaces 102, which can be four, five, or six. Based on actual server requirements, the internal cables of the conversion element 1 and a corresponding matching connection board 7 can be designed.

[0125] In the first specific implementation, please refer to Figures 1, 2 and 3. The conversion element 1 is provided with five second interfaces 102 for connecting a first network card 4 and four accelerators 3. The four conversion elements 1 are interconnected to form a fully interconnected mesh topology.

[0126] The second interface 102 can connect to the first network interface card 4 because the conversion element 1 is equipped with an interface for connecting the first network interface card 4. This allows the fully interconnected topology to meet the requirements of scale-up interconnection while also ensuring scale-out (horizontal expansion) capability. Specifically, it can scale out networking to expand into a thousand-card cluster or a ten-thousand-card cluster. Scale-out networking to expand into a thousand-card cluster or a ten-thousand-card cluster means adding more nodes to expand a distributed system, thereby forming a cluster containing thousands or tens of thousands of computing nodes.

[0127] In the second specific implementation, referring to Figures 22 and 23, the conversion element 1 is provided with six second interfaces 102, which can be used to connect two first network interface cards 4 and four accelerators 3. As shown in Figure 22, the four interconnected conversion elements 1 form a ring topology. In this form, since the conversion element 1 can connect two first network interface cards 4, the entire server can support higher scale-out interconnect bandwidth to meet the needs of large model training scenarios. Multiple servers can be networked in scale-out mode through more first network interface cards 4, thereby increasing the communication bandwidth between multiple servers.

[0128] In both of the above specific embodiments, the first network card 4 can be a 400G network card. The first network card 4 is connected through the second interface 102, and then further connected to an Ethernet switch or an IB (InfiniBand network) network switch through an optical fiber to perform scale-out network expansion and ensure scale-out capability.

[0129] In the third specific embodiment, referring to Figures 26 and 27, the conversion element 1 is provided with four second interfaces 102, which can be used to connect four accelerators 3. Referring to Figure 26, the four conversion elements 1 can form a double-ring topology. In this form, the interconnection bandwidth between the conversion elements 1 is further enhanced, and the communication bandwidth between the accelerators 3 corresponding to different conversion elements 1 is strengthened. This form is more geared towards inference application scenarios, deploying model computation within a single server. It should be noted that the further enhancement here refers to the ability to design the conversion element 1 so that the second interface 102 originally used to connect the first network card 4 can be changed to the first interface 101 used for interconnection between the conversion elements 1, thereby further enhancing the interconnection bandwidth between the conversion elements 1 compared to the first and second specific embodiments.

[0130] Taking one specific implementation as an example, the conversion element 1 is specifically a PCIe switch module. The second interface 102 connecting the conversion element 1 to the accelerator 3 is a PCIe interface. As a universal and commonly used interface, the PCIe interface is compatible with accelerators 3 from various manufacturers. This improves compatibility based on the PCIe interconnection protocol ecosystem.

[0131] As shown in Figure 3, in one specific implementation, taking an accelerator 3 with x8 interfaces supported by the second interface 102 and four second interfaces 102 connected to the accelerator 3 as an example, each second interface 102 can connect to two accelerators 3, corresponding to eight accelerators 3 connected to each conversion element 1. The entire interconnected topology can connect to 32 accelerators 3, corresponding to a 32-card server. In this method, compared to an 8-card server, the number of accelerators 3 connected to the conversion element 1 is quadrupled, increasing the number of accelerators 3 configured on the server. Without requiring the accelerators 3 to inherently support inter-card interconnection protocols, scale-up interconnection between accelerators 3 can be achieved, doubling the scale-up size of the accelerators 3, increasing interconnection bandwidth, and improving processing capacity.

[0132] As shown in Figure 2, in one specific implementation, taking an accelerator 3 with x16 interface supported by the second interface 102 and four second interfaces 102 for connecting the accelerator 3 as an example, each second interface 102 can connect one accelerator 3, and each conversion element 1 can connect four accelerators 3. The entire fully interconnected topology can connect 16 accelerators 3, corresponding to a 16-card server. In this method, compared to an 8-card server, the number of accelerators 3 connected to the conversion element 1 is doubled, increasing the number of accelerators 3 configured on the server. Without requiring the accelerators 3 to inherently support inter-card interconnection protocols, scale-up interconnection between accelerators 3 can be achieved, doubling the scale-up size of the accelerators 3, increasing interconnection bandwidth, and improving processing capacity.

[0133] The two methods described above only differ in the number of configured accelerators (3). The actual interconnect bandwidth of the four conversion elements (1) is consistent. The bandwidth of the interconnected conversion elements (1) depends on the interface standard. For example, if the conversion element (1) is a Broadcom PCIe Gen5 Switch, a single PCIe Switch module supports 144 PCIe Gen5 lanes (144 data transmission channels under the PCIe 5.0 interface standard). The bandwidth corresponding to the PCIe 5.0 interface standard is 128 GB / s. Therefore, the aggregated communication bandwidth formed by the topology of the four interconnected conversion elements (1) is 384 GB / s. More specifically, four accelerators (3) connected to the same conversion element (1) are considered a group. The four accelerators (3) within a group communicate through the internal processing of the conversion element (1), resulting in an aggregated communication bandwidth of 384 GB / s. Four accelerators (3) in different groups communicate through the interconnect bus between conversion elements (1), also with an aggregated communication bandwidth of 384 GB / s.

[0134] In both of the above methods, since the number of accelerators can be doubled, the number of hosts required is halved compared to the traditional 8-card server cluster or 1,000-card cluster. The number of network card modules, switches, etc. used is also reduced, which reduces management and maintenance costs, computing power costs, overall energy consumption, physical space, and improves transmission speed and efficiency.

[0135] Based on any of the above embodiments, please refer to Figures 1, 2 and 3. The conversion element 1 is provided with a third interface 103, and the third interface 103 corresponding to the conversion element 1 is connected to the central processing unit.

[0136] Taking one specific implementation as an example, if the server is a dual-processor server, then the central processing units corresponding to the host board 6 are the first central processing unit 2 and the second central processing unit 5. The first central processing unit 2 and the second central processing unit 5 are interconnected and communicate with each other through a UPI (Ultra Path Interconnect) bus. Each conversion element 1 is provided with a third interface 103, through which the first central processing unit 2 or the second central processing unit 5 is connected.

[0137] Taking four conversion elements 1 as SW-0, SW-1, SW-2, and SW-3 respectively, and the first central processing unit 2 and the second central processing unit 5 as CPU0 and CPU1 respectively, the third interface 103 on SW-0 and SW-1 is connected to CPU0, while the third interface 103 on SW-2 and SW-3 is connected to CPU1.

[0138] Of course, this application is not limited to dual-processor servers, and the corresponding central processing unit is not limited to the first central processing unit 2 and the second central processing unit 5 mentioned above. In practice, the number of conversion elements 1 and the form of the third interface 103 can be determined according to the specific design of the server.

[0139] Based on any of the above embodiments, the conversion element 1 has multiple data channels, the data channel corresponding to the first interface 101 is in Fabric mode, the data channel corresponding to the second interface 102 is in Device mode, and the data channel corresponding to the third interface 103 is in Host mode.

[0140] Please refer to Figures 1, 22, and 26. When the conversion element 1 is further specified as a Broadcom PCIe GEN5 Switch module, a single PCIe Switch module supports 144 PCIe GEN5 lanes (144 data transmission channels under the PCIe 5.0 interface standard). The 144 data transmission channels are divided into 9 groups, corresponding to the first interface 101, the second interface 102, and the third interface 103 on the conversion element 1. That is, the number of the first interface 101, the second interface 102, and the third interface 103 on each conversion element 1 is 9.

[0141] As shown in Figure 1, each conversion element 1 has 3 x16 data channels configured in Fabric mode (modular architecture mode) corresponding to three first interfaces 101, used for full interconnection between the 4 conversion elements 1 to form a PCIe Fabric network; 1 x16 data channel configured in Host mode (host mode) corresponding to one third interface 103, used to connect to the central processing unit (CPU) to establish a communication connection between the CPU and the conversion element 1; and 5 data channels configured in Device mode (device mode) corresponding to five second interfaces 102, of which 4 x16 data channels are connected to the accelerator 3 and 1 x16 data channel is connected to the first network interface card (NIC) 4.

[0142] As shown in Figures 22 and 23, each conversion element 1 has two sets of x16 data channels configured in Fabric mode corresponding to two first interfaces 101, used for full interconnection between the four conversion elements 1 to form a PCIe Fabric network; one set of x16 data channels is configured in Host mode corresponding to one third interface 103, used to connect to the central processing unit, enabling communication between the central processing unit and the conversion element 1; and six sets of data channels are configured in Device mode corresponding to six second interfaces 102, of which four sets of x16 data channels are connected to four accelerators 3 and two sets of x16 data channels are connected to two first network cards 4.

[0143] As shown in Figures 26 and 27, the four sets of x16 data channels in each conversion element 1 are configured in Fabric mode, corresponding to four first interfaces 101, for full interconnection between the four conversion elements 1 to form a PCIe Fabric network; one set of x16 data channels is configured in Host mode, corresponding to one third interface 103, for connecting to the central processing unit, enabling communication between the central processing unit and the conversion element 1; and four sets of data channels are configured in Device mode, corresponding to four second interfaces 102, for connecting four accelerators 3.

[0144] Based on any of the above embodiments, please refer to Figures 6, 18, and 19. The connection board 7 includes a cable backplane 703, and the accelerator board 10 and the host board 6 are both connected to the cable backplane 703. Here, "connection" refers to signal connection.

[0145] The cable backplane 703 is provided with multiple connector assemblies, which are sequentially arranged along a first direction of the cable backplane 703. The first direction is consistent with the stacking direction of at least two accelerator boards 10; and the stacking direction of the at least two accelerator boards 10 is perpendicular to the surface of the host board 6. By arranging the multiple connector assemblies along the first direction, the stacked architecture formed by the host board 6 and the at least two accelerator boards 10 can be matched. More specifically, the first direction is illustrated as the y-direction in Figures 18 and 19.

[0146] Specifically, the matching refers to the corresponding connection of multiple connector assemblies to at least two accelerator boards 10 and host boards 6, thereby realizing signal connections between host boards 6 and accelerator boards 10, as well as signal connections between at least two accelerator boards 10. Indirectly, this enables signal connections between the central processing unit of host board 6, the conversion element 1 of accelerator boards 10, and the configured accelerators 3, and also enables signal connections between the multiple accelerators 3 configured on at least two accelerator boards 10, thus effectively improving the server's computing power.

[0147] In this embodiment, the number of connector components can be three, four, or more, specifically corresponding to the server architecture. Here, the server architecture refers to the stacked architecture formed by the host board 6 and at least two accelerator boards 10. For example, if the stacked architecture has three layers, then there are three connector components, and so on for other layers.

[0148] Based on any of the above embodiments, the connector assembly includes a plurality of high-density connectors 7031, which are sequentially arranged along a second direction of the cable backplane 703. The second direction is perpendicular to the first direction, and the plane formed by the second direction and the first direction is perpendicular to the surface of the motherboard 6. Specifically, the second direction is the x-direction in Figures 18 and 19. The number of high-density connectors 7031 included in each connector assembly is not limited, and can be designed according to the number required for the actual connector assembly to connect to the motherboard 6 or the accelerator board 10.

[0149] Please refer to Figures 18 and 19. The high-density connector 7031 has a first end close to the host board 6 and the accelerator board 10, and a second end away from the host board 6 and the accelerator board 10. The first end is used to plug into the host board 6 or the accelerator board 10, and the second end is connected to the transmission cable 701. The second ends of the two high-density connectors 7031 corresponding to any two connector components are connected by a transmission cable 701.

[0150] In this embodiment, the first end of the high-density connector 7031 is essentially the male portion of the connector, which is specifically capable of being plugged into the female portion of the host board 6 or the accelerator board 10. The female portion mentioned here is either a part of the host board 6 or the accelerator board 10. Both the host board 6 and the accelerator board 10 are connected to the high-density connector 7031 via a plug-in connection, thus facilitating board disassembly and maintenance, and increasing the maintainability and availability of the server system.

[0151] In this embodiment, the transmission cable 701 connects the second ends of two high-density connectors 7031 to achieve signal transmission. Please refer to Figures 20, 24, and 28. Specifically, it is used for signal connection between the conversion element 1 and the host board 6, that is, it can realize the communication connection between the accelerator 3 connected to the signal of the conversion element 1 and the host board 6; or specifically, it is used for signal connection between the conversion element 1 of one of the two accelerator boards 10 and the conversion element 1 of the other, that is, it can realize the communication connection between the multiple accelerators 3 corresponding to the two conversion elements 1.

[0152] Based on any of the above embodiments, multiple conversion elements 1 located on at least two accelerator boards 10 are connected by multiple transmission cables 701 and multiple high-density connectors 7031 to form a mesh topology. Referring to Figure 1, four conversion elements 1 are interconnected to form a fully interconnected topology. Specifically, refer to the arrangement of the high-density connectors 7031 and the connection relationship of the transmission cables 701 in Figure 20. This fully interconnected topology corresponds to the architecture in Figures 2 and 3. Each conversion element 1 can establish a signal connection with the other three conversion elements 1, which can effectively improve the communication interconnection bandwidth and enhance the server's computing power.

[0153] Alternatively, multiple conversion elements 1 located on at least two accelerator boards 10 can be connected via multiple transmission cables 701 and multiple high-density connectors 7031 to form a ring topology. Refer to Figure 24 for the arrangement of the high-density connectors 7031 and the connection relationships of the transmission cables 701. This topology corresponds to the architecture shown in Figure 23. Referring to Figures 22 and 23, SW-0 is connected to SW-1 and SW-2; SW-1 is connected to SW-0 and SW-3; SW-2 is connected to SW-0 and SW-3; and SW-3 is connected to SW-1 and SW-2. This ring topology avoids the cross-tangle of transmission cables 701 during connection, facilitating cable connections and providing more interfaces for connecting the first network interface card 4. This allows the server to increase scale-up interconnect bandwidth while supporting scale-out network expansion, thus enhancing scale-out capabilities.

[0154] Alternatively, multiple conversion elements 1 located on at least two accelerator boards 10 can be connected via multiple transmission cables 701 and multiple high-density connectors 7031 to form a dual-ring topology. Refer to Figure 28 for the arrangement of the high-density connectors 7031 and the connection relationship of the transmission cables 701. This interconnection topology corresponds to the architecture shown in Figure 27. Referring to Figures 26 and 27, the two interfaces of SW-0 and SW-1, and the two interfaces of SW-2 are connected; the two interfaces of SW-1 and SW-0, and the two interfaces of SW-3 are connected; the two interfaces of SW-2 and SW-3, and the two interfaces of SW-1 are connected; and the two interfaces of SW-3 and SW-2, and the two interfaces of SW-1 are connected. The interface here is the first interface 101. In the schematic diagram of Figure 26, the dual rings interconnecting the conversion elements 1 are respectively a ring formed by four relatively thin buses and a ring formed by four relatively thick buses. This dual-ring topology avoids the cross-tangling of transmission cables 701 during connection, facilitating cable connection and further improving communication bandwidth and server computing power compared to the mesh and ring topologies described above.

[0155] Based on any of the above embodiments, please refer to Figures 18, 19, and 6. The connecting board 7 also includes a power supply backplane 702. The accelerator board 10 and the host board 6 are electrically connected to the power supply backplane 702 to meet the power requirements of the accelerator board 10, the host board 6, and the accelerator 3 configured on the accelerator board 10.

[0156] In one specific embodiment, the power supply backplane 702 and the cable backplane 703 are arranged relatively independently, one for power supply and the other for signal transmission.

[0157] In another specific embodiment, the power supply backplane 702 and the cable backplane 703 are connected. Specifically, the cable backplane 703 includes a metal plate, a high-density connector 7031 disposed on the metal plate, and a transmission cable 701. The power supply backplane 702 is fastened to the metal plate by fasteners to form a connection between the power supply backplane 702 and the cable backplane 703. In this way, the cable backplane 703 and the power supply backplane 702 are integrated into an assembly unit, which can improve the integration of the connection board 7, save space in the server chassis 34, and facilitate the connection between the board and the connection board 7. The metal plate includes, but is not limited to, an aluminum plate.

[0158] Based on any of the above embodiments, the server also includes a chassis 34, a power supply unit 32, a power supply board 9, and a heat dissipation module 8, as shown in Figure 6.

[0159] The power supply unit 32, the host board 6, and at least two layers of accelerator boards 10 are stacked sequentially along the direction parallel to the surface of the connecting board 7. The power supply unit 32 is electrically connected to the power supply board 9, and the power supply board 9 is provided with a power supply interface 901. Specifically, the power supply interface 901 can be connected to 220V power supply, and then the power supply board 9 converts the 220V power supply to 54V power supply to power the server.

[0160] For the mainboard 6 and the accelerator board 10, power is obtained by connecting the connector board 7 to the power supply board 9, and then by connecting the mainboard 6 and the accelerator board 10 to the connector board 7.

[0161] The heat dissipation module 8 is located in the chassis 34 and is used to dissipate heat from the host board 6 and the accelerator board 10. The heat dissipation module 8 is also electrically connected to the power supply board 9 to provide power. As shown in Figure 6, the heat dissipation module 8 is located at the rear window of the chassis 34, and specifically, the connecting plate 7 is located between the heat dissipation module 8, the accelerator board 10, and the host board 6, which facilitates cable connection and installation and disassembly.

[0162] In this embodiment, the power supply unit 32 can be designed with redundancy to ensure the reliability of the server power supply.

[0163] In this embodiment, taking a specific implementation as an example, the height of the chassis 34 can be set to 8U (U is a rack unit), that is, the server is a 14-inch server, then the host board 6 can occupy 1U of space, the accelerator board 10 occupies 3U of space, and the power supply board 9 and power supply unit 32 occupy 1U of space. This implementation is only a preferred method, and can be flexibly changed according to the actual situation.

[0164] Based on any of the above embodiments, please refer to Figures 8 and 9. The heat dissipation module 8 includes multiple sets of fans 801 arranged in a direction perpendicular to the surface of the power supply board 9. At least one set of fans 801 is used to dissipate heat from the host board 6, and at least two sets of fans 801 are used to dissipate heat from the accelerator board 10.

[0165] The heat dissipation module 8 may specifically include, but is not limited to, 15 8086 fans and 9 4056 fans. These 15 8086 fans and 9 4056 fans work together to dissipate heat from the host board 6 and the accelerator board 10, ensuring the reliable operation of both boards and the server. In Figure 8, the 15 8086 fans in the three-layer structure dissipate heat from at least two accelerator boards 10, while the 9 4056 fans in the single-layer structure dissipate heat from the host board 6.

[0166] In this embodiment, the 8086 fan and 4056 fan are only preferred models, but other types of fans can also be used to meet the usage requirements.

[0167] Based on any of the above embodiments, the motherboard 6 includes: a motherboard 604, which has a first central processing unit 2 and a second central processing unit 5; a power adapter board 605, which connects the motherboard 604 and the connecting board 7, and is used to convert power into power available to the motherboard 604; and a front window input / output module 603, with the motherboard 604 located between the power adapter board 605 and the front window input / output module 603.

[0168] Please refer to Figures 6 and 9. The mainboard 6 specifically includes a motherboard 604, a power adapter board 605, and a front input / output module 603. The first central processing unit 2 and the second central processing unit 5 here are the central processing units set on the mainboard 6, forming a dual-processor server structure.

[0169] In a specific implementation, both the first CPU 2 and the second CPU 5 support at least 88 GEN5 PCIe lanes, corresponding to 11 data transmission channels, which correspond to the six interfaces in Figure 10: PE0, PE1, PE2, PE3, PE4, and PE5. All PCIe resources of the first CPU 2 and the second CPU 5 are connected to the MCIO connector 6041 on the motherboard 604. Some of these PCIe resources are used for interconnection between the first CPU 2 or the second CPU 5 and the conversion element 1, while other PCIe resources are used to connect I / O modules such as the M.2 hard drive 13, the second network card 14, and the OCP (Open Compute Project) network card.

[0170] The PE4 and PE5 interfaces in Figure 10 are used to connect two conversion elements 1. These two conversion elements 1 are specifically located within different accelerator boards 10. For example, as shown in Figure 2, these two conversion elements 1 are SW-0 and SW-2, or SW-1 and SW-3. The PE4 and PE5 interfaces are connected to the power adapter board 605 via cables, enabling the first central processing unit 2 or the second central processing unit 5 to obtain the power converted by the power conversion board 405.

[0171] In addition, the PE3 interface of the first central processing unit 2 in Figure 10 is used to connect the OCP network card via a cable. The PE0 interface connects to four E1.S connectors via high-speed cables.

[0172] The PE1 interface of the first central processing unit 2 is used to connect to the USB (Universal Serial Bus) controller 12, the M.2 hard disk 13 for storing the operating system, and the management controller 11 for VGA (Video Graphic Array) display.

[0173] Specifically, in Figure 10, the PE1 interface of the first central processing unit 2 is connected to a USB controller 12. The USB controller 12 can be a uPD720201 controller. Because the PE1 interface is a PCIe interface, the USB controller 12 can convert the PCIe interface to a USB 3.0 interface and a USB 2.0 interface to connect to the user interface board 17, i.e., the UI board. The user interface board 17 includes elements such as buttons and indicator lights, mainly used by developers to more intuitively understand and design user interactions, interface layouts, and function implementations. Furthermore, the USB 2.0 interface is connected to the USB interface of the management controller 11.

[0174] In Figure 10, the PE1 interface of the first central processing unit 2 is also connected to the PCIE interface of the management controller 11 to realize the VGA display function.

[0175] Unlike the first central processing unit 2, the PE1 interface of the second central processing unit 5 is not connected to any device.

[0176] If the power supply board 9 uses a 54V power output, then the motherboard 6 also needs to use a 54V to 12V adapter module 6051 to convert the power supply of the power supply board 9 into a power supply usable by the motherboard 604, so as to meet the power requirements of the motherboard 6.

[0177] The front window input / output module 603 includes a front window IO panel 6032 (supporting power button, fault indicator, VGA interface, USB interface, network port, etc.), eight E1.S form factor solid-state drives 33, and a second network card 14.

[0178] Referring to Figure 9, the motherboard 604 also includes multiple DIMM (Dual-Inline-Memory-Modules) connectors 6043, which serve as memory devices for expanding memory capacity. The motherboard 604 also features an IMC (Integrated Memory Controller), which performs data read and / or write operations on the dual-inline-modules based on DDR (Double Data Rate). Specifically, there are 32 of these multiple DIMMs.

[0179] The motherboard 604 is also equipped with a voltage regulation module 6042, which can be used to regulate the voltage provided by the power supply board 9 to a stable voltage suitable for the central processing unit and memory settings, ensuring reliable voltage supply and guaranteeing the stability and reliability of the motherboard 6.

[0180] Based on any of the above embodiments, please refer to Figures 9 and 11. The motherboard 604 is provided with an interface, and the interface is connected to a management controller 11. The management controller 11 is disposed perpendicular to the surface of the motherboard 604. The management controller 11 is signal connected to the first central processing unit 2, the second central processing unit 5, the accelerator board 10, and the front window input / output module 603.

[0181] The management controller 11 includes, but is not limited to, a BMC (Baseboard Management Controller) or other management controllers with server management functions. The management controller 11 is used for out-of-band management and control of the entire server. The management controller 11 has a BMC, a FWSPI (Firmware Serial Peripheral Interface) interface of the BMC connecting to the Boot Flash, and an EMMC (Embedded MultiMedia Card) interface of the BMC connecting to the embedded multimedia card 12. The management controller 11 is interconnected with the motherboard 604 via a 4C+ connector. In addition, the management controller 11 also has an FWSPI interface, a DOR (Doorbell Register) interface, and an EMMC interface, with the EMMC interface connecting to the motherboard 6.

[0182] The signal logic design block diagram of the motherboard 6 is shown in Figure 11. The management controller 11 is connected to the front window input / output module 603, meaning that the management controller 11 outputs signals to the front window IO panel 6032, such as UART (Universal Asynchronous Receiver / Transmitter) signals, VGA signals, and RGMII (Reduced Gigabit Media Independent Interface) signals. Specifically, the BMC's UART interface is connected to the front window Type-C port 26 of the front window IO panel 6032 via converter 24, which converts USB signals to UART signals. The BMC's VGA interface is connected to the front window VGA port 25 of the front window IO panel 6032. The BMC's RGMII interface is connected to the front window RJ45 port of the front window IO panel 6032 via port physical layer 22, while the motherboard 6 communicates with external devices via the front window RJ45 port 23.

[0183] The management controller 11 connects to the first central processing unit 2 and the second central processing unit 5. That is, the baseboard management controller module outputs signals to the first central processing unit 2 and the second central processing unit 5, such as ESPI (Enhanced Serial Peripheral Interface), PECI (Platform Environment Control Interface), SPI, and I3C (Improved Inter-Integrated Circuit). To shorten the trace distance, the management controller 11 is placed on the motherboard 6 near the first central processing unit 2 and the front I / O panel 6032. To save space, the management controller 11 is designed as a vertical insert card, with a height less than the height of the 1U chassis 34. It should be noted that this is based on a server height of 8U and the overall height of the motherboard 6 being 1U.

[0184] The server uses a three-tier architecture, as shown in Figure 11. The management controller 11 also needs to manage cross-boards. Specifically, the I2C interface of the management controller 11 is connected to the accelerator board 10 via a connector to read and monitor some statuses of the accelerator board 10, such as temperature, voltage, and alarm information. Furthermore, the I2C interface is connected via the I2C bus to the following components: FRU29 (Field Replaceable Unit), DMPU (Device Management Processor Unit), temperature sensor 30, fan assembly 31, power supply unit 32, solid-state drive 33, accelerator board 10, logic processing element 27, VR6042, MISC28 (miscellaneous), OCP network card, M.2 hard drive 13, and Riser card (expansion card).

[0185] Based on any of the above embodiments, the motherboard 604 is provided with a logic processing element 27, which is connected to the accelerator board 10, the host board 6, and the power supply board 9, for at least the power-on and power-off timing control of the accelerator board 10, the host board 6, and the power supply board 9.

[0186] The phrase "at least for power-on / off timing control" here means it can also be used for signal processing, such as processing digital signals, including signal amplification, filtering, encoding, and decoding. The logic processing element 27 helps the device achieve applications such as data transmission and image processing. The logic processing element 27 can be a programmable logic device such as a CPLD (Complex Programmable Logic Device).

[0187] Please refer to Figure 12. Specifically, the power is supplied via the power supply board 9P12V-INPUT. After power-on, the management controller 11 STBY (standby mode) is powered on. Then, the management controller 11 sends an STBY EN signal (enable signal in standby mode), powering on the mainboard 604 STBY (standby mode) of the host board 6. After that, the management controller 11 sends a power-on signal to the accelerator board 10, powering on the accelerator 3 STBY (standby mode). Then, the host board 6 receives the power-on signal, which can be a remotely sent signal or a signal received after pressing the start button. After that, the host board 6 sends a start signal, powering on the main circuit of the accelerator board 10. Through the above process, the power-on timing control and signal processing of the host board 6 and the accelerator board 10 in the entire server are completed.

[0188] Based on any of the above embodiments, please refer to Figures 6 and 9. A first signal connector 6053 is provided at one end of the power adapter board 605 near the connecting plate 7. The socket of the first signal connector 6053 is arranged parallel to the surface of the power adapter board 605. This arrangement of being parallel to the surface of the power adapter board 605 is essentially the same as being perpendicular to the connecting plate 7, so that the first signal connector 6053 can be vertically inserted into the connecting plate 7 to achieve signal connection.

[0189] Specifically, the socket of the first signal connector 6053 is connected to the connector assembly on the cable backplane 703 closest to the host board 6. This description is based on the fact that multiple connector assemblies are arranged along the first direction, corresponding to the accelerator board 10 and the host board 6. Therefore, in Figure 18, the lowermost set of connector assemblies is plugged into the socket of the first signal connector 6053, while the other connector assemblies are used to connect to the accelerator board 10.

[0190] In this embodiment, the first signal connector 6053 is specifically connected to the first end of the high-density connector 7031 corresponding to the host board 6. Then, the transmission cable 701 at the second end of the high-density connector 7031 is connected to another high-density connector 7031 corresponding to the accelerator board 10 to realize the communication connection between the central processing unit of the host board 6 and the conversion element 1 of the accelerator board 10. Then, through the interconnection between the conversion elements 1 corresponding to at least two accelerator boards 10, the communication connection between the central processing unit and multiple accelerators 3 is realized, thereby improving the server's computing power.

[0191] In this embodiment, the communication connection between the motherboard 6 and the connector board 7 is achieved through a plug-in connection, which facilitates the disassembly and maintenance of the motherboard 6 and increases the maintainability and availability of the system.

[0192] In this embodiment, the number of high-density connectors 7031 provided on the connection board 7 is also designed to be redundant, that is, more than the number required by the accelerator board 10 and the host board 6, in order to meet the redundancy design and ensure the reliability of the server.

[0193] Based on any of the above embodiments, referring to Figures 6 and 9, a first power connector 6052 is also provided at one end of the power adapter board 605 near the connecting plate 7, that is, the first power connector 6052 is provided on the power adapter board 605 near the rear window. The socket of the first power connector 6052 is arranged parallel to the surface of the power adapter board 605. This arrangement of being parallel to the surface of the power adapter board 605 is actually perpendicular to the connecting plate 7.

[0194] The first power connector 6052 is connected to the second power connector 7021 on the power supply backplane 702, which is closest to the motherboard 6, so that the motherboard 6 can obtain power from the power supply backplane 702.

[0195] In this embodiment, it should be noted that a plurality of second power connectors 7021 are also provided on the power supply backplane 702 along the first direction. The plurality of second power connectors 7021 can be used to power the host board 6 and the accelerator board 10. Among them, the second power connector 7021 closest to the host board 6, as shown in FIG. 18, is the lowermost second power connector 7021 used for connection to the socket of the first power connector 6052.

[0196] In this embodiment, the power supply to the motherboard 6 is obtained through a plug-in connection, which facilitates the disassembly and maintenance of the motherboard 6 and increases the maintainability and availability of the system.

[0197] In this embodiment, the number of second power connectors 7021 provided on the connection board 7 can be set to n+1, where n is a positive integer and corresponds to the number of electrical connectors of the host board 6 and the accelerator board 10. The additional second power connectors 7021 are used to achieve redundancy design and improve the reliability of the server.

[0198] Based on any of the above embodiments, please refer to Figures 13 and 14. The accelerator board 10 includes a conversion base plate 1001 and a slot structure 10018 connected to the conversion base plate 1001. The slot structure 10018 is fixed in the chassis 34 by screws or other fasteners and can achieve communication and power connection between the conversion base plate 1001 and the slot structure 10018 through signal lines and power lines.

[0199] Multiple conversion elements 1 are disposed on the conversion base plate 1001. A slot structure 10018 is used to connect the accelerator 3 and the first network interface card 4. The specific structure of the slot structure 10018 is designed based on the accelerator 3 and the first network interface card 4 configured on the accelerator board 10, and its specific form is not limited. In practical applications, the accelerator 3 connected to the slot structure 10018 can have good compatibility and be applicable to different manufacturers because the conversion elements 1 are connected based on an interconnection protocol.

[0200] Please refer to Figure 13. The conversion base plate 1001 is provided with a second signal connector 10011. The second signal connector 10011 is arranged parallel to the surface of the conversion base plate 1001 and can be plugged into the cable backplane 703 to realize the signal connection between the accelerator board 10 and the connection board 7. The plugging into the cable backplane 703 here is actually plugging into the first end of the high-density connector 7031 on the cable backplane 703 corresponding to the accelerator board 10. Then, the transmission cable 701 at the second end of this high-density connector 7031 is connected to another high-density connector 7031 corresponding to the host board 6 to realize the communication connection between the central processing unit of the host board 6 and the conversion element 1 of the accelerator board 10. Then, through the interconnection between the conversion elements 1 corresponding to at least two accelerator boards 10, the communication connection between the central processing unit and multiple accelerators 3 is realized.

[0201] In this embodiment, the communication connection between the accelerator board 10 and the connecting board 7 is achieved through a plug-in connection, which facilitates the disassembly and maintenance of the accelerator board 10 and increases the maintainability and availability of the system.

[0202] In this embodiment, the conversion baseboard 1001 also provides two clocks 15, a co-source clock and a non-co-source clock, providing more reliable input clock source redundancy. Both the co-source clock and the non-co-source clock are connected to a clock generator, which uses an external clock signal clk to generate a series of clock signals, such as clk1, fetch, alu_clk, etc. These signals are sent to the central processing unit, namely the first central processing unit 2 and the second central processing unit 5.

[0203] As shown in Figure 17, in addition to being connected to the management controller 11 of the host board 6 for management, control, status monitoring, etc., the accelerator board 10 also has its own RUNBMC module for independent control.

[0204] Based on any of the above embodiments, referring to FIG15, a first connector 10012, a second connector 10013, a third connector 10014, a fourth connector 10015, and a fifth connector 10016 are provided on the outer periphery of the conversion element 1 on the conversion base plate 1001. In one specific embodiment, as shown in FIG15, two conversion elements 1 are provided on the same conversion base plate 1001, corresponding to 4 first connectors 10012, 16 second connectors 10013, 4 third connectors 10014, 8 fourth connectors 10015, and 4 fifth connectors 10016, specifically corresponding to the mesh topology shown in FIG1 and the corresponding architecture forms in FIG2 and FIG3. In another specific embodiment, please refer to Figure 25. Two conversion elements 1 are provided on the same conversion base plate 1001. There are 8 of them corresponding to the first connector 10012, 16 of them corresponding to the second connector 10013, 4 of them corresponding to the third connector 10014, 4 of them corresponding to the fourth connector 10015, and 4 of them corresponding to the fifth connector 10016. Specifically, they correspond to the ring topology shown in Figure 22 and the architecture shown in Figure 23.

[0205] In mesh and ring topologies, the first connector 10012 connects to the first network interface card 4, and the second connector 10013 connects to the accelerator 3. Specifically, the second interface 102 of the conversion element 1 can connect to the first network interface card 4 via the first connector 10012 and to the accelerator 3 via the second connector 10013. The third connector 10014 connects to the motherboard 6, and the fourth connector 10015 is used for interconnection between at least two accelerator boards 10. The fifth connector 10016 is used for interconnection between conversion elements 1 located on the conversion base plate 1001, specifically through the first interface 101 of two conversion elements 1 and the fifth connector 10016, to achieve interconnection between conversion elements 1 on the conversion base plate 1001, enabling multiple accelerators 3 corresponding to the conversion base plate 1001 to communicate, thereby increasing the number of accelerators 3 configured in the server and improving computing power.

[0206] In one specific embodiment, referring to Figure 29, a second connector 10013, a third connector 10014, a fourth connector 10015, and a fifth connector 10016 are arranged along the outer periphery of the conversion element 1 on the conversion base plate 1001. Two conversion elements 1 are arranged on the same conversion base plate 1001. There are 16 second connectors 10013, 4 third connectors 10014, 8 fourth connectors 10015, and 8 fifth connectors 10016, specifically corresponding to the double-ring topology shown in Figure 26 and the architecture shown in Figure 27.

[0207] Sixteen second connectors 10013 connect to accelerators 3, four third connectors 10014 connect to the motherboard 6, and eight fourth connectors 10015 are used for interconnection between at least two accelerator boards 10. Eight fifth connectors 10016 are used for interconnection between conversion elements 1 located on the conversion baseboard 1001, specifically through the first interface 101 of two conversion elements 1 and the fifth connectors 10016, to realize the interconnection between conversion elements 1 on the conversion baseboard 1001, enabling multiple accelerators 3 corresponding to the conversion baseboard 1001 to communicate, thereby increasing the number of accelerators 3 configured in the server and improving computing power.

[0208] Based on any of the above embodiments, please refer to Figures 13, 14, and 16. The accelerator board 10 also includes a power supply board 1002. The power supply board 1002 is provided with a third power connector 10021, which is connected to a corresponding second power connector 7021 on the power supply backplane 702, so that the power supply board 1002 can supply power to the conversion base plate 1001 and the accelerator 3.

[0209] The power supply board 1002 supplies power to the conversion base plate 1001. Specifically, the base plate power connector 10024 on the power supply board 1002 is connected to the conversion base plate 1001, enabling the conversion base plate 1001 to obtain power. Then, the slot power connector 10017 on the conversion base plate 1001 can provide 3V power to the slot structure 10018.

[0210] The power supply board 1002 supplies power to the accelerator 3. The accelerator card power connector 10023 on the power supply board 1002 is directly connected to the accelerator 3 so as to provide 12V power to the accelerator 3.

[0211] The power supply board 1002 also includes a power converter 10022, which can convert power into usable power and supply it to the base plate power connector 10024 and the accelerator card power connector 10023. Specifically, since the power supply board 9 provides 54V, the power converter 10022 is needed to step down the 54V to 12V to meet the power needs of the base plate 1001 and the accelerator 3 itself.

[0212] In this embodiment, it should be noted that the power supply board 1002 and the conversion base plate 1001 corresponding to the accelerator board 10 also have a two-layer architecture, which is stacked. Taking Figures 13 and 14 as examples, the power supply board 1002 is located on the upper layer, and the conversion base plate 1001 is located on the lower layer. The power supply board 1002 is connected to the power supply backplane 702 through the third power connector 10021, and the conversion base plate 1001 is connected to the cable backplane 703 through the second signal connector 10011. Here, the upper layer is the direction away from the bottom of the chassis 34, and the lower layer is the direction close to the bottom of the chassis 34.

[0213] Based on any of the above embodiments, please refer to FIG14. The chassis 34 is provided with an installation area, the slot structure 10018 is located in the installation area, and the power supply board 1002 has a gap between its end away from the connecting plate 7 and the installation area, so as to provide installation space for the accelerator 3 and the first network card 4 to be connected to the slot structure 10018.

[0214] It should be noted that the conversion base plate 1001 and the slot structure 10018 are located on the same plane within the chassis 34, which facilitates the signal and electrical connection between the conversion base plate 1001 and the slot structure 10018. The power supply board 1002 has an accelerator card power connector 10023 that is directly connected to the accelerator 3 to supply power. The accelerator 3 is vertically inserted. In order to provide installation space, the end of the power supply board 1002 away from the connecting plate 7, or the end of the power supply board 1002 closer to the installation area, is at a certain distance from the installation area. This allows the accelerator 3 to be placed using the height space of the chassis 34, improving space utilization and facilitating the reliable arrangement of the various components corresponding to the accelerator board 10.

[0215] Please refer to Figures 2, 3, and 4. The server architecture consists of two accelerator boards 10 and a host board 6. The high-speed signal interconnections between the host board 6 and one of the accelerator boards 10, between the host board 6 and the other accelerator board 10, and between the two accelerator boards 10 are all signal transmission cables. The difference is that the high-speed signal interconnections between the host board 6 and one of the accelerator boards 10, and between the host board 6 and the other accelerator board 10, consist of two sets of signal transmission cables, while the high-speed signal interconnection between the two accelerator boards 10 consists of four sets of signal transmission cables. The number of sets of transmission cables is explained based on the premise that the 144 data transmission channels of the conversion element 1 are divided into 9 groups.

[0216] Each accelerator board 10 corresponds to two conversion elements 1. The two third interfaces 103 corresponding to the two conversion elements 1 are connected to the first central processing unit 2 and the second central processing unit 5 respectively. That is, each layer of accelerator board 10 is connected to the host board 6 through two sets of signal transmission cables to transmit high-speed signals.

[0217] The relationship between the two accelerator boards 10 is shown in Figure 4. The two conversion elements 1 located in the same accelerator board 10 are connected by a set of transmission cables, and the two conversion elements 1 located in different accelerator boards 10 are connected by two sets of signal transmission cables, so that each of the four conversion elements 1 can be connected to the other three to form a fully interconnected mode.

[0218] In addition, each accelerator board 10 includes two first network cards 4, two conversion elements 1, and either eight or sixteen accelerators 3, depending on the type of accelerator interface. If the accelerator interface is x16, then the accelerator board 10 corresponds to eight accelerators 3; if the accelerator interface is x8, then the accelerator board 10 corresponds to sixteen accelerators 3.

[0219] By connecting the first network interface card 4 to the conversion element 1, the server can increase scale-up interconnect bandwidth while supporting scale-out network expansion, ensuring scale-out capability. The aforementioned server, through the host board 6 and accelerator board 10, forms at least a three-layer server architecture, providing extremely high computing power density, high inter-card communication bandwidth, and low communication latency within a fixed chassis height 34, meeting computing power requirements, improving data transmission and processing speed, and enhancing core competitiveness.

[0220] The aforementioned server can achieve signal connection between the host board 6 and the accelerator board 10 through the connection board 7, and can meet the power supply requirements of the host board 6 and the accelerator board 10 through the connection board 7. It can form a complete server structure that can improve computing power and has good market application prospects.

[0221] The aforementioned server achieves high-bandwidth interconnect expansion with more accelerators 3 while maintaining the same number of central processing units, and enables pluggable and isolated cards, improving system maintainability and availability. Simultaneously, the server supports scale-out networking expansion, requiring half the number of hosts compared to traditional server clusters with thousands or tens of thousands of cards, and consequently reducing the number of network cards, switches, and other components used.

[0222] The aforementioned server can achieve scale-up interconnection between cards without requiring the accelerator 3 itself to support the card interconnection protocol, thereby improving the scale-up interconnection bandwidth. At the same time, the interconnection protocol ecosystem is compatible and can be used by different manufacturers.

[0223] Based on the 16-card server provided in this application, experimental studies have shown that, compared to two traditional 8-card servers, the basic communication bandwidth is increased by at least 50%, the communication latency is reduced by at least 30%, and the inference throughput performance is increased by at least 45%.

[0224] In addition to the aforementioned server, this application also provides a server system including the aforementioned server, wherein the server system further includes an accelerator 3, which is specifically connected to an accelerator board 10 to form a server system having multiple accelerators 3 capable of parallel processing.

[0225] Furthermore, multiple accelerators 3 are connected via bridges. Taking a server with four conversion elements 1, each connecting four accelerators 3, as an example, the four accelerators 3 connected to the same conversion element 1 are considered a group. The four accelerators 3 within a group communicate through the internal processing of the conversion element 1 (specifically, a Broadcom PCIE GEN5 Switch module), achieving an aggregated communication bandwidth of 384 GB / s. The four accelerators 3 in different groups communicate via the interconnect bus between conversion elements 1, also with an aggregated communication bandwidth of 384 GB / s. Building upon this, accelerators 3 in different groups within the same accelerator board 10 can be interconnected via bridges to further enhance the interconnect communication bandwidth. This enhancement refers to an increase beyond 384 GB / s; the specific increase depends on the bandwidth supported by the interconnect protocol between the accelerators 3. The server architecture supports accelerators 3 connected via bridges to extend interaction bandwidth, further improving interconnect communication bandwidth and data transmission speed.

[0226] This application also provides a data processing method for a server system applied to the above embodiments. The data processing method includes: based on a general interconnection protocol, enabling multiple conversion elements 1 corresponding to at least two accelerator boards 10 to obtain data to be processed; and using at least four accelerators 3 connected to each conversion element 1 to perform parallel processing on the data to be processed.

[0227] As shown in Figures 1, 22, and 26, taking a server comprising four conversion elements 1 as an example, based on a universal interconnection protocol, each of the four conversion elements 1 can communicate with each other, and each conversion element 1 can acquire data to be processed. The data to be processed acquired by each conversion element 1 can be a set of data to be processed that has been processed and sent out by the central processing unit. After all four conversion elements 1 have acquired the data to be processed, they are processed in parallel through the four accelerators 3 or eight accelerators 3 connected to each conversion element 1, thereby improving the data processing speed, increasing the computing power density, and enhancing the core competitiveness of the product.

[0228] By interconnecting four conversion elements 1, the number of connectable accelerators 3 is increased, the aggregated communication bandwidth is improved, the parallel processing capability is enhanced, the data processing speed is reliably increased, and the computing power requirements are met.

[0229] This application also provides an apparatus for performing the above-described data processing method. The apparatus specifically includes: a storage element 41 for storing a computer program; and a processor 35 for executing the computer program to implement the steps of the data processing method as described in the above embodiments.

[0230] The devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0231] The processor 35 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 35 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 35 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may integrate a Graphics Processing Unit (GPU) responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 35 may also include an Artificial Intelligence (AI) processor for handling computational operations related to machine learning.

[0232] Storage element 41 may include one or more computer-readable storage media, which may be non-transitory. Storage element 41 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, storage element 41 is used to store at least the following computer program 411, wherein, after being loaded and executed by a processor, the computer program 411 is able to implement the relevant steps of the data processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in storage element 41 may also include an operating system 412 and data 413, and the storage method may be temporary storage or permanent storage. The operating system 412 may include Windows, Unix, Linux, etc.

[0233] In some embodiments, the device may further include a display screen 36, an input / output interface 39, a communication interface 38, a power supply 37, and a communication bus 40.

[0234] Those skilled in the art will understand that the structure shown in FIG21 does not constitute a limitation on the device and may include more or fewer components than shown.

[0235] It is understood that if the data processing methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical disks, and other media capable of storing program code.

[0236] Based on this, this application embodiment also provides a non-volatile storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the data processing method described above.

[0237] The foregoing has provided a detailed description of a server, server system, data processing method, device, non-volatile storage medium, and computer program product provided in the embodiments of this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0238] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0239] The foregoing has provided a detailed description of a server, server system, data processing method, device, non-volatile storage medium, and computer program product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server, characterized in that, include: The motherboard (6) includes at least two central processing units; Accelerator board (10), at least two of the accelerator boards (10) are stacked in a direction perpendicular to the surface of the host board (6), and the accelerator boards (10) can be configured to connect a plurality of accelerators (3); The accelerator board (10) includes a conversion element (1), and multiple conversion elements (1) are signal-connected to the central processing unit. The multiple conversion elements (1) are signal-connected to each other to realize communication between the multiple accelerators (3) connected to the accelerator board (10). A connecting plate (7) is set perpendicular to the accelerator board (10) and the host board (6). The accelerator board (10) and the host board (6) are both signal connected to the connecting plate (7) so as to realize the signal connection between the host board (6) and the accelerator board (10) corresponding to the accelerator (3) through the connecting plate (7), and to realize the signal connection between at least two accelerator boards (10) corresponding to the accelerators (3) respectively through the connecting plate (7).

2. The server according to claim 1, characterized in that, The accelerator (3) is positioned above the accelerator board (10).

3. The server according to claim 1, characterized in that, The multiple conversion elements (1) corresponding to the accelerator board (10) are connected based on an interconnection protocol. Each conversion element (1) is provided with multiple first interfaces (101), and at least one of the first interfaces (101) corresponding to any two conversion elements (1) are connected.

4. The server according to claim 3, characterized in that, The conversion element (1) is provided with a plurality of second interfaces (102), which are configured to connect a plurality of the accelerators (3) and at least one first network card (4); Alternatively, multiple second interfaces (102) may be configured to connect multiple accelerators (3).

5. The server according to claim 4, characterized in that, The conversion element (1) is provided with at least one third interface (103), and the third interface (103) corresponding to the conversion element (1) is connected to the central processing unit.

6. The server according to claim 5, characterized in that, The third interface (103) corresponding to the conversion element (1) is connected to at least two of the central processing units.

7. The server according to claim 5, characterized in that, The conversion element (1) has multiple data channels. The data channel corresponding to the first interface (101) is in Fabric mode, the data channel corresponding to the second interface (102) is in Device mode, and the data channel corresponding to the third interface (103) is in Host mode.

8. The server according to claim 1, characterized in that, The connecting plate (7) includes a cable backplate (703), and the accelerator board (10) and the host board (6) are both connected to the cable backplate (703); The cable backplate (703) is provided with a plurality of connector assemblies, which are arranged sequentially along a first direction of the cable backplate (703), and the first direction is consistent with the stacking direction of at least two of the accelerator boards (10). The plurality of connector assemblies are respectively connected to at least two of the accelerator boards (10) and the host board (6) to realize signal connection between the host board (6) and the accelerator boards (10) and signal connection between at least two of the accelerator boards (10).

9. The server according to claim 8, characterized in that, The connector assembly includes a plurality of high-density connectors (7031), which are arranged sequentially along a second direction of the cable backplate (703), the second direction being perpendicular to the first direction, and the plane formed by the second direction and the first direction being perpendicular to the surface of the motherboard (6). The high-density connector (7031) has a first end close to the host board (6) and the accelerator board (10) and a second end away from the host board (6) and the accelerator board (10). The first end is configured to be plugged into the host board (6) or the accelerator board (10), and the second end is connected to a transmission cable (701). The second ends of the two high-density connectors (7031) corresponding to any two connector assemblies are connected to each other through a transmission cable (701).

10. The server according to claim 9, characterized in that, Signal connections are made between a plurality of the conversion elements (1) located on at least two of the accelerator boards (10) via a plurality of the transmission cables (701) and a plurality of the high-density connectors (7031) to form a mesh topology; Alternatively, signal connections are made between multiple conversion elements (1) located on at least two of the accelerator boards (10) via multiple transmission cables (701) and multiple high-density connectors (7031) to form a ring topology; Alternatively, signal connections are made between multiple conversion elements (1) located on at least two of the accelerator boards (10) via multiple transmission cables (701) and multiple high-density connectors (7031) to form a dual-ring topology.

11. The server according to claim 10, characterized in that, The connecting plate (7) also includes a power supply backplane (702), and the accelerator board (10) and the host board (6) are electrically connected to the power supply backplane (702).

12. The server according to claim 11, characterized in that, Also includes: Chassis (34); A power supply unit (32) is provided. The power supply unit (32), the main board (6), and at least two layers of the accelerator boards (10) are stacked sequentially along a direction parallel to the surface of the connecting plate (7). The power supply unit (32) is electrically connected to the power supply board (9). The main board (6) and the accelerator boards (10) are both connected to the power supply board (9) through the connecting plate (7). A heat dissipation module (8) is located in the chassis (34) and is configured to dissipate heat from the host board (6) and the accelerator board (10), and the heat dissipation module (8) is electrically connected to the power supply board (9).

13. The server according to claim 12, characterized in that, The heat dissipation module (8) includes multiple sets of fans (801) arranged in a direction perpendicular to the surface of the power supply board (9), at least one set of the fans (801) is configured to dissipate heat from the host board (6), and at least two sets of the fans (801) are configured to dissipate heat from the accelerator board (10).

14. The server according to claim 13, characterized in that, The motherboard (6) includes: The motherboard (604) is provided with a first central processing unit (2) and a second central processing unit (5); A power adapter board (605), connecting the motherboard (604) and the connection board (7), is configured to convert power into power available to the motherboard (604); The front window input / output module (603) is located between the power adapter board (605) and the front window input / output module (603).

15. The server according to claim 14, characterized in that, The motherboard (604) is connected to a management controller (11), which is disposed perpendicular to the surface of the motherboard (604); The management controller (11) is signal-connected to the first central processing unit (2), the second central processing unit (5), the accelerometer board (10), and the front window input / output module (603).

16. The server according to claim 15, characterized in that, The motherboard (604) is provided with a logic processing element (27), which is connected to the accelerator board (10), the host board (6), and the power supply board (9) to be configured at least for the power-on and power-off timing control of the accelerator board (10), the host board (6), and the power supply board (9).

17. The server according to claim 16, characterized in that, The power adapter board (605) is provided with a first signal connector (6053) at one end near the connecting board (7). The socket of the first signal connector (6053) is arranged parallel to the surface of the power adapter board (605), and the socket of the first signal connector (6053) is connected to the connector assembly of the cable backplate (703) closest to the host board (6).

18. The server according to claim 17, characterized in that, The power adapter board (605) is also provided with a first power connector (6052) at one end near the connecting board (7). The socket of the first power connector (6052) is arranged parallel to the surface of the power adapter board (605), and the socket of the first power connector (6052) is connected to the second power connector (7021) of the power supply backplane (702) that is closest to the host board (6).

19. The server according to any one of claims 8 to 18, characterized in that, The accelerator board (10) includes a conversion base plate (1001) and a slot structure (10018) connected to the conversion base plate (1001). A plurality of conversion elements (1) are disposed on the conversion base plate (1001). The slot structure (10018) is configured to connect the accelerator (3) and the first network card (4). The conversion base plate (1001) is provided with a second signal connector (10011), which is arranged parallel to the surface of the conversion base plate (1001) and can be plugged into the cable back plate (703) to realize the signal connection between the accelerator board (10) and the connection board (7).

20. The server according to claim 19, characterized in that, The conversion base plate (1001) is provided with a first connector (10012), a second connector (10013), a third connector (10014), a fourth connector (10015), and a fifth connector (10016) along the outer periphery of the conversion element (1); Alternatively, a second connector (10013), a third connector (10014), a fourth connector (10015), and a fifth connector (10016) may be provided on the conversion base plate (1001) along the outer periphery of the conversion element (1); The first connector (10012) is configured to connect to the first network card (4), the second connector (10013) is configured to connect to the accelerator (3); the third connector (10014) is connected to the host board (6), the fourth connector (10015) is configured to interconnect at least two of the accelerator boards (10), and the fifth connector (10016) is configured to interconnect the conversion elements (1) located on the conversion base plate (1001).

21. The server according to claim 20, characterized in that, The accelerator board (10) also includes a power supply board (1002), which is provided with a third power connector (10021). The third power connector (10021) is connected to the power supply backplate (702) of the connection board (7) so that the power supply board (1002) can supply power to the conversion base plate (1001) and the accelerator (3).

22. The server according to claim 21, characterized in that, The chassis (34) has an installation area, the slot structure (10018) is located in the installation area, and the power supply board (1002) is spaced apart from the end of the connecting plate (7) and the installation area to provide installation space for the accelerator (3) and the first network card (4) to be connected to the slot structure (10018).

23. A server system, characterized in that, include: The server is the server described in any one of claims 1 to 22; Accelerator (3), the accelerator board (10) of the server is connected to multiple accelerators (3), and the multiple accelerators (3) are connected to each other through a bridge.

24. A data processing method, characterized in that, The data processing method, applied to the server system of claim 23, includes: Based on the interconnection protocol, at least two of the conversion elements (1) corresponding to the accelerator boards (10) are made to obtain the data to be processed; The data to be processed is processed in parallel using the accelerators (3) that are connected to each of the conversion elements (1).

25. A device, characterized in that, include: Storage element (41) is configured to store computer program (411); The processor (35) is configured to execute the computer program (411) to implement the steps of the data processing method as claimed in claim 22.

26. A non-volatile storage medium, characterized in that, The computer-readable storage medium stores a computer program (411), which, when executed by a processor (35), implements the steps of the data processing method as described in claim 24.

27. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor (35), they implement the steps of the data processing method of claim 24.

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