Display panel and display device

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises a hole area, a winding area, and a display area. The winding area is located between the hole area and the display area and surrounds the hole area. The display panel further comprises a plurality of first signal lines, a plurality of second signal lines, and a shielding layer. Each first signal line comprises a first winding portion located in the winding area, and the first winding portion is arranged around at least part of the edge of the hole area. Each second signal line comprises a second winding portion located in the winding area, and the second winding portion is arranged around at least part of the edge of the hole area. The shielding layer is arranged around at least part of the edge of the hole area. At least part of the orthographic projection of the shielding layer on a base substrate of the display panel is located between the orthographic projection of the first winding portion on the base substrate and the orthographic projection of the second winding portion on the base substrate.

Description

Display panel and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510228962.0, filed in China on February 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] With the continuous development of display technology, consumers have increasingly higher requirements for the image quality and appearance design of display products. In order to improve the appearance design of display products and reduce the bezel width, sensor components such as cameras are integrated into the perforated area of ​​the display product. However, the perforated area is generally surrounded by the display area. This means that some traces in the display area need to bypass the perforated area. However, these traces are usually used to transmit different types of signals, which can easily lead to crosstalk between signal lines transmitting different types of signals near the perforated area, affecting the display effect of the display product. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display panel and a display device.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a display panel, including: an aperture area, a winding area, and a display area, wherein the winding area is located between the aperture area and the display area, and the winding area surrounds the aperture area; the display panel further includes:

[0008] Multiple first signal lines, each first signal line including a first winding portion located in the winding area, the first winding portion being disposed around at least a portion of the edge of the hole area;

[0009] Multiple second signal lines, each second signal line including a second winding portion located in the winding region, the second winding portion being disposed around at least a portion of the edge of the hole region;

[0010] A shielding layer is disposed around at least a portion of the edge of the hole area, and at least a portion of the shielding layer's orthographic projection on the substrate of the display panel is located between the orthographic projections of the first winding portion and the second winding portion on the substrate.

[0011] Optionally, the display panel further includes a light-shielding layer and a plurality of display sub-pixels; the light-shielding layer includes a plurality of light-shielding patterns arranged in an array and a plurality of first connecting lines, the light-shielding patterns located in the same row along a first direction are coupled to each other by the corresponding first connecting lines, the orthographic projection of the light-shielding pattern on the substrate overlaps at least partially with the orthographic projection of the transistor structure in the corresponding display sub-pixel on the substrate; the shielding layer is coupled to at least a portion of the first connecting lines.

[0012] Optionally, the shielding layer and the light-shielding layer are made of the same material and layer.

[0013] Optionally, the display panel further includes a power signal line, and the light-shielding layer is coupled to the power signal line.

[0014] Optionally, the orthographic projection of the first winding portion on the substrate does not overlap with the orthographic projection of the second winding portion on the substrate.

[0015] Optionally, the orthographic projection of the first winding portion on the substrate is located between the orthographic projection of the second winding portion on the substrate and the orthographic projection of the hole region on the substrate.

[0016] Optionally, the orthographic projection of the second winding portion on the substrate is located between the orthographic projection of the first winding portion on the substrate and the orthographic projection of the hole region on the substrate.

[0017] Optionally, the first signal line further includes two first lead portions arranged along a second direction, the first lead portions extending along the second direction, the first winding portion being located between the two first lead portions, a first end of the first winding portion being coupled to one of the first lead portions, and a second end of the first winding portion being coupled to the other first lead portion.

[0018] The second signal line further includes two second lead portions arranged along the first direction, the second lead portions extending along the first direction, the second winding portion being located between the two second lead portions, the first end of the second winding portion being coupled to one of the second lead portions, and the second end of the second winding portion being coupled to the other second lead portion; the second direction intersects the first direction.

[0019] Optionally, the plurality of first signal lines are divided into a first group of first signal lines and a second group of first signal lines, wherein the first group of first signal lines includes n1 first signal lines and the second group of first signal lines includes n2 first signal lines.

[0020] Along the first direction, the first winding portion of the n1 first signal lines is located on the first side of the aperture region, and the first winding portion of the n2 first signal lines is located on the second side of the aperture region, where n1 and n2 may be equal or unequal.

[0021] Optionally, the display area further includes a plurality of virtual sub-pixels, wherein the orthographic projection of the first winding portion of the n2 first signal lines on the substrate is located between the orthographic projection of the virtual sub-pixels on the substrate and the orthographic projection of the hole area on the substrate; n2 is greater than n1.

[0022] Optionally, the winding area includes a first sub-region and a second sub-region opposite to each other along a first direction. The first winding portion of the n1 first signal lines is arranged in the first sub-region, and the first winding portion of the n2 first signal lines is arranged in the second sub-region. In the extension direction of the aperture diameter parallel to the first direction, the width of the first sub-region is smaller than the width of the second sub-region.

[0023] Optionally, the plurality of second signal lines are divided into a first group of second signal lines and a second group of second signal lines, wherein the first group of second signal lines includes m1 second signal lines and the second group of second signal lines includes m2 second signal lines.

[0024] Along the second direction, the second winding portion of the m1 second signal lines is located on the third side of the hole area, and the second winding portion of the m2 second signal lines is located on the fourth side of the hole area. m1 and m2 may be equal or unequal.

[0025] Optionally, the display area further includes a plurality of virtual sub-pixels, wherein the orthographic projection of the second winding portion of the m2 second signal lines on the substrate is located between the orthographic projection of the virtual sub-pixels on the substrate and the orthographic projection of the hole area on the substrate; m2 is greater than m1.

[0026] Optionally, the winding area includes a third sub-region and a fourth sub-region opposite to each other along the second direction. The second winding portion of the m1 second signal lines is disposed in the third sub-region, and the second winding portion of the m2 second signal lines is disposed in the fourth sub-region. In the extension direction of the aperture diameter parallel to the second direction, the width of the third sub-region is equal to the width of the fourth sub-region.

[0027] Optionally, the display panel includes at least two of the aperture areas, and the plurality of virtual sub-pixels are located between two adjacent aperture areas.

[0028] Optionally, the wiring method of the winding areas around each of the hole areas is the same.

[0029] Optionally, the orthographic projections of the plurality of first winding portions included in the plurality of first signal lines on the substrate are arranged sequentially along the direction close to the hole region, and adjacent first winding portions are disposed in different layers; and / or, the orthographic projections of the plurality of second winding portions included in the plurality of second signal lines on the substrate are arranged sequentially along the direction close to the hole region, and adjacent second winding portions are disposed in different layers.

[0030] Optionally, the display panel includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked along a direction away from the substrate.

[0031] Of the plurality of first signal lines, a portion of the first signal lines includes the first winding portion which is disposed in the same layer and material as the first source / drain metal layer, and another portion of the first signal lines includes the first winding portion which is disposed in the same layer and material as the second source / drain metal layer.

[0032] Of the plurality of second signal lines, a portion of the second signal lines includes a second winding portion that is disposed in the same layer and with the same material as the first gate metal layer, while another portion of the second signal lines includes a second winding portion that is disposed in the same layer and with the same material as the second gate metal layer.

[0033] Optionally, the first signal line includes a data line, and the second signal line includes a scan line.

[0034] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0036] Figure 1 is a schematic diagram of the layout of the hole area and the winding area in the display panel provided in an embodiment of this disclosure;

[0037] Figure 2 is a schematic diagram of the layout of the first signal line in the upper left part of the hole area in Figure 1;

[0038] Figure 3 is a schematic diagram of the layout of the second signal line in the upper left part of the hole area in Figure 1;

[0039] Figure 4 is a schematic diagram of the layout of the first signal line and part of the second signal line in the upper left part of the hole area in Figure 1;

[0040] Figure 5 is a schematic diagram of the layout of the first signal line, part of the second signal line, and part of the shielding layer in the upper left part of the hole area in Figure 1.

[0041] Figure 6 is a schematic diagram of the layout of the first signal line, part of the second signal line, and part of the shielding layer directly above the hole area in Figure 1.

[0042] Figure 7 is a schematic diagram of the layout of the first signal line, part of the second signal line, and part of the shielding layer in the upper right part of the hole area in Figure 1.

[0043] Figure 8 is a schematic diagram of the layout of the first signal line, part of the second signal line, and part of the shielding layer directly below the hole area in Figure 1.

[0044] Figure 9 is a schematic diagram of a layout of the first signal line near the hole area provided in an embodiment of this disclosure;

[0045] Figure 10 is a schematic diagram of a layout of the second signal line near the hole area provided in an embodiment of this disclosure;

[0046] Figure 11 is a schematic diagram of a layout of the first signal line near two hole regions provided in an embodiment of this disclosure. Detailed Implementation

[0047] To further illustrate the display panel and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0048] Please refer to Figures 1 to 8. This disclosure provides a display panel including: an aperture area 10, a winding area 20, and a display area. The winding area 20 is located between the aperture area 10 and the display area, and surrounds the aperture area 10. The display panel further includes:

[0049] Multiple first signal lines 41, each first signal line 41 including a first winding portion 410 located in the winding region 20, the first winding portion 410 being disposed around at least a portion of the edge of the hole region 10;

[0050] Multiple second signal lines 42, each second signal line 42 including a second winding portion 420 located in the winding region 20, the second winding portion 420 being disposed around at least a portion of the edge of the hole region 10;

[0051] A shielding layer 50 is disposed around at least a portion of the edge of the hole region 10, and at least a portion of the orthographic projection of the shielding layer 50 on the substrate of the display panel is located between the orthographic projection of the first winding portion 410 on the substrate and the orthographic projection of the second winding portion 420 on the substrate.

[0052] For example, the display panel includes at least one aperture area 10, at least one winding area 20, and a display area, wherein the winding area 20 surrounds a corresponding aperture area 10, and the display area surrounds each winding area 20. The aperture area 10 is used to house sensing components such as cameras, the winding area 20 is used to lay out signal lines in the display panel, and the display area includes an array of sub-pixels.

[0053] For example, the first signal line 41 includes a first winding portion 410 located in the winding region 20, the first winding portion 410 extending along at least a portion of the boundary of the aperture region 10. The second signal line 42 includes a second winding portion 420 located in the winding region 20, the second winding portion 420 extending along at least a portion of the boundary of the aperture region 10. The first signal line 41 and the second signal line 42 are used to transmit different signals.

[0054] For example, the shielding layer 50 extends along at least a portion of the boundary of the aperture region 10, and the shielding layer 50 has a stable potential. For example, the shielding layer 50 may be configured to surround the aperture region 10, but is not limited thereto.

[0055] For example, the width of the shielding layer 50 around the hole area 10 may be uniform or non-uniform, which is not limited here.

[0056] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, the first winding portion 410 of the first signal line 41 and the second winding portion 420 of the second signal line 42 are both disposed around at least a portion of the edge of the hole area 10; at the same time, the shielding layer 50 included in the display panel is also disposed around at least a portion of the edge of the hole area 10, and at least a portion of the orthographic projection of the shielding layer 50 on the substrate of the display panel is located between the orthographic projection of the first winding portion 410 on the substrate and the orthographic projection of the second winding portion 420 on the substrate; in this way, the shielding layer 50 can effectively shield the crosstalk between the signal transmitted by the first signal line 41 and the second signal transmitted by the second signal line 42, ensuring the display effect of the display panel.

[0057] As shown in Figures 1 to 8, in some embodiments, the display panel further includes a light-shielding layer 51 and a plurality of display sub-pixels (located in the display sub-pixel layout area Q5); the light-shielding layer 51 includes a plurality of light-shielding patterns 511 arranged in an array and a plurality of first connecting lines 512, the light-shielding patterns 511 located in the same row along a first direction are coupled to each other by corresponding first connecting lines 512, the orthographic projection of the light-shielding pattern 511 on the substrate overlaps at least partially with the orthographic projection of the transistor structure in the corresponding display sub-pixel on the substrate; the shielding layer 50 is coupled to at least a portion of the first connecting lines 512.

[0058] For example, the display substrate includes a plurality of display sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of display sub-pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0059] For example, the display sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0060] For example, the sub-pixel driving circuit includes multiple transistor structures and storage capacitors, such as a 7T1C (i.e., 7 transistors and 1 capacitor) circuit structure, an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, or a 9T1C (i.e., 9 transistors and 1 capacitor) circuit structure, but is not limited to these.

[0061] For example, the light-shielding layer 51 includes an array of multiple light-shielding patterns 511, multiple first connecting lines 512 and multiple second connecting lines. The light-shielding patterns 511 located in the same row along the first direction are coupled to each other through the corresponding first connecting lines 512, and the light-shielding patterns 511 located in the same column along the second direction are coupled to each other through the corresponding second connecting lines, so that the light-shielding layer 51 is formed into a grid structure.

[0062] For example, the orthographic projection of the light-shielding pattern 511 on the substrate at least partially overlaps with the orthographic projection of the driving transistor in the corresponding sub-pixel driving circuit on the substrate; and / or, the orthographic projection of the light-shielding pattern 511 on the substrate at least partially overlaps with the orthographic projection of the compensation transistor in the corresponding sub-pixel driving circuit on the substrate; and / or, the orthographic projection of the light-shielding pattern 511 on the substrate at least partially overlaps with the orthographic projection of the data writing transistor in the corresponding sub-pixel driving circuit on the substrate, but is not limited to these.

[0063] For example, the light-shielding layer 51 is located on the side of the sub-pixel driving circuit facing the substrate, and the light-shielding layer 51 has a stable potential.

[0064] For example, the shielding layer 50 and the light-shielding layer 51 are made of the same layer and material, so that the shielding layer 50 and the first connecting line 512 form an integral structure, but this is not limited to this. This arrangement allows the shielding layer 50 and the light-shielding layer 51 to be formed simultaneously in the same patterning process, which helps to simplify the manufacturing process of the display panel and reduce the manufacturing cost of the display panel.

[0065] In the display panel provided in the above embodiments, by setting the shielding layer 50 to be coupled with the light-shielding layer 51, the shielding layer 50 has the same stable potential as the light-shielding layer 51, thus ensuring the effective shielding effect of the shielding layer 50.

[0066] In some embodiments, the display panel further includes a power signal line, and the light-shielding layer 51 is coupled to the power signal line.

[0067] For example, the power signal line is used to transmit a power signal with a stable potential. By setting the light-shielding layer 51 to be coupled to the power signal line, the light-shielding layer 51 has the same stable potential as the power signal. Furthermore, the shielding layer 50 is set to be coupled to the light-shielding layer 51, so that the shielding layer 50 has the same stable potential as the power signal, thereby ensuring the shielding effect of the shielding layer 50.

[0068] For example, the power signal line may be located in the display area of ​​the display panel or in the surrounding area of ​​the display area, without limitation.

[0069] As shown in Figures 1 to 8, in some embodiments, the orthographic projection of the first winding portion 410 on the substrate does not overlap with the orthographic projection of the second winding portion 420 on the substrate.

[0070] For example, the first signal line 41 includes a data line for transmitting data signals, and the second signal line 42 includes a scan line for transmitting scan signals.

[0071] For example, the scan line includes at least one of a gate line, a reset signal line, and a light emission control signal line, but is not limited to this.

[0072] The specific layout of the second signal line 42 can vary. For example, the first gate line and the third reset signal line that need to be wound around the aperture region 10 can be connected together and reused by the same second signal line 42 to bypass the aperture region 10. The first gate line is coupled to the first row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10. The third reset signal line is coupled to the third row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10.

[0073] For example, the first and second light-emitting control signal lines that need to be wound around the aperture region 10 are connected together and multiplexed by the same second signal line 42 around the aperture region 10. The first light-emitting control signal line is coupled to the first row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10. The second light-emitting control signal line is coupled to the second row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10.

[0074] For example, the first gate line and the second reset signal line that need to be wound in the aperture region 10 are connected together and the same second signal line 42 is reused to bypass the aperture region 10. The first gate line is coupled to the first row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10. The second reset signal line is coupled to the second row of sub-pixel driving circuits, which are arranged along the first direction with the aperture region 10.

[0075] For example, each light-emitting control signal line that needs to be wound in the aperture area 10 bypasses the aperture area 10 through an independent second signal line 42.

[0076] As shown in Figures 4 and 5, by way of example, the orthographic projection of the first winding portion 410 on the substrate is located between the orthographic projection of the second winding portion 420 on the substrate and the orthographic projection of the hole region 10 on the substrate.

[0077] For example, the orthographic projection of the second winding portion 420 on the substrate is located between the orthographic projection of the first winding portion 410 on the substrate and the orthographic projection of the hole region 10 on the substrate.

[0078] The above-mentioned arrangement ensures that the orthographic projection of the first winding portion 410 on the substrate does not overlap with the orthographic projection of the second winding portion 420 on the substrate. This allows the first signal line 41 and the second signal line 42 to be wound in separate areas within the winding region, reducing the overlap area between the first signal line and the second signal line. This effectively reduces the impact of the second signal transition transmitted by the second signal line 42 on the first signal transmitted by the first signal line 41, thereby significantly improving the display quality of the display panel.

[0079] As shown in Figures 1 to 8, in some embodiments, the first signal line 41 further includes two first lead portions 411 arranged along a second direction, the first lead portions 411 extending along the second direction, the first winding portion 410 being located between the two first lead portions 411, a first end of the first winding portion 410 being coupled to one of the first lead portions 411, and a second end of the first winding portion 410 being coupled to the other first lead portion 411;

[0080] The second signal line 42 further includes two second lead portions 421 arranged along a first direction. The second lead portions 421 extend along the first direction. The second winding portion 420 is located between the two second lead portions 421. The first end of the second winding portion 420 is coupled to one of the second lead portions 421, and the second end of the second winding portion 420 is coupled to the other second lead portion 421. The second direction intersects with the first direction.

[0081] For example, the first lead portion 411 and the first winding portion 410 are formed as an integral structure, and the second lead portion 421 and the second winding portion 420 are formed as an integral structure, but not limited thereto.

[0082] For example, both the first lead portion 411 and the second lead portion 421 are located in the winding area 20.

[0083] For example, the first signal line 41 further includes two data transmission portions located in the display area, the two data transmission portions being coupled one-to-one with the two first lead portions 411, and the two first lead portions 411 and the first winding portion 410 being located between the two data transmission portions.

[0084] For example, the second signal line 42 further includes at least two scan transmission portions located in the display area, and the second lead portion 421 is coupled to at least one corresponding scan transmission portion. For instance, the second signal line 42 includes two scan transmission portions, each coupled to one of the two second lead portions 421, with both the two second lead portions 421 and the second winding portion 420 located between the two scan transmission portions. As another example, the second signal line 42 includes four scan transmission portions, divided into two transmission groups, each group including two scan transmission portions. The two second lead portions 421 correspond one-to-one with the two transmission groups, each coupled to two scan transmission portions in a corresponding transmission group, with both second lead portions 421 and the second winding portion 420 located between the two transmission groups.

[0085] For example, each transmission group may include two scan transmission sections, which may include a gate line and a reset signal line, or two light emission control signal lines, but are not limited to these.

[0086] It is worth noting that the orthographic projection of the first lead portion 411 on the substrate inevitably overlaps with the orthographic projection of the second winding portion 420 on the substrate, but the overlap area is very small. Compared with the case in the prior art where the orthographic projections of the first winding portion 410 and the second winding portion 420 overlap on the substrate, the solution of this application greatly reduces the overlap area of ​​the orthographic projections of the first signal line 41 and the second signal line 42 on the substrate, thereby effectively improving the crosstalk problem between the first signal transmitted by the first signal line 41 and the second signal transmitted by the second signal line 42.

[0087] In the display panel provided in the above embodiments, by setting the first signal line 41 to include the first winding portion 410 and the first lead portion 411, it is not only ensured that the first signal line 41 can bypass the hole area 10, but also that there is a good connection between the portion of the first signal line 41 located in the winding area 20 and the portion located in the display area.

[0088] In the display panel provided in the above embodiment, by setting the second signal line 42 to include the second winding portion 420 and the second lead portion 421, it is not only ensured that the second signal line 42 can bypass the hole area 10, but also that there is a good connection between the portion of the second signal line 42 located in the winding area 20 and the portion located in the display area.

[0089] As shown in Figures 1, 9 and 11, in some embodiments, the plurality of first signal lines 41 are divided into a first group of first signal lines Z1 and a second group of first signal lines Z2. The first group of first signal lines Z1 includes n1 first signal lines 41, and the second group of first signal lines Z2 includes n2 first signal lines 41.

[0090] Along the first direction, the first winding portion 410 of the n1 first signal lines 41 is located on the first side of the hole area 10, and the first winding portion 410 of the n2 first signal lines 41 is located on the second side of the hole area 10. n1 and n2 may be equal or unequal.

[0091] It should be noted that the arrows in Figures 9 to 11 indicate the boundary between adjacent signal line groups. Figures 9 and 10 also illustrate the outer isolation pillars 91 and inner isolation pillars 92. The number of outer isolation pillars 91 and inner isolation pillars 92 is not specifically limited; for example, the number of outer isolation pillars 91 may be greater than the number of inner isolation pillars 92, but this is not a limitation. The structure inside the hole area 10 in Figures 9 to 11 will eventually be removed, and a blocking structure can be installed in the area between the outer isolation pillars 91 and inner isolation pillars 92.

[0092] For example, both n1 and n2 are greater than 0.

[0093] The above settings of n1 and n2 being equal or unequal allow for flexible arrangement of the first signal lines 41 according to the actual layout space of the winding area 20. For example, when n1 equals n2, the first winding portions 410 of the multiple first signal lines 41 can be symmetrically arranged in the winding area 20; when n1 is greater than n2, there are more first winding portions 410 of the first signal lines 41 arranged in the winding area 20 on the first side of the hole area 10, and fewer first winding portions 410 of the first signal lines 41 arranged in the winding area 20 on the second side of the hole area 10; when n1 is less than n2, there are fewer first winding portions 410 of the first signal lines 41 arranged in the winding area 20 on the first side of the hole area 10, and more first winding portions 410 of the first signal lines 41 arranged in the winding area 20 on the second side of the hole area 10.

[0094] As shown in Figures 1, 9 and 11, in some embodiments, the display area further includes a plurality of virtual sub-pixels (located in the virtual sub-pixel layout area Q6), and the orthographic projection of the first winding portion 410 of the n2 first signal lines 41 on the substrate is located between the orthographic projection of the virtual sub-pixels on the substrate and the orthographic projection of the hole area 10 on the substrate; n2 is greater than n1.

[0095] For example, the display area further includes a plurality of display sub-pixels (located in the display sub-pixel layout area Q5), and the orthographic projection of the first winding portion 410 of the n1 first signal lines 41 on the substrate is located between the orthographic projection of the display sub-pixel on the substrate and the orthographic projection of the hole area 10 on the substrate.

[0096] For example, the display panel includes at least two aperture regions 10, and the plurality of virtual sub-pixels are located between two adjacent aperture regions 10. Taking a display panel including two aperture regions 10 as an example, the plurality of virtual sub-pixels are located between these two aperture regions 10. It is worth noting that the display sub-pixels in the display panel are capable of emitting light to realize the display function of the display panel. The film layer below the anode layer in the virtual sub-pixels of the display panel is consistent with the display sub-pixels, but the virtual sub-pixels do not include the anode layer and the light-emitting functional layer above the anode layer; that is, the virtual sub-pixels do not emit light.

[0097] For example, the wiring method of the winding areas 20 around each of the hole areas 10 is the same, that is, within the winding areas 20 around each hole area 10, the orthographic projection of the first winding portion 410 of the n2 first signal lines 41 on the substrate is located between the orthographic projection of the virtual sub-pixel on the substrate and the orthographic projection of the hole area 10 on the substrate. For example, as shown in FIG11, the wiring method of the winding areas 20 around the two shown hole areas 10 is symmetrically arranged.

[0098] The above arrangement results in a situation where more first winding portions 410 are arranged in the area near the virtual sub-pixel within the winding area 20, and fewer first winding portions 410 are arranged in the area near the display sub-pixel. That is, the multiple first winding portions 410 included in the multiple first signal lines 41 adopt an asymmetrical design, which helps to reduce the width of the area near the display sub-pixel in the winding area 20.

[0099] As shown in Figures 1, 9, and 11, in some embodiments, the winding region 20 includes a first sub-region Q1 and a second sub-region Q2 opposite to each other along a first direction. The first winding portion 410 of the n1 first signal lines 41 is disposed in the first sub-region Q1, and the first winding portion 410 of the n2 first signal lines 41 is disposed in the second sub-region Q2. In the extension direction of the aperture diameter parallel to the first direction, the width of the first sub-region Q1 is smaller than the width of the second sub-region Q2.

[0100] For example, the first sub-region Q1 is located between the aperture area 10 and the display sub-pixel, and the second sub-region Q2 is located between the aperture area 10 and the virtual sub-pixel.

[0101] For example, a larger layout space can be provided for the second sub-region Q2 by reducing the number of virtual sub-pixels.

[0102] For example, the multiple first lead portions 411 of the multiple first signal lines 41 can be connected to form a regular circle away from the edge of the hole area. The first winding portion 410 closest to the hole area 10 can form a regular circle. The area between these two circles has a fixed area. By fixing the position of the circle close to the hole area 10, taking the left hole area 10 in Figure 11 as an example, the distance between the two circles on the left side on the central axis is set to be smaller than the distance between the two circles on the right side on the central axis, which can effectively reduce the width of the area on the side of the winding area 20 close to the display sub-pixel.

[0103] The above configuration results in the first sub-region Q1 near the display sub-pixel within the winding area 20 having a smaller width along the radial direction of the aperture area 10, for arranging a smaller number of the first winding portions 410 included in the n1 first signal lines 41; and the second sub-region Q2 near the virtual sub-pixel within the winding area 20 having a larger width along the radial direction of the aperture area 10, for arranging a larger number of the first winding portions 410 included in the n2 first signal lines 41; the above configuration effectively reduces the width of the region near the display sub-pixel in the winding area 20.

[0104] As shown in Figures 1, 10 and 11, in some embodiments, the plurality of second signal lines 42 are divided into a first group of second signal lines Z3 and a second group of second signal lines Z4. The first group of second signal lines Z3 includes m1 second signal lines 42, and the second group of second signal lines Z4 includes m2 second signal lines 42.

[0105] Along the second direction, the second winding portion 420 of the m1 second signal lines 42 is located on the third side of the hole area 10, and the second winding portion 420 of the m2 second signal lines 42 is located on the fourth side of the hole area 10. m1 and m2 may be equal or unequal.

[0106] For example, both m1 and m2 are greater than 0.

[0107] The above settings of m1 and m2 being equal or unequal allow for flexible arrangement of the second signal lines 42 according to the actual layout space of the winding area 20. For example, when m1 equals m2, the second winding portions 420 of the multiple second signal lines 42 can be symmetrically arranged in the winding area 20; when m1 is greater than m2, there are more second winding portions 420 of the second signal lines 42 arranged in the winding area 20 located on the third side of the hole area 10, and fewer second winding portions 420 of the second signal lines 42 arranged in the winding area 20 located on the fourth side of the hole area 10; when m1 is less than m2, there are fewer second winding portions 420 of the second signal lines 42 arranged in the winding area 20 located on the third side of the hole area 10, and more second winding portions 420 of the second signal lines 42 arranged in the winding area 20 located on the fourth side of the hole area 10.

[0108] As shown in Figures 1, 10, and 11, in some embodiments, when m1 and m2 are equal, the winding region 20 includes a third sub-region Q3 and a fourth sub-region Q4 opposite to each other along the second direction. The second winding portion 420 of the m1 second signal lines 42 is disposed in the third sub-region Q3, and the second winding portion 420 of the m2 second signal lines 42 is disposed in the fourth sub-region Q4. In the extension direction of the aperture diameter parallel to the second direction, the width of the third sub-region Q3 is equal to the width of the fourth sub-region Q4.

[0109] In some embodiments, the display panel includes at least two aperture regions 10, the at least two aperture regions 10 are arranged along a second direction, the display area also includes a plurality of virtual sub-pixels, the virtual sub-pixels are located between two adjacent aperture regions 10, the second winding portion 420 of the m2 second signal lines 42 is projected onto the substrate between the projected virtual sub-pixels onto the substrate and the projected aperture regions 10 onto the substrate; m2 is greater than m1.

[0110] For example, the display area further includes a plurality of display sub-pixels. Around the aperture area 10, at least some of the display sub-pixels are located on one side of the aperture area 10 along the second direction, and at least some of the virtual sub-pixels are located on the other side of the aperture area 10 along the second direction. The second winding portion 420 of the m1 second signal line 42 is projected onto the substrate between the projection of the display sub-pixel onto the substrate and the projection of the aperture area 10 onto the substrate.

[0111] For example, the display panel includes at least two aperture regions 10 arranged along a second direction, and the plurality of virtual sub-pixels are located between two adjacent aperture regions 10. Taking the display panel including two aperture regions 10 arranged along a second direction as an example, the plurality of virtual sub-pixels are located between the two aperture regions 10.

[0112] For example, the wiring method of the winding area 20 around each of the hole areas 10 is the same, that is, in the winding area 20 around each hole area 10, the orthographic projection of the second winding portion 420 of the m2 second signal lines 42 on the substrate is located between the orthographic projection of the virtual sub-pixel on the substrate and the orthographic projection of the hole area 10 on the substrate.

[0113] The above arrangement results in a situation where more second winding portions 420 are arranged in the area near the virtual sub-pixel within the winding area 20, and fewer second winding portions 420 are arranged in the area near the display sub-pixel. That is, the multiple second winding portions 420 included in the multiple second signal lines 42 adopt an asymmetrical design, which helps to reduce the width of the area near the display sub-pixel in the winding area 20.

[0114] As shown in Figures 1 to 8, in some embodiments, the orthographic projections of the plurality of first winding portions 410 included in the plurality of first signal lines 41 on the substrate are arranged sequentially along the direction close to the hole region 10, and adjacent first winding portions 410 are disposed in different layers; and / or, the orthographic projections of the plurality of second winding portions 420 included in the plurality of second signal lines 42 on the substrate are arranged sequentially along the direction close to the hole region 10, and adjacent second winding portions 420 are disposed in different layers.

[0115] For example, among the multiple first winding portions 410 included in the multiple first signal lines 41, the first winding portions 410 included in the odd-numbered first signal lines 41 are arranged in the same layer and with the same material, and the first winding portions 410 included in the even-numbered first signal lines 41 are arranged in the same layer and with the same material.

[0116] For example, among the multiple second winding portions 420 included in the multiple second signal lines 42, the second winding portions 420 included in the odd-numbered second signal lines 42 are arranged in the same layer and with the same material, and the second winding portions 420 included in the even-numbered second signal lines 42 are arranged in the same layer and with the same material.

[0117] For example, the orthographic projection of the adjacent first winding portion 410 on the substrate does not overlap with the orthographic projection of the second winding portion 420 on the substrate.

[0118] For example, the lengths of each of the first winding portions 410 and each of the second winding portions 420 are different.

[0119] The above-mentioned arrangement of adjacent first winding portions 410 in different layers effectively avoids the problem of short circuit between adjacent first winding portions 410, reduces the difficulty of laying out the first signal line 41 in the winding area 20, and ensures the working stability and manufacturing yield of the display panel.

[0120] The above-mentioned arrangement of adjacent second winding portions 420 in different layers effectively avoids the problem of short circuit between adjacent second winding portions 420, reduces the difficulty of laying out the second signal line 42 in the winding area 20, and ensures the working stability and manufacturing yield of the display panel.

[0121] In some embodiments, the display panel includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked along a direction away from the substrate.

[0122] Of the plurality of first signal lines 41, a portion of the first signal lines 41 include the first winding portion 410 which is disposed in the same layer and with the same material as the first source / drain metal layer, and another portion of the first signal lines 41 include the first winding portion 410 which is disposed in the same layer and with the same material as the second source / drain metal layer.

[0123] Of the plurality of second signal lines 42, a portion of the second signal lines 42 include a second winding portion 420 that is disposed in the same layer and with the same material as the first gate metal layer, while another portion of the second signal lines 42 include a second winding portion 420 that is disposed in the same layer and with the same material as the second gate metal layer.

[0124] For example, the display panel includes a light-shielding layer 51, a first active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a third gate insulating layer, a second active layer, a fourth gate insulating layer, a third gate metal layer, an interlayer insulating layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, an anode layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer, all stacked sequentially along a direction away from the substrate. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0125] It is worth noting that the display panel may also include at least one passivation layer, which may be located between the source / drain metal layer and the planarization layer. The third gate insulating layer, the second active layer, the fourth gate insulating layer, and the third gate metal layer may be optionally provided as needed.

[0126] For example, a portion of the first signal line 41 described above may include an odd number of first winding portions 410, while another portion of the first signal line 41 described above may include an even number of first winding portions 410.

[0127] For example, a portion of the first signal line 41 described above may include an even number of first winding portions 410, while another portion of the first signal line 41 described above may include an odd number of first winding portions 410.

[0128] The above-mentioned configuration includes a portion of the first signal line 41 including the first winding portion 410 which is disposed in the same layer and with the same material as the first source / drain metal layer, and another portion of the first signal line 41 including the first winding portion 410 which is disposed in the same layer and with the same material as the second source / drain metal layer. This allows a portion of the first signal line 41 including the first winding portion 410 to be formed simultaneously with the first source / drain metal layer in the same patterning process, and allows the other portion of the first signal line 41 including the first winding portion 410 to be formed simultaneously with the second source / drain metal layer in the same patterning process, thereby effectively simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.

[0129] For example, a portion of the second signal line 42 described above may include an odd number of second winding portions 420, while another portion of the second signal line 42 described above may include an even number of second winding portions 420.

[0130] For example, a portion of the second signal line 42 described above may include an even number of second winding portions 420, while another portion of the second signal line 42 described above may include an odd number of second winding portions 420.

[0131] The above-mentioned configuration includes a portion of the second signal line 42 including the second winding portion 420 which is disposed in the same layer and with the same material as the first gate metal layer, and another portion of the second signal line 42 including the second winding portion 420 which is disposed in the same layer and with the same material as the second gate metal layer. This allows a portion of the second signal line 42 including the second winding portion 420 to be formed simultaneously with the first gate metal layer in the same patterning process, and allows the other portion of the second signal line 42 including the second winding portion 420 to be formed simultaneously with the second gate metal layer in the same patterning process, thereby effectively simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.

[0132] The display panel provided in the above embodiments does not require additional patterning processes, nor does it require increasing the thickness of the planarization layer in the display panel. This effectively solves the problem of crosstalk between the first signal line 41 and the second signal line 42, thereby improving the display quality of the display panel.

[0133] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0134] For example, the display panel includes an organic light-emitting diode (OLED) display panel, and the display device includes an OLED display device, but is not limited thereto. It should be noted that the display device can be any product or component with display functionality, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device may also include flexible circuit boards, printed circuit boards, and backplanes, etc.

[0135] In the display panel provided in the above embodiment, the first winding portion 410 of the first signal line 41 and the second winding portion 420 of the second signal line 42 are both disposed around at least a portion of the edge of the hole area 10; at the same time, the shielding layer 50 included in the display panel is also disposed around at least a portion of the edge of the hole area 10, and at least a portion of the orthographic projection of the shielding layer 50 on the substrate of the display panel is located between the orthographic projection of the first winding portion 410 on the substrate and the orthographic projection of the second winding portion 420 on the substrate; in this way, the shielding layer 50 can effectively shield the crosstalk between the signal transmitted by the first signal line 41 and the second signal transmitted by the second signal line 42, ensuring the display effect of the display panel.

[0136] The display device provided in this embodiment of the present disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0137] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0138] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0139] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0140] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0141] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0142] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0143] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0144] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: The device includes an aperture area, a winding area, and a display area, wherein the winding area is located between the aperture area and the display area, and the winding area surrounds the aperture area. The display panel also includes: Multiple first signal lines, each first signal line including a first winding portion located in the winding area, the first winding portion being disposed around at least a portion of the edge of the hole area; Multiple second signal lines, each second signal line including a second winding portion located in the winding region, the second winding portion being disposed around at least a portion of the edge of the hole region; A shielding layer is disposed around at least a portion of the edge of the hole area, and at least a portion of the shielding layer's orthographic projection on the substrate of the display panel is located between the orthographic projections of the first winding portion and the second winding portion on the substrate.

2. The display panel according to claim 1, wherein, The display panel further includes a light-shielding layer and a plurality of display sub-pixels; the light-shielding layer includes a plurality of light-shielding patterns arranged in an array and a plurality of first connecting lines, the light-shielding patterns located in the same row along the first direction are coupled to each other by the corresponding first connecting lines, and the orthographic projection of the light-shielding pattern on the substrate at least partially overlaps with the orthographic projection of the transistor structure in the corresponding display sub-pixel on the substrate. The shielding layer is coupled to at least a portion of the first connecting line.

3. The display panel according to claim 2, wherein, The shielding layer and the light-shielding layer are made of the same material and layer.

4. The display panel according to claim 2, wherein, The display panel also includes a power signal line, and the light-shielding layer is coupled to the power signal line.

5. The display panel according to claim 1, wherein, The orthographic projection of the first winding portion on the substrate does not overlap with the orthographic projection of the second winding portion on the substrate.

6. The display panel according to claim 5, wherein, The orthographic projection of the first winding portion on the substrate is located between the orthographic projection of the second winding portion on the substrate and the orthographic projection of the hole region on the substrate.

7. The display panel according to claim 5, wherein, The orthographic projection of the second winding portion on the substrate is located between the orthographic projection of the first winding portion on the substrate and the orthographic projection of the hole region on the substrate.

8. The display panel according to claim 5, wherein, The first signal line further includes two first lead portions arranged along a second direction, the first lead portions extending along the second direction, the first winding portion being located between the two first lead portions, a first end of the first winding portion being coupled to one of the first lead portions, and a second end of the first winding portion being coupled to the other first lead portion. The second signal line further includes two second lead portions arranged along the first direction, the second lead portions extending along the first direction, the second winding portion being located between the two second lead portions, the first end of the second winding portion being coupled to one of the second lead portions, and the second end of the second winding portion being coupled to the other second lead portion; the second direction intersects the first direction.

9. The display panel according to claim 8, wherein, The plurality of first signal lines are divided into a first group of first signal lines and a second group of first signal lines. The first group of first signal lines includes n1 first signal lines, and the second group of first signal lines includes n2 first signal lines. Along the first direction, the first winding portion of the n1 first signal lines is located on the first side of the aperture region, and the first winding portion of the n2 first signal lines is located on the second side of the aperture region, where n1 and n2 may be equal or unequal.

10. The display panel according to claim 9, wherein, The display area also includes multiple virtual sub-pixels, and the orthographic projection of the first winding portion of the n2 first signal lines on the substrate is located between the orthographic projection of the virtual sub-pixels on the substrate and the orthographic projection of the hole area on the substrate; n2 is greater than n1.

11. The display panel according to claim 10, wherein, The winding area includes a first sub-region and a second sub-region that are opposite each other along a first direction. The first winding portion of the n1 first signal lines is arranged in the first sub-region, and the first winding portion of the n2 first signal lines is arranged in the second sub-region. In the extension direction of the aperture diameter parallel to the first direction, the width of the first sub-region is smaller than the width of the second sub-region.

12. The display panel according to claim 8, wherein, The multiple second signal lines are divided into a first group of second signal lines and a second group of second signal lines. The first group of second signal lines includes m1 second signal lines, and the second group of second signal lines includes m2 second signal lines. Along the second direction, the second winding portion of the m1 second signal lines is located on the third side of the hole area, and the second winding portion of the m2 second signal lines is located on the fourth side of the hole area. m1 and m2 may be equal or unequal.

13. The display panel according to claim 12, wherein, The display area also includes multiple virtual sub-pixels. The orthographic projection of the second winding portion of the m2 second signal lines on the substrate is located between the orthographic projection of the virtual sub-pixels on the substrate and the orthographic projection of the hole area on the substrate; m2 is greater than m1.

14. The display panel according to claim 12, wherein, The winding area includes a third sub-region and a fourth sub-region opposite each other along the second direction. The second winding portion of the m1 second signal lines is arranged in the third sub-region, and the second winding portion of the m2 second signal lines is arranged in the fourth sub-region. In the extension direction of the aperture diameter parallel to the second direction, the width of the third sub-region is equal to the width of the fourth sub-region.

15. The display panel according to claim 10 or 13, wherein, The display panel includes at least two aperture areas, and the plurality of virtual sub-pixels are located between two adjacent aperture areas.

16. The display panel according to claim 15, wherein, The wiring method of the winding area around each of the hole areas is the same.

17. The display panel according to claim 1, wherein, The orthographic projections of the plurality of first winding portions included in the plurality of first signal lines on the substrate are arranged sequentially along the direction close to the hole area, and adjacent first winding portions are disposed in different layers. And / or, The multiple second signal lines include multiple second winding portions whose orthographic projections on the substrate are arranged sequentially along the direction close to the hole region, and adjacent second winding portions are disposed in different layers.

18. The display panel according to claim 17, wherein, The display panel includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked along a direction away from the substrate. Of the plurality of first signal lines, a portion of the first signal lines includes the first winding portion which is disposed in the same layer and material as the first source / drain metal layer, and another portion of the first signal lines includes the first winding portion which is disposed in the same layer and material as the second source / drain metal layer. Of the plurality of second signal lines, a portion of the second signal lines includes a second winding portion that is disposed in the same layer and with the same material as the first gate metal layer, while another portion of the second signal lines includes a second winding portion that is disposed in the same layer and with the same material as the second gate metal layer.

19. The display panel according to claim 1, wherein, The first signal line includes a data line, and the second signal line includes a scan line.

20. A display device comprising a display panel as claimed in any one of claims 1 to 19.

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