Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises a display area and a first area surrounding the bottom of the display area. The display panel comprises a base substrate and a multi-layer film structure, wherein the multi-layer film structure comprises a first metal layer, a first planarization layer, a first electrode layer, a pixel defining layer and a second electrode layer, which are sequentially arranged, wherein a first sub-portion of the first planarization layer is provided with a first channel penetrating in a first direction; a first sub-portion of the first electrode layer is electrically connected to the part of a first sub-portion of the first metal layer serving as a voltage source supply (VSS) trace by means of the first channel; a first sub-portion of the pixel defining layer is provided with a second channel penetrating in the first direction; and the polarity of the second electrode layer is opposite the polarity of the first electrode layer, and a first sub-portion of the second electrode layer is electrically connected to the first sub-portion of the first electrode layer by means of the second channel. The display panel can effectively reduce the impedance of a VSS line and also solve the problem of high brightness burns, without increasing the width of a frame.

Description

Display panel and display device

[0001] This disclosure claims priority to Chinese Patent Application No. 202510229415.4, filed on February 27, 2025, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0003] With the rapid development of OLED (Organic Light Emitting Diode) display technology, its application in smartphones, televisions, and smart wearable devices is becoming increasingly widespread. OLED display panels, with their advantages of high contrast, wide color gamut, fast response time, and flexibility, are gradually becoming the mainstream choice for display technology. However, as consumers' demands for the aesthetic design of display devices continue to rise, narrowing the bottom bezel of OLED display panels has become an industry trend. While this narrow bezel design improves the aesthetics and portability of products, it also brings new technological challenges.

[0004] In OLED display panels, the VSS (Voltage Source Supply) circuit is a crucial component of the panel's circuit design, providing a stable reference voltage. With the narrowing of the bottom bezel, the design space for the VSS circuit is becoming increasingly limited. This leads to increased impedance in the VSS circuit, especially during high-brightness displays, where excessive current can easily cause burn-in. Burn-in not only affects the display's performance but also shortens its lifespan.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the aforementioned related technologies and to provide a display panel and display device.

[0007] According to one aspect of this disclosure, a display panel is provided, comprising: a display area and a first area surrounding the bottom of the display area, the display panel including a substrate and a multilayer film structure located on the same side of the substrate along a first direction, wherein the multilayer film structure includes:

[0008] A first metal layer is located on the side of the substrate away from the substrate, and includes a first sub-section located in the first region, wherein at least a portion of the first sub-section is used as a negative power supply voltage trace.

[0009] A first planarization layer is located on the side of the first metal layer away from the substrate, and includes a first sub-part located in the first region; the first sub-part of the first planarization layer is provided with a first channel penetrating the first planarization layer in the first direction.

[0010] A first electrode layer, located on the side of the first planarization layer opposite to the substrate, includes a first sub-section located in the first region; the first sub-section of the first electrode layer is electrically connected to a portion of the first sub-section of the first metal layer that serves as a negative power supply voltage trace through the first channel.

[0011] A pixel definition layer is located on the side of the first electrode layer away from the substrate, and includes a first sub-part located in the first region. The first sub-part of the pixel definition layer is provided with a second channel that penetrates the pixel definition layer in the first direction.

[0012] The second electrode layer is located on the side of the pixel definition layer opposite to the substrate and has the opposite polarity to the first electrode layer. It includes a first sub-part located in the first region, and the first sub-part of the second electrode layer is electrically connected to the first sub-part of the first electrode layer through the second channel.

[0013] According to one embodiment of this disclosure, the multilayer film structure in the first region is provided with a first barrier groove and a second barrier groove, the second barrier groove being located on the side of the first barrier groove facing the display area; and in the orthographic projection of the multilayer film structure onto the substrate, the material of each layer of the multilayer film structure located within the area covered by the orthographic projection of the first barrier groove onto the substrate is inorganic, and the material of each layer of the multilayer film structure located within the area covered by the orthographic projection of the second barrier groove onto the substrate is inorganic.

[0014] The portion of the multilayer film structure located between the first barrier groove and the second barrier groove forms a first barrier portion; the first barrier portion is arranged around the bottom edge of the display area.

[0015] According to one embodiment of this disclosure, the second electrode layer is a negative electrode layer, wherein:

[0016] The orthographic projection of the first sub-part of the second electrode layer away from the display area onto the substrate is in contact with the boundary line of the first barrier portion onto the substrate facing the display area.

[0017] Alternatively, the orthographic projection of the first sub-part of the second electrode layer away from the display area onto the substrate is located within the orthographic projection of the first barrier portion onto the substrate.

[0018] Alternatively, the orthographic projection of the first sub-part of the second electrode layer on the side away from the display area is located on the side of the first barrier portion on the side of the substrate away from the display area.

[0019] According to one embodiment of this disclosure, the multilayer film structure in the first region is provided with a third barrier groove, the third barrier groove being located on the side of the second barrier groove facing the display area and spaced apart from the second barrier groove; the portion of the multilayer film structure located between the second barrier groove and one of the third barrier grooves forms a second barrier portion; the second barrier portion is disposed around at least a portion of the bottom edge of the display area; wherein:

[0020] The second channel in the pixel definition layer forms the third barrier groove;

[0021] Alternatively, the orthographic projection of the first channel in the first planarization layer onto the substrate covers the orthographic projection of the second channel in the pixel definition layer onto the substrate, so as to cooperate with the second channel in the pixel definition layer to form the third barrier groove.

[0022] According to one embodiment of this disclosure, the multilayer film structure in the first region is provided with at least two third barrier grooves. The third barrier grooves are located on the side of the second barrier groove facing the display area and are spaced apart from the second barrier groove. At least two of the third barrier grooves are spaced apart in the arrangement direction of the first region and the display area. The portion of the multilayer film structure between the second barrier groove and one of the third barrier grooves forms a second barrier portion, and the portion of the multilayer film structure between adjacent third barrier grooves forms a second barrier portion. The second barrier portion is provided around at least a portion of the bottom edge of the display area. Wherein:

[0023] The second channel in the pixel definition layer forms the third barrier groove;

[0024] Alternatively, the orthographic projection of the first channel in the first planarization layer onto the substrate covers the orthographic projection of the second channel in the pixel definition layer onto the substrate, so as to cooperate with the second channel in the pixel definition layer to form the third barrier groove.

[0025] According to one embodiment of this disclosure, a second region is further included, the second region being connected to the first region to form a peripheral region, the peripheral region being disposed around the display area, wherein the display panel:

[0026] The first barrier portion is disposed around the display area;

[0027] And / or, the second barrier is disposed around the display area.

[0028] According to one embodiment of the present disclosure, a first sub-part of the first electrode layer is provided with a first vent that penetrates the first sub-part in the first direction, and the orthographic projection of the first vent onto the substrate is located within the orthographic projection of the second barrier portion onto the substrate.

[0029] According to one embodiment of this disclosure, the first vent has a rectangular orthographic projection on the substrate.

[0030] According to one embodiment of this disclosure, the multilayer film structure further includes:

[0031] The second planarization layer is located between the first metal layer and the substrate, and includes a first sub-section located in the first region;

[0032] The second metal layer is located between the substrate and the second planarization layer, and includes a first sub-section located in the first region.

[0033] According to one embodiment of the present disclosure, a first sub-part of the first metal layer is provided with a second vent that penetrates the first sub-part in the first direction, and the orthographic projection of the second vent on the substrate is located within the orthographic projection of the second barrier portion on the substrate.

[0034] According to one embodiment of the present disclosure, at least a portion of the orthographic projection of the second vent on the substrate overlaps with the orthographic projection of the first vent on the substrate.

[0035] According to one embodiment of this disclosure, the second vent has a rectangular orthographic projection on the substrate.

[0036] According to one embodiment of this disclosure, the multilayer film structure further includes:

[0037] The third planarization layer is located between the second metal layer and the substrate, and includes a first sub-section located in the first region;

[0038] The third metal layer is located between the substrate and the third planarization layer, and includes a first sub-section located in the first region.

[0039] According to one embodiment of this disclosure, a second region is further included, the second region being connected to the first region to form a peripheral region, the peripheral region being disposed around the display area, wherein the display panel:

[0040] The first metal layer further includes a second sub-section located in the second region;

[0041] The first planarization layer further includes a second sub-section located in the second region; the second sub-section of the first planarization layer is provided with a third channel penetrating the first planarization layer in the first direction;

[0042] The first electrode layer further includes a second sub-section located in the second region; the second sub-section of the first electrode layer is electrically connected to the second sub-section of the first metal layer through the third channel;

[0043] The pixel definition layer further includes a second sub-section located in the second region; the second sub-section of the pixel definition layer is provided with a fourth channel that penetrates the pixel definition layer in the first direction.

[0044] The second electrode layer further includes a second sub-section located in the second region; the second sub-section of the second electrode layer is electrically connected to the second sub-section of the first electrode layer through the fourth channel.

[0045] According to another aspect of this disclosure, a display device is provided, including a display panel as provided in any of the above-described technical solutions.

[0046] The display panel disclosed herein can reduce VSS impedance without increasing the bottom size of the display panel, thereby reducing the risk of high-brightness burn-in. Specifically, in the display panel disclosed herein, the second electrode layer has the opposite polarity to the first electrode layer, and the two overlap in the first area at the bottom of the display area and are connected to the first metal layer, which serves as the VSS trace, thus optimizing the current transmission path. Furthermore, this structure can reduce the path length and contact resistance of the current during transmission, effectively reducing VSS impedance. Accordingly, when the VSS impedance is reduced, the possibility of VSSDrop phenomenon in the display panel disclosed herein can be reduced. This design enables a more uniform voltage distribution within the display panel, thereby improving the uniformity of display brightness.

[0047] Furthermore, one of the first and second electrode layers is a negative electrode layer. Since negative electrode layers are typically thinner, their surface resistivity is higher. By overlapping and connecting to the low-resistivity first metal layer within the first region, the resistance of the negative electrode layer can be combined with the low-resistivity characteristics of the first metal layer, thereby reducing the overall VSS impedance.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The above and other features and advantages of the present invention will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0050] Figure 1 is a cross-sectional schematic diagram of a display panel in the related art;

[0051] Figure 2 is a plan view of the display panel provided in the first area according to an embodiment of the present disclosure;

[0052] Figure 3 is a cross-sectional view of the display panel along line AA in Figure 2;

[0053] Figure 4 is a simplified schematic diagram of the overall structure of the display panel provided in an embodiment of this disclosure;

[0054] Figure 5 is a plan view of the second electrode layer in the display panel provided in an embodiment of this disclosure;

[0055] Figure 6 is a planar schematic diagram of the pixel definition layer in the display panel provided in an embodiment of this disclosure;

[0056] Figure 7 is a plan view of the first electrode layer and the first planarization layer in the display panel provided in an embodiment of the present disclosure;

[0057] Figure 8 is a plan view of the first metal layer and the first planarization layer in the display panel provided in an embodiment of this disclosure;

[0058] Figure 9 is a plan view of the second metal layer and the second planarization layer in the display panel provided in the embodiment of this disclosure;

[0059] Figure 10 is a plan view of the insulating layer and the third planarization layer in the display panel provided in an embodiment of this disclosure;

[0060] Figure 11 is a plan view of the third metal layer in the display panel provided in an embodiment of this disclosure.

[0061] Figure label:

[0062] Related technologies: 100', substrate layer; 200', cathode layer;

[0063] This disclosure includes: 01, display area; 02, first area; 03, pad area; 04, second area; 100, substrate; 200, first metal layer; 210, second vent; 300, first planarization layer; 310, first channel; 400, first electrode layer; 410, first vent; 500, pixel definition layer; 510, second channel; 600, second electrode layer; 700, second planarization layer; 800, second metal layer; 810, VSS trace; 820, VDD trace; 900, third planarization layer; 1000, third metal layer; 1010, VSS trace; 1020, VDD trace; 1100, insulating layer; G1, first barrier trench; G2, second barrier trench; G3, third barrier trench; P1, first barrier portion; P2, second barrier portion. Detailed Implementation

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Although relative terms such as “upper” and “lower” are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples described in the accompanying drawings. It will be understood that if the device of the icon is flipped so that it is upside down, the component described as “upper” will become the component described as “lower.” Other relative terms such as “top” and “bottom” are used with similar meanings. When a structure is “upper” than another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure through another structure.

[0065] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” etc. are used only as markers and are not a limitation on the number of objects.

[0066] Figure 1 is a cross-sectional schematic diagram of a display panel in the related art. The structure of the display panel in the related art shown in Figure 1 is illustrated by way of example. The display panel in the related art includes a display area and a bottom area surrounding the bottom of the display area (i.e., the portion shown in Figure 1). As shown in Figure 1, the display panel includes a substrate 100' and a multilayer film layer disposed on one side of the substrate 100', wherein the cathode layer 200' in the multilayer film layer extends only a small portion from the display area to the bottom area.

[0067] Therefore, the coverage area of ​​the cathode layer 200' in the bottom region is small, and the cathode layer 200' and the anode layer are not overlapped in the bottom region. This results in an increase in VSS impedance of the display panel in the bottom region, which makes it prone to high-brightness burn-in.

[0068] Therefore, there is an urgent need to provide a display panel that can effectively reduce VSS line impedance without increasing bezel width, while solving the problem of high-brightness burn-in.

[0069] This disclosure provides a display panel. Figure 2 is a plan view of the display panel provided in the first region 02; Figure 3 is a cross-sectional view of the display panel in Figure 2 along line AA; Figure 4 is a simplified schematic diagram of the overall structure of the display panel provided in the embodiment of this disclosure. As shown in Figures 2, 3 and 4, the display panel includes: a display area 01 and a first region 02 surrounding the bottom of the display area 01. The display panel includes a substrate 100 and a multilayer film structure located on the same side of the substrate 100 along a first direction.

[0070] Understandably, the material of each membrane layer can be set to be inorganic or organic, depending on the requirements.

[0071] In specific implementation, the substrate 100 included in the display panel can be a rigid substrate or a flexible substrate, without limitation. When the substrate 100 is a flexible substrate, the material of the flexible substrate can be polyimide film (PI) or polyethylene terephthalate (PET), etc., without limitation. The flexible substrate can be a structure including a single flexible substrate layer or a structure including multiple flexible substrate layers, such as a structure with two flexible substrate layers or a structure with three flexible substrate layers, without limitation. In addition, a support layer (barrier) can be provided between two adjacent flexible substrate layers.

[0072] The multilayer film structure includes: a first metal layer 200, a first planarization layer 300, a first electrode layer 400, a pixel definition layer 500, and a second electrode layer 600 sequentially disposed along a first direction. Specifically, the first metal layer 200 is located on the side of the substrate 100 away from the substrate 100, including a first sub-part located in a first region 02, at least a portion of which serves as a negative power supply voltage trace (i.e., a VSS trace); the first planarization layer 300 is located on the side of the first metal layer 200 away from the substrate 100, including a first sub-part located in the first region 02; the first sub-part of the first planarization layer 300 has a first channel penetrating the first planarization layer 300 in a first direction; the first electrode layer 400 is located on the side of the first planarization layer 300 away from the substrate 100, including a first sub-part located in the first region 02; the first sub-part of the first electrode layer 4 ... sub-part of the first electrode layer 400 has a first channel penetrating the first planarization layer 300 in a first direction; the first sub-part of the first electrode layer 400 has a first channel penetrating the first planarization layer 300 in a first direction; the first sub-part of the first electrode layer 400 has a first channel penetrating the first planarization layer 300 in a first direction; the first sub-part of the first electrode layer The first part is electrically connected to the first sub-part of the first metal layer 200 via the first channel, serving as a negative power supply voltage trace; the pixel definition layer 500 is located on the side of the first electrode layer 400 away from the substrate 100, including the first sub-part located in the first region 02, and the first sub-part of the pixel definition layer 500 is provided with a second channel penetrating the pixel definition layer 500 in a first direction; the second electrode layer 600 is located on the side of the pixel definition layer 500 away from the substrate 100, and has the opposite polarity to the first electrode layer 400, including the first sub-part located in the first region 02, and the first sub-part of the second electrode layer 600 is electrically connected to the first sub-part of the first electrode layer 400 via the second channel.

[0073] Understandably, VSS traces are typically provided in the low-voltage region of a display panel to provide a low-level reference and current return path. In some designs, VSS traces, along with VDD (Voltage Drain Drain) traces, are connected to the back of the display panel or other layers via metal vias or conductive layers to optimize resistance and wiring space. VDD typically represents a positive power supply voltage, used to power active devices in the circuit. VSS typically represents ground or a negative power supply voltage. In this embodiment, the first metal layer 200 is used as a VSS trace; however, the VSS traces within the display panel may include more than one metal layer.

[0074] It should be noted that the display panel provided in this embodiment can reduce VSS impedance without increasing the bottom size of the display panel, thereby reducing the risk of high-brightness burn-in. Specifically, in the display panel provided in this embodiment, the second electrode layer 600 has the opposite polarity to the first electrode layer 400. The two overlap in the first area 02 at the bottom of the display area 01 and are connected to the first metal layer 200, which serves as the VSS trace, thus optimizing the current transmission path. Furthermore, this structure can reduce the path length and contact resistance of the current during transmission, thereby effectively reducing VSS impedance. Accordingly, when the VSS impedance is reduced, the possibility of VSSDrop phenomenon in the display panel provided in this embodiment can be reduced. This design enables a more uniform voltage distribution within the display panel, thereby improving the uniformity of display brightness.

[0075] It is understandable that VSSDrop specifically refers to the voltage rise on the ground wire, because ideally, VSS should remain at 0V, but due to the influence of resistance and current, a voltage rise may occur.

[0076] Furthermore, one of the electrode layers, the first electrode layer 400 and the second electrode layer 600, is a negative electrode layer. Since negative electrode layers are typically thinner, their surface resistivity is higher. By overlapping and connecting to the low-resistivity first metal layer 200 within the first region 02, the resistance of the negative electrode layer can be combined with the low-resistivity characteristics of the first metal layer 200, thereby reducing the overall VSS impedance.

[0077] It is worth noting that no new process is required when manufacturing the display panel provided in this embodiment; existing processes are sufficient. Furthermore, the display panel optimization method in this embodiment can achieve performance improvement without increasing additional costs.

[0078] As can be understood, as shown in Figure 2, the display panel also includes a pad area 03, which is located on the side of the first area 02 opposite to the display area 01. The overlap position of the first electrode layer 400 and the second electrode layer 600 is located within the first area 02 between the pad area 03 and the display area 01, and will not be described in detail here.

[0079] Of course, the pixel definition layer 500 also includes a portion located within the display area 01 to define the pixel opening region. Similarly, the first planarization layer 300, the first electrode layer 400, and the second electrode layer 600 also include portions located within the display area 01, which will not be described in detail here.

[0080] As shown in Figure 3, in one embodiment of this disclosure, the multilayer film structure in the first region 02 is provided with a first barrier groove G1 and a second barrier groove G2. The second barrier groove G2 is located on the side of the first barrier groove G1 facing the display area 01. In the orthographic projection of the multilayer film structure onto the substrate 100, each layer of the multilayer film structure within the area covered by the orthographic projection of the first barrier groove G1 onto the substrate 100 is made of inorganic material, and each layer of the multilayer film structure within the area covered by the orthographic projection of the second barrier groove G2 onto the substrate 100 is made of inorganic material. The portion of the multilayer film structure located between the first barrier groove G1 and the second barrier groove G2 forms a first barrier portion P1. The first barrier portion P1 is arranged around the bottom edge of the display area 01, thereby providing protection for the display area 01. The arrangement direction of the display area 01 and the first region 02 forms a second direction, which is perpendicular to the first direction.

[0081] It is understandable that inorganic materials have good barrier properties and can effectively prevent water and oxygen penetration and material diffusion; organic materials are usually hygroscopic and can easily lead to water and oxygen intrusion, thus affecting the performance and lifespan of the display panel.

[0082] It should be noted that in the embodiment of this disclosure, the display panel is configured such that the film structure on both sides of the first barrier part P1 in the second direction is inorganic. In other words, the film structure of organic matter on both sides of the first barrier part P1 in the second direction is removed, cutting off the water and oxygen channels, which can effectively block the intrusion of external water and oxygen and form a better encapsulation effect.

[0083] It is worth noting that the membrane structure within the first barrier portion P1 is not limited to that shown in Figure 3, and will not be described in detail here.

[0084] It is understood that during the manufacturing process of a display panel, the negative electrode layer is generally fabricated as a single layer, while the positive electrode layer is generally patterned to form a corresponding pattern. In one embodiment of this disclosure, the second electrode layer 600 is a negative electrode layer, which can extend from the display area 01 into the first area 02. The edge of the second electrode layer 600 away from the display area 01 is its cutoff edge, and the cutoff position of this cutoff edge can have multiple possibilities, at least one of the following structural forms:

[0085] Structure Form 1: As shown in Figure 3, the orthographic projection of the first sub-part of the second electrode layer 600 away from the display area 01 onto the substrate 100 contacts the boundary line of the first blocking part P1 onto the substrate 100 facing the display area 01. Figure 5 is a planar schematic diagram of the second electrode layer in the display panel provided in this embodiment; referring to the structure shown in Figure 5 in conjunction with Figure 3, the cutoff edge of the second electrode layer 600 contacts the boundary line of the first blocking part P1 facing the display area 01, thereby increasing the coverage area of ​​the first sub-part of the second electrode layer 600.

[0086] Structure Form Two: The orthographic projection of the first sub-part of the second electrode layer 600 away from the display area 01 onto the substrate 100 lies within the orthographic projection of the first blocking part P1 onto the substrate 100. That is, the cutoff edge of the second electrode layer 600 extends further to the position corresponding to the first blocking part P1 compared to the position in Structure Form One, further increasing the coverage area of ​​the first sub-part of the second electrode layer 600.

[0087] Structure Form 3: The orthographic projection of the first sub-part of the second electrode layer 600 away from the display area 01 onto the substrate 100 is located on the side of the first blocking part P1 away from the display area 01. That is, the cutoff edge of the second electrode layer 600 extends further to the side of the first blocking part P1 away from the display area 01 compared to the position in Structure Form 2, further increasing the coverage area of ​​the first sub-part of the second electrode layer 600.

[0088] It should be noted that the coverage area of ​​the negative electrode layer in the display panel provided in this embodiment is increased, which means that the effective reaction area of ​​the electrode is increased. According to Ohm's law, impedance is inversely proportional to the cross-sectional area of ​​the current path. When the coverage area of ​​the negative electrode layer increases, the current can be distributed more evenly, thereby reducing the current density per unit area and thus reducing the impedance. Moreover, when the coverage area of ​​the negative electrode layer increases, the overlap position between the second electrode layer 600 and the first electrode layer 400 increases, which can further reduce the VSS impedance and reduce the risk of burns.

[0089] It is worth noting that the pixel definition layer 500 and the first planarization layer 300 can be made of organic materials. Therefore, when the pixel definition layer 500 is made of organic materials, the first sub-part of the pixel definition layer 500 is removed in the portions corresponding to the first barrier trench G1 and the second barrier trench G2; when the first planarization layer 300 is made of organic materials, the first sub-part of the first planarization layer 300 is removed in the portions corresponding to the first barrier trench G1 and the second barrier trench G2.

[0090] In one embodiment of this disclosure, as shown in FIG3, the multilayer film structure in the first region 02 is provided with at least two third barrier grooves G3. The third barrier grooves G3 are located on the side of the second barrier groove G2 facing the display area 01 and are spaced apart from the second barrier groove G2. The at least two third barrier grooves G3 are spaced apart in the arrangement direction (i.e., the second direction) of the first region 02 and the display area 01. The portion of the multilayer film structure between the second barrier groove G2 and one third barrier groove G3 forms a second barrier portion P2. The portion of the multilayer film structure between adjacent third barrier grooves G3 forms a second barrier portion P2. The second barrier portion P2 is provided around at least a portion of the bottom edge of the display area 01.

[0091] When a display panel is fabricated using IJP (Ink Jet Printing) technology, the liquid luminescent material ejected from the printhead tends to flow from display area 01 to the first area 02. At this time, the liquid luminescent material can flow into the third barrier groove G3, where the second barrier P2 initially blocks the liquid luminescent material.

[0092] It is worth noting that, since there are at least two second blocking parts P2 in this embodiment, at least two second blocking parts P2 can sequentially block the liquid luminescent material to weaken its flow tendency.

[0093] If the liquid light-emitting material continues to flow into the first barrier groove G1, it can be blocked again by the first barrier part P1. Therefore, the structural configuration in this design can largely prevent the liquid light-emitting material from overflowing along the first direction, thereby improving the yield of the display panel.

[0094] When specifically setting the third blocking groove G3, the second channel in the pixel definition layer 500 forms the third blocking groove G3. Figure 6 is a plan view of the pixel definition layer 500 in the display panel provided in this embodiment; referring to the structure shown in Figure 6 in conjunction with Figure 3, and referring to the area near the display area 01 and the first second blocking part G2, the second channel 510 of the pixel definition layer 500 is shown in Figure 6 as an elongated groove, that is, the pixel definition layer 500 at the position corresponding to the third blocking groove G3 is removed. At this time, the pixel definition layer 500 that is not removed near the second channel 510 forms the second blocking part P2.

[0095] Alternatively, the orthographic projection of the first channel in the first planarization layer 300 onto the substrate 100 covers the orthographic projection of the second channel in the pixel definition layer 500 onto the substrate 100, so as to cooperate with the second channel in the pixel definition layer 500 to form a third barrier trench G3. Figure 7 is a plan view of the first electrode layer 400 and the first planarization layer 300 in the display panel provided in the embodiment of the present disclosure; Figure 8 is a plan view of the first metal layer 200 and the first planarization layer 300 in the display panel provided in the embodiment of the present disclosure. Referring to the structures shown in Figures 7 and 8 in conjunction with Figures 3 and 6, and referring to the area between the two second barrier portions G2, the first channel 310 is shown in the form of an elongated trench in Figures 7 and 8, that is, the first planarization layer 300 at the position corresponding to the third barrier trench G3 is removed. It can be understood that the first channel 310 in Figures 7 and 8 corresponds to the second channel 510 of the pixel definition layer 500 between the two second barrier portions G2 in Figure 6. At this time, the pixel definition layer 500 and the first planarization layer 300 form a second barrier portion P2.

[0096] It should be noted that in this embodiment, only the pixel definition layer 500 or the pixel definition layer 500 and the first planarization layer 300 are removed to form the second barrier portion P2, which does not affect the underlying metal traces (e.g., the first metal layer 200). This can shorten the distance between the second barrier portion P2 and the display area 01, conforming to the trend of narrow bezel design in display panels. Furthermore, the height of the second barrier portion P2 is relatively low, which can minimize the risk of residues remaining in the third barrier groove G3 during subsequent fabrication of TSP (Touch Screen Panel) traces, thereby improving the yield of the display panel.

[0097] Understandably, the number of second barrier sections P2 can be set according to requirements. However, since the size of the first region O2 in the second direction is limited, the number of sub-barrier sections within the second barrier section P2 cannot be set indefinitely.

[0098] When setting the second barrier P2 within the display panel, there are various possibilities for the number of the second barrier P2.

[0099] As an example, let's take a case where there are two second blocking sections P2. In this case, the first area 02 of the display panel has a total of four blocking slots, such as one first blocking slot G1, one second blocking slot G2, and two third blocking slots G3.

[0100] As another example, let's take three second blocking sections P2. In this case, the first area 02 of the display panel has a total of five blocking slots, such as one first blocking slot G1, one second blocking slot G2, and three third blocking slots G3.

[0101] It is worth noting that when there are multiple second barrier parts P2 in the first zone 02, the structural forms of the multiple first barrier parts P1 can be the same or different, and correspondingly, the structures of the third barrier groove G3 can be the same or different.

[0102] In a specific embodiment, taking the example that there are two first barrier portions P1 in the first region 02, as shown in Figure 3, in this specific embodiment, only the pixel definition layer 500 is removed from the first third barrier groove G3 near the display region 01 to form the first second barrier portion P2. The height of the second barrier portion P2 in the first direction is relatively low, which has a certain blocking effect on IJP, but does not affect the underlying metal traces (e.g., the first metal layer 200), thus shortening the distance with the display region 01. The second barrier groove G2 removes the pixel definition layer 500 and the first planarization layer 300 to form the second second barrier portion P2, so as to control the height of the sub-barrier portion and minimize the risk of material residue in the third barrier groove G3 when the TSP traces are subsequently fabricated, thereby improving the yield of the display panel.

[0103] In another embodiment of this disclosure, the multilayer film structure in the first region 02 is provided with a third barrier groove G3, the third barrier groove G3 is located on the side of the second barrier groove G2 facing the display area 01 and is spaced apart from the second barrier groove G2; the portion of the multilayer film structure located between the second barrier groove G2 and a third barrier groove G3 forms a second barrier portion P2; the second barrier portion P2 is provided around at least a portion of the bottom edge of the display area 01.

[0104] It should be noted that when using IJP technology to fabricate the display panel, the liquid luminescent material ejected from the nozzle tends to flow from display area 01 to the first area 02. At this point, the liquid luminescent material can flow into the third barrier groove G3, where the second barrier P2 initially blocks it. If the liquid luminescent material continues to flow into the first barrier groove G1, it can be blocked again by the first barrier P1. Therefore, the structural design in this configuration can largely prevent the liquid luminescent material from overflowing along the first direction, thus improving the yield of the display panel.

[0105] In a specific embodiment, referring to the first third barrier groove G3 and the second barrier portion P2 near the display area 01 in FIG3, the second channel in the pixel definition layer 500 forms the third barrier groove G3, that is, the second barrier portion P2 only contains the pixel definition layer 500.

[0106] In another specific embodiment, referring to the second third barrier groove G3 and the second barrier portion P2 near the display area 01 in FIG. 3, the orthographic projection of the first channel in the first planarization layer 300 onto the substrate 100 covers the orthographic projection of the second channel in the pixel definition layer 500 onto the substrate 100, so as to cooperate with the second channel in the pixel definition layer 500 to form the third barrier groove G3. That is, the third barrier portion includes the pixel definition layer 500 and the first planarization layer 300.

[0107] Please refer to Figures 6 to 8 for the structures shown in Figure 3. It is noteworthy that when the second channel 510 of the pixel definition layer 500 and the first channel 310 of the first planarization layer 300 cooperate to form the third barrier groove G3, the overlap area between the first sub-part of the second electrode layer 600 and the first sub-part of the first electrode layer 400 is relatively large, as is the overlap area between the first sub-part of the first electrode layer 400 and the first sub-part of the first metal layer 200. Furthermore, the aforementioned overlap areas are located between the second barrier portion G2 and the display area 01.

[0108] When the second channel 510 of the pixel definition layer 500 forms the third barrier groove G3, the first flat layer 300 in the bottom area of ​​the third barrier groove G3 may not have the second channel 310 provided, or the second channel 310 in the form of a small hole may be provided to realize the overlapping relationship between the first sub-part of the first electrode layer 400 and the first sub-part of the first metal layer 200.

[0109] In one embodiment of this disclosure, as shown in Figures 3 and 7, a first sub-part of the first electrode layer 400 is provided with a first vent 410 penetrating the first sub-part in a first direction. The orthographic projection of the first vent 410 onto the substrate 100 is located within the orthographic projection of the second barrier portion P2 onto the substrate 100. This structural arrangement allows the first planarization layer 300 covered by the first electrode layer 400 to release air during the fabrication process, thereby preventing the display panel from bulging in the first region 02.

[0110] In one specific embodiment, the first vent 410 is rectangular in its orthographic projection onto the substrate 100 to reduce fabrication difficulty. Of course, the first vent 410 can also be configured as other shapes as needed, which will not be elaborated here.

[0111] Figure 9 is a planar schematic diagram of the second metal layer and the second planarization layer in a display panel provided in an embodiment of this disclosure. Referring to the structure shown in Figure 9 in conjunction with Figure 3, in one embodiment of this disclosure, the multilayer film structure further includes: a second planarization layer 700 and a second metal layer 800.

[0112] The second planarization layer 700 is located between the first metal layer 200 and the substrate 100, and includes a first sub-section located in the first region 02; the second metal layer 800 is located between the substrate 100 and the second planarization layer 700, and includes a first sub-section located in the first region 02.

[0113] It is understood that when the second planarization layer 700 serves as an organic layer covering the second metal layer 800, the positions of the second planarization layer 700 corresponding to the first barrier groove G1 and the second barrier groove G2 need to be removed. The first barrier portion P1 may include the second planarization layer 700.

[0114] Furthermore, it is worth noting that, as shown in Figure 3, a portion of the first sub-section within the second metal layer 800 is used as a VSS trace 810, and another portion is used as a VDD trace 820. The first metal layer 200 is electrically connected to the portion of the first sub-section within the second metal layer 800 used as the VSS trace 810 through a via provided in the second planarization layer 700, in order to further reduce the VSS impedance.

[0115] Referring to Figure 3 and then to the structure shown in Figure 8, in one embodiment of this disclosure, the first sub-part of the first metal layer 200 is provided with a second vent 210 penetrating through the first sub-part in a first direction. The orthographic projection of the second vent 210 onto the substrate 100 is located within the orthographic projection of the second barrier portion P2 onto the substrate 100. This structural arrangement allows the second planarization layer 700, covered by the first metal layer 200, to release air during fabrication, thereby preventing the display panel from bulging in the first region 02.

[0116] In one embodiment of this disclosure, at least a portion of the orthographic projection of the second vent 210 onto the substrate 100 overlaps with the orthographic projection of the first vent 410 onto the substrate 100 to improve the air permeability.

[0117] In one embodiment of this disclosure, the second vent 210 is rectangular in its orthographic projection onto the substrate 100 to reduce fabrication difficulty. Of course, the second vent 210 can also be configured with other shapes as needed, which will not be elaborated here.

[0118] Figure 10 is a plan view of the insulating layer and the third planarization layer in the display panel provided in an embodiment of the present disclosure; Figure 11 is a plan view of the third metal layer in the display panel provided in an embodiment of the present disclosure. Referring to Figure 3 in conjunction with Figures 9 and 10, in one embodiment of the present disclosure, the multilayer film structure further includes: a third planarization layer 900 and a third metal layer 1000, wherein the third planarization layer 900 is located between the second metal layer 800 and the substrate 100, and includes a first sub-part located in the first region 02; the third metal layer 1000 is located between the substrate 100 and the third planarization layer 900, and includes a first sub-part located in the first region 02.

[0119] It is understood that when the third planarization layer 900 serves as an organic layer covering the third metal layer 1000, the positions of the third planarization layer 900 corresponding to the first barrier groove G1 and the second barrier groove G2 need to be removed. The first barrier portion P1 may include the third planarization layer 900.

[0120] Furthermore, it is worth noting that, as shown in Figure 3, a portion of the first sub-section within the third metal layer 1000 is used as a VSS trace 1010, and another portion is used as a VDD trace 1020. The second metal layer 800 is electrically connected to the portion of the first sub-section within the third metal layer 1000 used as the VSS trace 1010 through a via provided in the third planarization layer 900, in order to further reduce the VSS impedance.

[0121] As shown in Figure 4, in one embodiment of this disclosure, the display panel provided in this embodiment further includes a second region 04, which connects to the first region 02 to form a peripheral region, which surrounds the display region 01. In this display panel: a first barrier portion P1 is disposed around the display region 01, and a second barrier portion P2 is disposed around the display region 01 to effectively protect the display region 01 from all directions. Specifically, the second barrier portion P2 can block the liquid light-emitting material from all directions, preventing it from further overflowing along the first direction, thereby improving the yield of the display panel; the first barrier portion P1 forms a barrier structure surrounding the display region 01, which can cut off the water and oxygen transmission channels in all directions, further ensuring the stability of the display region 01.

[0122] Of course, it is also possible to set the first blocking part P1 to wrap around the partial display area 01, or to set the second blocking part P2 to wrap around the partial display area 01. Further details will not be elaborated here.

[0123] It is worth noting that the various membrane structures can also be designed accordingly within the second region 04.

[0124] For example, the first metal layer 200 further includes a second sub-part located in the second region 04; the first planarization layer 300 further includes a second sub-part located in the second region 04; the second sub-part of the first planarization layer 300 is provided with a third channel penetrating the first planarization layer 300 in a first direction; the first electrode layer 400 further includes a second sub-part located in the second region 04; the second sub-part of the first electrode layer 400 is electrically connected to the second sub-part of the first metal layer 200 through the third channel; the pixel definition layer 500 further includes a second sub-part located in the second region 04; the second sub-part of the pixel definition layer 500 is provided with a fourth channel penetrating the pixel definition layer 500 in a first direction; the second electrode layer 600 further includes a second sub-part located in the second region 04; the second sub-part of the second electrode layer 600 is electrically connected to the second sub-part of the first electrode layer 400 through the fourth channel.

[0125] It is worth noting that in this embodiment of the present disclosure, the first electrode layer 400 and the second electrode layer 600 are also overlapped in the second region 04, and the first electrode layer 400 is connected to the second sub-part of the first metal layer 200 to reduce VSS impedance.

[0126] It is worth noting that the display panel provided in this embodiment may contain other film layers. Therefore, the film layer structure in the first barrier portion P1 and the second barrier portion P2 is not limited to that shown in the figures. For example, as shown in Figures 3 and 10, the display panel is further provided with an insulating layer 1100, which is located between the third metal layer 1000 and the third planarization layer 900.

[0127] This disclosure also provides a display device. The display device includes a display panel as provided in any of the above-described technical solutions.

[0128] The display panel in the display device provided in this disclosure can reduce VSS impedance without increasing the bottom size of the display panel, thereby reducing the risk of high-brightness burn-in. Specifically, the second electrode layer 600 in the display panel has opposite polarities to the first electrode layer 400. The two overlap in the first region 02 at the bottom of the display area 01 and are connected to the first metal layer 200, which serves as the VSS trace, thus optimizing the current transmission path. Furthermore, this structure can reduce the path length and contact resistance of the current during transmission, effectively reducing VSS impedance. Accordingly, when the VSS impedance is reduced, the possibility of VSSDrop phenomenon in the display panel provided in this disclosure can be reduced. This design enables a more uniform voltage distribution within the display panel, thereby improving the uniformity of display brightness.

[0129] Furthermore, one of the electrode layers, the first electrode layer 400 and the second electrode layer 600, is a negative electrode layer. Since negative electrode layers are typically thinner, their surface resistivity is higher. By overlapping and connecting to the low-resistivity first metal layer 200 within the first region 02, the resistance of the negative electrode layer can be combined with the low-resistivity characteristics of the first metal layer 200, thereby reducing the overall VSS impedance.

[0130] It should be understood that the application of this invention is not limited to the detailed structure and arrangement of the components presented in this specification. The invention can have other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this invention. It should be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of the invention. The embodiments described in this specification illustrate the best known mode for carrying out the invention and will enable those skilled in the art to utilize the invention.

Claims

1. A display panel, characterized in that, include: The display panel includes a display area and a first area surrounding the bottom of the display area. The display panel also includes a substrate and a multilayer film structure located on the same side of the substrate along a first direction. The multilayer film structure includes: A first metal layer is located on the side of the substrate away from the substrate, and includes a first sub-section located in the first region, wherein at least a portion of the first sub-section is used as a negative power supply voltage trace. A first planarization layer is located on the side of the first metal layer away from the substrate, and includes a first sub-part located in the first region; the first sub-part of the first planarization layer is provided with a first channel penetrating the first planarization layer in the first direction. A first electrode layer, located on the side of the first planarization layer opposite to the substrate, includes a first sub-section located in the first region; the first sub-section of the first electrode layer is electrically connected to a portion of the first sub-section of the first metal layer that serves as a negative power supply voltage trace through the first channel. A pixel definition layer is located on the side of the first electrode layer away from the substrate, and includes a first sub-part located in the first region. The first sub-part of the pixel definition layer is provided with a second channel that penetrates the pixel definition layer in the first direction. The second electrode layer is located on the side of the pixel definition layer opposite to the substrate and has the opposite polarity to the first electrode layer. It includes a first sub-part located in the first region, and the first sub-part of the second electrode layer is electrically connected to the first sub-part of the first electrode layer through the second channel.

2. The display panel according to claim 1, characterized in that, The multilayer film structure in the first region is provided with a first barrier groove and a second barrier groove, the second barrier groove being located on the side of the first barrier groove facing the display area; and in the orthographic projection of the multilayer film structure onto the substrate, the material of each layer of the multilayer film structure located within the area covered by the orthographic projection of the first barrier groove onto the substrate is inorganic, and the material of each layer of the multilayer film structure located within the area covered by the orthographic projection of the second barrier groove onto the substrate is inorganic. The portion of the multilayer film structure located between the first barrier groove and the second barrier groove forms a first barrier portion; the first barrier portion is arranged around the bottom edge of the display area.

3. The display panel according to claim 2, characterized in that, The second electrode layer is a negative electrode layer, wherein: The orthographic projection of the first sub-part of the second electrode layer away from the display area onto the substrate is in contact with the boundary line of the first barrier portion onto the substrate facing the display area. Alternatively, the orthographic projection of the first sub-part of the second electrode layer away from the display area onto the substrate is located within the orthographic projection of the first barrier portion onto the substrate. Alternatively, the orthographic projection of the first sub-part of the second electrode layer on the side away from the display area is located on the side of the first barrier portion on the side of the substrate away from the display area.

4. The display panel according to claim 2, characterized in that, The multilayer film structure in the first region is provided with a third barrier groove, which is located on the side of the second barrier groove facing the display area and is spaced apart from the second barrier groove; the portion of the multilayer film structure between the second barrier groove and one of the third barrier grooves forms a second barrier portion; the second barrier portion is disposed around at least a portion of the bottom edge of the display area; wherein: The second channel in the pixel definition layer forms the third barrier groove; Alternatively, the orthographic projection of the first channel in the first planarization layer onto the substrate covers the orthographic projection of the second channel in the pixel definition layer onto the substrate, so as to cooperate with the second channel in the pixel definition layer to form the third barrier groove.

5. The display panel according to claim 2, characterized in that, The multilayer film structure in the first region is provided with at least two third barrier grooves. The third barrier grooves are located on the side of the second barrier groove facing the display area and are spaced apart from the second barrier groove. At least two of the third barrier grooves are spaced apart in the arrangement direction of the first region and the display area. A portion of the multilayer film structure between the second barrier groove and one of the third barrier grooves forms a second barrier portion, and a portion of the multilayer film structure between adjacent third barrier grooves forms a second barrier portion. The second barrier portion is provided around at least a portion of the bottom edge of the display area. Wherein: The second channel in the pixel definition layer forms the third barrier groove; Alternatively, the orthographic projection of the first channel in the first planarization layer onto the substrate covers the orthographic projection of the second channel in the pixel definition layer onto the substrate, so as to cooperate with the second channel in the pixel definition layer to form the third barrier groove.

6. The display panel according to claim 4 or 5, characterized in that, It also includes a second area, which connects to the first area to form a peripheral area, the peripheral area being arranged around the display area, in the display panel: The first barrier portion is disposed around the display area; And / or, the second barrier is disposed around the display area.

7. The display panel according to claim 4 or 5, characterized in that, The first sub-part of the first electrode layer is provided with a first vent that penetrates the first sub-part in the first direction, and the orthographic projection of the first vent on the substrate is located within the orthographic projection of the second barrier portion on the substrate.

8. The display panel according to claim 7, characterized in that, The first vent has a rectangular shape when projected onto the substrate.

9. The display panel according to claim 7, characterized in that, The multilayer film structure further includes: The second planarization layer is located between the first metal layer and the substrate, and includes a first sub-section located in the first region; The second metal layer is located between the substrate and the second planarization layer, and includes a first sub-section located in the first region.

10. The display panel according to claim 9, characterized in that, The first sub-part of the first metal layer is provided with a second vent that penetrates the first sub-part in the first direction, and the orthographic projection of the second vent on the substrate is located within the orthographic projection of the second barrier portion on the substrate.

11. The display panel according to claim 10, characterized in that, The orthographic projection of the second vent on the substrate overlaps at least partially with the orthographic projection of the first vent on the substrate.

12. The display panel according to claim 10, characterized in that, The second vent is rectangular in its orthographic projection onto the substrate.

13. The display panel according to claim 9, characterized in that, The multilayer film structure further includes: The third planarization layer is located between the second metal layer and the substrate, and includes a first sub-section located in the first region; The third metal layer is located between the substrate and the third planarization layer, and includes a first sub-section located in the first region.

14. The display panel according to any one of claims 1-5, characterized in that, It also includes a second area, which connects to the first area to form a peripheral area, the peripheral area being arranged around the display area, in the display panel: The first metal layer further includes a second sub-section located in the second region; The first planarization layer further includes a second sub-section located in the second region; the second sub-section of the first planarization layer is provided with a third channel penetrating the first planarization layer in the first direction; The first electrode layer further includes a second sub-section located in the second region; the second sub-section of the first electrode layer is electrically connected to the second sub-section of the first metal layer through the third channel; The pixel definition layer further includes a second sub-section located in the second region; the second sub-section of the pixel definition layer is provided with a fourth channel that penetrates the pixel definition layer in the first direction. The second electrode layer further includes a second sub-section located in the second region; the second sub-section of the second electrode layer is electrically connected to the second sub-section of the first electrode layer through the fourth channel.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

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