Chip and manufacturing method therefor, and electronic device
Patent Information
- Application Number
- PCT/CN2026/074196
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-27
- Filing Date
- 2026-01-22
- Publication Date
- 2026-09-03
Smart Images
Figure CN2026074196_03092026_PF_FP_ABST
Abstract
Description
Chips and their fabrication methods, as well as electronic devices
[0001] This application claims priority to Chinese Patent Application No. 202510228711.2, filed on February 27, 2025, entitled "Chip and Method of Fabrication Thereof, and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and more particularly to a chip, a method for fabricating the chip, and an electronic device. Background Technology
[0003] Metal-Insulator-Metal-Capacitor (MIMCAP) capacitors are widely used passive devices that play an important role in voltage regulation and filtering in circuits. A typical MIMCAP structure usually consists of at least three layers: a first metal layer, an intermediate insulating layer, and a second metal layer. With the trend towards miniaturization of semiconductor devices, the evolution of MIMCAPs is also moving towards reducing projected area and increasing capacitance density.
[0004] In existing technologies, various methods are commonly used to increase the capacitance of a MIMCAP without increasing the layout area. For example, adjusting the intermediate insulating layer can improve the capacitance. These methods include reducing the thickness of the intermediate insulating layer or using a material with a higher dielectric constant. However, these methods may increase leakage current or decrease breakdown voltage, thereby reducing the stability and lifespan of the MIMCAP. Therefore, the existing technology for increasing the capacitance per unit area of MIMCAPs still needs improvement. Summary of the Invention
[0005] The chip, its fabrication method, and electronic device provided in this application can improve the capacitance per unit area of MIMCAP while ensuring chip reliability. To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0006] In a first aspect, embodiments of this application provide a chip, the chip comprising: a semiconductor structure in which a semiconductor device is formed; a capacitor layer stacked with the semiconductor structure, the capacitor layer including an insulating layer and a plurality of capacitor structures embedded in the insulating layer, each of the plurality of capacitor structures including a first electrode, a second electrode, and a dielectric layer for isolating the first electrode and the second electrode; wherein the first electrode includes a first structure extending along a stacking direction and a plurality of first electrode plates extending outward from the first structure, the plurality of first electrode plates being connected together through the first structure; the second electrode includes a second structure extending along a stacking direction and a plurality of second electrode plates extending outward from the second structure, the plurality of second electrode plates being connected together through the second structure; the plurality of first electrode plates and the plurality of second electrode plates are alternately stacked along the stacking direction; and a first through-hole penetrating the upper and lower surfaces of the insulating layer, the first through-hole being located in a region of the insulating layer where the plurality of capacitor structures are not disposed, the conductive material filling the first through-hole connecting the plurality of capacitor structures to the semiconductor device.
[0007] The chip provided in this application embodiment has a first electrode comprising a first structure extending along the stacking direction and a plurality of first electrode plates extending outward from the first structure. The second electrode comprises a second structure extending along the stacking direction and a plurality of second electrode plates extending outward from the second structure. The first electrode plates and second electrode plates are stacked together along the stacking direction. Thus, in cross-sectional views of the first and second electrodes, both the first and second structures resemble tree trunks, and the plurality of first electrode plates resemble branches extending from the first structure, and the plurality of second electrode plates resemble branches extending from the second structure. Therefore, the chip provided in this application embodiment can fully utilize the area of the capacitor layer along the stacking direction, increasing the surface area of the first and second electrodes without increasing the chip layout area. Thus, compared to the prior art method of adjusting the intermediate insulating layer of the MIMCAP to increase the capacitance per unit area, the MIMCAP shown in this application embodiment can greatly increase the capacitance per unit area while ensuring capacitor reliability. Furthermore, the chip provided in this application embodiment can form multiple capacitor structures through a small number of photolithography-deposition processes, thereby simplifying the manufacturing process.
[0008] In one possible implementation, along the stacking direction, multiple first electrode plates located on the same side of the first structure are arranged in parallel at intervals, and a second electrode plate is arranged between every two first electrode plates.
[0009] This application embodiment, by configuring the first electrode as a structure including a first structure and a plurality of first electrode plates extending from the first structure to the surrounding area, allows the first structure to support the plurality of first electrode plates and connect the plurality of first electrode plates, thereby increasing the capacity of the first electrode without increasing the layout area, while also improving the stability and reliability of the first electrode. In one possible implementation, the first structure can be a cylindrical structure or a sidewall structure. When the first structure is a cylindrical structure, first electrode plates can be provided on all four sides of the first structure, that is, the first electrode plates extend from the cylindrical structure in multiple directions (e.g., front, back, left, and right directions); when the first structure is a sidewall structure, the first electrode plates extend in a direction perpendicular to the sidewall plane, and first electrode plates are provided on both sides of the sidewall.
[0010] In one possible implementation, multiple second electrode plates located on the same side of the second structure are arranged in parallel and spaced apart along the stacking direction, and a first electrode plate is arranged between every two second electrode plates.
[0011] This application embodiment, by configuring the second electrode as a structure including a second structure and multiple second electrode plates extending outwards from the second structure, allows the second structure to support the multiple second electrode plates and connect the multiple second electrode plates, thereby increasing the capacity of the second electrode without increasing the layout area, while also improving the stability and reliability of the second electrode. In one possible implementation, the second structure can be a cylindrical structure or a sidewall structure. When the second structure is a cylindrical structure, second electrode plates can be provided on all four sides of the second structure, that is, the second electrode plates extend from the cylindrical structure in multiple directions (e.g., front, back, left, and right). When the second structure is a sidewall structure, the second electrode plates extend in a direction perpendicular to the sidewall plane, and second electrode plates are provided on both sides of the sidewall. It should be noted that if the first structure in the first electrode is a cylindrical structure, then the second structure in the second electrode can be a sidewall structure; if the first structure in the first electrode is a sidewall structure, then the second structure in the second electrode can be a cylindrical structure.
[0012] In one possible implementation, both the first electrode and the second electrode are made of titanium nitride.
[0013] In one possible implementation, along the stacking direction, at least one of the first structure and the second structure extends from the capacitor layer into the interior of the semiconductor structure. By extending at least one of the first structure and the second structure into the interior of the semiconductor structure and embedding it within the semiconductor structure, the stability of the first electrode and / or the second electrode can be further increased, preventing capacitor structure breakage, thereby further improving the reliability of the capacitor structure and thus improving the reliability of the chip.
[0014] In one possible implementation, multiple capacitor structures are arranged in parallel along a direction perpendicular to the stacking direction; wherein multiple first capacitor structures among the multiple capacitor structures are connected in parallel. By connecting multiple parallel capacitor structures in parallel, the capacitance can be further increased, which is beneficial for meeting the needs of large capacitor scenarios.
[0015] In one possible implementation, the chip further includes a wiring layer; the wiring layer is disposed on the surface of the capacitor layer away from the semiconductor structure; the wiring layer includes at least one conductive line and a plurality of second vias, wherein the conductive material in each second via connects the at least one conductive line to a first electrode in the first capacitor structure; the first electrodes in the plurality of first capacitor structures are connected in parallel through the plurality of second vias and at least one conductive line.
[0016] In one possible implementation, the second electrodes in multiple first capacitor structures are connected together to form a continuous structure.
[0017] In one possible implementation, the semiconductor structure includes a device layer and a redistribution layer. The device layer includes a semiconductor device, and the redistribution layer includes at least one wiring layer and multiple pins for bringing out ports of the semiconductor device. A capacitor layer is stacked on top of the redistribution layer and is isolated from the redistribution layer by an insulating material. A conductive material in a first via connects a second electrode in the first capacitor structure to one of the multiple pins.
[0018] In one possible implementation, the semiconductor device includes at least one of the following: a transistor, a resistor, or a capacitor.
[0019] In a second aspect, embodiments of this application provide an electronic device, which includes a circuit board and a chip as described in the first aspect; the chip is disposed on the circuit board by a plurality of solders; the circuit board includes at least one electronic circuit, which includes at least one of a power line, a ground line, and a signal line; the pins of semiconductor devices on the chip are connected to at least one electronic circuit through a plurality of capacitor structures.
[0020] Thirdly, embodiments of this application provide a method for fabricating a chip, the method comprising: providing a substrate, forming a semiconductor structure on the substrate, and forming a semiconductor device in the semiconductor structure; forming a capacitor layer on the semiconductor structure, the capacitor layer including an insulating layer and a plurality of capacitor structures embedded in the insulating layer, each of the plurality of capacitor structures including a first electrode, a second electrode, and a dielectric layer for isolating the first electrode and the second electrode; wherein the first electrode includes a first structure extending along a stacking direction and a plurality of first electrode plates extending outward from the first structure, the plurality of first electrode plates being connected together through the first structure; the second electrode includes a second structure extending along a stacking direction and a plurality of second electrode plates extending outward from the second structure, the plurality of second electrode plates being connected together through the second structure; and the plurality of first electrode plates and the plurality of second electrode plates being alternately stacked along the stacking direction; forming a first through-hole penetrating the upper and lower surfaces of the insulating layer in the capacitor layer, the first through-hole being located in a region of the insulating layer where the plurality of capacitor structures are not disposed, and a conductive material filling the first through-hole connecting the plurality of capacitor structures to the semiconductor device.
[0021] In one possible implementation, forming a capacitor layer on a semiconductor structure includes: arranging a plurality of first electrode plates located on the same side of a first structure in parallel and spaced apart along a stacking direction, and arranging a second electrode plate between every two first electrode plates.
[0022] In one possible implementation, forming a capacitor layer on a semiconductor structure includes: wherein, along the stacking direction, a plurality of second electrode plates located on the same side of the second structure are arranged in parallel and spaced apart, and a first electrode plate is arranged between every two second electrode plates.
[0023] In one possible implementation, the method further includes: connecting a plurality of first capacitor structures in parallel; wherein the plurality of capacitor structures are arranged in parallel along a direction perpendicular to the stacking direction.
[0024] In one possible implementation, connecting multiple first capacitor structures in parallel includes: forming a wiring layer on the side away from the semiconductor structure above the capacitor layer; the wiring layer includes at least one conductive line and multiple second vias, wherein the conductive material in each second via connects the at least one conductive line to a first electrode in the first capacitor structure; and the first electrodes in the multiple first capacitor structures are connected in parallel through the multiple second vias and at least one conductive line.
[0025] It should be understood that the second and third aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description
[0026] Figure 1 is a schematic diagram of a structure of MIMCAP in the related technology;
[0027] Figure 2 is a schematic diagram of an electronic device provided in an embodiment of this application;
[0028] Figure 3 is a schematic diagram of the structure of a chip provided in an embodiment of this application;
[0029] Figure 4 is a partial structural schematic diagram of the chip shown in Figure 3 provided in an embodiment of this application;
[0030] Figure 5A is a three-dimensional structural schematic diagram of the electrode 211 provided in an embodiment of this application;
[0031] Figure 5B is a three-dimensional structural schematic diagram of the electrode 213 provided in an embodiment of this application;
[0032] Figure 5C is a three-dimensional structural schematic diagram of the relative positional relationship between electrode 211 and electrode 213 provided in an embodiment of this application;
[0033] Figure 6 is another structural schematic diagram of the chip provided in the embodiment of this application;
[0034] Figure 7A is a flowchart of the chip fabrication method shown in Figure 3 provided in an embodiment of this application;
[0035] Figure 7B is another flowchart of the chip fabrication method shown in Figure 3 provided in the embodiments of this application;
[0036] Figures 8A-8J are schematic diagrams of various structures in the chip fabrication process shown in Figure 3. Detailed Implementation
[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.
[0038] The terms "first" and "second," etc., in the specification and drawings of the embodiments of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.
[0039] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0040] It should be noted that in the description of the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.
[0041] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.
[0042] In existing technologies, various methods are commonly used to increase the capacitance per unit area of a MIMCAP. For example, adjusting the intermediate insulating layer of the MIMCAP can increase its capacitance per unit area. These methods include reducing the thickness of the intermediate insulating layer or using a material with a higher dielectric constant. However, this approach may increase leakage current or decrease breakdown voltage, thereby reducing the stability and lifespan of the MIMCAP.
[0043] The industry has further proposed using a three-dimensional MIMCAP approach to improve the capacitance per unit area of the MIMCAP. This approach utilizes semiconductor processing techniques to form a certain three-dimensional structure, and uses the surface area of the three-dimensional structure to increase the effective area of the MIMCAP, thereby improving the capacitance value. As shown in Figure 1, Figure 1 is a structural schematic diagram of the MIMCAP in the related technology provided in the embodiments of this application. As shown in Figure 1, a semiconductor layer is disposed on a substrate 01 on which the semiconductor device is formed. Multiple grooves and multiple protrusions are formed on the upper surface of the semiconductor layer. The grooves and protrusions are alternately arranged along the direction x shown in the figure. The MIMCAP 02 is disposed on the grooves and protrusions of the semiconductor layer. Thus, the surface area of the MIMCAP 02 is increased by utilizing the grooves and protrusions of the semiconductor layer, thereby improving the capacitance per unit area of the MIMCAP. In addition, the MIMCAP 02 includes a bottom electrode 021, a middle electrode 022, and a top electrode 023, with each pair of electrodes separated by a dielectric layer. The bottom electrode 021 is deposited on the surface of the grooves and the surface of the protrusions. The dielectric layer, the middle electrode 022, the dielectric layer, and the top electrode 023 are stacked sequentially on the electrode 021. In other words, as shown in Figure 1, the cross-sectional structure of MIMCAP02 is an electrode 021-dielectric layer-electrode 022-dielectric layer-electrode 023 morphology. By setting multiple layers of electrodes, the capacitance per unit area of MIMCAP can be further improved. In the scheme of increasing the number of electrode and insulating layers to improve the capacitance of MIMCAP, it is necessary to, or can be achieved by increasing the number of electrode and insulating layers to improve the capacitance per unit area of MIMCAP.
[0044] As shown in Figure 1, the capacitance of MIMCAP02 increases by increasing the number of MIMCAP layers without increasing the additional area of the circuit board. That is, each electrode and dielectric layer needs to be deposited layer by layer; the more electrode and dielectric layers there are, the more deposition cycles are required. Assuming MIMCAP02 includes 5 electrode layers and 4 dielectric layers, it requires 5 electrode deposition cycles and 4 dielectric layer deposition cycles, and each electrode layer requires a separate photolithography-etching process for shape definition, which significantly increases cost. Furthermore, the surface area of MIMCAP02 depends on the height of the groove sidewalls along the direction y shown in the figure. The higher the groove sidewall height, the larger the surface area of MIMCAP02, and the higher the capacitance per unit area. However, as chip sizes move towards higher integration, the thickness of the semiconductor layers used to form MIMCAPs and metal traces is typically thin, for example, usually not exceeding 1 μm. The sidewall height of the grooves formed at this thickness is limited, thus limiting the increase in the surface area of the MIMCAP. Therefore, increasing the capacitance per unit area of MIMCAP without increasing the layout area becomes a problem that needs to be solved.
[0045] The chip provided in this application embodiment has multiple capacitor structures in the capacitor layer. Each capacitor structure includes a first electrode, a second electrode, and a dielectric layer for isolating the first and second electrodes. The first electrode includes a first structure extending along the stacking direction and multiple first electrode plates extending outward from the first structure. The multiple first electrode plates are connected together through the first structure. The second electrode includes a second structure extending along the stacking direction and multiple second electrode plates extending outward from the second structure. The multiple second electrode plates are connected together through the second structure. Along the stacking direction, the multiple first electrode plates and multiple second electrode plates are alternately stacked. Thus, in the cross-sectional view of the first and second electrodes, both the first and second structures resemble tree trunks, and the multiple first electrode plates resemble branches extending from the first structure, and the multiple second electrode plates resemble branches extending from the second structure. Therefore, the chip provided in this application embodiment can fully utilize the area of the capacitor layer along the stacking direction, and can increase the surface area of the first and second electrodes without increasing the chip layout area. Therefore, compared with the prior art of adjusting the intermediate insulating layer of the MIMCAP to increase the capacitance per unit area, the MIMCAP shown in this application embodiment can greatly increase the capacitance per unit area while ensuring capacitor reliability. Furthermore, in the chip provided in this application embodiment, multiple capacitor structures can be formed through a small number of photolithography-deposition processes. Compared with the prior art of multiple photolithography-deposition processes, this greatly simplifies the manufacturing process and saves process costs. In addition, compared with the prior art where the capacitance of the MIMCAP is limited by the height of the recess sidewalls, the electrical structure provided in this application embodiment is not limited by the height of the recess sidewalls. For the same layout area, this application embodiment can further increase the surface area of the MIMCAP to increase its capacitance compared with the prior art.
[0046] The chips provided in this application embodiment may include, but are not limited to, systems on a chip (SoC), memory, discrete devices, application processors (APs), micro-electro-mechanical systems (MEMS), microwave radio frequency chips, and application-specific integrated circuits (ASICs). In specific applications, the aforementioned application processors or ASICs may be central processing units (CPUs), graphics processing units (GPUs), or artificial intelligence processors, such as network processing units (NPUs). Memory may be cache memory, random access memory (RAM), read-only memory (ROM), or other types of memory. Discrete devices may include, but are not limited to, field-effect transistors (FETs) and bipolar transistors (BJTs).
[0047] Please refer to Figure 2, which is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device provided in this embodiment can be an integrated circuit product. In addition to the chip described in this embodiment, the integrated circuit product may also include other integrated circuits, enabling the chip shown in this embodiment to cooperate with other integrated circuits to achieve various circuit functions. The electronic device 200 includes a chip 100 and a circuit board.
[0048] The circuit board can be, for example, a printed circuit board (PCB). The chip 100 is disposed on the surface of the PCB via a plurality of microbumps 50. The PCB can be a single-layer board or a multi-layer board, and each layer can be provided with patterned conductive lines. These patterned conductive lines can be, for example, power lines, ground lines, or signal lines. The chip 100 is connected to the patterned conductive lines on the PCB via the plurality of microbumps 50 to interconnect with power lines, ground lines, signal lines, or other components on the PCB.
[0049] Chip 100 includes a semiconductor structure 10 and a capacitor layer 20. The semiconductor structure 10 and capacitor layer 20 are stacked together along direction y shown in FIG. 2. Multiple semiconductor devices can be integrated in the semiconductor structure 10, including but not limited to transistors, resistors, and capacitors. The semiconductor devices in the semiconductor structure 10 can be formed in a silicon substrate using standard front-end of line (FEOL) processes and materials during wafer fabrication. These standard processes include, but are not limited to, epitaxial growth, oxidation, deposition, doping, ion implantation, and planarization, etc., which are not specifically limited in this embodiment. Furthermore, a plurality of mutually isolated pins 121 are provided on the surface of the semiconductor structure 10 near the capacitor layer 20. These mutually isolated pins 121 are used to bring out the input / output ports of the semiconductor devices.
[0050] The capacitor layer 20 includes multiple capacitor structures 21. These capacitor structures 21 can be disposed between pins 121 of the semiconductor device (e.g., power pins, and / or ground pins) and power lines on the PCB (e.g., power lines and / or ground lines) to achieve functions such as voltage regulation or filtering of power signals, thereby improving chip operational stability. In one possible implementation, the capacitor layer 20 can be fabricated during wafer fabrication using a back-end of line (BEOL) process. In this embodiment, the multiple capacitor structures 21 can be connected to one or more pins of the semiconductor device. In one possible implementation, all multiple capacitor structures 21 are connected to the same pin of the semiconductor device; in this implementation, the multiple capacitor structures 21 are connected in parallel. In another possible implementation, the multiple capacitor structures 21 are connected to multiple pins of the semiconductor device, such as two pins or three pins. When multiple capacitor structures 21 are connected to multiple pins of a semiconductor device, in one possible implementation, the multiple capacitor structures 21 can be connected one-to-one with the multiple pins; in another possible implementation, the multiple capacitor structures 21 can be divided into multiple isolated parts, with the capacitor structures 21 in each part connected in parallel, and the capacitor structures 21 in each part connected one-to-one with the multiple pins. For example, Figure 2 schematically shows six capacitor structures 21, where every two capacitor structures 21 are connected in parallel and in contact with one of the pins 121. It is understood that the number of capacitor structures, the number of pins connected to the capacitor structures, and the number of capacitor structures connected in parallel to the same pin 121 shown in Figure 2 are all schematic and set according to the needs of the actual scenario. The specific structure of the capacitor structure 21 is shown in Figures 3 to 5C.
[0051] Based on the electronic device 200 shown in Figure 2, the following describes the chip 100 provided in this application embodiment in more detail, taking the connection of two parallel capacitor structures 21 with one pin 121 as an example, in conjunction with the embodiments shown in Figures 3 to 5C. Please continue to refer to Figure 3, which is a structural schematic diagram of the chip 100 provided in this application embodiment. As shown in Figure 3, the semiconductor structure 10 may include a device layer 11 and a wiring layer 12 disposed on the device layer 11. The device layer 11 may integrate multiple semiconductor devices, which have been described above and will not be repeated here. The wiring layer 12 may include one or more layers of patterned conductive lines for leading out multiple pins 121 of the input / output ports of the semiconductor devices, disposed in the wiring layer 12. In addition, the patterned conductive lines on the wiring layer 12 can also interconnect the semiconductor devices in the device layer 11 so that the chip can realize specific functions. For example, when the chip 100 is a logic chip, the interconnection of multiple semiconductor devices can realize logic functions; as another example, when the chip 100 is a memory chip, the interconnection of multiple semiconductor devices can realize memory functions.
[0052] Along direction y shown in Figure 3, capacitor layer 20 is disposed above wiring layer 12 in semiconductor structure 10. Capacitor layer 20 includes insulating layer 22 and multiple capacitor structures 21 embedded in insulating layer 22. Each capacitor structure 21 includes an electrode 211, a dielectric layer 212, and an electrode 213. Dielectric layer 212 is used to isolate electrode 211 and electrode 213. A more detailed description of each capacitor structure 21 is provided in conjunction with Figures 3 to 5C. Figure 4 is a partially enlarged schematic diagram of AA' in capacitor structure 21 shown in Figure 3; Figure 5A is a perspective view of electrode 211 in capacitor structure 21 shown in Figure 3; Figure 5B is a perspective view of electrode 213 in capacitor structure 21 shown in Figure 3; Figure 5C is a perspective view showing the positional relationship between electrode 211 and electrode 213 encased in dielectric layer 212 as shown in Figure 3.
[0053] Electrode 211 includes multiple electrode plates P1, which are all connected together. In one possible implementation of this application embodiment, the electrode 211 in the capacitor structure 21 may include a structure G1 extending along the direction y shown in FIG3 and multiple electrode plates P1 extending outward from the structure G1. The multiple electrode plates P1 are connected to the structure G1, thereby connecting the multiple electrode plates P1 together through the structure G1. The structure G1 can be a cylindrical structure, a sidewall structure, or other types of structures; this application embodiment does not specifically limit it. FIG5A schematically shows the case where the structure G1 of electrode 211 is a sidewall structure. As shown in the perspective view in Figure 5A, structure G1 extends not only along the y-direction but also along the z-direction. Along the x-direction, multiple electrode plates P1 extend from structure G1 to both sides; that is, along the x-direction, electrode plates P1 are provided on both sides of structure G1. Along the y-direction, multiple electrode plates P1 are disposed in different layers. On the same side of structure G1, multiple layers of electrode plates P1 are arranged parallel and spaced along the y-direction. Figures 3 and 5A schematically show four layers of electrode plates P1. As can be seen from Figures 3 to 5A, structure G1 resembles a tree trunk, and the multiple electrode plates P1 resemble branches extending from structure G1. It is understood that along the y-direction, there may be more or fewer layers of electrode plates P1. This application does not specifically limit the number of electrode plates P1 in its embodiments. In one possible implementation, the material of electrode 211 can be, for example, titanium nitride (TiN).
[0054] Electrode 213 also includes multiple electrode plates P2, which are all connected together. In one possible implementation of this application embodiment, the electrode 213 in the capacitor structure 21 may include a structure G2 extending along the direction y shown in FIG3 and multiple electrode plates P2 extending outward from the structure G2. The multiple electrode plates P2 are connected to the structure G2, thereby connecting the multiple electrode plates P2 together through the structure G2. The structure G2 can be a cylindrical structure, a sidewall structure, or other types of structures, and this application embodiment does not specifically limit it. FIG5B schematically shows the case where the structure G2 of electrode 213 is a cylindrical structure. As can be seen from the perspective view shown in FIG5B, the structure G2 extends along the direction y, and the multiple electrode plates P2 extend outward from the structure G2. From FIG5B, the multiple electrode plates P2 are located in different layers, and the structure G2 is embedded in and penetrates multiple layers of electrode plates P2. Along direction y, multiple layers of electrode plates P2 are arranged in parallel at intervals. Figures 3 and 5B schematically show four layers of electrode plates P2. As can be seen from Figures 3 and 5B, structure G2 resembles a tree trunk, and the multiple electrode plates P2 resemble branches extending from structure G2. It is understood that along direction y, there may be more or fewer layers of electrode plates P2. The embodiments of this application do not specifically limit the number of electrode plates P2. In one possible implementation, the material of electrode 213 can be the same as that of electrode 211, for example, it can also be TiN.
[0055] As can be seen from Figures 3, 4, and 5C, along the stacking direction of chip 100, i.e., direction y shown in Figure 3, multiple electrode plates P1 in electrode 211 and multiple electrode plates P2 in electrode 213 are alternately stacked, with electrode plates P1 and P2 separated by a dielectric layer 212. In one possible implementation, as shown in Figure 5C, a structure G2 is provided between every two structures G1. The structure G2 penetrates through the stacked electrode plates P1 and P2, wherein the structure G2 communicates with the multiple electrode plates P2 it penetrates, and is isolated from the electrode plates P1 by the dielectric layer 212. Figure 5C schematically shows electrode plate P1 being wrapped by the dielectric layer 212. It can be understood that electrode plate P2 can also be wrapped by the dielectric layer, exposing the surface of the top electrode plate P1 to the outside. The dielectric layer 212 can be formed of one or more film layers. For example, the dielectric layer 212 may include a film layer, such as HfO2; when the dielectric layer 212 includes multiple films, such as an etch barrier layer and a high-k dielectric layer, the material of the etch barrier layer may include, but is not limited to, Ta2O5, Al2O3 or HfO2, and the material of the high-k dielectric layer may be, for example, a ZAZ film layer or HfO2.
[0056] As shown in Figure 3, along the y-direction, an electrode plate P2 is disposed between every two electrode plates P1, with the electrode plate P2 embedded between the two electrode plates P1. By alternately stacking multiple electrode plates P1 in electrode 211 and multiple electrode plates P2 in electrode 213, the surface areas of electrode 211 and electrode 213 can be greatly increased. Since electrode plates P1 and P2 are fully wrapped together, the relative surface area between electrode 211 and electrode 213 can also be increased, thereby greatly improving the capacitance of MIMCAP. In addition, since electrode plates P1 and P2 are stacked together, if the capacitance of MIMCAP is to be further improved, the number of electrode plates P1 and P2 layers can be increased. Therefore, compared with the prior art of adjusting the intermediate insulating layer of the MIMCAP to increase the capacitance per unit area, the MIMCAP formed by the capacitor structure 21 shown in this application embodiment can greatly increase the capacitance per unit area while ensuring capacitor reliability. In addition, compared with the prior art where the capacitance of the MIMCAP is limited by the height of the groove sidewall, the MIMCAP provided in this application embodiment is not limited by the height of the groove sidewall. For the same layout area, the surface area of the MIMCAP can be further increased to increase the capacitance of the MIMCAP compared with the prior art.
[0057] Referring again to Figure 3, the chip 100 shown in Figure 3 also includes a redistribution layer 30. Along the direction y shown in Figure 3, the redistribution layer 30 is disposed on the surface of the capacitor layer 20 away from the semiconductor layer 10. The redistribution layer 30 may include one or more patterned conductive lines and vias for connecting the multiple conductive lines. The one or more conductive lines in the redistribution layer 30 are used to connect the capacitor structure 21 to the pins 121 in the semiconductor layer 10. Specifically, as shown in Figure 3, a via 31 is provided between the redistribution layer 30 and the capacitor layer 20. The via 31 extends from the redistribution layer 30 to the capacitor layer 20 and penetrates the upper and lower surfaces of the capacitor layer 20 to expose the pins 121 in the semiconductor layer. It should be noted that the area of the via 31 in the capacitor layer 20 is the area where the capacitor structure 21 is not disposed. A conductive material, such as copper, can be disposed in the via 31. The conductive material in the via 31 connects the pin 121 to the conductive line in the redistribution layer 30, and then connects to one of the electrodes in the capacitor structure 21 through the conductive line in the redistribution layer 30. The pin 121 in the semiconductor layer 10 can be connected to any electrode in the capacitor structure 21. When the pin 121 is connected to electrode 211 in the capacitor structure 21, electrode 213 can be connected to the signal line on the PCB shown in Figure 2 through the conductive line in the redistribution layer 30. When the pin 121 is connected to electrode 213 in the capacitor structure 21, electrode 211 can be connected to the signal line on the PCB shown in Figure 2 through the conductive line in the redistribution layer 30.
[0058] Furthermore, one or more conductive lines in the redistribution layer 30 are also used to connect multiple capacitor structures 21 in the capacitor layer 20 in parallel. As shown in FIG3, the electrodes 213 used to form multiple capacitor structures 21 are a continuous structure, which connects multiple electrodes 213 together, while the electrodes 211 of the multiple capacitor structures 21 are isolated by the dielectric layer 212 and the electrodes 213. Therefore, multiple vias 33 are also provided between the redistribution layer 30 and the capacitor layer 20. The vias 33 extend from the redistribution layer 30 to the capacitor layer 20, and the conductive material in the vias 33 is used to connect the electrodes 211 in the capacitor structures 21 to the conductive lines on the redistribution layer 30; thus, the electrodes 211 in the multiple capacitor structures 21 are connected together through the vias 33 and the conductive lines in the redistribution layer 30, realizing the parallel connection between the multiple capacitor structures 21. In addition, an insulating material is provided in the through hole 22. The insulating material can be, for example, silicon oxide. The insulating material is used to wrap the exposed electrode 213 to isolate the electrode 213 from the conductive material, thereby achieving isolation between the electrode 211 and the electrode 213.
[0059] In the chip 100 shown in Figure 3, all structures in the capacitor structure 21 are disposed on the surface of the semiconductor 10. In one possible implementation, some structures in the capacitor structure 21 can extend into the interior of the semiconductor structure 10. Specifically, as shown in Figure 6, which is another structural schematic diagram of the chip 100 provided in this embodiment, the structure G1 in the electrode 211 of the capacitor structure 21, which connects and supports the electrode plate P1, can extend from the capacitor layer 20 to the semiconductor layer 30 along the direction y shown in Figure 6, and extend into the semiconductor layer 30, embedding itself in the semiconductor material (e.g., silicon) within the semiconductor layer 30. By extending the structure G1 along the direction y into the interior of the semiconductor structure 10, the capacitor structure 21 can be more tightly and firmly disposed on the semiconductor layer 10, preventing the capacitor layer 20 from detaching from the semiconductor layer 10, thus improving the reliability of the chip 100. It should be noted that the portion of the semiconductor layer 10 embedded in structure G1 is wrapped with an insulating layer (e.g., a high-k dielectric layer) to isolate it from the semiconductor material in the semiconductor layer 10 through the insulating layer.
[0060] The above embodiments, shown in Figures 3 to 6, illustrate the structure of the chip 100 provided in this application. This application also provides a method for fabricating the chip 100. The method for fabricating the chip 100 is described below using the chip 100 shown in Figure 3 as an example, in conjunction with the structures in each step shown in Figures 8A to 8J. Referring to Figure 7A, which is a flowchart 700 for fabricating the chip 100 provided in this application, the flowchart 700 includes steps 701 to 703 as shown below.
[0061] Step 701: Provide a substrate and form a semiconductor structure 10 on the substrate.
[0062] The substrate can be, for example, a silicon-based substrate, including but not limited to silicon substrates or silicon carbide substrates. In this step, standard front-end processes and materials used in wafer fabrication can be employed to form a semiconductor device on the substrate. These standard processes include, but are not limited to, epitaxial growth, oxidation, deposition, doping, ion implantation, and planarization. Then, a redistribution layer 12 is formed on the semiconductor device layer 11 using processes such as deposition, photolithography, and planarization. The redistribution layer 12 has a plurality of isolated pins 121 on the side away from the semiconductor device layer 11, which are used to bring out the input / output ports of the semiconductor device. The semiconductor device includes, but is not limited to, transistors, capacitors, or resistors.
[0063] Step 702: A capacitor layer 20 is stacked on the semiconductor structure 10. The capacitor layer 20 includes an insulating layer 22 and a plurality of capacitor structures 21 embedded in the insulating layer 22. Each capacitor structure 21 includes an electrode 211, an electrode 213, and a dielectric layer 212 for isolating the electrodes 211 and 213. The first electrode includes a structure G1 extending along the stacking direction and a plurality of electrode plates P1 extending outwards from the structure G1. The second electrode includes a structure G2 extending along the stacking direction and a plurality of electrode plates P2 extending outwards from the structure G2. Along the stacking direction, the plurality of electrode plates P1 and P2 are alternately stacked. Step 702 may further include steps 7021 to 7029.
[0064] Step 7021: An etch barrier layer A is deposited on the semiconductor structure 10, and a first material and a second material are alternately deposited on the etch barrier layer A to form an alternately arranged film layer B and film layer C.
[0065] In this step, a deposition process (e.g., chemical vapor deposition, physical physical vapor deposition, or atomic layer deposition) can be used. First, an etch barrier layer A is deposited on the semiconductor structure 10 to completely cover the semiconductor structure 10. The material of the etch barrier layer A can be, for example, a high-k material, such as hafnium dioxide (HfO2). Then, using the deposition process described above, a first material and a second material are alternately deposited on the etch barrier layer A to form alternating film layers B and C, respectively. The number of film layers B can be one or more, and the number of film layers C can also be one or more. When the number of film layers B and C are both multiple, film layers B and C are alternately arranged, that is, a film layer C is disposed between every two film layers B; or a film layer B is disposed between every two film layers C. The materials of film layers B and C have a high selective etching ratio. Film layer B can be a support layer, and the first material used to form film layer B can be, for example, silicon dioxide (SiO2) or silicon (Si). Film layer C can be a sacrificial layer. When the material of film layer B is SiO2, the second material used to form film layer C can be silicon nitride (SiN); when the material of film layer B is Si, the second material used to form film layer C can be silicon germanium (SiGe). Furthermore, the thickness of the etch stop layer A along the y-direction ranges, for example, from 50 Å to 1000 Å, preferably 200 Å; the thickness of film layer B along the y-direction ranges, for example, from 50 Å to 1000 Å, preferably 200 Å; the thickness of film layer C along the y-direction ranges, for example, from 50 Å to 1000 Å, preferably 200 Å. The structure after this step is shown in Figure 8A, which schematically shows four layers each for film layers B and C. It can be understood that the number of film layers B and C can be more or less.
[0066] Step 7022: Etch alternating layers B and C to form a via through layers B and C, exposing the lowest layer of film in the via.
[0067] In this step, photoresist is first coated on film layer C, and then etched using a patterned mask to form via V1; then the photoresist is removed. The structure formed after this step is shown in Figure 8B, where (1) is a top view and (2) is a cross-sectional view along BB'. As can be seen from (2) in Figure 8B, via V1 extends from the topmost film layer C to the bottommost film layer B, and the bottommost film layer B is exposed. As can be seen from (1) in Figure 8B, via V1 is arranged in an array.
[0068] Step 7023: Deposit the first material in the through-hole V1 and on the surface of the top film layer C.
[0069] In this step, the aforementioned deposition process can be used to deposit a first material on the surfaces of the via V1 and the top film layer C. The first material is as described above and will not be repeated here. The result after this step is shown in Figure 8C. As can be seen from Figure 8C, the via V1 is filled with the first material. Thus, the first material in the via V1, the first material on the surface of the top film layer C, and the film layer B are all connected together to form a continuous structure.
[0070] Step 7024: In the structure shown in Figure 8C, etch the area around the via V1 to form a plurality of through structures V2.
[0071] In this step, photoresist can first be coated on film layer B, and then etched using a patterned mask to form a through-structure V2; then the photoresist is removed. The through-structure V2 includes, but is not limited to, vias or trenches. The structure formed after this step is shown in Figure 8D, where (1) is a top view and (2) is a cross-sectional view along CC'. As can be seen from (2) in Figure 8D, the through-structure V2 extends from the topmost film layer B to the bottommost film layer B, and the bottommost film layer B is exposed. When the through-structure V2 is a trench, as can be seen from (1) in Figure 8D, the via V1 is surrounded by the through-structure V2. In addition, by forming the through-structure V2, the sides of the stacked film layers B and C are exposed to the outside through the through-structure V2.
[0072] Step 7025: Remove part of the film layer C through the through structure V2.
[0073] In this step, a high-selectivity wet etching process can be used to remove part of the film layer C (i.e., the sacrificial layer) in the stacked structure by penetrating structure V2, while retaining film layer B (i.e., the support layer). In one possible implementation, if the materials of film layer B and film layer C are SiO2 and SiN, respectively, phosphoric acid (H3PO4) can be used to remove SiN and retain SiO2; if the materials of film layer B and film layer C are Si and SiGe, respectively, a combination of TMAH or HF+H2O2+HAc can be used to remove SiGe and retain Si. It should be noted that the etching length of film layer C along direction x can be controlled by the immersion time in the wet etching solution. By controlling the time, the length of film layer C along direction x can be controlled, thereby retaining part of film layer C. The structure formed after this step is shown in Figure 8E. As can be seen from Figure 8E, after film layer C is partially removed, a connected channel is formed between the penetrating structure V2 and the region after etching film layer C.
[0074] Step 7026: Dielectric layer 212 and electrode 211 are sequentially deposited in the through structure V2.
[0075] In this step, a dielectric layer 212 can first be formed on the inner surface of the multilayer film B through a deposition process, penetrating the structure V2. The dielectric layer 212 can include one or more materials. In one possible implementation, the dielectric layer 212 can further include an etch stop layer and a high-k dielectric layer. The materials of the etch stop layer and the high-k dielectric layer can be the same or different. When the materials of the etch stop layer and the high-k dielectric layer are the same, the material can be, for example, HfO2; an atomic layer deposition process can be used to form HfO2 on the inner wall of film C, wherein the HfO2 completely covers the inner surface of film C. When the materials of the etch stop layer and the high-k dielectric layer are different, the material of the etch stop layer can include, but is not limited to, Ta2O5, Al2O3, or HfO2, and the material of the high-k dielectric layer can be, for example, a ZAZ film or HfO2; an atomic layer deposition process can be used to sequentially form the etch stop layer and the high-k dielectric layer on the inner wall of film C. After the dielectric layer 212 is formed on the inner wall of the film C, electrode material can be further deposited in the through-structure V2 to form electrode 211. The electrode material can be, for example, TiN, wherein atomic layer deposition can be used to deposit TiN in the through-structure V2.
[0076] Then, the excess dielectric and electrode materials on top of film B are etched away to expose the top surface of film B and the electrode materials. Specifically, one of wet etching, dry etching, or chemical mechanical planarization can be used to etch away the excess dielectric and electrode materials on top.
[0077] Finally, a dielectric layer is deposited on the top surface of the exposed electrode material to encapsulate and cover it. The material of the dielectric layer has been described previously and will not be repeated here. This step is then illustrated in Figure 8F.
[0078] Step 7027: Etch film layer B and the unetched film layer C to expose dielectric layer 212.
[0079] In this step, film layer B and the unetched film layer C from step 7025 can be removed by high-selectivity wet etching, with the etching stopping at dielectric layer 212. In one possible implementation, if film layer B is silicon oxide (e.g., SiO2) and dielectric layer 212 includes an etch barrier layer (material such as Ta2O5), film layer B can be etched using a hydrochloric acid-based solution, with the etching eventually stopping at Ta2O5. The process after this step is shown in Figure 8G.
[0080] Step 7028: Deposit electrode material in the voids of electrode 211 encapsulating dielectric layer 212 and on dielectric layer 212 to form electrode 213.
[0081] In this step, a high-coverage film deposition method is used to deposit electrode material on the structure shown in Figure 8G and in the gaps between the two electrode plates P1 extending from electrode 211. The gaps between the electrode plates P1 are completely filled, and the electrode plates P1 are encased in a dielectric layer 212 to isolate them from electrode 213. In one possible implementation, an ALD process can be used to deposit TiN on the top dielectric layer 212 and in the gaps between the electrode plates P1. The result after this step is shown in Figure 8H.
[0082] Multiple capacitor structures 21 can be formed through steps 702 to 728 above.
[0083] Step 7029: Deposit a film layer D on the formed plurality of capacitor structures 21 to cover and encapsulate the plurality of capacitor structures 21.
[0084] In this step, a film layer D can be further deposited on the structure formed in step 710 (i.e., on electrode 211) to cover and encapsulate the capacitor structure 21, providing support and protection for the capacitor structure 21. Then, the deposited film layer D is planarized using a planarization process to form the insulating layer 22 in the capacitor layer 20. The film layer D can be, for example, silicon oxide. The subsequent steps are shown in Figure 8I.
[0085] Based on the above steps, step 703 may be further included: forming a redistribution layer 30 on the upper surface of the capacitor structure 20, the redistribution layer 30 being used to connect the plurality of capacitor structures to a semiconductor device. The redistribution layer 30 is also used to interconnect at least a portion of the plurality of capacitor structures. Step 703 further includes the following steps 7031 to 7032.
[0086] Step 7031: Using multiple photolithography processes, a plurality of vias 33 are formed on the capacitor structure 21, vias 31 are formed in the area of the capacitor layer 20 where the capacitor structure 21 is not provided, a line 32 connecting the plurality of vias 33 is formed on the upper surface of the insulating layer 22, and a line connecting the vias 33 and vias 31 is formed on the upper surface of the insulating layer 22.
[0087] In this step, photolithography can be used first to etch the film layer on top of structure G1 in electrode 211 to form via 33, thereby exposing the top surface of structure G1 of electrode 211. Then, insulating material is deposited in via 33. Finally, the insulating material is etched so that the exposed portion of electrode 213 is wrapped with insulating material, and the top surface of structure G1 of electrode 211 is exposed. In the above-mentioned process of forming via 33, the portion of insulating layer 22 without capacitor structure 21 can also be etched in the same process to form via 31. In addition, the upper surface of insulating layer 22 can be etched to form lines 32 connecting multiple via 33 through etching. The via 33 penetrates the upper and lower surfaces of insulating layer 22 above capacitor structure 21, the electrode 213 of capacitor structure 21, and dielectric layer 212 to expose electrode 211, and the exposed portion of electrode 213 is wrapped with insulating material in via 33. The via 2 penetrates the upper and lower surfaces of the insulating layer 22 in the capacitor layer 20, in the area where the capacitor structure 21 is not located, to expose the pin 121 on the semiconductor structure 10. This step is then shown in Figure 8J.
[0088] Step 7032: Deposit conductive material on the lines on the surface of via 33, via 31 and insulating layer 22 so that multiple electrodes 21 are interconnected through multiple vias 1 and conductive lines, and the electrodes 21 are interconnected with pins 121 on semiconductor structure 10.
[0089] After steps 701 to 703 described above, the chip 100 shown in Figure 3 can be fabricated. It is understood that step 702, as described above, may include more or fewer sub-steps in the steps used to fabricate the chip 100; similarly, step 703, as described above, may also include more or fewer sub-steps, and this embodiment does not specifically limit the steps. Furthermore, when it is necessary to fabricate the chip 100 shown in Figure 6, in step 7024, the penetrating structure V2 can extend from the topmost film layer B into the interior of the semiconductor structure 10; in step 7026, when depositing the dielectric layer 212 and the electrode 211, the dielectric layer 212 and electrode material can be further deposited in the trenches extending into the interior of the semiconductor structure 10, thereby allowing the structure G1 in the electrode 211 to extend from the top film layer B into the semiconductor structure 10, further improving the reliability of the chip 100.
[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A chip, characterized in that, include: A semiconductor structure in which a semiconductor device is formed; A capacitor layer stacked with the semiconductor structure includes an insulating layer and a plurality of capacitor structures embedded in the insulating layer. Each of the plurality of capacitor structures includes a first electrode, a second electrode, and a dielectric layer for isolating the first electrode and the second electrode. The first electrode includes a first structure extending along the stacking direction and a plurality of first electrode plates extending outward from the first structure. The second electrode includes a second structure extending along the stacking direction and a plurality of second electrode plates extending outward from the second structure. The plurality of first electrode plates and the plurality of second electrode plates are alternately stacked along the stacking direction. A first through-hole penetrates the upper and lower surfaces of the insulating layer. The first through-hole is located in a region of the insulating layer where the plurality of capacitor structures are not disposed. The conductive material filling the first through-hole connects the plurality of capacitor structures to the semiconductor device.
2. The chip according to claim 1, characterized in that, Along the stacking direction, a plurality of first electrode plates located on the same side of the first structure are arranged in parallel at intervals, and a second electrode plate is arranged between every two first electrode plates; Along the stacking direction, a plurality of second electrode plates located on the same side of the second structure are arranged in parallel at intervals, and a first electrode plate is arranged between every two second electrode plates.
3. The chip according to claim 1 or 2, characterized in that, Along the stacking direction, at least one of the first structure and the second structure extends from the capacitor layer into the interior of the semiconductor structure and is isolated from the semiconductor structure by an insulating layer.
4. The chip according to any one of claims 1 to 3, characterized in that, The plurality of capacitor structures are arranged in parallel along a direction perpendicular to the stacking direction; wherein, The multiple first capacitor structures in the plurality of capacitor structures are connected in parallel.
5. The chip according to claim 4, characterized in that, The chip also includes a wiring layer; The wiring layer is disposed on the surface of the capacitor layer on the side away from the semiconductor structure; The wiring layer includes at least one layer of conductive lines and a plurality of second vias, wherein the conductive material in each second via connects the at least one layer of conductive lines to the first electrode in the first capacitor structure. The first electrodes in the plurality of first capacitor structures are connected in parallel through the plurality of second through holes and the at least one layer of conductive lines.
6. The chip according to claim 4 or 5, characterized in that, The second electrodes in the plurality of first capacitor structures are all connected together to form a continuous structure.
7. The chip according to any one of claims 4 to 6, characterized in that, The semiconductor structure includes a device layer and a redistribution layer. The device layer includes the semiconductor device, and the redistribution layer includes at least one wiring layer and a plurality of pins, the plurality of pins being used to bring out the ports of the semiconductor device. The capacitor layer is stacked on top of the redistribution layer and is isolated from the redistribution layer by an insulating material; The conductive material in the first through hole connects the second electrode in the first capacitor structure to one of the plurality of pins.
8. The chip according to any one of claims 1 to 7, characterized in that, The semiconductor device includes at least one of the following: a transistor, a resistor, or a capacitor.
9. An electronic device, characterized in that, Includes a circuit board and a chip as described in any one of claims 1 to 8; The chip is mounted on the circuit board using multiple solder pads; The circuit board includes at least one electronic circuit, which includes at least one of a power line, a ground line, and a signal line. The pins of the semiconductor devices on the chip are connected to the at least one electronic circuit through the plurality of capacitor structures.
10. A method for fabricating a chip, characterized in that, include: A substrate is provided on which a semiconductor structure is formed, and a semiconductor device is formed in the semiconductor structure; A capacitor layer is formed on the semiconductor structure. The capacitor layer includes an insulating layer and a plurality of capacitor structures embedded in the insulating layer. Each of the plurality of capacitor structures includes a first electrode, a second electrode, and a dielectric layer for isolating the first electrode and the second electrode. The first electrode includes a first structure extending along the stacking direction and a plurality of first electrode plates extending outward from the first structure. The second electrode includes a second structure extending along the stacking direction and a plurality of second electrode plates extending outward from the second structure. The plurality of first electrode plates and the plurality of second electrode plates are alternately stacked along the stacking direction. A first through-hole is formed in the capacitor layer, penetrating the upper and lower surfaces of the insulating layer. The first through-hole is located in a region of the insulating layer where the plurality of capacitor structures are not disposed. The conductive material filling the first through-hole connects the plurality of capacitor structures to the semiconductor device.
11. The method according to claim 10, characterized in that, The formation of a capacitor layer on the semiconductor structure includes: Along the stacking direction, a plurality of first electrode plates located on the same side of the first structure are arranged in parallel and spaced apart, and a second electrode plate is arranged between every two first electrode plates. Along the stacking direction, a plurality of second electrode plates located on the same side of the second structure are arranged in parallel at intervals, and a first electrode plate is arranged between every two second electrode plates.
12. The method according to claim 10 or 11, characterized in that, The method further includes: Multiple first capacitor structures are connected in parallel; wherein the multiple capacitor structures are arranged in parallel along a direction perpendicular to the stacking direction.
13. The method according to claim 12, characterized in that, The step of connecting multiple first capacitor structures in parallel includes: A wiring layer is formed on the side of the capacitor layer away from the semiconductor structure; The wiring layer includes at least one layer of conductive lines and a plurality of second vias, wherein the conductive material in each second via connects the at least one layer of conductive lines to the first electrode in the first capacitor structure. The first electrodes in the plurality of first capacitor structures are connected in parallel through the plurality of second through holes and the at least one layer of conductive lines.