Array substrate and display apparatus

Abstract

An array substrate and a display apparatus. The array substrate comprises a base substrate, a plurality of sub-pixels, a common connection line and a common electrode line, wherein the plurality of sub-pixels comprise display sub-pixels and virtual sub-pixels, the common connection line is at least electrically connected to a common electrode of the display sub-pixels, and the common electrode line is located in a non-display area and is connected to the common connection line. The common electrode line comprises a first signal line extending in a first direction and a second signal line extending in a second direction, wherein the maximum size of at least part of the first signal line in the second direction is a first size, the maximum size of the common connection line in the second direction is a second size, and the ratio of the first size to the second size is 4 to 30. According to the array substrate provided in at least one embodiment of the present disclosure, a proportional relationship between a first size and a second size is set, such that the line width of a first signal line can be increased, the voltage uniformity of a common electrode can be improved, and the possibility of the occurrence of adverse phenomena such as horizontal crosstalk and image sticking can be reduced.

Description

Array substrate and display device

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202510213057.8, filed on February 25, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least one embodiment of this disclosure relates to an array substrate and a display device. Background Technology

[0004] Liquid Crystal Displays (LCDs) employ narrow bezel technology to reduce the width of the screen bezels, providing viewers with a better viewing experience. However, while achieving narrow bezels, issues such as crosstalk and image retention still need to be addressed. Summary of the Invention

[0005] At least one embodiment of this disclosure provides an array substrate and a display device.

[0006] An array substrate includes: a substrate including a display area and a non-display area, the non-display area being located on at least one side of the display area; a plurality of sub-pixels located on the substrate, each sub-pixel including a common electrode; the plurality of sub-pixels including display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels being located in the display area, and the virtual sub-pixels being located in the non-display area; a common connection line at least a portion being located within the display area and electrically connected to at least the common electrode of the display sub-pixels; a common electrode line located within the non-display area and electrically connected to the common connection line; wherein the common connection line extends along a first direction, the common electrode line including a first signal line extending along the first direction and a second signal line extending along a second direction, a portion of the first signal line being electrically connected to the common electrode of the virtual sub-pixels, and another portion of the first signal line being electrically connected to the common electrode of the display sub-pixels; the maximum dimension of at least a portion of the first signal line in the second direction is a first dimension, the maximum dimension of the common connection line in the second direction is a second dimension, the ratio of the first dimension to the second dimension is 4 to 30, and the first direction intersects the second direction.

[0007] For example, according to at least one embodiment of the present disclosure, the first signal line includes a first trace and a trace attachment structure, the first trace extending along the first direction, and the trace attachment structure being connected to at least one side of the first trace in the second direction.

[0008] For example, according to at least one embodiment of the present disclosure, the maximum dimension of the first trace in the second direction is a third dimension, and the ratio of the third dimension to the second dimension is 0.9-1.1.

[0009] For example, according to at least one embodiment of the present disclosure, the additional wiring structure includes a second wiring and a first connection portion, the second wiring extending along the first direction, the first connection portion being located at least between the first wiring and the second wiring; the second wiring is located on the side of the first wiring away from the display area, and the maximum dimension of the second wiring in the second direction is a fourth dimension, the fourth dimension being not less than the third dimension.

[0010] For example, according to at least one embodiment of the present disclosure, the portion between the first trace and the second trace, excluding the first connection portion, includes a gap; the array substrate further includes a plurality of data lines, each data line being electrically connected to the pixel electrode of the sub-pixel, the plurality of data lines being arranged along the first direction, and at least one data line overlapping the gap in a direction perpendicular to the substrate.

[0011] For example, according to at least one embodiment of this disclosure, the plurality of sub-pixels are arranged in an array along the first direction and the second direction; the plurality of sub-pixels are divided into multiple rows of sub-pixel rows arranged along the second direction, each row of sub-pixel rows extending along the first direction, and the sub-pixel row closest to the first signal line in the multiple rows of sub-pixel rows is the first row of sub-pixel rows; the first row of sub-pixel rows includes a plurality of display sub-pixels and at least one virtual sub-pixel, the plurality of display sub-pixels are arranged along the first direction, and the at least one virtual sub-pixel is located on at least one side of the plurality of display sub-pixels in the first direction; the trace attachment structure is electrically connected between the first trace and the common electrode of the sub-pixels of the first row of sub-pixel rows.

[0012] For example, according to at least one embodiment of the present disclosure, the sub-pixel includes a pixel region, and the ratio of the area of ​​the orthographic projection of the wiring attachment structure on the substrate to the area of ​​the pixel region is not greater than 3 / 4.

[0013] For example, according to at least one embodiment of this disclosure, the maximum size of the common electrode of the sub-pixels of the first row of sub-pixels in the second direction is a fifth size; in the other sub-pixel rows besides the first row of sub-pixel rows, the maximum size of the common electrode of the sub-pixels of at least one sub-pixel row in the second direction is a sixth size; the ratio of the fifth size to the sixth size is not less than 0.5 and less than 1.

[0014] For example, according to at least one embodiment of this disclosure, in the sub-pixel rows other than the first sub-pixel row, the maximum size of the common electrode of the sub-pixels of at least one sub-pixel row in the second direction is a sixth size; the maximum size of the trace additional structure in the second direction is a seventh size; and the ratio of the sum of the fifth size and the seventh size to the sixth size is 0.9-1.1.

[0015] For example, according to at least one embodiment of the present disclosure, the maximum dimension of the additional wiring structure in the first direction is an eighth dimension; the maximum dimension of the common electrode of the sub-pixels of the first row of sub-pixels in the first direction is a ninth dimension; and the ratio of the eighth dimension to the ninth dimension is 0.9-1.1.

[0016] For example, according to at least one embodiment of the present disclosure, the non-display area includes a first peripheral area, a second peripheral area, and a bonding area, the bonding area being located on one side of the display area in the second direction, the first peripheral area being located between the bonding area and the display area; the second peripheral area being located on at least one side of the display area in the first direction; the first signal line being located in the first peripheral area, and the second signal line being located in the second peripheral area.

[0017] For example, according to at least one embodiment of this disclosure, the common electrode and the common electrode line are disposed in the same layer, and the material of the common electrode is different from the material of the common electrode line; or the common electrode and the common electrode line are disposed in different layers, and the common electrode and the common electrode line are electrically connected through a via.

[0018] At least one embodiment of this disclosure provides an array substrate, comprising: a substrate including a display area and a non-display area, the non-display area being at least located on one side of the display area in a first direction; a plurality of sub-pixels, each sub-pixel including a common electrode and a pixel electrode; the plurality of sub-pixels including display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels being located in the display area, and the virtual sub-pixels being located in the non-display area; a common electrode line located in the non-display area and electrically connected to the common electrode; a plurality of data lines located at least in the display area of ​​the substrate and electrically connected to the pixel electrode, the plurality of data lines being arranged along the first direction; wherein, the common electrode line includes a first signal line extending along the first direction and a second signal line extending along a second direction, the second signal line being located on the side of the common electrode of the virtual sub-pixels away from the common electrode of the display sub-pixels; the first direction intersects the second direction; the orthographic projection of the common electrode of the virtual sub-pixels on the substrate includes a first notch, the orthographic projection of the common electrode of the display sub-pixels on the substrate includes a second notch, and the area of ​​the first notch is larger than the area of ​​the second notch.

[0019] For example, according to at least one embodiment of the present disclosure, the display sub-pixel further includes at least one thin-film transistor; the array substrate further includes a plurality of gate lines, the plurality of gate lines being located at least in the display area of ​​the substrate and arranged along the second direction; the array substrate further includes a conductive connection portion and a gate driving circuit located in the non-display area, the conductive connection portion being electrically connected between the gate lines and the gate driving circuit; at least a portion of the orthographic projection of the conductive connection portion on the substrate is located in the first notch, and the thin-film transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the pixel electrode, the second electrode being located in the second notch.

[0020] For example, according to at least one embodiment of the present disclosure, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction is a tenth dimension, and the spacing between the data line and the common electrode of the adjacent display sub-pixel in the first direction is an eleventh dimension, the ratio of the tenth dimension to the eleventh dimension being 0.9-1.1.

[0021] For example, according to at least one embodiment of this disclosure, the common electrode of the virtual sub-pixel includes a first electrode portion and a second electrode portion, the second electrode portion being closer to the second signal line than the first electrode portion; the common electrode of the display sub-pixel includes a third electrode portion and a fourth electrode portion, the fourth electrode portion being closer to the second signal line than the third electrode portion; the maximum size of the second electrode portion in the second direction is a twelfth size, the maximum size of the first electrode portion in the second direction is a thirteenth size, the twelfth size being smaller than the thirteenth size; the maximum size of the fourth electrode portion in the second direction is a fourteenth size, the maximum size of the third electrode portion in the second direction is a fifteenth size, the fourteenth size being smaller than the fifteenth size; the twelfth size is different from the fourteenth size.

[0022] For example, according to at least one embodiment of this disclosure, the ratio of the thirteenth dimension to the fifteenth dimension is 0.9-1.1, the twelfth dimension is smaller than the fourteenth dimension; the maximum dimension of the second electrode portion in the first direction is the sixteenth dimension, the maximum dimension of the common electrode of the display sub-pixel in the first direction is the seventeenth dimension, and the ratio of the sixteenth dimension to the seventeenth dimension is not greater than 2 / 3.

[0023] For example, according to at least one embodiment of the present disclosure, a straight line extending along the first direction passes through the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the conductive connection portion on the substrate.

[0024] For example, according to at least one embodiment of this disclosure, the common electrode of the display sub-pixel includes a third electrode portion and a fourth electrode portion, the fourth electrode portion being closer to the second signal line than the third electrode portion; the maximum dimension of the common electrode of the virtual sub-pixel in the second direction is an eighteenth dimension, the maximum dimension of the fourth electrode portion in the second direction is a fourteenth dimension, the eighteenth dimension being smaller than the fourteenth dimension; a straight line extending along the first direction does not pass through the orthographic projection of the conductive connection portion on the substrate and the orthographic projection of the common electrode of the virtual sub-pixel on the substrate.

[0025] For example, according to at least one embodiment of the present disclosure, the orthographic projection of the common electrode of the virtual sub-pixel on the substrate is located between the orthographic projection of the second signal line on the substrate and the orthographic projection of the data line on the substrate.

[0026] For example, according to at least one embodiment of this disclosure, the second signal line includes a trace body portion and a second connecting portion, the trace body portion extending along the second direction, and the second connecting portion connected to the side of the trace body portion closer to the display area in the first direction; the second connecting portion is electrically connected to the common electrode of the virtual sub-pixel, the maximum size of the common electrode of the virtual sub-pixel in the first direction is the nineteenth size, and the maximum size of the common electrode of the display sub-pixel in the first direction is the seventeenth size; the nineteenth size is smaller than the seventeenth size.

[0027] For example, according to at least one embodiment of the present disclosure, a straight line extending along the second direction passes through the orthographic projection of the second connection portion on the substrate and the orthographic projection of the conductive connection portion on the substrate.

[0028] For example, according to at least one embodiment of this disclosure, the second connecting portion is disposed in the same layer as the common electrode of the virtual sub-pixel, and the material of the second connecting portion is different from the material of the common electrode of the virtual sub-pixel; or the second connecting portion is disposed in a different layer from the common electrode of the virtual sub-pixel, and the second connecting portion is electrically connected to the common electrode of the virtual sub-pixel through a via.

[0029] For example, according to at least one embodiment of the present disclosure, the orthographic projection of the pixel electrode of the virtual sub-pixel on the substrate overlaps with the orthographic projection of the common electrode of the virtual sub-pixel on the substrate, and also overlaps with the orthographic projection of the second connection portion on the substrate.

[0030] At least one embodiment of this disclosure provides an array substrate, comprising: a substrate including a display area and a non-display area, the non-display area being at least located on one side of the display area in a first direction; a plurality of sub-pixels, each sub-pixel including a common electrode and a pixel electrode; the plurality of sub-pixels including display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels being located in the display area, and the virtual sub-pixels being located in the non-display area; a common electrode line located within the non-display area and electrically connected to the common electrode; wherein, the pixel electrode of the virtual sub-pixel includes a plurality of strip electrodes; the common electrode line includes a first signal line extending along the first direction and a second signal line extending along a second direction, wherein only the orthographic projection of the common electrode on the substrate overlaps with the orthographic projection of the strip electrodes on the substrate; the maximum size of the common electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the common electrode of the display sub-pixel in the first direction, and the maximum size of the pixel electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the pixel electrode of the display sub-pixel in the first direction; the first direction intersects the second direction.

[0031] For example, according to at least one embodiment of this disclosure, of the virtual sub-pixels and the display sub-pixels, only the display sub-pixels include thin-film transistors.

[0032] At least one embodiment of this disclosure provides a display device, comprising: an array substrate as described in any of the above embodiments; and a counter substrate disposed opposite to the array substrate.

[0033] For example, according to at least one embodiment of the present disclosure, one of the array substrate and the opposing substrate is provided with a black matrix layer, the black matrix layer being configured to at least cover the common electrode line, the common connection line and the common electrode of the virtual sub-pixel. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0035] Figure 1 is a plan view of a display device provided in at least one embodiment of the present disclosure.

[0036] Figure 2 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0037] Figure 3 is a partially enlarged schematic diagram of the common electrode line in the array substrate shown in Figure 2.

[0038] Figure 4 is a partial schematic diagram of the array substrate and black matrix layer in a display device provided in at least one embodiment of the present disclosure.

[0039] Figure 5 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0040] Figures 6A and 6B are partially enlarged schematic diagrams of the common electrode line and common electrode in the array substrate provided in different examples of at least one embodiment of this disclosure.

[0041] Figure 7 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0042] Figures 8A and 8B are partially enlarged schematic diagrams of a portion of the structure in an array substrate provided in at least one embodiment of this disclosure.

[0043] Figure 9 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0044] Figures 10A and 10B are partially enlarged schematic diagrams of a portion of the structure in an array substrate provided in at least one embodiment of this disclosure.

[0045] Figure 11 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0048] The terms "parallel," "perpendicular," and "identical" as used in this disclosure include the strictly defined meanings of "parallel," "perpendicular," and "identical," as well as terms such as "approximately parallel," "approximately perpendicular," and "approximately identical," which include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent acceptable deviations for a specific value as determined by a person skilled in the art. In embodiments of this disclosure, "center" can include a strictly defined location at the geometric center as well as a location approximately at the center within a small area surrounding the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0049] To achieve the narrow bezel effect of LCD, the routing space of the common electrode bus (COM busline) outside the display area is reasonably compressed when designing for compatibility with the sensors in the array substrate.

[0050] During the research, the inventors of this application discovered that if the trace width of the common electrode bus is too narrow, it will affect the voltage uniformity of the LCD and easily generate adverse phenomena such as horizontal crosstalk (H-Crosstalk) and image retention, thus affecting the image quality of the LCD display.

[0051] At least one embodiment of this disclosure provides an array substrate. The array substrate includes a substrate, a plurality of sub-pixels, a common connection line, and a common electrode line. The substrate includes a display area and a non-display area, with the non-display area located on at least one side of the display area. The plurality of sub-pixels are located on the substrate, and each sub-pixel includes a common electrode; the plurality of sub-pixels include display sub-pixels and virtual sub-pixels, with at least a portion of the display sub-pixels located in the display area and the virtual sub-pixels located in the non-display area. The common connection line is located within the display area and is electrically connected to at least the common electrode of the display sub-pixels. The common electrode line is located within the non-display area and is connected to the common connection line. The common connection line extends along a first direction, and the common electrode line includes a first signal line extending along the first direction and a second signal line extending along a second direction. A portion of the first signal line is electrically connected to the common electrode of the virtual sub-pixels, and another portion of the first signal line is electrically connected to the common electrode of the display sub-pixels. The maximum dimension of at least a portion of the first signal line in the second direction is a first dimension, and the maximum dimension of the common connection line in the second direction is a second dimension. The ratio of the first dimension to the second dimension is 4 to 30, and the first direction intersects the second direction.

[0052] The array substrate provided in at least one embodiment of this disclosure, by setting the ratio between the first dimension and the second dimension, can increase the linewidth of the first signal line and improve the voltage uniformity of the common electrode. This reduces the likelihood of adverse phenomena such as horizontal crosstalk and image retention, thereby improving the image quality of display devices using the aforementioned array substrate.

[0053] At least one embodiment of this disclosure provides an array substrate. The array substrate includes a substrate, a plurality of sub-pixels, a common electrode line, and a plurality of data lines. The substrate includes a display area and a non-display area, with the non-display area located at least on one side of the display area in a first direction. Each sub-pixel includes a common electrode and a pixel electrode; the plurality of sub-pixels include display sub-pixels and virtual sub-pixels, with at least a portion of the display sub-pixels located in the display area and the virtual sub-pixels located in the non-display area. The common electrode line is located within the non-display area and is electrically connected to the common electrode. The plurality of data lines are located at least in the display area of ​​the substrate and are electrically connected to the pixel electrode, and the plurality of data lines are arranged along the first direction. The common electrode line includes a first signal line extending along the first direction and a second signal line extending along a second direction, the second signal line being located on the side of the common electrode of the virtual sub-pixel away from the common electrode of the display sub-pixel; the first direction and the second direction intersect. The orthographic projection of the common electrode of the virtual sub-pixel onto the substrate includes a first notch, and the orthographic projection of the common electrode of the display sub-pixel onto the substrate includes a second notch, the area of ​​the first notch being larger than the area of ​​the second notch.

[0054] At least one embodiment of the array substrate provided in this disclosure allows for the provision of more space for other structures used to implement electrical connections by setting the area of ​​the first notch to be larger than the area of ​​the second notch, utilizing the notch of the common electrode of the virtual sub-pixels. This increases the linewidth of the second signal line, improves the voltage uniformity of the common electrode, and reduces the area of ​​the non-display area, facilitating narrowing of the bezel.

[0055] At least one embodiment of this disclosure provides an array substrate. The array substrate includes a substrate, a plurality of sub-pixels, and a common electrode line. The substrate includes a display area and a non-display area, with the non-display area located at least on one side of the display area in a first direction. Each sub-pixel includes a common electrode and a pixel electrode; the plurality of sub-pixels include display sub-pixels and virtual sub-pixels, with at least a portion of the display sub-pixels located in the display area and the virtual sub-pixels located in the non-display area. The common electrode line is located within the non-display area and is electrically connected to the common electrode. The pixel electrode of the virtual sub-pixel includes a plurality of strip electrodes, the orthographic projections of the plurality of strip electrodes on the substrate overlapping only with the orthographic projections of the common electrode on the substrate. The maximum size of the common electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the common electrode of the display sub-pixel in the first direction, and the maximum size of the pixel electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the pixel electrode of the display sub-pixel in the first direction; the first direction intersects with a second direction.

[0056] The array substrate provided in at least one embodiment of this disclosure reduces the space occupied by the virtual sub-pixels by decreasing the size of the common electrode and pixel electrode, thereby providing more space for the arrangement of other structures without significantly affecting the display effect. This allows for an increase in the linewidth of the second signal line, improved voltage uniformity of the common electrode, and a reduction in the area of ​​the non-display region, facilitating narrower bezels. Simultaneously, changing the size and shape of the pixel electrode of the virtual sub-pixels does not affect the display or reduce the storage capacitance of the display sub-pixels, ensuring the display effect.

[0057] At least one embodiment of this disclosure provides a display device, including an array substrate and a counter substrate as described in the above embodiments. The counter substrate is disposed opposite to the array substrate.

[0058] The display device provided in at least one embodiment of this disclosure can increase the linewidth of the common electrode line, improve the voltage uniformity of the common electrode, and reduce the area of ​​the non-display area by setting the array substrate described above, which is beneficial for narrowing the bezel.

[0059] The array substrate and display device are described below with reference to the accompanying drawings and through some embodiments.

[0060] Figure 1 is a plan view of a display device provided in at least one embodiment of the present disclosure. Figure 2 is a partial plan view of an array substrate provided in at least one embodiment of the present disclosure. Figure 3 is a partially enlarged view of the common electrode lines in the array substrate shown in Figure 2.

[0061] For example, the array substrate shown in FIG2 can be applied to the display device shown in FIG1. ​​For example, when the array substrate shown in FIG2 is applied to the display device shown in FIG1, a partial structure of the array substrate shown in FIG2 can be located at the upper left corner of the display device shown in FIG1.

[0062] For example, the accompanying drawings in the embodiments of this disclosure only schematically show a part of the structure on the substrate and omit another part of the structure, but this disclosure does not limit it. As shown in Figure 2, nine sub-pixels are provided on the substrate, but this disclosure does not limit such things as the number of sub-pixels, and will not be repeated hereafter.

[0063] For example, in Figure 3 of this embodiment, the selected area is schematically shown by the outermost dashed box to represent a partial enlarged view. In the examples described later, the outermost dashed boxes shown in Figures 6A, 6B, 8A, 8B, 10A, and 10B will not be explained again. It should also be noted that, for clarity, some structures are omitted in the figures of this embodiment. For example, compared to Figure 2, Figures 5 and 9 omit structures such as the gate drive circuit and power supply lines, which will not be described again in this disclosure.

[0064] Referring to Figures 1 and 2, the array substrate includes a substrate 10, a plurality of sub-pixels 100, a common connection line 200, and a common electrode line 300. The substrate 10 includes a display area 11 and a non-display area 12, with the non-display area 12 located on at least one side of the display area 11. For example, the display area can be a region used for display, and the non-display area can be a region not used for display. For example, the non-display area can be located only on one side of the display area, or it can be located on both sides of the display area or surround the display area.

[0065] Referring to Figures 1 and 2, a plurality of sub-pixels 100 are located on a substrate 10, and each sub-pixel 100 includes a common electrode 110. The plurality of sub-pixels 100 includes display sub-pixels 101 and virtual sub-pixels 102. For example, a display sub-pixel can be a sub-pixel used for image display, such as one that can be driven to emit light. A virtual sub-pixel can be a sub-pixel not used for actual image display, such as one that is not driven to emit light.

[0066] Referring to Figures 1 and 2, at least a portion of the display subpixel 101 is located in the display area 11, and the virtual subpixel 102 is located in the non-display area 12. For example, a display subpixel may be partially located in the display area and partially located in the non-display area. For example, a display subpixel may be entirely located in the display area.

[0067] Referring to Figures 1 and 2, at least a portion of the common connection line 200 is located within the display area 11 and is electrically connected to at least the common electrode 110 of the display sub-pixels 101. For example, the common connection line may be partially located within the display area and partially located within the non-display area. For example, the common connection line may be electrically connected only to the common electrode of the display sub-pixels and the virtual sub-pixels. For example, the common connection line may be electrically connected to both the common electrode of the display sub-pixels and the common electrode of the virtual sub-pixels.

[0068] Referring to Figures 1, 2, and 3, the common electrode line 300 is located within the non-display area 12 and is electrically connected to the common connection line 200. The common connection line 200 extends along a first direction X. The common electrode line 300 includes a first signal line 310 extending along the first direction X and a second signal line 320 extending along a second direction Y. A portion of the first signal line 310 is electrically connected to the common electrode 110 of the virtual sub-pixel 102, and another portion of the first signal line 310 is electrically connected to the common electrode 110 of the display sub-pixel 101.

[0069] Referring to Figures 1, 2 and 3, the maximum dimension of at least a portion of the first signal line 310 in the second direction Y is a first dimension D1, the maximum dimension of the common connection line 200 in the second direction Y is a second dimension D2, the ratio of the first dimension D1 to the second dimension D2 is 4 to 30, and the first direction X intersects the second direction Y.

[0070] Referring to Figures 1, 2, and 3, the array substrate provided in this embodiment, by setting the ratio between the first dimension D1 and the second dimension D2, can increase the linewidth of the first signal line 310 and improve the voltage uniformity of the common electrode 110. This reduces the likelihood of adverse phenomena such as horizontal crosstalk and image retention, thus improving the image quality of the display device using the aforementioned array substrate.

[0071] For example, referring to Figures 1, 2, and 3, a virtual sub-pixel 102 is provided in the non-display area 12 to improve the image quality displayed by the display sub-pixels 101 in the display area 11. Since the virtual sub-pixel 102 is not used for light emission, at least part of the structure of the virtual sub-pixel 102 can be removed, thereby providing more space for the common electrode line 300. In this way, the structural layout of the array substrate is easier to achieve during the narrow bezel design, such as achieving sensor compatibility. Moreover, the linewidth of the common electrode line 300 can be increased without increasing the area of ​​the non-display area 12, thereby enhancing the voltage uniformity of the common electrode 110.

[0072] For example, referring to Figures 1 and 2, the boundary of the display area 11 shown in Figure 1 can be the gap between the sub-pixel 100 and the common electrode line 300, or the edge of the sub-pixel 100 near the common electrode line 300.

[0073] For example, a common connection line may be electrically connected only to the common electrode of a display sub-pixel. Alternatively, a common connection line may be electrically connected to both the common electrode of a display sub-pixel and the common electrode of a virtual sub-pixel.

[0074] For example, referring to Figures 2 and 3, the common electrode line 300 and the common connection line 200 can be arranged in the same layer and connected to each other, such as the common electrode line 300 and the common connection line 200 being in direct contact. For example, the common electrode line 300 and the common connection line 200 can be an integral structure.

[0075] For example, referring to Figures 2 and 3, the first signal line 310 and the second signal line 320 are connected. For example, the first signal line 310 and the second signal line 320 can be a single integrated structure.

[0076] For example, referring to Figures 2 and 3, the first signal line 310 extends entirely along the first direction X, and the first dimension D1 can be the linewidth of the first signal line 310. For example, in conjunction with the example described later, when the first signal line includes multiple parts in the second direction, the first dimension can be the sum of the dimensions of the multiple parts in the second direction, which will be explained in detail later and will not be repeated here.

[0077] For example, the first direction can be perpendicular to the second direction.

[0078] For example, referring to Figure 3, the ratio of the first dimension D1 to the second dimension D2 can be from 4 to 30. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 5 to 28. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 7 to 25. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 9 to 23. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 11 to 20. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 13 to 18. For example, the ratio of the first dimension D1 to the second dimension D2 can be from 15 to 16. Of course, the ratio of the first dimension D1 to the second dimension D2 can also be other values, which will not be listed here.

[0079] For example, referring to Figure 3, the second dimension D2 can be no less than 5 micrometers. For example, the second dimension D2 can be 5 micrometers to 20 micrometers to prevent affecting pixel transmittance. For example, the second dimension D2 can be 6 micrometers to 18 micrometers. For example, the second dimension D2 can be 8 micrometers to 16 micrometers. For example, the second dimension D2 can be 10 micrometers to 14 micrometers. For example, the second dimension D2 can be 11 micrometers to 12 micrometers.

[0080] For example, referring to Figure 3, the first dimension D1 can be from 21 micrometers to 145 micrometers. For example, the first dimension D1 can be from 25 micrometers to 130 micrometers. For example, the first dimension D1 can be from 30 micrometers to 120 micrometers. For example, the first dimension D1 can be from 40 micrometers to 110 micrometers. For example, the first dimension D1 can be from 50 micrometers to 100 micrometers. For example, the first dimension D1 can be from 60 micrometers to 90 micrometers. For example, the first dimension D1 can be from 70 micrometers to 80 micrometers. However, this disclosure does not limit the values ​​of the first dimension D1 and the second dimension D2; the first dimension D1 and the second dimension D2 can also be other values, which will not be listed here.

[0081] Referring to Figures 2 and 3, in some examples, the first signal line 310 includes a first trace L1 and a trace attachment structure 311. The dashed box in Figure 3 schematically outlines the portion of the first signal line 310 containing the first trace L1 and the portion containing the trace attachment structure 311. The first trace L1 extends along a first direction X, and the trace attachment structure 311 connects to at least one side of the first trace L1 in a second direction Y. Thus, the overall linewidth of the first signal line 310 can be increased simultaneously with the first trace L1 by utilizing the trace attachment structure 311.

[0082] For example, the maximum dimension of the additional trace structure in the second direction can be greater than the maximum dimension of the first trace in the second direction. For example, the additional trace structure may include multiple parts (such as the second trace and the first connection in the example described later), in which case the maximum dimension of the additional trace structure in the second direction can be the sum of the maximum dimensions of the second trace and the first connection in the second direction. For example, the maximum dimension of the second trace in the second direction is not less than 5 micrometers.

[0083] For example, the maximum dimension of the additional structure for the trace in the second direction, such as the maximum dimension of the second trace in the second direction, may also be equal to or less than the maximum dimension of the first trace in the second direction, and this disclosure does not impose any restrictions on this.

[0084] For example, Figure 3 schematically shows the additional wiring structure 311 connected to the side of the first wiring L1 away from the display area 11. However, this disclosure is not limited to this. For example, the additional wiring structure can also be connected to the side of the first wiring closer to the display area, as will be illustrated in the examples described later, and will not be repeated here.

[0085] Referring to Figure 3, in some examples, multiple sub-pixels 100 can be divided into multiple rows of sub-pixel rows R, with the first row of sub-pixel rows R1 closest to the first signal line 310 including multiple display sub-pixels 101 and at least one virtual sub-pixel 102.

[0086] Unlike the array substrate shown in Figure 3, in some other embodiments of the array substrate, the first row of subpixel rows is a virtual subpixel row, meaning that all the subpixels in the first row are virtual subpixels. Meanwhile, the second row of subpixel rows is the same as the first subpixel row R1 shown in Figure 3, meaning that the second row includes multiple display subpixels and at least one virtual subpixel.

[0087] By connecting the additional wiring structure 311 shown in Figure 3 to the side of the first wiring L1 away from the display area 11, and simultaneously setting the sub-pixel 100 in the first sub-pixel row R1, it can be considered that the aforementioned virtual sub-pixel row has been removed, while the additional wiring structure 311 occupies the area where the original virtual sub-pixel row was located. For example, the size of the additional wiring structure 311 in the second direction Y can be smaller than the size of the common electrode 110 of the sub-pixel 100 in the second direction Y. This will not affect the display of the sub-pixels and is beneficial for narrowing the bezel.

[0088] Referring to Figures 1 and 2, in some examples, the non-display area 12 includes a first peripheral area 1201, a second peripheral area 1202, and a bonding area 1203. The bonding area 1203 is located on one side of the display area 11 in the second direction Y, and the first peripheral area 1201 is located between the bonding area 1203 and the display area 11. The second peripheral area 1202 is located on at least one side of the display area 11 in the first direction X. A first signal line 310 is located in the first peripheral area 1201, and a second signal line 320 is located in the second peripheral area 1202.

[0089] Chip-on-film (COF) technology is a chip packaging technology that can effectively reduce the space occupied by traces. For example, an array substrate can be connected to a flexible circuit board and a driver chip via a COF film in the bonding area. For example, referring to Figures 1 and 2, the virtual sub-pixel row near the bonding area 1203 can be removed, thereby reserving more space for widening the first signal line 310.

[0090] It should be noted that, referring to Figures 1 and 2, in the array substrate, the last row of sub-pixel rows in the peripheral area opposite to the first peripheral area 1201 in the second direction Y can be virtual sub-pixel rows, meaning that all sub-pixels in the last row are virtual sub-pixels. The common connection line also includes a trace portion located on the side of the last row of sub-pixel rows away from the display area 11. The structure of this trace portion can also refer to the structure of the first signal line 310 shown in Figures 1 to 3. For example, the maximum dimension (i.e., line width) of this trace portion in the second direction Y can be the same as the maximum dimension of the first signal line 310 in the second direction Y, such as 10 micrometers to 100 micrometers. However, this disclosure is not limited to this; the structure of the trace portion can also differ from the structure of the first signal line, and the line width of the trace portion can be greater than or less than the maximum dimension of the first signal line in the second direction.

[0091] For example, referring to FIG1, the non-display area 12 may also include a region located on the side of the display area 11 away from the first peripheral area 1201. For example, the second peripheral area 1202 may be located on both sides of the display area 11 in the first direction X. However, this disclosure is not limited thereto, such as the second peripheral area may also be located only on one side of the display area in the first direction.

[0092] Referring to Figure 3, in some examples, the maximum dimension of the first trace L1 in the second direction Y is the third dimension D3, and the ratio of the third dimension D3 to the second dimension D2 is 0.9-1.1. Therefore, the linewidth of the first trace L1 is close to the linewidth of the common connection line 200, which helps to make the voltage obtained by the common electrode of each sub-pixel 100 more uniform. This results in more uniform brightness and color of the displayed image, preventing problems such as local over-brightness or under-brightness, color deviation, etc., and improving display quality.

[0093] Referring to Figure 3, in some examples, the additional trace structure 311 includes a second trace L2 and a first connection portion 3110. The dashed boxes in Figure 3 schematically outline the portion of the additional trace structure 311 containing the second trace L2 and the portion containing the first connection portion 3110. The second trace L2 extends along a first direction X, and the first connection portion 3110 is located at least between the first trace L1 and the second trace L2. The second trace L2 is located on the side of the first trace L1 away from the display area 11, and the maximum dimension of the second trace L2 in the second direction Y is a fourth dimension D4. The fourth dimension D4 is not less than the third dimension D3. Therefore, the linewidth of the first signal line 310 can be maximized by utilizing the combined action of the second trace L2 and the first connection portion 3110. Simultaneously, the location of the second trace L2 on the side of the first trace L1 away from the display area 11 helps improve the uniformity of the sub-pixel configuration 100 on the array substrate. For example, the row of sub-pixels closest to the first trace is the first row of sub-pixels. The shape of the common electrode of the first row of sub-pixels can be consistent with the shape of the common electrode of the other row of sub-pixels. At the same time, the shape of the first trace and the common connection line can be consistent, thereby improving the uniformity of the electric field.

[0094] For example, referring to FIG3, when the first signal line 310 includes a first trace L1, a second trace L2 and a first connection portion 3110, the maximum dimension of the first signal line 310 in the second direction Y (i.e., the first dimension D1) can be the sum of the maximum dimension of the first trace L1 in the second direction Y (i.e., the third dimension D3), the maximum dimension of the second trace L2 in the second direction Y (i.e., the fourth dimension D4), and the maximum dimension of the first connection portion 3110 in the second direction Y.

[0095] For example, the maximum dimension of the first connecting portion in the second direction can be from 6 micrometers to 40 micrometers. For example, the maximum dimension of the first connecting portion in the second direction can be from 8 micrometers to 35 micrometers. For example, the maximum dimension of the first connecting portion in the second direction can be from 10 micrometers to 30 micrometers. For example, the maximum dimension of the first connecting portion in the second direction can be from 15 micrometers to 25 micrometers. For example, the maximum dimension of the first connecting portion in the second direction can be 20 micrometers. However, this disclosure does not limit the value of the maximum dimension of the first connecting portion in the second direction; the maximum dimension of the first connecting portion in the second direction can also be other values, which will not be listed here.

[0096] Referring to Figure 3, for example, the fourth dimension D4 can be equal to the third dimension D3. For example, the fourth dimension D4 can be greater than the third dimension D3. For example, the fourth dimension D4 can be from 10 micrometers to 100 micrometers. For example, the fourth dimension D4 can be from 20 micrometers to 90 micrometers. For example, the fourth dimension D4 can be from 30 micrometers to 80 micrometers. For example, the fourth dimension D4 can be from 40 micrometers to 70 micrometers. For example, the fourth dimension D4 can be from 50 micrometers to 60 micrometers. However, this disclosure does not limit the value of the fourth dimension D4; the fourth dimension D4 can also be other values, which will not be listed here.

[0097] Referring to FIG3, for example, the first connecting part 3110 can be connected between the first trace L1 and the second trace L2 as shown in FIG3 to realize the electrical connection between the first trace L1 and the second trace L2.

[0098] However, this disclosure is not limited thereto. For example, the first connection portion can also be connected to the side of the second trace away from the first trace. For example, if the first connection portion is located on the side of the second trace away from the first trace, an electrical connection with other common electrode lines of different film layers can be achieved by providing a via.

[0099] Referring to Figure 3, in some examples, the portion between the first trace L1 and the second trace L2, excluding the first connection portion 3110, includes a spacer G. The array substrate also includes multiple data lines 400, each of which is electrically connected to the pixel electrode 120. The multiple data lines 400 are arranged along a first direction X, and at least one data line 400 overlaps with the spacer G in a direction perpendicular to the substrate 10. Therefore, the spacer G can be used to reduce the overlapping area of ​​the data line 400 and the first signal line 310, thereby reducing parasitic capacitance and signal interference.

[0100] Referring to Figure 3, for example, each data line 400 overlaps with a corresponding interval G.

[0101] Referring to Figure 3, for example, the maximum dimension of the interval G in the second direction Y is smaller than the maximum dimension of the first signal line 310 in the second direction Y.

[0102] Referring to Figure 3, for example, the ratio of the maximum dimension of the interval G in the second direction Y to the maximum dimension of the first connecting portion 3110 in the second direction Y can be 0.9-1.1, such as a ratio of 1.

[0103] Referring to Figure 3, for example, a straight line extending along the second direction Y can pass through the orthographic projection of the first connection portion 3110 on the substrate 10 and the orthographic projection of the common electrode 110 corresponding to a sub-pixel 100 on the substrate 10. For example, when the first connection portion and the common electrode are disposed on the same layer, the orthographic projection of the first connection portion overlaps with the orthographic projection of the common electrode on a reference plane perpendicular to the second direction. As a result, the resistance of the first signal line can be reduced, and excessive load on the data line can be prevented, such as preventing excessive parasitic capacitance between the data line and other signal lines or conductors such as electrodes.

[0104] Referring to Figure 3, for example, the size of the first connecting portion 3110 in the first direction X can be substantially the same as the size of the common electrode 110 corresponding to a sub-pixel 100 in the first direction X. However, this disclosure is not limited to this. On a reference plane perpendicular to the second direction Y, the orthographic projection of the first connecting portion 3110a overlaps with the orthographic projection of the second signal line 320, and the maximum size of the first connecting portion 3110a in the first direction X can be the same as the maximum size of the second signal line 320 in the first direction X.

[0105] Referring to Figure 3, for example, a plurality of first connection portions 3110 are arranged in the first direction X. The interval G may be located between the second signal line 320 and the first connection portion 3110, or the interval G may be located between two adjacent first connection portions 3110.

[0106] For example, a first connection may not be provided between the first trace and the second trace, and the first trace and the second trace may be electrically connected through a second signal line. In this case, the first trace and the second trace may have a gap extending in a first direction. This disclosure does not impose any limitations on this.

[0107] Figure 4 is a partial schematic diagram of the array substrate and black matrix layer in a display device provided in at least one embodiment of the present disclosure. For example, the display substrate shown in Figure 4 may be the same as or different from the display device shown in Figure 1, and the present disclosure does not impose any limitations on this.

[0108] Referring to FIG4, an embodiment of the present disclosure provides a display device, including an array substrate 01 and an opposing substrate 02 as shown in FIG2, wherein the opposing substrate 01 and the array substrate 02 are disposed opposite to each other. Since the display device according to the embodiment of the present disclosure includes the above-mentioned array substrate 01, it also has corresponding beneficial technical effects, such as increasing the linewidth of the common electrode lines, improving the voltage uniformity of the common electrodes, and reducing the area of ​​the non-display area, which is beneficial for narrowing the bezel, which will not be elaborated here.

[0109] Referring to Figure 4, in some examples, one of the array substrate 01 and the opposing substrate 02 is provided with a black matrix layer BM. The black matrix layer BM is configured to at least cover the common electrode line 300, the common connection line 200, and the common electrode 110 of the virtual sub-pixel 102. In this way, the traces such as the common electrode line 300 and the common connection line 200 can be blocked by the black matrix layer BM, and the non-light-emitting virtual sub-pixel 102 can also be blocked by the black matrix layer BM, which is beneficial to improving the display effect.

[0110] For example, Figure 4 schematically shows a black matrix layer disposed on an opposing substrate; however, this disclosure is not limited thereto, and the black matrix layer may also be disposed on an array substrate.

[0111] For example, referring to Figure 4, the black matrix layer BM can also obscure a portion of the common electrode 110 of the display sub-pixels 101. For example, the area of ​​the common electrode 110 of the display sub-pixels 101 closest to the non-display area 12 that is obscured by the black matrix layer BM is larger than the area of ​​the common electrode 110 of other display sub-pixels 101 that is obscured by the black matrix layer BM. For example, the black matrix layer BM can obscure 1 / 3 of the area of ​​the pixel region of the display sub-pixels 101 (described in detail later) to satisfy display uniformity.

[0112] For example, referring to Figure 4, the black matrix layer BM includes multiple black matrix openings BM1 to define the light-emitting area of ​​sub-pixel 100.

[0113] Figure 5 is a partial planar schematic diagram of an array substrate provided in one example of at least one embodiment of the present disclosure. Figures 6A and 6B are partially enlarged schematic diagrams of common electrode lines and common electrodes in array substrates provided in different examples of at least one embodiment of the present disclosure.

[0114] For example, the array substrate shown in FIG5 can be applied to the display device shown in FIG1, and this disclosure is not limiting in this regard. For example, when the array substrate shown in FIG5 is applied to the display device shown in FIG1, a partial structure of the array substrate shown in FIG5 can be located at the upper left corner of the display device shown in FIG1. ​​For example, the difference between the array substrate shown in FIG5 and the array substrate shown in FIG2 is that the common electrode shown in FIG5 is different from the common electrode shown in FIG2, and the common electrode line shown in FIG5 is different from the common electrode line shown in FIG2. However, this disclosure is not limited to this, and the array substrate shown in FIG5 and the array substrate shown in FIG2 can have more differences. For example, the common electrode line and common electrode shown in FIG6A can be the same as the common electrode line and common electrode shown in FIG5. But this disclosure is not limited to this, and the common electrode line and common electrode shown in FIG6B can also be applied to the array substrate shown in FIG5.

[0115] Referring to Figure 5, in some examples, multiple sub-pixels 100 are arranged in an array along a first direction X and a second direction Y. The multiple sub-pixels 100 are divided into multiple rows of sub-pixel rows R arranged along the second direction Y. Each row of sub-pixel rows R extends along the first direction X. The sub-pixel row R closest to the first signal line 310 in the multiple rows of sub-pixel rows R is the first row of sub-pixel rows R1.

[0116] Referring to Figure 5, in some examples, the first row of subpixels R1 includes a plurality of display subpixels 101 and at least one virtual subpixel 102. The plurality of display subpixels 101 are arranged along a first direction X, and the at least one virtual subpixel 102 is located on at least one side of the plurality of display subpixels 101 in the first direction X. For example, in the first row of subpixels, the virtual subpixel may be located on only one side of the plurality of display subpixels in the first direction. For example, in the first row of subpixels, there may be multiple virtual subpixels, such as two, and the two virtual subpixels may be located on opposite sides of the plurality of display subpixels in the first direction, respectively.

[0117] Referring to Figures 5, 6A, and 6B, the additional wiring structure 311 is electrically connected between the common electrode 110 of the sub-pixels 100 of the first wiring L1 and the first row of sub-pixels R1, thereby widening the line width of the common electrode line 310. Simultaneously, the additional wiring structure 311 extends in a direction away from the non-display area 12, which helps to reduce the area of ​​the non-display area 12 and achieve a narrower bezel.

[0118] Referring to Figures 5, 6A, and 6B, for example, the additional wiring structure 311 can work together with the common electrode 110 to provide a potential difference to the pixel electrode 120, thereby forming an electric field. For instance, the area of ​​the common electrode 110 of the sub-pixel 100 can be reduced, and the additional wiring structure 311 can replace the reduced portion of the common electrode 100. In this way, the additional wiring structure 311 does not need to occupy the area of ​​the non-display area 12, which is beneficial for narrowing the bezel. Moreover, the combined action of the additional wiring structure 311 and the common electrode 110 does not affect the storage capacitance of the sub-pixel 100, thus making the display effect of each display sub-pixel 101 more consistent. For example, the storage capacitance of the display sub-pixels in the first row of sub-pixels is basically the same as that in the other rows of sub-pixels, improving the display effect.

[0119] Referring to Figures 5, 6A, and 6B, in some examples, sub-pixel 100 includes pixel area (dot) D100 (see the dotted line box shown in Figure 5). The ratio of the area of ​​the orthographic projection of the trace attachment structure 311 on the substrate 10 to the area of ​​pixel area D100 is no greater than 3 / 4, in order to prevent the trace attachment structure 311 from occupying too large an area and causing the risk of uneven edge display brightness, thereby preventing the display effect from being affected.

[0120] It is understood that Figures 5 to 6B schematically show that the additional wiring structure 311 is rectangular in shape, and the maximum size of the additional wiring structure 311 in the first direction X is substantially the same as the maximum size of the common electrode 110 in the first direction X, but this disclosure is not limited thereto. As long as the area occupied by the additional wiring structure does not exceed 3 / 4 of the pixel area and can be obscured by the black matrix layer, this disclosure does not limit the shape and size of the additional wiring structure.

[0121] For example, the ratio of the area of ​​the orthographic projection of the wiring attachment structure on the substrate to the area of ​​the pixel region can be 1 / 10 to 3 / 4. For example, the ratio of the area of ​​the orthographic projection of the wiring attachment structure on the substrate to the area of ​​the pixel region can be 1 / 5 to 1 / 2. For example, the ratio of the area of ​​the orthographic projection of the wiring attachment structure on the substrate to the area of ​​the pixel region can be 1 / 4. However, this disclosure is not limited to the above values, and the above ratios can also be other values, which will not be listed here.

[0122] Referring to Figure 5, for example, the array substrate also includes multiple gate lines 500, which intersect with multiple data lines 400 to define multiple pixel regions D100. For example, one pixel region D100 corresponds to one sub-pixel 100. For example, the area of ​​a pixel region can be the area enclosed by the gate lines and data lines, such as the area formed by the intersection of the center line of the gate line and the center line of the data line. For example, in the first row of sub-pixel rows R1, the area of ​​a pixel region D100 can be the area enclosed by the data line 400, the gate line 500, and the first signal line 310, such as the area formed by the intersection of the center line of the data line 400, the center line of the gate line 500, and the center line of the first signal line 310.

[0123] Referring to Figure 5, in some examples, the maximum size of the common electrode 110 of the sub-pixels 100 in the first sub-pixel row R1 in the second direction Y is the fifth size D5. In the other sub-pixel rows R2 besides the first sub-pixel row R1, the maximum size of the common electrode 110 of the sub-pixels 100 in at least one sub-pixel row in the second direction Y is the sixth size D6. The ratio of the fifth size D5 to the sixth size D6 is not less than 0.5 and less than 1, to facilitate meeting requirements such as electric field formation, display effects, and charge transfer.

[0124] For example, in the sub-pixel rows other than the first row, the maximum size of the common electrode of the sub-pixels in each sub-pixel row in the second direction is the sixth size.

[0125] For example, the ratio of the fifth dimension to the sixth dimension can be 0.5-0.99. For example, the ratio of the fifth dimension to the sixth dimension can be 0.55-0.95. For example, the ratio of the fifth dimension to the sixth dimension can be 0.6-0.9. For example, the ratio of the fifth dimension to the sixth dimension can be 0.65-0.85. For example, the ratio of the fifth dimension to the sixth dimension can be 0.7-0.8. For example, the ratio of the fifth dimension to the sixth dimension can be 0.75. For example, the ratio of the fifth dimension to the sixth dimension can be 2 / 3. However, this disclosure is not limited to the above values; the ratios can also be other values, which will not be listed here.

[0126] Referring to FIG5, for example, the display sub-pixel 101 further includes a thin-film transistor T electrically connected to the pixel electrode 120, and the common electrode 110 has a notch to avoid at least a portion of the structure in the thin-film transistor T. In this case, the maximum dimension of the common electrode 110 in the second direction Y refers to the dimension of the portion excluding the notch in the second direction Y.

[0127] Referring to Figure 5, for example, the thin-film transistor T in the display sub-pixel 101 can be electrically connected to the pixel electrode 120 of the display sub-pixel 101 via a via. For example, the virtual sub-pixel 102 is not used for display, so the virtual sub-pixel 102 can only have a structure with the thin-film transistor T without electrically connecting the thin-film transistor T to the pixel electrode 120.

[0128] Referring to Figure 5, in some examples, in the sub-pixel rows R2 other than the first sub-pixel row R1, the maximum size of the common electrode 110 of the sub-pixels 100 in at least one sub-pixel row in the second direction Y is the sixth size D6, and the maximum size of the additional wiring structure 311 in the second direction Y is the seventh size D7. The ratio of the sum of the fifth size D5 and the seventh size D7 to the sixth size D6 is 0.9-1.1, so that the overall structure of the sub-pixels 100 in the first sub-pixel row R1 tends to be consistent with the overall structure of the sub-pixels in the other sub-pixel rows R2 other than the first sub-pixel row R1.

[0129] For example, the ratio of the sum of the fifth and seventh dimensions to the sixth dimension can be 0.91-1.09. For example, the ratio of the sum of the fifth and seventh dimensions to the sixth dimension can be 0.95-1.05. For example, the ratio of the sum of the fifth and seventh dimensions to the sixth dimension can be 1. However, this disclosure is not limited to the above values; the ratios can also be other values, which will not be listed here.

[0130] For example, referring to FIG5, when the first signal line 310 includes a first trace L1 and a trace attachment structure 311, the maximum dimension of the first signal line 310 in the second direction Y (i.e., the first dimension D1) can be the sum of the maximum dimension of the first trace L1 in the second direction Y and the maximum dimension of the trace attachment structure 311 in the second direction Y (i.e., the seventh dimension D7). For example, the maximum dimension of the first trace L1 in the second direction Y shown in FIG5 can be different from the third dimension D3 shown in FIG3, such as being larger than the third dimension D3 shown in FIG3 to facilitate the widening of the first signal line 310. However, this disclosure does not limit this, and the maximum dimension of the first trace L1 in the second direction Y shown in FIG5 can also be the same as the third dimension D3 shown in FIG3.

[0131] Referring to Figure 5, in some examples, the maximum dimension of the additional trace structure 311 in the first direction X is the eighth dimension D8, and the maximum dimension of the common electrode 110 of the sub-pixels 100 of the first row of sub-pixels R1 in the first direction X is the ninth dimension D9. The ratio of the eighth dimension D8 to the ninth dimension D9 is 0.9-1.1. For example, the maximum dimension of the additional trace structure 311 in the first direction X and the maximum dimension of the corresponding common electrode 110 in the first direction X tend to be consistent, which helps to simplify the manufacturing process.

[0132] Referring to FIG5, for example, the display sub-pixel 100 also includes a thin-film transistor T electrically connected to the pixel electrode 120, and a common electrode 110 having a notch to avoid at least a portion of the structure in the thin-film transistor T. In this case, the maximum dimension of the common electrode 110 in the first direction X refers to the dimension of the portion excluding the notch in the first direction X.

[0133] For example, the ratio of the eighth dimension to the ninth dimension can be 0.91-1.09. For example, the ratio of the eighth dimension to the ninth dimension can be 0.95-1.05. For example, the ratio of the eighth dimension to the ninth dimension can be 1. However, this disclosure is not limited to the above values, and the above ratios can also be other values, which will not be listed here.

[0134] Referring to Figure 6A, in some examples, the common electrode 110 is disposed in the same layer as the common electrode line 300, and the material of the common electrode 110 is different from the material of the common electrode line 300, in order to simplify the manufacturing process.

[0135] For example, the common electrode can be directly connected to a common electrode line. For example, the material of the common electrode can include indium tin oxide (ITO). For example, the material of the common electrode line can include metals such as aluminum or copper.

[0136] Referring to Figure 6B, for example, the common electrode 110 and the common electrode line 311 are disposed in different layers, and the common electrode 110 and the common electrode line 311 are electrically connected through a via V1. The electrical connection between the common electrode 110 and the common electrode line 311 via the via V1 increases the design freedom of each film layer.

[0137] Referring to Figure 6B, it is understood that Figure 6B only schematically shows that the common electrode 110 and the common electrode line 311 can be electrically connected through via V1, and does not limit the number of vias. For example, more vias can be provided to increase the current flow capacity.

[0138] Referring to Figure 6B, for example, via V1 can be a semi-via, meaning that on the substrate, a portion of the orthogonal projection of via V1 overlaps with the orthogonal projection of common electrode 110, and another portion overlaps with the orthogonal projection of common electrode line 311. The semi-via design facilitates the flow of polyimide (PI) liquid in subsequent processes (e.g., coating processes). For example, pixel electrode 120 can completely cover via V1 to prevent PI liquid from corroding via V1.

[0139] Figure 7 is a partial planar schematic diagram of an array substrate provided in one example of at least one embodiment of the present disclosure. Figures 8A and 8B are partially enlarged schematic diagrams of partial structures in the array substrates provided in different examples of at least one embodiment of the present disclosure.

[0140] For example, the array substrate shown in FIG. 7 differs from the array substrate shown in FIG. 2 in that the common electrode shown in FIG. 7 is different from the common electrode shown in FIG. 2, and the common electrode line shown in FIG. 7 is different from the common electrode line shown in FIG. 2. However, this disclosure is not limited thereto, and the array substrate shown in FIG. 7 and the array substrate shown in FIG. 2 may have many more differences.

[0141] For example, the common electrode of the virtual sub-pixel shown in FIG8A can be the same as the common electrode of the virtual sub-pixel shown in FIG7. However, this disclosure is not limited thereto, and the common electrode of the virtual sub-pixel shown in FIG8B can also be applied to the array substrate shown in FIG5.

[0142] Referring to Figures 7 and 8A, the array substrate includes a substrate 10, a plurality of sub-pixels 100, and a common electrode line 300. The substrate 10 includes a display area 11 and a non-display area 12, with the non-display area 12 located at least on one side of the display area 11 in a first direction X. Each sub-pixel 100 includes a common electrode 110 and a pixel electrode 120. The plurality of sub-pixels 100 includes display sub-pixels 101 and virtual sub-pixels 102, with at least a portion of the display sub-pixels 101 located in the display area 11 and the virtual sub-pixels 102 located in the non-display area 12. The common electrode line 300 is located within the non-display area 12 and is electrically connected to the common electrode 110. For example, the substrate 10 and sub-pixels 100 can be described with reference to the relevant descriptions in Figures 1 to 5 above, and will not be repeated here.

[0143] Referring to Figures 7 and 8A, the array substrate further includes multiple data lines 400, located at least in the display area 11 of the substrate and electrically connected to the pixel electrode 120. The multiple data lines 400 are arranged along a first direction X. The common electrode line 300 includes a first signal line 310 extending along the first direction X and a second signal line 320 extending along a second direction Y. The second signal line 320 is located on the side of the common electrode 110 of the virtual sub-pixel 102 away from the common electrode 110 of the display sub-pixel 101. The first direction X and the second direction Y intersect.

[0144] Referring to Figures 7 and 8A, the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 onto the substrate 10 includes a first notch 111, and the orthographic projection of the common electrode 110 of the display sub-pixel 101 onto the substrate 10 includes a second notch 112. The area of ​​the first notch 111 is larger than the area of ​​the second notch 112. For example, the common electrode 110 of the virtual sub-pixel 102 may have a notch, and the common electrode of the display sub-pixel 101 may have a notch.

[0145] Referring to Figures 7 and 8A, in the array substrate provided in this embodiment, the common electrode 110 of the sub-pixel 100 may have a notch. When establishing an electrical connection between the pixel electrode 120 and the data line 400, the connection path between the pixel electrode 120 and the data line 400 is isolated from the common electrode 110 to prevent short circuits. Since the virtual sub-pixel 102 is not used for actual display, the pixel electrode 120 of the virtual sub-pixel 102 may not be electrically connected to the data line 400, thus allowing for more flexible design of the common electrode 110 of the virtual sub-pixel 102. By setting the area of ​​the first notch 111 to be larger than the area of ​​the second notch 112, the notch of the common electrode 110 of the virtual sub-pixel 102 can be used to provide more space for other structures used to establish electrical connections. This allows for an increase in the linewidth of the second signal line 320, improves the voltage uniformity of the common electrode 110, and reduces the area of ​​the non-display area 12, facilitating narrowing of the bezel.

[0146] Referring to Figures 7 and 8A, in some examples, the display sub-pixel 101 further includes at least one thin-film transistor T. The array substrate also includes multiple gate lines 500, which are located at least in the display area 11 of the substrate 10 and arranged along the second direction Y. The array substrate also includes a conductive connection portion 600 and a gate driving circuit 700 located in the non-display area 12, with the conductive connection portion 600 electrically connected between the gate lines 500 and the gate driving circuit 700. At least a portion of the orthographic projection of the conductive connection portion 600 onto the substrate 10 is located at a first notch 111. The thin-film transistor T includes a first electrode T01 connected to the data line 400, a gate electrode T03 connected to the gate line 500, and a second electrode T02 connected to the pixel electrode 120, with the second electrode T02 located at a second notch 112. Thus, the thin-film transistor T of the display sub-pixel 101 can realize the electrical connection between the pixel electrode 120 and the data line 400. Meanwhile, since the common electrode 110 of the virtual sub-pixel 102 can be provided with a larger notch, it can provide arrangement space for the conductive connection portion 600 and reduce the size of the non-display area 12 in the first direction X.

[0147] Referring to Figures 7 and 8A, for example, the first electrode T01 is the source electrode, and the second electrode T02 is the drain electrode. For example, the second electrode T02 can be connected to the pixel electrode 120 through a via.

[0148] Referring to Figure 7, for example, the area of ​​the orthographic projection of the conductive connection portion 600 onto the substrate 10 is larger than the area of ​​the orthographic projection of the second electrode T02 of the thin-film transistor T onto the substrate 10. Therefore, the area of ​​the first notch 111 can be set to be larger than the area of ​​the second notch 112. This allows for efficient use of the arrangement space on the substrate 10, which is beneficial for increasing the aperture ratio while narrowing the bezel.

[0149] For example, referring to FIG2, when the conductive connection portion 600 is disposed between the second signal line 320 and the virtual sub-pixel 102, the distance between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 in the first direction X is 50 micrometers or more. Referring to FIG7, when the first notch 111 is provided, the conductive connection portion 600 can be closer to the display sub-pixel 101, and the distance between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 in the first direction X can be less than 50 micrometers.

[0150] For example, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction can be 6 micrometers to 50 micrometers. For example, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction can be 7 micrometers to 40 micrometers. For example, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction can be 8 micrometers to 30 micrometers. For example, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction can be 9 micrometers to 20 micrometers. For example, the spacing between the second signal line and the common electrode of the virtual sub-pixel in the first direction can be 10 micrometers to 15 micrometers.

[0151] For example, referring to Figures 7 and 8A, the orthographic projection of the conductive connection 600 onto the substrate 10 in the first direction X is larger than the orthographic projection of the second electrode T02 onto the substrate 10 in the first direction X. Therefore, the size of the first notch 111 in the first direction X can be set to be larger than the size of the second notch 112 in the first direction X. Similarly, the orthographic projection of the conductive connection 600 onto the substrate 10 in the second direction Y is larger than the orthographic projection of the second electrode T02 onto the substrate 10 in the second direction Y. Therefore, the size of the first notch 111 in the second direction Y can be set to be larger than the size of the second notch 112 in the second direction Y. It is understood that this disclosure does not impose any limitations on the arrangement of the conductive connection and the second electrode, as long as it is beneficial to the arrangement of the conductive connection and the second electrode.

[0152] For example, referring to FIG7, the array substrate may also include structures such as a common connection line 200 and a power line VGL. For example, the common connection line 200 can be referred to the relevant description of the common connection line 200 in FIG1 to FIG5 above. For example, the orthographic projection of the power line VGL on the substrate may be located between the second signal line 320 and the gate driving circuit 700. For example, the power line VGL may be used to provide the gate voltage. Specifically, the power line VGL may be electrically connected to the drain of the thin-film transistor in the gate driving circuit 700. When the gate signal is turned off in the display area, the noise reduction signal turns on the gate of the thin-film transistor in the gate driving circuit 700, which is equivalent to the gate of the thin-film transistor in the display area being directly connected to the power line VGL, thereby the gate voltage is provided by the power line VGL.

[0153] The difference between the array substrate shown in Figure 7 and the array substrate shown in Figure 2 is that the virtual sub-pixels in the array substrate shown in Figure 2 are different from the virtual sub-pixels in the array substrate shown in Figure 7, and the relative positional relationship between the conductive connection and other structures in the array substrate shown in Figure 2 is different from the relative positional relationship between the conductive connection and other structures in the array substrate shown in Figure 7.

[0154] Referring to Figure 7, among the virtual sub-pixel 102 and the display sub-pixel 101, only the display sub-pixel 101 includes a thin-film transistor T. For example, the virtual sub-pixel 102 does not include a thin-film transistor. It can be understood that since the virtual sub-pixel 102 is not used for display, the thin-film transistor in the virtual sub-pixel 102 can be removed, providing more arrangement space for other structures (such as the conductive connection portion 600). Compared to Figure 2, the array substrate shown in Figure 7 changes the position of the conductive connection portion 600, thereby reducing the spacing between the second signal line 320 and the virtual sub-pixel 102 in the first direction X, and reducing the size of the non-display area 12 in the first direction X.

[0155] Referring to Figures 7 and 8A, in some examples, the spacing in the first direction X between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 is a tenth dimension D10, and the spacing in the first direction X between the data line 400 and the common electrode 110 of the adjacent display sub-pixel 101 is an eleventh dimension D11. The ratio of the tenth dimension D10 to the eleventh dimension D11 is 0.9-1.1, so that the relative positional relationship between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 tends to be consistent with the relative positional relationship between the data line 400 and the common electrode 110 of the display sub-pixel 101, which can improve voltage uniformity.

[0156] For example, referring to Figures 7 and 8A, "adjacent to the common electrode 101 of the data line 400 and the display sub-pixel 101" means that there are no other structures between the data line 400 and the common electrode 101 of the display sub-pixel 101 in the first direction X.

[0157] For example, the ratio of the tenth dimension to the eleventh dimension can be 0.91-1.09. For example, the ratio of the tenth dimension to the eleventh dimension can be 0.95-1.05. For example, the ratio of the tenth dimension to the eleventh dimension can be 1.

[0158] Referring to FIG8A, in some examples, the common electrode 110 of the virtual sub-pixel 102 includes a first electrode portion 1101 and a second electrode portion 1102, wherein the second electrode portion 1102 is closer to the second signal line 320 than the first electrode portion 1101. The common electrode 110 of the display sub-pixel 101 includes a third electrode portion 1103 and a fourth electrode portion 1104, wherein the fourth electrode portion 1104 is closer to the second signal line 320 than the third electrode portion 1103.

[0159] Referring to Figure 8A, the maximum dimension of the second electrode portion 1102 in the second direction Y is the twelfth dimension D12, and the maximum dimension of the first electrode portion 1101 in the second direction Y is the thirteenth dimension D13. The twelfth dimension D12 is smaller than the thirteenth dimension D13, so that the orthogonal projection of the common electrode 110 of the virtual sub-pixel 102 onto the substrate 10 can form the first notch 111.

[0160] Referring to Figure 8A, the maximum dimension of the fourth electrode portion 1104 in the second direction Y is the fourteenth dimension D14, and the maximum dimension of the third electrode portion 1103 in the second direction Y is the fifteenth dimension D15. The fourteenth dimension D14 is smaller than the fifteenth dimension D15, thereby displaying that the orthogonal projection of the common electrode 110 of the sub-pixel 101 onto the substrate 10 can form the second notch 112.

[0161] Referring to Figure 8A, the twelfth dimension D12 is different from the fourteenth dimension D14, so the dimensions of the first notch 111 and the second notch 112 can be different, which is beneficial to realize the avoidance of the common electrode 110 of the virtual sub-pixel 102 from the conductive connection portion 600.

[0162] Referring to FIG8A, for example, on the substrate 10, the orthographic projection of the second electrode portion 1102 on the side edge away from the first signal line 310 in the second direction Y can form one edge of the first notch 111, and the orthographic projection of the first electrode portion 1101 on the side edge near the second signal line 320 in the first direction X can form another edge of the first notch 111. On the substrate 10, the orthographic projection of the fourth electrode portion 1104 on the side edge away from the first signal line 310 in the second direction Y can form one edge of the second notch 111, and the orthographic projection of the third electrode portion 1103 on the side edge near the second signal line 320 in the first direction X can form another edge of the second notch 112.

[0163] Referring to Figure 8A, in some examples, the ratio of the thirteenth dimension D13 to the fifteenth dimension D15 is 0.9-1.1, and the twelfth dimension D12 is smaller than the fourteenth dimension D14. The maximum dimension of the second electrode portion 1102 in the first direction X is the sixteenth dimension D16, and the maximum dimension of the common electrode 110 of the display sub-pixel 101 in the first direction X is the seventeenth dimension D17. The ratio of the sixteenth dimension D16 to the seventeenth dimension D17 is not greater than 2 / 3. By setting the above-mentioned dimensional relationships, the common electrode 110 of the virtual sub-pixel 102 can avoid the conductive connection portion 600 while making the structure of the first electrode portion 1101 and the structure of the third electrode portion 1103 more consistent, thereby making the loads such as parasitic capacitances of different data lines 400 more consistent.

[0164] Specifically, referring to Figure 8A, data line 401 is located between virtual sub-pixel 102 and display sub-pixel 101, and data line 402 is located between two adjacent display sub-pixels 101. The first electrode portion 1101 located on the left side of data line 401 (i.e., the side closer to the second signal line 320) is substantially the same as the third electrode portion 1103 located on the left side of data line 402, and the common electrode 110 of all display sub-pixels 101 is substantially the same. Therefore, the common electrode patterns on both sides of data line 401 and data line 402 are substantially the same, and the loads of data line 401 and data line 402 are substantially the same.

[0165] Specifically, referring to FIG8A, the maximum size of the first electrode portion 1101 in the second direction Y and the maximum size of the third electrode portion 1103 in the second direction Y tend to be consistent, and the ratio of the maximum size of the first electrode portion 1101 in the first direction X to the maximum size of the common electrode 110 of the display sub-pixel 101 in the first direction X is more than 1 / 3. As a result, the length of the first electrode portion 1101 and the length and width of the third electrode portion 1103 tend to be consistent. The load of the data line 400 located between the first electrode portion 1101 and the fourth electrode portion 1104 tends to be consistent with the load of the data line 400 located between the common electrode 110 of two adjacent display sub-pixels 101, thereby improving voltage uniformity.

[0166] For example, the ratio of the thirteenth dimension to the fifteenth dimension can be 0.91-1.09. For example, the ratio of the thirteenth dimension to the fifteenth dimension can be 0.95-1.05. For example, the ratio of the thirteenth dimension to the fifteenth dimension can be 1.

[0167] For example, the seventeenth dimension D17 shown in Figure 8A can be the same as the ninth dimension D9 shown in Figure 5 above.

[0168] For example, the ratio of the sixteenth dimension to the seventeenth dimension can be 1 / 10 to 2 / 3. For example, the ratio of the sixteenth dimension to the seventeenth dimension can be 1 / 6 to 3 / 5. For example, the ratio of the sixteenth dimension to the seventeenth dimension can be 1 / 5 to 1 / 2. For example, the ratio of the sixteenth dimension to the seventeenth dimension can be 1 / 3 to 2 / 5. However, this disclosure is not limited to the above values, and the ratios can also be other values, which will not be listed here.

[0169] Referring to Figures 7 and 8A, in some examples, the straight line LN1 extending along the first direction X passes through the orthographic projection of the first electrode portion 1101 on the substrate 10 and the orthographic projection of the conductive connection portion 600 on the substrate 10. This allows full utilization of the clearance space of the first notch 111, which is beneficial for the arrangement of structures such as the sub-pixel 100, the conductive connection portion 600, and the gate line 500 on the substrate 10.

[0170] It is understood that the straight line LN1 mentioned above, as well as the straight lines LN2 and LN3 mentioned in the examples below, are all straight lines shown for ease of understanding and do not represent the actual structure in the display substrate. This disclosure will not be repeated hereafter.

[0171] Referring to Figure 8B, in some examples, the common electrode 110 of the sub-pixel 101 includes a third electrode portion 1103 and a fourth electrode portion 1104, with the fourth electrode portion 1104 being closer to the second signal line 120 than the third electrode portion 1103. The maximum dimension of the common electrode 110 of the virtual sub-pixel 102 in the second direction Y is the eighteenth dimension D18, and the maximum dimension of the fourth electrode portion 1104 in the second direction Y is the fourteenth dimension D14, where the eighteenth dimension D18 is smaller than the fourteenth dimension D14. The straight line LN2 extending along the first direction X does not pass through the orthographic projection of the conductive connection portion 600 on the substrate 10 and the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 on the substrate 10, allowing the conductive connection portion 600 to have a larger arrangement space and more flexible positioning.

[0172] Referring to Figure 8B, the common electrode 110 of the virtual sub-pixel 102 can be approximately rectangular in shape, meaning that the maximum dimension (i.e., the eighteenth dimension D18) of the common electrode 110 of the virtual sub-pixel 102 in the second direction Y is basically the same everywhere. In this case, it can be considered that the length of the common electrode 110 of the virtual sub-pixel 102 is shortened to less than the fourteenth dimension D14, thereby simplifying the manufacturing method of the common electrode 110 of the virtual sub-pixel 102 while avoiding the conductive connection portion 600.

[0173] For example, the eighteenth dimension D18 shown in Figure 8B can be the same as the twelfth dimension D12 shown in Figure 8A.

[0174] The difference between the array substrate shown in Figure 7 and the array substrate shown in Figure 2 is that the relative positional relationship of the second signal line, data line and virtual sub-pixel in the array substrate shown in Figure 2 is different from that in the array substrate shown in Figure 7.

[0175] Referring to Figures 7 to 8B, in some examples, the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 onto the substrate 10 is located between the orthographic projection of the second signal line 320 onto the substrate 10 and the orthographic projection of the data line 400 onto the substrate 10, thereby making the spacing between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 smaller, which makes it easier to reduce the size of the non-display area 12 in the first direction X.

[0176] In the array substrate shown in Figure 2, a data line 400 is provided between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102. In the array substrate shown in Figure 7, no data line 400 is provided between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102. That is, the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 on the substrate 10 is adjacent to the orthographic projection of the second signal line 320 on the substrate 10, and there are no other structures orthographic projections on the substrate between them. Since the virtual sub-pixel 102 is not used for display, removing the data line 400 between the second signal line 320 and the common electrode 110 of the virtual sub-pixel 102 will have virtually no impact on the display effect and is beneficial for achieving a narrow bezel.

[0177] Figure 9 is a partial planar schematic diagram of an array substrate provided in one example of at least one embodiment of the present disclosure. Figures 10A and 10B are partially enlarged schematic diagrams of partial structures in the array substrates provided in different examples of at least one embodiment of the present disclosure.

[0178] For example, the difference between the array substrate shown in FIG. 9 and the array substrate shown in FIG. 7 is that the common electrode shown in FIG. 9 is different from the common electrode shown in FIG. 7, and the common electrode line shown in FIG. 9 is different from the common electrode line shown in FIG. 7. For example, the common electrode of the virtual sub-pixel shown in FIG. 10A can be the same as the common electrode of the virtual sub-pixel shown in FIG. 9, and the common electrode line shown in FIG. 10A can be the same as the common electrode line shown in FIG. 9. However, this disclosure is not limited thereto, and the common electrode and common electrode line of the virtual sub-pixel shown in FIG. 10B can also be applied to the array substrate shown in FIG. 9.

[0179] Referring to Figures 9 and 10A, in some examples, the second signal line 320 includes a trace body portion 3201 and a second connecting portion 3202. The dashed boxes in Figures 10A and 10B schematically delineate the portions of the second signal line 320 containing the trace body portion 3201 and the second connecting portion 3202. The trace body portion 3201 extends along the second direction Y, and the second connecting portion 3202 is connected to the side of the trace body portion 3201 in the first direction X near the display area 11. The second connecting portion 3202 is electrically connected to the common electrode 110 of the virtual sub-pixel 102. The maximum size of the common electrode 110 of the virtual sub-pixel 102 in the first direction X is the nineteenth dimension D19, and the maximum size of the common electrode 110 of the display sub-pixel 101 in the first direction X is the seventeenth dimension D17. The nineteenth dimension D19 is smaller than the seventeenth dimension D17.

[0180] Referring to Figures 9 and 10A, while narrowing the common electrode 110 of the virtual sub-pixel 102, a second connection portion 3202 is provided. The first notch 111 can be formed by the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 onto the substrate 10 and the orthographic projection of the second connection portion 3202 onto the substrate 10, thus avoiding the conductive connection portion 600. Simultaneously, the second connection portion 3202 is far from the data line 400, therefore the coupling voltage between the second connection portion 3202 and the data line 400 is negligible, and providing the second connection portion 3202 and narrowing the common electrode 110 of the virtual sub-pixel 102 does not significantly change the load on the data line 400. Therefore, providing the second connection portion 3202 can widen the linewidth of the second signal line 320, significantly reducing the voltage drop across the common electrode, enhancing the uniformity of the connection of the common electrode 110, and having virtually no impact on the display effect. Furthermore, the second connecting portion 3202 is positioned close to the display area 11 relative to the main wiring portion 3202, so it does not increase the size of the non-display area 12 in the first direction X, which is beneficial for narrowing the bezel.

[0181] Referring to Figures 9 and 10A, for example, on the substrate 10, the orthographic projection of the second connection portion 3202 on the side edge away from the first signal line 310 in the second direction Y can form one edge of the first notch 111, and the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 on the side edge away from the data line 400 in the first direction X can form another edge of the first notch 111.

[0182] Referring to Figures 9 and 10A, for example, the orthographic projection of the second connection portion 3202 on the substrate 10 may be located between the orthographic projection of the trace connection portion 3201 on the substrate 10 and the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 on the substrate 10.

[0183] Referring to Figures 9 and 10A, for example, the main wiring portion 3201 and the second connecting portion 3202 can be an integrally formed structure.

[0184] For example, referring to Figure 10A, the ratio of the nineteenth dimension D19 to the seventeenth dimension D17 is not less than 1 / 3, so that the structure of the virtual sub-pixel 102 is consistent with the structure of the display sub-pixel 101, thereby making the loads of different data lines 400, such as parasitic capacitance, consistent.

[0185] For example, the ratio of the nineteenth dimension to the seventeenth dimension can be 1 / 3 to 2 / 3. For example, the ratio of the nineteenth dimension to the seventeenth dimension can be 4 / 9 to 5 / 8. For example, the ratio of the nineteenth dimension to the seventeenth dimension can be 1 / 2 to 5 / 12. However, this disclosure is not limited to the above values, and the above ratios can also be other values, which will not be listed here.

[0186] Referring to Figures 9 and 10A, in some examples, the straight line LN3 extending along the second direction Y passes through the orthographic projection of the second connection portion 3202 on the substrate 10 and the orthographic projection of the conductive connection portion 600 on the substrate 10. Therefore, by setting the maximum dimension of the second connection portion 3202 in the second direction Y, the conductive connection portion 600 can be avoided.

[0187] For example, if a straight line extending in the second direction passes through the orthographic projection of the second connection portion on the substrate and the orthographic projection of the conductive connection portion on the substrate, another straight line extending in the second direction may also pass through the orthographic projection of the common electrode of the virtual sub-pixel on the substrate and the orthographic projection of the conductive connection portion on the substrate. For example, in the second direction, while the orthographic projections of the second connection portion and the conductive connection portion on the substrate are opposite each other, the orthographic projections of the common electrode of the virtual sub-pixel on the substrate and the conductive connection portion on the substrate may also be opposite each other.

[0188] For example, the shape of the common electrode of the virtual sub-pixel can be as shown in Figure 10A, which is rectangular in shape. However, this disclosure is not limited to this; the shape of the common electrode of the virtual sub-pixel can also be irregular, as shown in Figure 8A.

[0189] For example, FIG10A schematically shows that the maximum size of the common electrode 110 of the virtual sub-pixel 102 in the second direction Y is greater than the maximum size of the second connection portion 3202 in the second direction Y. However, this disclosure is not limited thereto; for example, the maximum size of the common electrode of the virtual sub-pixel in the second direction may also be the same as the maximum size of the second connection portion in the second direction.

[0190] It is understood that as long as the second connecting part and the common electrode of the virtual sub-pixel can jointly avoid the conductive connecting part, and at the same time it is beneficial to simplify the manufacturing process of the second connecting part and the common electrode of the virtual sub-pixel, this disclosure does not impose any restrictions on the shape of the second connecting part and the common electrode of the virtual sub-pixel, or the relative positional relationship between the conductive connecting part and the common electrode of the virtual sub-pixel.

[0191] Referring to Figures 9 and 10A, in some examples, the second connection portion 3202 is disposed in the same layer as the common electrode 110 of the virtual sub-pixel 102, and the material of the second connection portion 3202 is different from the material of the common electrode 110 of the virtual sub-pixel 102, so as to simplify the manufacturing process.

[0192] For example, the second connection portion is directly connected to the common electrode of the virtual sub-pixel. For example, the material of the common electrode of the virtual sub-pixel may include indium tin oxide (ITO). For example, the material of the second connection portion may include a metal material such as aluminum or copper.

[0193] Referring to Figure 10B, the second connecting portion 3202 and the common electrode 110 of the virtual sub-pixel 102 are disposed in different layers, and the second connecting portion 3202 and the common electrode 110 of the virtual sub-pixel 102 are electrically connected through a via V2. The electrical connection between the second connecting portion 3202 and the common electrode 110 of the virtual sub-pixel 102 via the via V2 increases the design freedom of each film layer.

[0194] It is understood that Figure 10B only schematically illustrates that the common electrode 110 of the second connection portion 3202 and the virtual sub-pixel 102 can be electrically connected through via V2. However, this disclosure does not limit the number of vias V2, etc. For example, the arrangement of vias V2 can refer to the arrangement of vias V1 in Figure 6B above, and will not be repeated here.

[0195] Referring to FIG9, in some examples, the orthographic projection of the pixel electrode 120 of the virtual sub-pixel 102 on the substrate 10 overlaps with the orthographic projection of the common electrode 110 of the virtual sub-pixel 102 on the substrate 10, and also overlaps with the orthographic projection of the second connection portion 3202 on the substrate 10, so as to improve the structural consistency between the virtual sub-pixel 102 and the common sub-pixel 101.

[0196] Referring to FIG9, for example, in a direction perpendicular to the substrate 10, the pixel electrode 120 of the virtual sub-pixel 102 may cover the common electrode 110 of the virtual sub-pixel 102, and simultaneously cover the second connection portion 3202 of the second signal line 320. For example, the structure of the pixel electrode 120 of the virtual sub-pixel 102 may be substantially the same as the structure of the pixel electrode 120 of the display sub-pixel 101.

[0197] Referring to FIG9, for example, the orthographic projection of the pixel electrode 120 of the virtual sub-pixel 102 on the substrate 10 does not overlap with the orthographic projection of the conductive connection portion 600 on the substrate 10, so as to avoid the conductive connection portion 600.

[0198] Figure 11 is a partial planar schematic diagram of an array substrate provided in at least one embodiment of the present disclosure.

[0199] For example, the difference between the array substrate shown in FIG11 and the array substrate shown in FIG9 is that the pixel electrode of the virtual sub-pixel shown in FIG11 is different from the pixel electrode of the virtual sub-pixel shown in FIG9. However, this disclosure is not limited thereto, and the array substrate shown in FIG7 and the array substrate shown in FIG2 may have many more differences.

[0200] Referring to Figures 1 and 11, the array substrate includes a substrate, a plurality of sub-pixels 100, and a common electrode line 300. The substrate includes a display area 11 and a non-display area 12, with the non-display area 12 located at least on one side of the display area 11 in a first direction X. Each sub-pixel 100 includes a common electrode 110 and a pixel electrode 120. The plurality of sub-pixels 100 includes display sub-pixels 101 and virtual sub-pixels 102, with at least a portion of the display sub-pixels 101 located in the display area 11 and the virtual sub-pixels 102 located in the non-display area 101. The common electrode line 300 is located within the non-display area 12 and is electrically connected to the common electrode 110. For example, the substrate 10 and the sub-pixels 100 can be referred to the relevant descriptions in Figures 1 to 5 above, which will not be repeated here.

[0201] Referring to Figure 11, the pixel electrode 120 of the virtual sub-pixel 102 includes a plurality of strip electrodes 121. Among the common electrode 110 and the second signal line 320, only the orthographic projection of the common electrode 110 on the substrate overlaps with the orthographic projection of the strip electrodes 121 on the substrate. The maximum size of the common electrode 110 of the virtual sub-pixel 102 in the first direction X is smaller than the maximum size of the common electrode 110 of the display sub-pixel 101 in the first direction X, and the maximum size of the pixel electrode 120 of the virtual sub-pixel 102 in the first direction X is smaller than the maximum size of the pixel electrode 120 of the display sub-pixel 101 in the first direction X. The first direction X intersects with the second direction Y.

[0202] Referring to Figure 11, in the array substrate provided in this embodiment, since the virtual sub-pixel 102 is not used for display, the structure of the virtual sub-pixel 102 can be adjusted to reduce the space occupied by the structure of the virtual sub-pixel 102. This reduces the overall size of the virtual sub-pixel 102 in the first direction X, thereby providing more space for the arrangement of other structures without significantly affecting the display effect. Consequently, the linewidth of the second signal line 320 can be increased, improving the voltage uniformity of the common electrode 110, and the area of ​​the non-display area 12 can be reduced, facilitating narrower bezels. While ensuring sufficient linewidth of the second signal line 320, more routing space can be compressed for sensor mounting design, which is beneficial for smart display.

[0203] It should also be noted that, referring to Figure 11, the pixel electrode 120 of the virtual sub-pixel 102 is a floating design. Changing the size and shape of the pixel electrode 120 of the virtual sub-pixel 102 will not affect the display, nor will it reduce the storage capacitance of the display sub-pixel 101, thus ensuring the display effect. In addition, the area of ​​the common electrode 110 of the virtual sub-pixel 102 matches that of the pixel electrode 120 of the virtual sub-pixel 102, resulting in a more uniform electric field distribution. This also helps to reduce unnecessary electric field losses and current leakage, improve response speed, and reduce parasitic capacitance and electromagnetic interference between the pixel electrode 120 and the common electrode 110.

[0204] Referring to FIG11, for example, the orthographic projection of the plurality of strip electrodes 121 on the substrate only overlaps with the orthographic projection of the common electrode 110 on the substrate, meaning that the orthographic projection of the plurality of strip electrodes 121 on the substrate does not overlap with the orthographic projection of the second signal line 320 on the substrate.

[0205] Referring to Figure 11, for example, the first direction X and the second direction Y can be perpendicular to each other.

[0206] Referring to FIG11, for example, the common electrode 110 of the virtual sub-pixel 102 may include a first portion 110A and a second portion 110B arranged in the second direction Y, wherein the first portion 110A is closer to the first signal line 310 than the second portion 110B. The maximum size of the common electrode 110 of the virtual sub-pixel 102 in the first direction X may be the size of the first portion 110A in the first direction X.

[0207] Referring to FIG11, for example, the pixel electrode 120 of the virtual sub-pixel 102 may include a third portion 120A and a fourth portion 120B arranged in the second direction Y, wherein the third portion 120A is closer to the first signal line 310 than the fourth portion 120B. The maximum size of the pixel electrode 120 of the virtual sub-pixel 102 in the first direction X may be the size of the third portion 120A in the first direction X.

[0208] It is understandable that the pixel electrode scheme for narrowing the virtual sub-pixel shown in Figure 11 can also be applied to the array substrate shown in Figure 5. That is, the size of the pixel electrode of the virtual sub-pixel shown in Figure 5 in the second direction can be reduced, such that it tends to be consistent with the size of the common electrode of the virtual sub-pixel shown in Figure 5 in the second direction.

[0209] It is understood that, apart from the pixel electrode of the virtual sub-pixel, the arrangement of other structures in the array substrate shown in FIG11 can be referred to the relevant descriptions in FIG9 to FIG10B. For example, referring to FIG11, the array substrate may also include a conductive connection portion 600, and the second signal line 320 shown in FIG11 may also include a trace body portion 3201 and a second connection portion 3202. The second connection portion 3202 may cooperate with the common electrode 110 of the virtual sub-pixel 102 to avoid the conductive connection portion 600.

[0210] It should be noted that Figures 2, 5, 7, 9, and 11 schematically show a partial structure of the upper left corner of the array substrate, and schematically show that the conductive connection portion 600 and the gate driving circuit 700 are located on the left side of the figure. When the array substrate is a single-sided driven array substrate, the conductive connection portion and the gate driving circuit can be provided only on one side of the display area in the first direction, thus allowing the structure shown in Figures 7 to 11 to be provided only on one side of the array substrate. When the array substrate is a double-sided driven array substrate, the conductive connection portion and the gate driving circuit can be provided on both opposite sides of the display area in the second direction, thus allowing the structure shown in Figures 7 to 11 to be provided on both sides of the array substrate, with the structure on the right side symmetrically arranged with the structure on the left side.

[0211] It is understood that in the array substrates shown in Figures 2, 5, 7, 9, and 11, the structural arrangement of the common electrode lines, the position arrangement of the conductive connection parts, and the structural arrangement of the common electrode and pixel electrode in the virtual sub-pixel can all be combined with each other, and this disclosure does not impose any restrictions on them.

[0212] This disclosure also provides a display device, including the array substrate and the opposing substrate as described in the above embodiments, wherein the opposing substrate is disposed opposite to the array substrate. Since the display device according to the embodiments of this disclosure includes the aforementioned array substrate, it also has corresponding beneficial technical effects, such as increasing the linewidth of the common electrode lines, improving the voltage uniformity of the common electrodes, and reducing the area of ​​the non-display area, which facilitates narrowing the bezel; these will not be elaborated further here.

[0213] In some examples, one of the array substrate and the opposing substrate is provided with a black matrix layer. The black matrix layer is configured to at least cover the common electrode lines, common connection lines, and the common electrodes of the virtual sub-pixels. In this way, the traces such as the common electrode lines and common connection lines can be blocked by the black matrix layer, and the non-emitting virtual sub-pixels can also be blocked by the black matrix layer, which is beneficial to improving the display effect.

[0214] For example, the relative positional relationship between the black matrix layer and other structures in the array substrate in the display device can be referred to the relevant description in the display device shown in Figure 4. The array substrates shown in Figures 5, 7, 9, and 11 can all be matched with the black matrix layer shown in Figure 4, and this disclosure will not elaborate further. It can be understood that since the array substrates shown in Figures 2, 5, 7, 9, and 11 are all adjustments to the structure located in the non-display area, that is, adjustments to the structure of the area covered by the black matrix layer, the display effect of the display area will not be affected.

[0215] For example, the display device can be a liquid crystal display device.

[0216] For example, the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0217] The following points need to be explained:

[0218] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0219] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0220] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: A substrate includes a display area and a non-display area, wherein the non-display area is located on at least one side of the display area; Multiple sub-pixels are located on the substrate, and each sub-pixel includes a common electrode; the multiple sub-pixels include display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels are located in the display area, and the virtual sub-pixels are located in the non-display area; A common connection line is located at least partially within the display area and is electrically connected to at least the common electrode of the display sub-pixel; The common electrode line is located within the non-display area and is electrically connected to the common connection line; The common connection line extends along a first direction, and the common electrode line includes a first signal line extending along the first direction and a second signal line extending along a second direction. A portion of the first signal line is electrically connected to the common electrode of the virtual sub-pixel, and another portion of the first signal line is electrically connected to the common electrode of the display sub-pixel. The maximum dimension of at least a portion of the first signal line in the second direction is a first dimension, the maximum dimension of the common connection line in the second direction is a second dimension, the ratio of the first dimension to the second dimension is 4 to 30, and the first direction intersects the second direction.

2. The array substrate according to claim 1, wherein, The first signal line includes a first trace and a trace attachment structure, the first trace extending along the first direction, and the trace attachment structure connected to at least one side of the first trace in the second direction.

3. The array substrate according to claim 2, wherein, The maximum dimension of the first trace in the second direction is the third dimension, and the ratio of the third dimension to the second dimension is 0.9-1.

1.

4. The array substrate according to claim 3, wherein, The additional wiring structure includes a second wiring and a first connection portion, wherein the second wiring extends along the first direction and the first connection portion is located at least between the first wiring and the second wiring; The second trace is located on the side of the first trace away from the display area, and the maximum dimension of the second trace in the second direction is the fourth dimension, which is not less than the third dimension.

5. The array substrate according to claim 4, wherein, The portion between the first trace and the second trace, excluding the first connection portion, includes a gap; The array substrate further includes multiple data lines, each data line being electrically connected to the pixel electrode of the sub-pixel. The multiple data lines are arranged along the first direction, and at least one data line overlaps with the spacing in a direction perpendicular to the substrate.

6. The array substrate according to claim 2 or 3, wherein, The plurality of sub-pixels are arranged in an array along the first direction and the second direction; The plurality of sub-pixels are divided into multiple rows of sub-pixel rows arranged along the second direction, each row of sub-pixel rows extending along the first direction, and the sub-pixel row closest to the first signal line in the multiple rows of sub-pixel rows is the first row of sub-pixel rows. The first row of subpixels includes a plurality of display subpixels and at least one virtual subpixel, the plurality of display subpixels being arranged along the first direction, and the at least one virtual subpixel being located on at least one side of the plurality of display subpixels in the first direction; The additional wiring structure is electrically connected between the first wiring and the common electrode of the sub-pixels of the first row of sub-pixels.

7. The array substrate according to claim 6, wherein, The sub-pixel includes a pixel region, and the ratio of the area of ​​the orthographic projection of the wiring attachment structure on the substrate to the area of ​​the pixel region is no greater than 3 / 4.

8. The array substrate according to claim 6 or 7, wherein, The maximum size of the common electrode of the sub-pixels in the first row of sub-pixels in the second direction is the fifth size; In the multi-row sub-pixel rows other than the first row, the maximum size of the common electrode of the sub-pixels in at least one sub-pixel row in the second direction is the sixth size; The ratio of the fifth dimension to the sixth dimension is not less than 0.5 and less than 1.

9. The array substrate according to any one of claims 6-8, wherein, In the multi-row sub-pixel rows other than the first row, the maximum size of the common electrode of the sub-pixels in at least one sub-pixel row in the second direction is the sixth size; The maximum dimension of the additional wiring structure in the second direction is the seventh dimension; The ratio of the sum of the fifth dimension and the seventh dimension to the sixth dimension is 0.9-1.

1.

10. The array substrate according to any one of claims 6-9, wherein, The maximum dimension of the additional wiring structure in the first direction is the eighth dimension; The maximum size of the common electrode of the sub-pixels in the first row of sub-pixels in the first direction is the ninth size; The ratio of the eighth dimension to the ninth dimension is 0.9-1.

1.

11. The array substrate according to any one of claims 1-10, wherein, The non-display area includes a first peripheral area, a second peripheral area, and a binding area. The binding area is located on one side of the display area in the second direction. The first peripheral area is located between the binding area and the display area. The second peripheral area is located on at least one side of the display area in the first direction. The first signal line is located in the first peripheral area, and the second signal line is located in the second peripheral area.

12. The array substrate according to claim 11, wherein, The common electrode is disposed in the same layer as the common electrode line, and the material of the common electrode is different from the material of the common electrode line; or The common electrode and the common electrode line are disposed in different layers, and the common electrode and the common electrode line are electrically connected through vias.

13. An array substrate, comprising: A substrate includes a display area and a non-display area, wherein the non-display area is located at least on one side of the display area in a first direction; Multiple sub-pixels, each sub-pixel including a common electrode and a pixel electrode; the multiple sub-pixels include display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels is located in the display area, and the virtual sub-pixels are located in the non-display area; A common electrode line is located within the non-display area and is electrically connected to the common electrode; Multiple data lines are located at least in the display area of ​​the substrate and electrically connected to the pixel electrode, and the multiple data lines are arranged along the first direction; The common electrode line includes a first signal line extending along the first direction and a second signal line extending along the second direction, wherein the second signal line is located on the side of the common electrode of the virtual sub-pixel away from the common electrode of the display sub-pixel; the first direction intersects the second direction; The orthographic projection of the common electrode of the virtual sub-pixel onto the substrate includes a first notch, and the orthographic projection of the common electrode of the display sub-pixel onto the substrate includes a second notch, wherein the area of ​​the first notch is larger than the area of ​​the second notch.

14. The array substrate according to claim 13, wherein, The display sub-pixel also includes at least one thin-film transistor; The array substrate further includes multiple gate lines, which are located at least in the display area of ​​the substrate and arranged along the second direction; The array substrate further includes a conductive connection portion and a gate driving circuit located in the non-display area, wherein the conductive connection portion is electrically connected between the gate line and the gate driving circuit; At least a portion of the orthographic projection of the conductive connection portion on the substrate is located in the first notch, and the thin-film transistor includes a first electrode connected to the data line, a gate electrode connected to the gate line, and a second electrode connected to the pixel electrode, wherein the second electrode is located in the second notch.

15. The array substrate according to claim 14, wherein, The distance between the second signal line and the common electrode of the virtual sub-pixel in the first direction is the tenth dimension, and the distance between the data line and the common electrode of the adjacent display sub-pixel in the first direction is the eleventh dimension. The ratio of the tenth dimension to the eleventh dimension is 0.9-1.

1.

16. The array substrate according to claim 15, wherein, The common electrode of the virtual sub-pixel includes a first electrode portion and a second electrode portion, wherein the second electrode portion is closer to the second signal line than the first electrode portion; the common electrode of the display sub-pixel includes a third electrode portion and a fourth electrode portion, wherein the fourth electrode portion is closer to the second signal line than the third electrode portion. The maximum dimension of the second electrode portion in the second direction is the twelfth dimension, and the maximum dimension of the first electrode portion in the second direction is the thirteenth dimension, wherein the twelfth dimension is smaller than the thirteenth dimension; The maximum dimension of the fourth electrode portion in the second direction is the fourteenth dimension, and the maximum dimension of the third electrode portion in the second direction is the fifteenth dimension, wherein the fourteenth dimension is smaller than the fifteenth dimension; The twelfth dimension is different from the fourteenth dimension.

17. The array substrate according to claim 16, wherein, The ratio of the thirteenth dimension to the fifteenth dimension is 0.9-1.1, and the twelfth dimension is smaller than the fourteenth dimension; The maximum size of the second electrode portion in the first direction is the sixteenth size, and the maximum size of the common electrode of the display sub-pixel in the first direction is the seventeenth size, and the ratio of the sixteenth size to the seventeenth size is not greater than 2 / 3.

18. The array substrate according to claim 16 or 17, wherein, A straight line extending along the first direction passes through the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the conductive connection portion on the substrate.

19. The array substrate according to claim 15, wherein, The common electrode of the display sub-pixel includes a third electrode portion and a fourth electrode portion, wherein the fourth electrode portion is closer to the second signal line than the third electrode portion; The maximum size of the common electrode of the virtual sub-pixel in the second direction is the eighteenth size, and the maximum size of the fourth electrode portion in the second direction is the fourteenth size, wherein the eighteenth size is smaller than the fourteenth size; A straight line extending along the first direction does not pass through the orthographic projection of the conductive connection portion on the substrate and the orthographic projection of the common electrode of the virtual sub-pixel on the substrate.

20. The array substrate according to any one of claims 13-19, wherein, The orthographic projection of the common electrode of the virtual sub-pixel on the substrate is located between the orthographic projection of the second signal line on the substrate and the orthographic projection of the data line on the substrate.

21. The array substrate according to claim 14, wherein, The second signal line includes a trace body and a second connecting part. The trace body extends along the second direction, and the second connecting part is connected to the side of the trace body that is closer to the display area in the first direction. The second connecting portion is electrically connected to the common electrode of the virtual sub-pixel. The maximum size of the common electrode of the virtual sub-pixel in the first direction is the nineteenth size, and the maximum size of the common electrode of the display sub-pixel in the first direction is the seventeenth size; the nineteenth size is smaller than the seventeenth size.

22. The array substrate according to claim 21, wherein, A straight line extending along the second direction passes through the orthographic projection of the second connection portion on the substrate and the orthographic projection of the conductive connection portion on the substrate.

23. The array substrate according to claim 21 or 22, wherein, The second connecting portion is disposed on the same layer as the common electrode of the virtual sub-pixel, and the material of the second connecting portion is different from the material of the common electrode of the virtual sub-pixel; or The second connecting portion is disposed on a different layer from the common electrode of the virtual sub-pixel, and the second connecting portion is electrically connected to the common electrode of the virtual sub-pixel through a via.

24. The array substrate according to any one of claims 21-23, wherein, The orthographic projection of the pixel electrode of the virtual sub-pixel on the substrate overlaps with the orthographic projection of the common electrode of the virtual sub-pixel on the substrate, and also overlaps with the orthographic projection of the second connection portion on the substrate.

25. An array substrate, comprising: A substrate includes a display area and a non-display area, wherein the non-display area is located at least on one side of the display area in a first direction; Multiple sub-pixels, each sub-pixel including a common electrode and a pixel electrode; the multiple sub-pixels include display sub-pixels and virtual sub-pixels, at least a portion of the display sub-pixels is located in the display area, and the virtual sub-pixels are located in the non-display area; A common electrode line is located within the non-display area and is electrically connected to the common electrode; The pixel electrode of the virtual sub-pixel includes a plurality of strip electrodes; the common electrode line includes a first signal line extending along the first direction and a second signal line extending along the second direction, wherein only the orthographic projection of the common electrode on the substrate overlaps with the orthographic projection of the strip electrode on the substrate. The maximum size of the common electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the common electrode of the display sub-pixel in the first direction, and the maximum size of the pixel electrode of the virtual sub-pixel in the first direction is smaller than the maximum size of the pixel electrode of the display sub-pixel in the first direction; the first direction intersects with the second direction.

26. The array substrate according to any one of claims 13-25, wherein, Of the virtual sub-pixels and the display sub-pixels, only the display sub-pixels include thin-film transistors.

27. A display device, comprising: Array substrate according to any one of claims 1-26; The opposing substrate is disposed opposite to the array substrate.

28. The display device according to claim 27, wherein, One of the array substrate and the opposing substrate is provided with a black matrix layer, which is configured to at least cover the common electrode line, the common connection line and the common electrode of the virtual sub-pixel.

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