Display substrate, display apparatus and contact resistance test method

Abstract

A display substrate, a display apparatus and a contact resistance test method. The display substrate comprises a display area, and a first frame area located on at least one side, wherein the first frame area comprises at least one test group. Each test group comprises a plurality of driving test pads, a plurality of binding test pads and a plurality of test signal lines, wherein in the same test group, the binding test pads are located on the side of the driving test pads that is away from the display area; the plurality of binding test pads correspond to the plurality of test signal lines on a one-to-one basis; one binding test pad is electrically connected to one of the driving test pads by means of a corresponding test signal line; one driving test pad is electrically connected to at least one binding test pad by means of at least one test signal line; and the plurality of driving test pads are located adjacent to the plurality of binding test pads.

Description

Display substrate, display device, contact resistance test method

[0001] This application claims priority to Chinese Patent Application No. 202510239092.7, filed on February 28, 2025, entitled "Display Substrate, Display Device, Contact Resistance Testing Method", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a display device, and a contact resistance testing method. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0006] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0007] At least one test group is located in the first border area, and the same test group includes multiple drive test pads, multiple bonding test pads and multiple test signal lines;

[0008] In the same test group: the plurality of bonding test pads are located on the side of the plurality of driving test pads away from the display area; the plurality of bonding test pads correspond one-to-one with the plurality of test signal lines; one of the bonding test pads is electrically connected to one of the driving test pads through a corresponding test signal line; one of the driving test pads is electrically connected to at least one of the bonding test pads through at least one of the plurality of test signal lines; at least two of the driving test pads are electrically connected; and the plurality of driving test pads are located adjacent to the plurality of bonding test pads.

[0009] In an exemplary embodiment, the display substrate further includes:

[0010] Multiple drive pads are located in the first frame region, and in a first direction, multiple drive test pads in the at least one test group are located on at least one side of the multiple drive pads;

[0011] Multiple bonding pads are located in the first frame area, and the multiple bonding pads are located on the side of the multiple driving pads away from the display area. In the first direction, multiple bonding test pads in the at least one test group are located on at least one side of the multiple bonding pads.

[0012] In the same test group, in the first direction, the plurality of drive test pads, the plurality of bonding test pads, and the plurality of test signal lines are located on the same side of the plurality of drive pads and the plurality of bonding pads.

[0013] In an exemplary embodiment, the display substrate further includes:

[0014] Multiple sub-pixels are located on one side of the substrate and in the display area;

[0015] Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels;

[0016] The plurality of driving pads include a plurality of first driving pads and a plurality of second driving pads. The plurality of second driving pads are located on the side of the plurality of first driving pads away from the display area. The plurality of first driving pads are electrically connected to the plurality of data lines. At least a portion of the plurality of bonding pads are electrically connected to the plurality of second driving pads. The conductivity of at least a portion of the structure of the plurality of test signal lines in the at least one test group is consistent with the conductivity of the plurality of data lines.

[0017] In an exemplary embodiment, the at least one test group includes at least one first test group and at least one second test group;

[0018] In the same first test group: it includes multiple first driver test pads, multiple first bonding test pads, and multiple first test signal lines. The multiple first bonding test pads correspond one-to-one with the multiple first test signal lines. One of the multiple first bonding test pads is electrically connected to one of the multiple first driver test pads through a corresponding first test signal line. The one first driver test pad is electrically connected to at least one of the multiple first bonding test pads through at least one of the multiple first test signal lines.

[0019] In the same second test group: it includes multiple second driver test pads, multiple second bonding test pads, and multiple second test signal lines. The multiple second bonding test pads correspond one-to-one with the multiple second test signal lines. One of the multiple second bonding test pads is electrically connected to one of the multiple second driver test pads through a corresponding second test signal line. The one second driver test pad is electrically connected to at least one of the multiple second bonding test pads through at least one of the multiple second test signal lines.

[0020] The plurality of second drive test pads are located on the side of the plurality of first drive test pads that are away from the display area.

[0021] In an exemplary embodiment, at least one of the plurality of test signal lines includes a first structural portion, a second structural portion, and a third structural portion;

[0022] In the same test signal line: one end of the second structure is connected to the first structure, and the other end is connected to the third structure; the other end of the first structure is electrically connected to one of the plurality of drive test pads, and the other end of the third structure is electrically connected to the corresponding bonding test pad.

[0023] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the first structural portion and the third structural portion are located on the side of the second structural portion closer to the substrate, or the first structural portion and the third structural portion are located on the side of the second structural portion away from the substrate, or the first structural portion and the third structural portion are disposed in the same layer as the second structural portion.

[0024] In an exemplary embodiment, the display area includes a plurality of sub-pixels and a plurality of data lines, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; at least one of the plurality of sub-pixels includes a pixel driving circuit, the pixel driving circuit including a plurality of transistors and at least one capacitor;

[0025] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer, a control electrode, a first electrode, and a second electrode, the active layer being located between the first electrode plate and the substrate, the control electrode being disposed on the same layer as the first electrode plate, the first electrode and the second electrode being located on the side of the second electrode plate away from the substrate, and the data line being located on the side of the first electrode and the second electrode away from the substrate;

[0026] The second structural part is disposed on the same layer as at least one of the first pole, the second pole, and the data line.

[0027] In an exemplary embodiment, the first structural portion and the third structural portion are disposed on the same layer as at least one of the control electrode and the second electrode plate, or the first structural portion and the third structural portion are disposed on the same layer as at least one of the first electrode, the second electrode, and the data line.

[0028] In an exemplary embodiment, the same test group includes at least two drive test pads, at least two bonding test pads, and at least two test signal lines, wherein the at least two drive test pads are electrically connected to the at least two bonding test pads through the at least two test signal lines.

[0029] In an exemplary embodiment, within the same test group: the number of test signal lines and the number of drive test pads are both integer multiples of 2, the number of bonding test pads is the same as the number of test signal lines, and not less than the number of drive test pads.

[0030] In an exemplary embodiment, in the same test group, there are two drive test pads, two bonding test pads, and two test signal lines. The first ends of the two test signal lines are electrically connected to the two bonding test pads, and the second ends are electrically connected to the two drive test pads.

[0031] In an exemplary embodiment, in the same test group, there are two drive test pads, four bonding test pads, and four test signal lines. The first ends of the four test signal lines are electrically connected to the four bonding test pads, the second ends of two of the test signal lines are electrically connected to one of the drive test pads, and the second ends of the other two test signal lines are electrically connected to the other drive test pad.

[0032] In an exemplary embodiment, in the same test group, there are two drive test pads, six bonding test pads, and six test signal lines. The first ends of the six test signal lines are electrically connected to the six bonding test pads, the second ends of three of the test signal lines are electrically connected to one of the drive test pads, and the second ends of the other three test signal lines are electrically connected to the other drive test pad.

[0033] In an exemplary embodiment, the at least one test group further includes a jumper wire, and in the same test group, the number of drive test pads is two, and the two drive test pads are electrically connected through the jumper wire.

[0034] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0035] Thirdly, this disclosure also provides a contact resistance testing method for testing the contact resistance of driving test pads in a display substrate according to any of the above embodiments. The display substrate includes a display area and a first frame area located on at least one side of the display area. The first frame area includes at least one test group, and the same test group includes multiple driving test pads, multiple bonding test pads, and multiple test signal lines. In the same test group, the multiple bonding test pads are located on the side of the multiple driving test pads away from the display area. The multiple bonding test pads correspond one-to-one with the multiple test signal lines. One of the multiple bonding test pads is electrically connected to one of the multiple driving test pads through a corresponding test signal line. The one driving test pad is electrically connected to at least one of the multiple bonding test pads through at least one of the multiple test signal lines. At least two of the multiple driving test pads are electrically connected. The multiple driving test pads are located adjacent to the multiple bonding test pads. The multiple bonding test pads include at least one first type of bonding test pad and at least one second type of bonding test pad. The method includes:

[0036] A first electrical signal is provided to the first type of bonding test pad, a second electrical signal is tested to the second type of bonding test pad, and a first contact resistance of the drive test pad is obtained based on the first electrical signal and the second electrical signal.

[0037] In an exemplary embodiment, the at least one test group further includes a jumper wire; within the same test group: the number of drive test pads is two, the two drive test pads are electrically connected through the jumper wire, the plurality of bonding test pads include two first-type bonding test pads and two second-type bonding test pads, the plurality of test signal lines include two first-type test signal lines and two second-type test signal lines, the two first-type bonding test pads are electrically connected to the two drive test pads respectively through the two first-type test signal lines, and the two second-type bonding test pads are electrically connected to the two drive test pads respectively through the two second-type test signal lines.

[0038] In an exemplary embodiment, providing a first electrical signal to the first type of bonding test pad and testing a second electrical signal to the second type of bonding test pad includes: providing a first current signal to one of the first type of bonding test pads, providing a ground signal to the other first type of bonding test pad, and testing a second voltage signal to the two second type of bonding test pads; the first electrical signal includes the first current signal and the ground signal, and the second electrical signal includes the second voltage signal.

[0039] In an exemplary embodiment, within the same test group, the plurality of bonding test pads further include two third-type bonding test pads, and the plurality of test signal lines further include two third-type test signal lines. The two third-type bonding test pads are electrically connected to the two drive test pads respectively through the two third-type test signal lines.

[0040] Before providing a first electrical signal to the first type of bonding test pad, or after obtaining the first contact resistance of the drive test pad based on the first electrical signal and the second electrical signal, the method further includes: providing a third electrical signal to the third type of bonding test pad, testing a fourth electrical signal of the third type of bonding test pad, and obtaining a second contact resistance of the drive test pad based on the third electrical signal and the fourth electrical signal.

[0041] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0043] Figure 1a is a schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0044] Figure 1b is another schematic diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0045] Figure 2 is a schematic cross-sectional view of the display area of ​​the display substrate shown in Figure 1a, taken along line aa'.

[0046] Figure 3 is a partial schematic diagram of the first signal access area provided in an exemplary embodiment of this disclosure;

[0047] Figure 4a is a magnified view of the details of region S in Figure 3;

[0048] Figure 4b is a schematic cross-sectional view of the structure at position AA in Figure 4a;

[0049] Figure 5 is a schematic diagram of the signal connection between the first signal access area and the second signal access area;

[0050] Figure 6a is a schematic diagram of a connection between a drive test pad and a bonding test pad provided in an exemplary embodiment of this disclosure;

[0051] Figure 6b is a schematic diagram of a connection between a drive test pad and a bonding test pad provided in an exemplary embodiment of this disclosure;

[0052] Figure 7 is an enlarged structural diagram of position R1 in Figure 6a;

[0053] Figure 8 is a schematic diagram of the structure of one test group in Figure 6a;

[0054] Figure 9 is a schematic diagram of one test group in Figure 6a;

[0055] Figure 10 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0056] Figure 11 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0057] Figure 12 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0058] Figure 13 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0059] Figure 14 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0060] Figure 15 is a schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0061] Figure 16 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0062] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0063] It is understood that the various figures in the embodiments of this disclosure are only used to schematically show the connection relationship between the various components. The dimensions of the various components in the figures are not drawn to scale, and their relative positional relationship may not completely correspond to the actual position.

[0064] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0065] In this disclosure, "electrical connection" includes the situation where components are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0066] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0067] The "patterning process" as described in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0068] Figure 1a is a schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1b is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Both Figures 1a and 1b show planar schematic diagrams of the display substrate before the bending process.

[0069] In some examples, as shown in Figures 1a and 1b, the display substrate may include a display area AA and a border area BB surrounding the display area AA. For example, the border area BB may include a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (e.g., a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display substrate; the second border area B2 may be, for example, the top border of the display substrate; the third border area B3 may be, for example, the left border of the display substrate; and the fourth border area B4 may be, for example, the right border of the display substrate.

[0070] In some examples, as shown in Figures 1a and 1b, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display substrate can be a flexible panel, and therefore the display substrate can be deformable, such as rolled, bent, folded, or rolled up.

[0071] In some examples, as shown in Figures 1a and 1b, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals, or may include scan signals, or may include scan signals, reset control signals, and light emission control signals.

[0072] In some examples, as shown in Figures 1a and 1b, the first direction X can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the second direction Y can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y can intersect each other, for example, they can be perpendicular to each other.

[0073] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0074] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0075] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit (indicated by L in FIG1a; note that for simplicity, the light-emitting element L is shown in only one sub-pixel PX in FIG1a, which does not represent a limitation of this disclosure). The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, T in the above circuit structure refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0076] In some examples, multiple transistors in the pixel circuit can be employed as low-temperature polysilicon (LTPS) thin-film transistors (TFTs) and oxide (OPT) thin-film transistors (OTPTs). The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate, i.e., an LTPS+Opide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0077] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0078] In some examples, the display substrate can integrate a touch structure. The display substrate may include an organic light-emitting diode (OLED) display structure, a plasma display structure, or an electrophoretic display structure. For example, the display substrate may include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure, forming a Touch on Thin Film Encapsulation (TFE) structure. The integration of the display structure and the touch structure offers advantages such as thinness, lightness, and foldability, meeting the product requirements for flexible folding and narrow bezels.

[0079] In some examples, the touch structure on thin-film encapsulation mainly includes the Flexible Multi-Layer On Cell (FMLOC) structure and the Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure operates based on mutual capacitance detection, typically using two metal layers to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) detects the mutual capacitance between the driving and sensing electrodes to achieve touch action. The FSLOC structure operates based on self-capacitance (or voltage) detection, typically using a single metal layer to form the touch electrode. The integrated circuit detects the self-capacitance (or voltage) of the touch electrode to achieve touch action.

[0080] Figure 2 is a schematic cross-sectional view of the display area of ​​the display substrate shown in Figure 1a, taken along line aa'. Figure 2 illustrates the structure of a sub-pixel in the display area as an example. In this example, multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit can be both LTPS and OPS. Furthermore, this example illustrates the integration of a mutual capacitance touch structure into the display substrate to form an FMLOC structure.

[0081] In some examples, as shown in Figure 2, in the direction Z perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least light-emitting elements for multiple sub-pixels.

[0082] In some examples, Figure 2 illustrates an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 20 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, a buffer layer may be disposed on the side of the semiconductor layer closest to the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display substrate and also increases the adhesion of the film layers in the display substrate to the substrate. In still other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer closest to the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor in the pixel circuitry to prevent external light from affecting the performance of the thin-film transistor. In still other examples, a passivation layer may be omitted between the first and second source-drain metal layers, and only a first planarization layer may be disposed between the first and second source-drain metal layers.

[0083] In some examples, as shown in FIG2, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 232 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0084] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0085] In some examples, as shown in Figure 2, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303 (cathode). The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 100, and the isolation pillar layer may include multiple isolation pillars (PS).

[0086] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0087] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0088] In some examples, as shown in Figure 2, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked in a direction perpendicular to the substrate. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0089] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0090] In some examples, as shown in Figure 2, the touch structure layer 50 of the display area may include, in the direction perpendicular to the substrate, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, arranged sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 can be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connection portions. The first touch electrodes and the first connection portions can be an integrally connected structure. The second touch conductive layer 512 may include multiple second connection portions. The second connection portions can be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0091] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0092] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0093] In some examples, as shown in FIG2, in a direction perpendicular to the substrate, the color filter on encapsulation (COE) 60 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially. The color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0094] In some examples, as shown in Figure 1a, the first border region B1 of the display substrate may include a fan-out trace region B11 and a signal access region B12 arranged sequentially along a direction away from the display region AA. Figure 1a only illustrates a few traces within the first border region for illustrative purposes. This example does not limit the number of traces in the first border region.

[0095] In some examples, as shown in Figure 1a, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can have at least multiple data fan-out lines 42. These multiple data fan-out lines 42 can be electrically connected to multiple data lines DL within the display area AA; for example, the multiple data fan-out lines 42 and multiple data lines DL can be electrically connected in a one-to-one correspondence. The multiple data fan-out lines 42 can extend into the signal access area B12 using a fan-out routing method. The multiple data fan-out lines 42 and the multiple data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias formed in the insulating layer.

[0096] In some examples, as shown in FIG1a, the signal access area B12 may include at least one first signal access area B121. This example illustrates and describes one first signal access area. In other examples, the display substrate is a large-size panel, and the display substrate may include multiple first signal access areas, which may be arranged sequentially along a first direction X.

[0097] In some examples, as shown in Figure 1a, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 may be provided with multiple driver pads 31, which can be configured to be bonded to at least one driver chip. The driver chip can be configured to generate drive signals required to drive sub-pixels and provide the drive signals to the data lines DL of the display area AA. For example, the drive signals can be data signals for driving sub-pixels. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the driver chip can also include hardware circuitry and computer-executable code. The hardware circuitry can include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuitry can also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0098] In some examples, as shown in Figure 1a, the signal access area B12 may be provided with at least a plurality of data line leads 101, which can be electrically connected to a plurality of data fan-out lines 42 in the fan-out routing area B11, for example, in a one-to-one correspondence. For example, the data line leads 101 and the connected data fan-out lines 42 can be an integrated structure interconnected. That is, the plurality of data line leads 101 are electrically connected to a plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one correspondence. The plurality of data line leads 101 can extend into the first signal access area B121 and be electrically connected to a plurality of drive pads 31 within the first signal access area B121. For example, the plurality of data line leads 101 and the plurality of drive pads 31 can be electrically connected in a one-to-one correspondence, or one data line lead 101 can be electrically connected to at least one drive pad 31. The data line leads 101 and the data fan-out lines 42 can transmit the data signals provided by the driver chip to the data lines DL of the display area.

[0099] In some examples, as shown in Figure 1b, the first border region B1 of the display substrate may include: a fan-out trace region B11, a bending region B13, and a signal access region B12 arranged sequentially along a direction away from the display region AA. Figure 1b only illustrates a few traces within the first border region for illustrative purposes. This example does not limit the number of traces in the first border region.

[0100] In some examples, as shown in Figure 1b, the bending region B13 can connect the fan-out trace region B11 and the signal access region B12, and can be configured to bend the signal access region B12 to the back of the display region AA. The bending region B13 can have at least multiple data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out trace region B11, and the other end can be connected to the data line lead 101 in the signal access region B12. The multiple data bending connection lines 43 can be in the same layer, for example, located in the first source-drain metal layer or the second source-drain metal layer. The remaining structure of the first border region B1 in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0101] As shown in Figures 1a and 1b, the signal access area B12 may further include a second signal access area B122. The second signal access area B122 has multiple bonding pads 32 for bonding with a flexible printed circuit board (FPC). The FPC can be bonded to the second signal access area B122 using a FOP (FPC On Panel) process. A driver pad 31 is used for bonding with at least one driver chip.

[0102] Figure 3 is a partial enlarged view of the first signal access area according to an embodiment of the present disclosure. In some examples, as shown in Figure 3, the plurality of drive pads 31 of the first signal access area B121 can be arranged in multiple rows (e.g., four rows). The plurality of drive pads 31 included in each row can be arranged sequentially along a first direction X, and the multiple rows of drive pads 31 can be arranged sequentially along a second direction Y. The drive pads 31 of adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the plurality of pads of the first signal access area B121 can be arranged in a single row.

[0103] In some examples, the multiple drive pads 31 in the first signal access area can be divided into at least multiple groups (e.g., two groups). Figure 3 illustrates and explains two groups of pads (e.g., the first group of drive pads 31A and the second group of drive pads 31B). The second group of drive pads 31B can be located on the side of the first group of drive pads 31A away from the display area. The first group of drive pads 31A can include multiple first drive pads 311 arranged in three rows along the first direction X. The second group of drive pads 31B can include multiple second drive pads 312 arranged in one row along the first direction X. In some examples, the second group of drive pads 31B is used for input signals, which are converted by the bonded IC and output to the first group of drive pads 31A. The first group of drive pads 31A then transmits the signals (e.g., data signals) to multiple sub-pixels PX through multiple signal lines (e.g., multiple data lines DL). The first group of drive pads 31A and the second group of drive pads 31B can be staggered in the first direction X. For example, the pads in the first group of driving pads 31A and the second group of driving pads 31B may not be aligned in the second direction Y. There are gaps between adjacent pads within the same group, and gaps between pads in adjacent groups. In some embodiments, a group of pads may be one row, two rows, or three rows of pads. This disclosure does not limit the number of rows of pads or the number of pads in each row.

[0104] Figure 4a is a magnified view of region S in Figure 3. In some examples, as shown in Figure 4a, multiple data line leads 101 can extend approximately along the second direction Y between the intervals of multiple drive pads 31. For example, two data line leads 101 can be provided between two adjacent drive pads 31 of a set of pads. A data line lead 101 can be electrically connected to at least one drive pad 31, for example, a data line lead 101 can be connected to one drive pad 31.

[0105] Figure 4b is a cross-sectional view of position AA in Figure 4a. At least one of the multiple pads 31, the driving pad 31, may include:

[0106] A first insulating layer 102 is located on the side of the plurality of data line leads 101 facing away from the substrate 100. The first insulating layer 102 includes a first opening 110 that exposes at least a portion of at least one of the plurality of data line leads 101.

[0107] A first metal layer 1031 is located on the side of the plurality of data line leads 101 facing away from the substrate 100, and is electrically connected to at least one of the plurality of data line leads 101 through a first opening 110. The first metal layer 1031 includes a first bottom 1031a and a stepped portion surrounding the first bottom 1031a. The orthographic projection of the first bottom 1031a onto the substrate 100 lies within the orthographic projection of the first opening 110 onto the substrate 100. The first bottom 1031a is connected to the plurality of data line leads 101 through a first opening 110. At least one of the data line leads 101 is electrically connected. The stepped portion may include a first stepped portion 1031b located on the side of the first insulating layer 102 away from the substrate 100 and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c connects the first bottom 1031a and the first stepped portion 1031b. The orthographic projection of the second stepped portion 1031c on the substrate 100 is located in the orthographic projection of the first opening 110 on the substrate 100.

[0108] The second insulating layer 104 is located on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100, wherein the second insulating layer 104 includes a second opening 120 that exposes at least a portion of the first bottom 1031a of the first metal layer 1031.

[0109] In some examples, as shown in FIG4b, the drive pad 31 may further include a second metal layer 1032 located on the side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100, wherein the second metal layer 1032 is electrically connected to the first metal layer 1031 through a second opening 120, and the orthographic projection of the second metal layer 1032 on the substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the substrate 100.

[0110] In an exemplary embodiment, as shown in FIG4b, the driving pad 31 may further include:

[0111] The third metal layer 1033 is located on the side of the second metal layer 1032 away from the substrate 100. The third metal layer 1033 is electrically connected to the second metal layer 1032, and the orthogonal projection of the third metal layer 1033 on the substrate 100 covers the orthogonal projection of the second metal layer 1032 on the substrate 100.

[0112] In an exemplary embodiment, as shown in FIG4b, the display substrate may further include:

[0113] The third insulating layer 106 is located on the side of the third metal layer 1033 facing away from the substrate 100, and the third insulating layer 106 includes a third opening 130.

[0114] As shown in Figure 4b, the orthographic projection of the third opening 130 on the substrate 100 is within the range of the orthographic projection of the second opening 120 on the substrate 100, and the orthographic projection of the first opening 110 on the substrate 100 is within the range of the orthographic projection of the third opening 130 on the substrate 100.

[0115] In an exemplary embodiment, the third insulating layer 106 may include at least one of an inorganic insulating layer and an organic insulating layer.

[0116] In an exemplary embodiment, as shown in FIG4b, the first metal layer 1031 may further include a second bottom 1031e surrounding the step portion, and the step portion may further include a third step portion 1031d forming an angle with the first step portion 1031b. The third step portion 1031d connects the second bottom 1031e and the first step portion 1031b. The orthographic projection of the second insulating layer 104 on the substrate 100 at least partially overlaps with the orthographic projection of the second bottom 1031e on the substrate 100.

[0117] In an exemplary embodiment, as shown in FIG4b, the display substrate may further include:

[0118] The fourth metal layer 108 is located on the side of the third metal layer 1033 and the third insulating layer 106 away from the substrate 100. The fourth metal layer 108 can be electrically connected to the third metal layer 1033 through the third opening 130. The orthographic projection of the fourth metal layer 108 on the substrate 100 at least partially overlaps with the orthographic projection of the third metal layer 1033 on the substrate 100. For example, the orthographic projection of the fourth metal layer 108 on the substrate 100 can cover the orthographic projection of the third metal layer 1033 on the substrate 100.

[0119] In an exemplary embodiment, as shown in FIG4b, the display substrate may further include:

[0120] The fourth insulating layer 107 is located in the direction Z perpendicular to the plane of the substrate 100. The fourth insulating layer 107 may be located between the third insulating layer 106 and the fourth metal layer 108. The fourth insulating layer 107 may include a fourth opening 140. The orthographic projection of the fourth opening 140 on the substrate 100 is located within the orthographic projection of the third opening 130 on the substrate 100. The fourth metal layer 108 may be electrically connected to the third metal layer 1033 through the third opening 130 and the fourth opening 140.

[0121] In an exemplary embodiment, as shown in Figures 2 and 4b, the first insulating layer 102 can be disposed in the same layer as the interlayer insulating layer 203 and the second gate insulating layer 202; the second insulating layer 104 can be disposed in the same layer as the passivation layer 204; the third insulating layer 106 can be disposed in the same layer as the third planarization layer 207; and the fourth insulating layer 107 can be disposed in the same layer as at least one of the touch interlayer insulating layer 502 and the pixel definition layer 304. Between the substrate and the multiple data line leads (i.e., gate metal layers), a barrier layer, a buffer layer, etc., can also be arranged, as indicated by film layer 105 in Figure 4b. The data line lead 101 can be disposed in the same layer as at least one of the first gate metal layer and the second gate metal layer; the first metal layer 1031 can be disposed in the same layer as the first source-drain metal layer; the second metal layer 1032 can be disposed in the same layer as the second source-drain metal layer; the third metal layer 1033 can be disposed in the same layer as the third source-drain metal layer; and the fourth metal layer 108 can be disposed in the same layer as one of the first touch conductive layer and the second touch conductive layer. In an exemplary embodiment, the third insulating layer 106 is not limited to being disposed in the same layer as the third planarization layer 207. For example, the third insulating layer 106 may be disposed in the same layer as the third planarization layer 207, or the third insulating layer 106 may be located between the third planarization layer 207 and the first electrode 301 (i.e., the anode) in the direction Z perpendicular to the plane of the substrate 100.

[0122] In an exemplary embodiment, the difference between Figure 1a and Figure 1b is that Figure 1a does not have a bending region B13, so the signal access region B12 cannot be bent to the back of the display region AA. The other structures are the same as in Figure 1b. The signal connection diagram between the first signal access region B121 and the second signal access region B122 in Figures 1a and 1b can be shown in Figure 5. In this diagram, the first signal access region B121 is configured to be bonded to an integrated circuit. This structure can be called a COP (Chip on Panel) structure, and the integrated circuit can be a driver integrated circuit. The circuit (abbreviated as DIC) is divided into two regions: the first signal access area B121, which can be called the COP area or the DIC area (driving integrated circuit area); and the second signal access area B122, which can be called the flexible circuit board bonding area (abbreviated as FPC area). The first signal access area B121 and the second signal access area B122 can be collectively referred to as the pad area (i.e., PAD area). The bonding test pad 32c in the FPC area can be connected to the driving test pad 31c in the DIC area through the test signal line L11. The bonding test pad 32c can provide a test signal to the driving test pad 31c through the test signal line L11 (used to test the contact resistance of the driving pad 31). The driving test pad 31c can be the driving pad in the first signal access area B121 used to test the contact resistance, and the bonding test pad 32c can be the bonding pad in the second signal access area B122 used to test the contact resistance. The DIC area can be connected to the FPC area through the connecting line L21. The bonding pad 32 in the FPC area can provide a working signal to the driving pad 31 in the DIC area through the connecting line L21. The driver integrated circuit (DIC) can also be bonded to a flexible circuit board, which can reduce the size of the first border area B1. This structure can be called chip on flex (COF).

[0123] In the COP structure, the COP area needs to provide signals through a flexible printed circuit board (FPC). The contact resistance of the drive pad 31 (IC Bonding Pad) also needs to be monitored through the FPC. When testing the contact resistance of the drive pad 31, if the length of the test signal line L11 is large and the resistance of the test signal line L11 is high (for example, the resistance will be large for metal materials with low conductivity), the resistance of the test signal line L11 will usually be large, resulting in inaccurate test results for the contact resistance of the drive pad 31. The contact resistance of the drive pad 31 (i.e., the contact resistance between the drive pad 31 and the pin of the drive integrated circuit) is important for evaluating the performance of the display substrate. Inaccurate test results for the contact resistance of the drive pad 31 will lead to inaccurate test results for the performance of the display substrate.

[0124] This disclosure provides a display substrate, which may include:

[0125] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0126] At least one test group is located in the first border area, and the same test group includes multiple drive test pads, multiple bonding test pads and multiple test signal lines;

[0127] In the same test group: the plurality of bonding test pads are located on the side of the plurality of driving test pads away from the display area; the plurality of bonding test pads correspond one-to-one with the plurality of test signal lines; one of the bonding test pads is electrically connected to one of the driving test pads through a corresponding test signal line; one of the driving test pads is electrically connected to at least one of the bonding test pads through at least one of the plurality of test signal lines; at least two of the driving test pads are electrically connected; and the plurality of driving test pads are located adjacent to the plurality of bonding test pads.

[0128] The display substrate provided in this embodiment includes a display area and a first frame area located on at least one side. The first frame area includes at least one test group, which includes multiple drive test pads, multiple bonding test pads, and multiple test signal lines. In the same test group, the bonding test pads are located on the side of the drive test pads away from the display area. Each bonding test pad corresponds one-to-one with a multiple test signal line. One bonding test pad is electrically connected to one of the drive test pads through a corresponding test signal line. One drive test pad is electrically connected to at least one bonding test pad through at least one test signal line. The multiple drive test pads are located adjacent to the multiple bonding test pads, which can minimize the length of the test signal lines, reduce their resistance, and improve the accuracy of testing the contact resistance of the drive pads. The accompanying drawings of this embodiment only illustrate the structures involved in this embodiment; other structures can be referred to in general designs.

[0129] As shown in Figures 1a, 1b, and 6a to 8, Figures 1a and 1b are schematic diagrams of the planar structure of the display substrate, Figures 6a and 6b are schematic diagrams of the connection between the driving test pad and the bonding test pad, Figure 7 is an enlarged schematic diagram of the R1 position in Figure 6a, and Figure 8 is a schematic diagram of a test group in Figure 6a. The display substrate provided in this embodiment may include:

[0130] The substrate 100 may include a display area AA and a first border area B1 located on at least one side of the display area AA.

[0131] At least one test group C11 is located in the first border area B1. The same test group C11 may include multiple drive test pads 31c, multiple bonding test pads 32c and multiple test signal lines L11.

[0132] In the same test group C11, the bonding test pad 32c can be located on the side of the drive test pad 31c away from the display area AA. Multiple bonding test pads 32c can correspond one-to-one with multiple test signal lines L11. One of the bonding test pads 32c can be electrically connected to one of the drive test pads 31c through the corresponding test signal line L11. One drive test pad 31c can be electrically connected to at least one of the bonding test pads 32c through at least one of the test signal lines L11. At least two of the drive test pads 31c can be electrically connected. The multiple drive test pads 31c can be located in a position adjacent to the multiple bonding test pads 32c.

[0133] In an exemplary embodiment, in the same test group C11, multiple drive test pads 31c are located adjacent to multiple bonding test pads 32c, which can reduce the length of the test signal line L11, thereby reducing the resistance of the test signal line L11 and improving the accuracy of the contact resistance of the test drive pads.

[0134] In an exemplary embodiment, as shown in Figures 6a to 8, the display substrate may further include:

[0135] Multiple drive pads 31 are located in the first border region B1 in the first direction X, and multiple drive test pads 31c in the at least one test group C11 may be located on at least one side of the multiple drive pads 31.

[0136] Multiple bonding pads 32 are located in the first border area B1. Multiple bonding pads 32 are located on the side of multiple driving pads 31 away from the display area AA. In the first direction X, multiple bonding test pads 32c in the at least one test group C11 may be located on at least one side of the multiple bonding pads 32.

[0137] In the same test group C11, in the first direction X, multiple drive test pads 31c, multiple bond test pads 32c, and multiple test signal lines L11 are located on the same side of the multiple drive pads 31 and multiple bond pads 32.

[0138] In an exemplary embodiment, the contact resistance of the drive test pad 31c refers to the contact resistance between the drive test pad 31c and the pin in the drive integrated circuit.

[0139] In an exemplary embodiment, the plurality of drive test pads 31c in test group C11 can be fabricated together with the plurality of drive pads 31. The structure of the drive test pads 31c is substantially the same as that of the drive pads 31 (for example, they can be the same structure, as shown in FIG. 4b). The drive test pads 31c in test group C11 are used to test the contact resistance between the drive test pads 31c and the pins in the drive integrated circuit, and are not electrically connected to the data lines DL in the display area AA. The detected contact resistance between the drive test pads 31c and the pins in the drive integrated circuit can be regarded as the contact resistance between the drive pads 31 and the pins in the drive integrated circuit.

[0140] In an exemplary embodiment, the multiple bonding test pads 32c in test group C11 can be fabricated together with multiple bonding pads 32. The structure of the bonding test pads 32c can be substantially the same as the structure of the bonding pads 321 (e.g., the same structure). The bonding test pads 32c are used to provide test signals to the drive test pads 31c that are electrically connected to them and to transmit corresponding electrical signals to the flexible circuit board FPC. The flexible circuit board FPC is provided with corresponding test points. The electrical signals are obtained through the test points. The contact resistance between the drive test pads 31c and the pins in the drive integrated circuit is obtained based on the provided test signals and the obtained electrical signals, thereby obtaining the contact resistance between the drive pads 31c and the pins in the drive integrated circuit.

[0141] In an exemplary embodiment, as shown in Figures 6a to 7, the display substrate may further include a plurality of driving virtual pads 33 and a plurality of bonding virtual pads 34. The driving pads 31, driving test pads 31c, and driving virtual pads 33 may be located within the range of the first signal access area B121. The bonding pads 32, bonding test pads 32c, and bonding virtual pads 34 may be located within the range of the second signal access area B122 in the first direction X. The driving test pads 31c may be located on both sides of the plurality of driving pads 31, the bonding test pads 32c may be located on both sides of the plurality of bonding pads 32, the plurality of driving virtual pads 33 may be located on the side of the driving test pads 31c away from the plurality of driving pads 31, and the plurality of bonding virtual pads 34 may be located on the side of the bonding test pads 32c away from the plurality of bonding pads 32. In the first direction X, the virtual pads 33 and 34 are located at the outermost edge. The virtual pads 33 and 34 are not electrically connected to other signal lines and do not transmit signals during normal operation of the display substrate. The virtual pad 33 can protect the test pad 31c and the test pad 31, and the virtual pad 34 can protect the test pad 32 and the test pad 32c.

[0142] In an exemplary embodiment, as shown in Figures 1a, 1b and 3, the display substrate may further include:

[0143] Multiple sub-pixels PX are located on one side of the substrate and within the display area AA;

[0144] Multiple data lines DL are located in the display area AA and electrically connected to multiple sub-pixels PX. The multiple data lines DL are configured to provide data signals to the multiple sub-pixels PX.

[0145] The plurality of driving pads 31 may include a plurality of first driving pads 311 and a plurality of second driving pads 312. The plurality of second driving pads 312 may be located on the side of the plurality of first driving pads 311 away from the display area AA. The plurality of first driving pads 311 are electrically connected to a plurality of data lines DL. At least a portion of the plurality of bonding pads 32 are electrically connected to the plurality of second driving pads 312. The conductivity of at least a portion of the structure of the plurality of test signal lines L11 in the at least one test group C11 is consistent with the conductivity of the plurality of data lines DL.

[0146] In an exemplary embodiment, the data line DL is typically made of a material with high conductivity and low resistance. The conductivity of at least a portion of the structure of the test signal line L11 is consistent with that of the data line DL. This can be achieved by using the same material as the data line DL for at least a portion of the structure of the test signal line L11, or by using a material with a conductivity substantially consistent with or the same as that of the data line DL for at least a portion of the structure of the test signal line L11. This results in a lower resistance of the test signal line L11, thereby improving the accuracy of the contact resistance test of the drive pad 31.

[0147] In an exemplary embodiment, as shown in FIG5, at least some of the bonding pads 32 can be electrically connected to a plurality of second driving pads 312 via a plurality of connecting lines L21, thereby realizing the electrical connection between the DIC region and the FPC region.

[0148] In an exemplary embodiment, as shown in FIG6b, the at least one test group C11 may include at least one first test group C111 and at least one second test group C112;

[0149] In the same first test group C111, there may be multiple first driver test pads 31c1, multiple first bonding test pads 32c1, and multiple first test signal lines L11c1. The multiple first bonding test pads 32c1 correspond one-to-one with the multiple first test signal lines L11c1. One of the multiple first bonding test pads 32c1 is electrically connected to one of the multiple first driver test pads 31c1 through the corresponding first test signal line L11c1. One of the first driver test pads 31c1 can be electrically connected to at least one of the multiple first bonding test pads 32c1 through at least one of the multiple first test signal lines L11c1.

[0150] In the same second test group C112, there may be multiple second drive test pads 31c2, multiple second bonding test pads 32c2, and multiple second test signal lines L11c2. The multiple second bonding test pads 32c2 correspond one-to-one with the multiple second test signal lines L11c2. One of the multiple second bonding test pads 32c2 is electrically connected to one of the multiple second drive test pads 31c2 through the corresponding second test signal line L11c2. One of the second drive test pads 31c2 can be electrically connected to at least one of the multiple second bonding test pads 32c2 through at least one of the multiple second test signal lines L11c2.

[0151] The plurality of second drive test pads 31c2 may be located on the side of the plurality of first drive test pads 31c1 away from the display area AA. In the first direction X, the plurality of first bonding test pads 32c1 may be located on the side of the plurality of second bonding test pads 32c2 away from the plurality of bonding pads 32.

[0152] In an exemplary embodiment, as shown in FIG6b, in the first direction X, multiple first drive test pads 31c1 in the same first test group C111 can be located on one side of multiple first drive test pads 311, and multiple second drive test pads 31c2 in the same second test group C112 can be located on one side of multiple second drive test pads 312. That is, multiple first drive test pads 31c1 in the first test group C111 and multiple second drive test pads 31c2 in the second test group C112 can be located at the edge of the first signal access area B121. Similarly, multiple first bonding test pads 32c1 in the first test group C111 and multiple second bonding test pads 32c2 in the second test group C112 can be located at the edge of the second signal access area B122. That is, in the first direction X, multiple first bonding test pads 32c1 and multiple second bonding test pads 32c2 can be located on one side of multiple bonding pads 32.

[0153] In an exemplary embodiment, the first test group C111 can be used to test the contact resistance between the first drive pad 311 (which can be called the signal output pad) and the pin of the drive integrated circuit, and the second test group C112 can be used to test the contact resistance between the second drive pad 312 (which can be called the signal input pad) and the pin of the drive integrated circuit.

[0154] In an exemplary embodiment, as shown in FIG6a and FIG8, at least one of the plurality of test signal lines L11 may include a first structural portion h1, a second structural portion h2 and a third structural portion h3.

[0155] In the same test signal line L11: one end of the second structure h2 is connected to the first structure h1, and the other end is connected to the third structure h3; the other end of the first structure h1 is electrically connected to one of the multiple drive test pads 31c, and the other end of the third structure h3 is electrically connected to the corresponding bonding test pad 32c.

[0156] In an exemplary embodiment, as shown in Figures 6a and 8, the first structural part h1 can be a broken line or a strip extending along the first direction X, the second structural part h2 can be a strip or a broken line extending along the second direction Y, and the third structural part h3 can be a broken line extending along the first direction X.

[0157] In an exemplary embodiment, in the direction Z perpendicular to the plane where the substrate is located, the first structural portion h1 and the third structural portion h3 may be located on the side of the second structural portion h2 close to the substrate, or the first structural portion h1 and the third structural portion h3 may be located on the side of the second structural portion h2 away from the substrate, or the first structural portion h1 and the third structural portion h3 may be disposed in the same layer as the second structural portion h2.

[0158] In an exemplary embodiment, as shown in Figures 1a to 2, the display area AA may include a plurality of sub-pixels PX and a plurality of data lines DL. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX and are configured to provide data signals to the sub-pixels PX. At least one of the plurality of sub-pixels PX may include a pixel driving circuit, which may include a plurality of transistors and at least one capacitor.

[0159] In the direction Z perpendicular to the plane where the substrate 100 is located, the capacitor may include: a first electrode plate located on one side of the substrate 100, and a second electrode plate located on the side of the first electrode plate away from the substrate 100; the transistor may include: an active layer, a control electrode, a first electrode and a second electrode, the active layer may be located between the first electrode plate and the substrate 100, the control electrode may be disposed in the same layer as the first electrode plate, the first electrode and the second electrode may be located on the side of the second electrode plate away from the substrate 100, and the data line DL may be located on the side of the first electrode and the second electrode away from the substrate 100;

[0160] The second structural part h2 can be disposed in the same layer as at least one of the first pole, the second pole, and the data line DL. That is, the conductivity of the second structural part h2 is basically the same as the conductivity of the data line DL, which can reduce the resistance of the test signal line L11. The conductivity can be the same, or there can be some difference, but the difference is not significant.

[0161] In an exemplary embodiment, as shown in FIG2, the first electrode and the second electrode may be located in the first source-drain metal layer, and the data line DL may be located in the second source-drain metal layer or the third source-drain metal layer. That is, the second structural part h2 may be a single-layer structure or a multi-layer structure located in at least one film layer of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0162] In an exemplary embodiment, as shown in Figures 6a, 7 and 8, the second structural part h2 may be disposed on the same layer as the first electrode and the second electrode, but is not limited thereto. For example, the second structural part h2 may be a double-layer structure disposed on the same layer as the first electrode, the second electrode and the data line DL, which may further reduce the resistance of the test signal line L11, thereby improving the accuracy of the contact resistance test of the drive test pad 31c.

[0163] In an exemplary embodiment, as shown in Figures 6a and 8, the first structural portion h1 and the third structural portion h3 can be disposed on the same layer as at least one of the control electrode and the second electrode plate, or the first structural portion h1 and the third structural portion h3 can be disposed on the same layer as at least one of the first electrode, the second electrode, and the data line DL. For example, the first structural portion h1 and the third structural portion h3 can be disposed on the same layer as the control electrode, or the first structural portion h1 and the third structural portion h3 can be a double-layer structure disposed on the same layer as the control electrode and the second electrode plate, or the first structural portion h1 and the third structural portion h3 can be a double-layer structure disposed on the same layer as the first electrode, the second electrode, and the data line DL. The double-layer structure can reduce the resistance of the first structural portion h1 and the third structural portion h3, thereby reducing the resistance of the test signal line L11 and improving the accuracy of the contact resistance test of the drive test pad 31c.

[0164] In an exemplary embodiment, as shown in FIG2, the control electrode can be located in the first gate metal layer, and the second electrode plate of the capacitor can be located in the second gate metal layer. That is, the first structural part h1 and the third structural part h3 can be a single-layer structure or a double-layer structure located in at least one film layer of the first gate metal layer and the second gate metal layer; or, the first structural part h1 and the third structural part h3 can be a single-layer structure or a multi-layer structure located in at least one film layer of the first source drain metal layer, the second source drain metal layer, and the third source drain metal layer. In an exemplary embodiment, as shown in FIG2, at least one sub-pixel PX may further include a light-emitting structure layer 30. The light-emitting structure layer 30 may be located on the side of the data line DL away from the substrate 100. The light-emitting structure layer 30 may include an anode 301, a light-emitting layer 302, and a cathode 303. In the same sub-pixel PX, in the direction Z perpendicular to the plane of the substrate 100, the light-emitting layer 302 may be located between the anode 301 and the cathode 303. The second structure h2 may be disposed in the same layer as at least one of the first electrode and the second electrode, the data line DL, the anode 301, and the cathode 303. For example, the second structure h2 may be a multilayer structure disposed in the same layer as at least two of the first electrode and the second electrode, the data line DL, the anode 301, and the cathode 303. This can reduce the resistance of the second structure h2, thereby reducing the resistance of the test signal line L11.

[0165] In a structure in which the first structural portion h1 and the third structural portion h3 are located on the side of the second structural portion h2 away from the substrate 100, the first structural portion h1 and the third structural portion h3 can be disposed in the same layer as at least one of the anode and the cathode. In a double-layer structure in which the first structural portion h1 and the third structural portion h3 are disposed in the same layer as the anode and the cathode, the resistance of the first structural portion h1 and the third structural portion h3 can be reduced, thereby reducing the resistance of the test signal line L11, reducing the influence of the test signal line L11 on the contact resistance test, and improving the accuracy of the contact resistance test.

[0166] In an exemplary embodiment, as shown in Figures 2, 4b, and 6a, the first structural portion h1 and the third structural portion h3 are relatively close to the driving pad 31. The organic film layers (e.g., the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207) near the driving pad 31 and the bonding pad 32 (the structures of the bonding pad 32 and the bonding test pad 32c are basically the same as the structure of the driving pad 31) usually need to be removed. This can avoid poor contact between the driving integrated circuit and the driving pad 31, and can also avoid poor contact between the bonding pad 32 and the flexible circuit board FPC. For example, the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 in the organic insulating layer need to be removed at the positions of the driving pad 31 and the test pad 31c. The inorganic film layers (e.g., the first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204) can be retained. That is, the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 on the side of the first structural portion h1 and the third structural portion h3 away from the substrate 100 are etched away. The first structural portion h1 and the third structural portion h3 are configured as a single-layer structure or a double-layer structure located in at least one film layer of the first gate metal layer and the second gate metal layer. The first structural portion h1 and the third structural portion h3 also have an interlayer insulating layer 203 and a passivation layer 204 as protective layers on the side away from the substrate 100, which are used in the preparation of subsequent film layers (e.g., In the process of preparing subsequent film layers (which may include anode, cathode, etc.), the first structural portion h1 and the third structural portion h3 are not easily etched away; in the structure in which the first structural portion h1 and the third structural portion h3 are located in at least one film layer of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, the side of the first structural portion h1 and the third structural portion h3 away from the substrate 100 does not have a protective film layer, and are easily etched away in the process of preparing subsequent film layers (for example, the subsequent film layers may include anode, cathode, etc.).

[0167] In an exemplary embodiment, as shown in Figures 2, 4b, and 6a, the second structural portion h2 is relatively far from the driving pad 31 and the driving test pad 31c, so it will not affect the electrical connection between the driving pad 31 and the driving integrated circuit, nor will it affect the electrical connection between the bonding pad 32 and the flexible circuit board FPC. The organic film layer (which may include the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207) located on the side of the second structural portion h2 away from the substrate 100 will not be etched away. In the structure where the second structural portion h2 is located in at least one of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, at least one organic film layer is provided on the side of the second structural portion h2 away from the substrate 100 as a protective film layer (for example, in the organic film layers, at least the third planarization layer 207 is used as a protective film layer). It will not be etched away in the process of preparing subsequent film layers (for example, the subsequently prepared film layers may include anode, cathode, and other film layers).

[0168] In an exemplary embodiment, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc.

[0169] In an exemplary embodiment, the first, second, and third source-drain metal layers are typically made of materials with high conductivity and low resistance, resulting in lower resistance of the second structural portion h2 in the test signal line L11, which improves the accuracy of the contact resistance test of the drive pad 31. The conductivity of the first and second gate metal layers is typically lower than that of the first, second, and third source-drain metal layers, resulting in relatively higher resistance of the first and third structural portions h1 and h3. Therefore, the lengths of the first and third structural portions h1 and h3 can be set to be smaller than the length of the second structural portion h2 to minimize the lengths of the first and third structural portions h1 and h3 in the test signal line L11, thereby reducing the resistance of the test signal line L11.

[0170] In an exemplary embodiment, as shown in Figures 8 to 15, Figures 8 and 9 are schematic diagrams of a test group in Figure 6a, and Figures 10 to 15 are several schematic diagrams of test group C11. The same test group C11 may include at least two drive test pads 31c, at least two bonding test pads 32c, and at least two test signal lines L11. At least two drive test pads 31c can be electrically connected to at least two bonding test pads 32c through at least two test signal lines L11.

[0171] In an exemplary embodiment, as shown in Figures 9 to 15, in the same test group C11, at least two drive test pads 31c can be located adjacent to at least two bond test pads 32c, which can reduce the length of the test signal line L11 and reduce the resistance of the test signal line L11, thereby improving the accuracy of the contact resistance test of the drive test pads 31c.

[0172] In an exemplary embodiment, as shown in Figures 9 to 15, in the same test group C11: the number of test signal lines L11 and the number of drive test pads 31c are both integer multiples of 2, and the number of bonded test pads 32c is the same as the number of test signal lines L11 and not less than the number of drive test pads 31c.

[0173] In an exemplary embodiment, as shown in Figures 14 and 15, in the same test group C11, there are two drive test pads 31c, two bonding test pads 32c, and two test signal lines L11. The first ends of the two test signal lines L11 are electrically connected to the two bonding test pads 32c, and the second ends are electrically connected to the two drive test pads 31c. In this exemplary embodiment, the structure shown in Figures 14 and 15 can be used to test contact resistance using the two-wire method.

[0174] In an exemplary embodiment, the first end of the test signal line L11 is located at the end near the bonding pad 32 (i.e., away from the display area AA), and the second end of the test signal line L11 can be the end near the driving pad 31 (i.e., near the display area AA).

[0175] In an exemplary embodiment, as shown in Figures 9 and 12, within the same test group C11, there are two drive test pads 31c, four bonding test pads 32c, and four test signal lines L11. The first ends of the four test signal lines L11 are electrically connected to the four bonding test pads 32c, respectively. The second ends of two test signal lines L11 are electrically connected to one of the drive test pads 31c, and the second ends of the other two test signal lines L11 are electrically connected to the other drive test pad 31c. In this exemplary embodiment, the structure shown in Figures 9 and 12 can be used to test contact resistance using the four-wire method.

[0176] In an exemplary embodiment, as shown in Figures 10, 11, and 13, within the same test group C11, there are two drive test pads 31c, six bonding test pads 32c, and six test signal lines L11. The first ends of the six test signal lines L11 are electrically connected to the six bonding test pads 32c, respectively. The second ends of three test signal lines L11 are electrically connected to one of the drive test pads 31c, and the second ends of the other three test signal lines L11 are electrically connected to the other drive test pad 31c. In this exemplary embodiment, the structure shown in Figures 10, 11, and 13 can be used to test contact resistance using a combination of the four-wire and two-wire methods.

[0177] In an exemplary embodiment, as shown in Figures 9 to 15, the at least one test group C11 may further include a jumper wire L31, in which two drive test pads 31c can be electrically connected through the jumper wire L31.

[0178] In an exemplary embodiment, the first test group C111 typically uses the four-wire method or a combination of the four-wire and two-wire methods to test the contact resistance, and the second test group C112 typically uses the two-wire method to test the contact resistance, but is not limited thereto. For example, both the first test group C111 and the second test group C112 can use the four-wire method or a combination of the four-wire and two-wire methods to test the contact resistance.

[0179] In an exemplary embodiment, in the structures shown in Figures 9 to 11, the second structural portion h2 is a low-resistance trace region, the first structural portion h1 and the third structural portion h3 in Figures 9 and 10 are high-resistance trace regions, and the first structural portion h1 and the third structural portion h3 in Figure 11 are low-resistance trace regions. In the structure shown in Figure 11, the first structural portion h1, the second structural portion h2, and the third structural portion h3 in the test signal line L11 all adopt low-resistance trace regions, which can reduce the resistance of the test signal line L11 and improve the accuracy of contact resistance testing. In an exemplary embodiment, the length of the second structural portion h2 is greater than the length of the first structural portion h1, and the length of the second structural portion h2 is greater than the length of the third structural portion h3, although the length of the third structural portion h3 can be greater than the length of the first structural portion h1. The second structural part h2 is usually made of low-resistance material. In the structure where the first structural part h1 and the third structural part h3 are made of high-resistance material, the length of the second structural part h2 is larger, while the length of the first structural part h1 and the third structural part h3 are smaller, which can reduce the resistance of the test signal line L11.

[0180] In an exemplary embodiment, in the structures shown in Figures 9 to 11, the low-resistance trace area is typically disposed on the same layer as at least one of the first electrode, the second electrode, and the data line DL, while the high-resistance trace area is typically disposed on the same layer as at least one of the control electrode of the transistor and the second electrode of the capacitor. For example, the low-resistance trace area can be a two-layer structure disposed on the same layer as the first electrode, the second electrode, and the data line DL, and the high-resistance trace area can be a two-layer structure disposed on the same layer as the control electrode of the transistor (the first electrode of the capacitor) and the second electrode of the capacitor. In an exemplary embodiment, in the structures shown in Figures 9 to 11, the low-resistance trace area can use a low-resistance trace material, that is, a material with high conductivity is used in the low-resistance trace area, and the resistance is usually relatively low, so that the resistance of the test signal line L11 is low, thereby improving the accuracy of the contact resistance test of the drive pad 31.

[0181] In an exemplary embodiment, in the structure shown in Figures 9 to 15, test group C11 may further include jumper wire L31. In the same test group C11, there are two drive test pads 31c, and the two drive test pads 31c can be electrically connected through jumper wire L31.

[0182] In an exemplary embodiment, in the structure shown in Figures 9 to 15, as shown in Figures 9 to 13, the jumper L31 can be located in the pin PAIC of the driver integrated circuit IC. The two pins PAIC of the driver integrated circuit IC corresponding to the two drive test pads 31c are electrically connected through the jumper L31. After the driver integrated circuit IC is pressed against the drive test pads 31c, the two drive test pads 31c can be electrically connected through the jumper L31. Alternatively, a jumper L31 can be provided between two adjacent pins of the driver integrated circuit. After the driver integrated circuit is pressed against the drive test pads 31c, the jumper L31 is connected to the two drive test pads 31c. 1c electrical connection; or, as shown in Figures 14 and 15, the jumper wire L31 connects two drive test pads 31c. The structure of the drive test pads 31c can be the same as that of the drive pads 31 shown in Figure 4b. The jumper wire L31 can be disposed on the same layer as at least one of the first metal layer 1031, the second metal layer 1032, the third metal layer 1033, and the fourth metal layer 108 in the drive test pads 31c. For example, the jumper wire L31 can be an integrally formed structure with at least one of the first metal layer 1031, the second metal layer 1032, the third metal layer 1033, and the fourth metal layer 108 in the drive test pads 31c.

[0183] In an exemplary embodiment, the structures of the bonding pad 32, the bonding test pad 32c, and the drive test pad 31c can be substantially the same as the structure of the drive pad 31 shown in FIG. 4b. The first structural part h1 can be disposed on the same layer as the data lead 101 in the drive test pad 31c. For example, the first structural part h1 can be an integrally formed structure with the data lead 101 in the drive test pad 31c. The data lead 101 of the bonding test pad 32c can be replaced by the third structural part h3, that is, the third structural part h3 extends into the corresponding bonding test pad 32c and is electrically connected to the first metal layer 1031. Alternatively, the third structural part h3 can be electrically connected to the first metal layer 1031 in the bonding test pad 32c through a via. The bonding pad 32 may not be provided with a data lead 101.

[0184] In an exemplary embodiment, in the same test signal line L11, the second structural part h2 can be electrically connected to the first structural part h1 and the third structural part h3 through a via.

[0185] This disclosure also provides a contact resistance testing method for testing the contact resistance of the driving test pads 31c in the display substrate described in any of the above embodiments. As shown in Figures 1a, 1b, and 6a to 13, the display substrate may include a display area AA and a first border area B1 located on at least one side of the display area AA. The first border area B1 may include at least one test group C11. The same test group C11 may include multiple driving test pads 31c, multiple bonding test pads 32c, and multiple test signal lines L11. In the same test group C11, the multiple bonding test pads 32c may be located on the side of the driving test pads 31c away from the display area AA, and the multiple bonding test pads 32c may correspond one-to-one with the multiple test signal lines L11. One of the multiple bonding test pads 32c can be electrically connected to one of the multiple drive test pads 31c through a corresponding test signal line L11. A drive test pad 31c can be electrically connected to at least one of the multiple bonding test pads 32c through at least one of the multiple test signal lines L11. At least two of the multiple drive test pads 31c are electrically connected. The multiple drive test pads 31c can be located adjacent to the multiple bonding test pads 32c. The multiple bonding test pads 32c can include at least one first-type bonding test pad 321 and at least one second-type bonding test pad 322. The method can include:

[0186] A first electrical signal is provided to the first type of bonding test pad 321, and a second electrical signal is tested to the second type of bonding test pad 322. The first contact resistance of the drive test pad 31c is obtained based on the first and second electrical signals.

[0187] In an exemplary embodiment, the contact resistance of the drive test pad 31c refers to the contact resistance between the drive test pad 31c and the pin in the drive integrated circuit. This contact resistance can be regarded as the contact resistance between the drive pad 31c and the pin in the drive integrated circuit.

[0188] In an exemplary embodiment, as shown in Figures 9 and 12, the at least one test group C11 may further include a jumper wire L31. In the same test group C11: the number of drive test pads 31c is two, and the two drive test pads 31c can be electrically connected through the jumper wire L31; the multiple bonding test pads 32c may include two first-type bonding test pads 321 and two second-type bonding test pads 322; the multiple test signal lines L11 may include two first-type test signal lines L111 and two second-type test signal lines L112; the two first-type bonding test pads 321 can be electrically connected to the two drive test pads 31c respectively through the two first-type test signal lines L111; and the two second-type bonding test pads 322 can be electrically connected to the two drive test pads 31c respectively through the two second-type test signal lines L112.

[0189] In an exemplary embodiment, in the test group C11 shown in FIG12, providing a first electrical signal to a first type of bonding test pad 321 and testing a second electrical signal to a second type of bonding test pad 322 may include: providing a first current signal to one of the first type of bonding test pads 321, providing a ground signal to the other first type of bonding test pad 321, and testing a second voltage signal to the two second type of bonding test pads 322; the first electrical signal may include a first current signal and a ground signal, and the second electrical signal may include a second voltage signal. For example, if the first current signal is I1, and the second voltage signal obtained from the test of the two second-type bonding test pads 322 is U2, since the two second-type bonding test pads 322 are connected by a voltmeter to test the second voltage signal, and the voltmeter has a large internal resistance, it can be considered that there is an open circuit between the two second-type bonding test pads 322. The current I12 flowing through the two second-type bonding test pads 322 can be ignored, and the current flowing through the two drive test pads 31c is I11. Therefore, I1 = I11 + I12 ≈ I11. When the test signal line L11 is made of a low-resistance material, the resistance of the test signal line L11 can be ignored, and the resistance of the first-type bonding test pad 321 can also be ignored. The voltage is mainly concentrated on the two drive test pads 31c, so U2 ≈ I1 * 2 * R31c, R31c1 ≈ U2 / (2 * I1). The first contact resistance R31c1 of the drive test pad 31c is basically unaffected by the test signal line L11, and the accuracy of the contact resistance test is relatively high.

[0190] In an exemplary embodiment, as shown in the schematic diagrams of Figures 9 and 12, two first-type bonding test pads 321 may be located between two second-type bonding test pads 322.

[0191] In an exemplary embodiment, as shown in Figures 10, 11 and 13, in the same test group C11, the multiple bonding test pads 32c may further include two third-type bonding test pads 323. Figures 10, 11 and 12 show the addition of two third-type bonding test pads 323 based on Figures 9 and 12. The multiple test signal lines L11 may further include two third-type test signal lines L113. The two third-type bonding test pads 323 can be electrically connected to the two drive test pads 31c respectively through the two third-type test signal lines L113.

[0192] Before providing a first electrical signal to the first type of bonding test pad 321, or after obtaining the first contact resistance of the drive test pad 31c based on the first and second electrical signals, the method may further include: providing a third electrical signal to the third type of bonding test pad 323, testing a fourth electrical signal of the third type of bonding test pad 323, and obtaining a second contact resistance of the drive test pad 31c based on the third and fourth electrical signals.

[0193] In an exemplary embodiment, the third electrical signal may include a third voltage signal, and the fourth electrical signal may include a third current signal. The second contact resistance R31c2 of the test pad 31c is tested based on the third voltage signal and the third current signal.

[0194] In an exemplary embodiment, in the structure shown in Figures 10, 11, and 13, a third voltage signal U3 is provided to two third-type bonding test pads 323, a third current signal I3 is tested on the third-type bonding test pads 323, the second contact resistance of the driving test pad 31c is R31c2, and the resistance of the third-type test signal line L113 is RL11. Then, we have: I3*2*R31c2+I3*2*R32c+I3*2*RL11=U3. Since the resistance R32c of the bonding test pad 32c is small, when the resistance of the test signal line L11 is low, I3*2*R31c≈U3, and the second contact resistance R31c2 of the driving test pad 31c≈U3 / (2*I3). When the resistance of the test signal line L11 is high, the resistance of the test signal line L11 is RL11, then: I3*2*R31c2+I3*2*L11≈U3, the second contact resistance of the driving test pad 31c R31c2≈(U3-I3*2*L11) / (2*I3), and the resistance RL11 of the test signal line L11 can be measured in advance.

[0195] In an exemplary embodiment, the third electrical signal may include a fourth current signal, and the fourth signal may include a fourth current signal. The second contact resistance R31c2 of the test pad 31c is tested based on the fourth voltage signal and the fourth current signal.

[0196] In an exemplary embodiment, as shown in FIG13, the resistance can be measured by providing a voltage signal to the third type of bonding test pad 323, testing the current signal of the third type of bonding test pad 323, and obtaining the second contact resistance R31c2 based on the provided voltage signal and the tested current signal; or, the resistance can be measured by providing a current signal to the third type of bonding test pad 323, testing the voltage signal of the third type of bonding test pad 323, and obtaining the second contact resistance R31c2 based on the provided current signal and the tested voltage signal.

[0197] In an exemplary embodiment, the value of the contact resistance R31c of the test pad 31c can be obtained by using the first contact resistance R31c1 and the second contact resistance R31c2 of the test pad 31c. For example, the final contact resistance R31c of the test pad 31c can be the average value of the first contact resistance R31c1 and the second contact resistance R31c2, i.e., R31c = (R31c1 + R31c2) / 2.

[0198] In an exemplary embodiment, in the structure shown in Figures 14 and 15, a test group C11 may include two test signal lines L11, two bonding test pads 32c, and two drive test pads 31c. After connecting the two bonding test pads 32c with a multimeter, the resistance R is measured as R = 2R32c + 2R31c + 2RL11. The obtained resistance includes the resistance RL11 of the test signal lines L11. Contact resistance testing is inaccurate. The multimeter has a resistance range. Pad 32c is connected to the interfaces of two resistance ranges of a multimeter. For example, the multimeter can provide a current signal I to the bonding test pad 32c and test the voltage U of the two bonding test pads 32c (which can be used as first-type bonding test pads and reused as second-type bonding test pads). Then, U = I * (2R32c + 2R31c + 2RL11), and the contact resistance R31c of the driving test pad 31c = U / (2*I) - R32c - RL11. In the structures shown in Figures 14 and 15, when the test signal line L11 is made of a low-resistance metal (a metal with high conductivity), the resistance of the test signal line can be reduced, which can improve the accuracy of the contact resistance test.

[0199] In an exemplary embodiment, in the structure shown in Figures 14 and 15, a voltage U can be provided to the bonding test pad 32c, and the current signal I of the two bonding test pads 32c (which can be used as first-type bonding test pads and reused as second-type bonding test pads) can be tested. The test results of this method are basically the same as the test results of providing a current signal I to the bonding test pad 32c and testing the voltage U of the two bonding test pads 32c.

[0200] This disclosure also provides a display device, as shown in FIG16, which may include a display substrate. The display substrate may be any of the display substrates provided in the foregoing embodiments.

[0201] In one exemplary embodiment, the display device can be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), or a Light Emitting Diode (LED) display device. The display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0202] The display substrate, display device, and contact resistance testing method provided in this disclosure include a display substrate comprising a display area and a first frame area located on at least one side. The first frame area includes at least one test group, which includes multiple drive test pads, multiple bonding test pads, and multiple test signal lines. In the same test group, the bonding test pads are located on the side of the drive test pads away from the display area. Each bonding test pad corresponds one-to-one with a multiple test signal line. One bonding test pad is electrically connected to one of the drive test pads via a corresponding test signal line. One drive test pad is electrically connected to at least one bonding test pad via at least one test signal line. The multiple drive test pads are located adjacent to the multiple bonding test pads, which can minimize the length of the test signal lines, reduce their resistance, and improve the accuracy of testing the contact resistance of the drive pads. The accompanying drawings of this disclosure only illustrate the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0203] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0204] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit them. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A substrate, the substrate including a display area and a first border area located on at least one side of the display area; At least one test group is located in the first border area, and the same test group includes multiple drive test pads, multiple bonding test pads and multiple test signal lines; In the same test group: the plurality of bonding test pads are located on the side of the plurality of driving test pads away from the display area; the plurality of bonding test pads correspond one-to-one with the plurality of test signal lines; one of the bonding test pads is electrically connected to one of the driving test pads through a corresponding test signal line; one of the driving test pads is electrically connected to at least one of the bonding test pads through at least one of the plurality of test signal lines; at least two of the driving test pads are electrically connected; and the plurality of driving test pads are located adjacent to the plurality of bonding test pads.

2. The display substrate according to claim 1, further comprising: Multiple drive pads are located in the first frame region, and in a first direction, multiple drive test pads in the at least one test group are located on at least one side of the multiple drive pads; Multiple bonding pads are located in the first frame area, and the multiple bonding pads are located on the side of the multiple driving pads away from the display area. In the first direction, multiple bonding test pads in the at least one test group are located on at least one side of the multiple bonding pads. In the same test group, in the first direction, the plurality of drive test pads, the plurality of bonding test pads, and the plurality of test signal lines are located on the same side of the plurality of drive pads and the plurality of bonding pads.

3. The display substrate according to claim 2, further comprising: Multiple sub-pixels are located on one side of the substrate and in the display area; Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels, and the multiple data lines are configured to provide data signals to the multiple sub-pixels; The plurality of driving pads include a plurality of first driving pads and a plurality of second driving pads. The plurality of second driving pads are located on the side of the plurality of first driving pads away from the display area. The plurality of first driving pads are electrically connected to the plurality of data lines. At least a portion of the plurality of bonding pads are electrically connected to the plurality of second driving pads. The conductivity of at least a portion of the structure of the plurality of test signal lines in the at least one test group is consistent with the conductivity of the plurality of data lines.

4. The display substrate according to claim 3, wherein, The at least one test group includes at least one first test group and at least one second test group; In the same first test group: it includes multiple first driver test pads, multiple first bonding test pads, and multiple first test signal lines. The multiple first bonding test pads correspond one-to-one with the multiple first test signal lines. One of the multiple first bonding test pads is electrically connected to one of the multiple first driver test pads through a corresponding first test signal line. The one first driver test pad is electrically connected to at least one of the multiple first bonding test pads through at least one of the multiple first test signal lines. In the same second test group: it includes multiple second driver test pads, multiple second bonding test pads, and multiple second test signal lines. The multiple second bonding test pads correspond one-to-one with the multiple second test signal lines. One of the multiple second bonding test pads is electrically connected to one of the multiple second driver test pads through a corresponding second test signal line. The one second driver test pad is electrically connected to at least one of the multiple second bonding test pads through at least one of the multiple second test signal lines. The plurality of second drive test pads are located on the side of the plurality of first drive test pads that are away from the display area.

5. The display substrate according to claim 1, wherein, At least one of the plurality of test signal lines includes a first structural portion, a second structural portion, and a third structural portion; In the same test signal line: one end of the second structure is connected to the first structure, and the other end is connected to the third structure; the other end of the first structure is electrically connected to one of the plurality of drive test pads, and the other end of the third structure is electrically connected to the corresponding bonding test pad.

6. The display substrate according to claim 5, wherein, In a direction perpendicular to the plane of the substrate, the first structural portion and the third structural portion are located on the side of the second structural portion closer to the substrate, or the first structural portion and the third structural portion are located on the side of the second structural portion away from the substrate, or the first structural portion and the third structural portion are disposed in the same layer as the second structural portion.

7. The display substrate according to claim 5, wherein, The display area includes multiple sub-pixels and multiple data lines, the multiple data lines being electrically connected to the multiple sub-pixels and configured to provide data signals to the multiple sub-pixels; at least one of the multiple sub-pixels includes a pixel driving circuit, the pixel driving circuit including multiple transistors and at least one capacitor; In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer, a control electrode, a first electrode, and a second electrode, the active layer being located between the first electrode plate and the substrate, the control electrode being disposed on the same layer as the first electrode plate, the first electrode and the second electrode being located on the side of the second electrode plate away from the substrate, and the data line being located on the side of the first electrode and the second electrode away from the substrate; The second structural part is disposed on the same layer as at least one of the first pole, the second pole, and the data line.

8. The display substrate according to claim 7, wherein, The first structural portion and the third structural portion are disposed on the same layer as at least one of the control electrode and the second electrode plate, or the first structural portion and the third structural portion are disposed on the same layer as at least one of the first electrode, the second electrode, and the data line.

9. The display substrate according to any one of claims 1 to 8, wherein, The same test group includes at least two drive test pads, at least two bonding test pads, and at least two test signal lines. The at least two drive test pads are electrically connected to the at least two bonding test pads through the at least two test signal lines.

10. The display substrate according to claim 9, wherein, In the same test group: the number of test signal lines and the number of drive test pads are both integer multiples of 2, the number of bonding test pads is the same as the number of test signal lines, and not less than the number of drive test pads.

11. The display substrate according to claim 10, wherein, In the same test group, there are two drive test pads, two bonding test pads, and two test signal lines. The first end of each of the two test signal lines is electrically connected to the two bonding test pads, and the second end is electrically connected to the two drive test pads.

12. The display substrate according to claim 10, wherein, In the same test group, there are two drive test pads, four bonding test pads, and four test signal lines. The first ends of the four test signal lines are electrically connected to the four bonding test pads, the second ends of two of the test signal lines are electrically connected to one of the drive test pads, and the second ends of the other two test signal lines are electrically connected to the other drive test pad.

13. The display substrate according to claim 10, wherein, In the same test group, there are two drive test pads, six bonding test pads and six test signal lines. The first end of each of the six test signal lines is electrically connected to one of the six bonding test pads, the second end of three of the test signal lines is electrically connected to one of the drive test pads, and the second end of the other three of the test signal lines is electrically connected to the other drive test pad.

14. The display substrate according to any one of claims 1 to 8, wherein, The at least one test group further includes a jumper wire, and in the same test group, there are two drive test pads, which are electrically connected through the jumper wire.

15. A display device comprising a display substrate as described in any one of claims 1 to 14.

16. A contact resistance testing method for testing the contact resistance of driving test pads in a display substrate as described in any one of claims 1 to 14, the display substrate including a display area and a first frame area located on at least one side of the display area, the first frame area including at least one test group, the same test group including a plurality of driving test pads, a plurality of bonding test pads and a plurality of test signal lines; in the same test group, the plurality of bonding test pads are located on the side of the plurality of driving test pads away from the display area, the plurality of bonding test pads correspond one-to-one with the plurality of test signal lines, one of the plurality of bonding test pads is electrically connected to one of the plurality of driving test pads through a corresponding test signal line, the one driving test pad is electrically connected to at least one of the plurality of bonding test pads through at least one of the plurality of test signal lines, at least two of the plurality of driving test pads are electrically connected, the plurality of driving test pads are located adjacent to the plurality of bonding test pads, the plurality of bonding test pads include at least one type of bonding test pad and at least one type of bonding test pad; the method includes: A first electrical signal is provided to the first type of bonding test pad, a second electrical signal is tested to the second type of bonding test pad, and a first contact resistance of the drive test pad is obtained based on the first electrical signal and the second electrical signal.

17. The contact resistance testing method according to claim 16, wherein, The at least one test group further includes a jumper wire; in the same test group: the number of drive test pads is two, the two drive test pads are electrically connected through the jumper wire, the plurality of bonding test pads include two first-type bonding test pads and two second-type bonding test pads, the plurality of test signal lines include two first-type test signal lines and two second-type test signal lines, the two first-type bonding test pads are electrically connected to the two drive test pads respectively through the two first-type test signal lines, and the two second-type bonding test pads are electrically connected to the two drive test pads respectively through the two second-type test signal lines.

18. The contact resistance testing method according to claim 17, wherein, Providing a first electrical signal to the first type of bonding test pad and testing a second electrical signal to the second type of bonding test pad includes: providing a first current signal to one of the first type of bonding test pads, providing a ground signal to the other first type of bonding test pad, and testing a second voltage signal to the two second type of bonding test pads; the first electrical signal includes the first current signal and the ground signal, and the second electrical signal includes the second voltage signal.

19. The contact resistance testing method according to any one of claims 17 to 18, wherein, In the same test group, the plurality of bonding test pads also include two third-type bonding test pads, and the plurality of test signal lines also include two third-type test signal lines. The two third-type bonding test pads are electrically connected to the two drive test pads respectively through the two third-type test signal lines. Before providing a first electrical signal to the first type of bonding test pad, or after obtaining the first contact resistance of the drive test pad based on the first electrical signal and the second electrical signal, the method further includes: providing a third electrical signal to the third type of bonding test pad, testing a fourth electrical signal of the third type of bonding test pad, and obtaining a second contact resistance of the drive test pad based on the third electrical signal and the fourth electrical signal.

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