Pixel circuit, display panel, and display device

Abstract

The present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a display panel, and a display device. The pixel circuit (200) comprises: a driving sub-circuit (10), configured to generate a driving current on the basis of a first power supply voltage (VDD) from a first power supply and a data signal (Vdata) from a data terminal under the control of a first control signal (CON1) from a first control terminal and a second control signal (CON2) from a second control terminal, and provide the driving current to a first node (N1); a control sub-circuit (20), configured to provide the driving current to at least one of a second node (N2) and a third node (N3) under the control of a third control signal (CON3) from a third control terminal and a fourth control signal (CON4) from a fourth control terminal; a first light-emitting element (30), a first terminal of the first light-emitting element (30) being electrically connected to the second node (N2), and a second terminal of the first light-emitting element (30) being electrically connected to a second power supply (VSS); and a second light-emitting element (40), a first terminal of the second light-emitting element (40) being electrically connected to the third node (N3), and a second terminal of the second light-emitting element (40) being electrically connected to the second power supply (VSS).

Description

Pixel circuits, display panels and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a pixel circuit, a display panel, and a display device. Background Technology

[0002] With the development of display and semiconductor technologies, end-users' demands for display functions are becoming increasingly diversified. For example, in the use of in-vehicle display devices, as well as electronic devices such as mobile phones, tablets, and computers, end-users require the display panels of these devices to provide functions such as active privacy protection and dual-view display. Summary of the Invention

[0003] This disclosure provides a pixel circuit, a display panel, and a display device.

[0004] One aspect of this disclosure provides a pixel circuit, comprising: a driving sub-circuit configured to generate a driving current based on a first power supply voltage from a first power source and a data signal from a data source, under the control of a first control signal from a first control terminal and a second control signal from a second control terminal, and to provide the driving current to a first node; a control sub-circuit configured to provide the driving current to at least one of a second node and a third node, under the control of a third control signal from a third control terminal and a fourth control signal from a fourth control terminal; a first light-emitting element, a first end of which is electrically connected to the second node, and a second end of which is electrically connected to a second power source; and a second light-emitting element, a first end of which is electrically connected to the third node, and a second end of which is electrically connected to the second power source.

[0005] Another aspect of this disclosure provides a display panel including a display area and a non-display area, wherein the display area is provided with a plurality of pixel circuits as described above.

[0006] Another aspect of this disclosure provides a display device including a display panel as described above. Attached Figure Description

[0007] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1A shows a schematic diagram of a unit pixel array arranged in Real-RGB.

[0009] Figure 1B shows a schematic diagram of the display of the segmented unit pixels.

[0010] Figure 2 schematically illustrates a pixel circuit according to an embodiment of the present disclosure.

[0011] Figure 3A schematically illustrates the structure of a control sub-circuit according to an embodiment of the present disclosure.

[0012] Figure 3B schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0013] Figure 4A schematically illustrates a pixel circuit according to another embodiment of the present disclosure.

[0014] Figure 4B schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0015] Figure 4C schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0016] Figure 4D schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0017] Figure 4E schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0018] Figure 4F schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0019] Figure 5A schematically illustrates the structure of a driver sub-circuit according to an embodiment of the present disclosure.

[0020] Figure 5B schematically illustrates a pixel circuit according to another embodiment of the present disclosure.

[0021] Figure 5C schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0022] Figure 5D schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0023] Figure 6A schematically illustrates the structure of a pixel circuit according to an embodiment of the present disclosure.

[0024] Figure 6B schematically illustrates the timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0025] Figure 6C schematically illustrates the timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0026] Figure 7A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0027] Figure 7B schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0028] Figure 7C schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0029] Figure 7D schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0030] Figure 8A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0031] Figure 8B schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0032] Figure 8C schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0033] Figure 8D schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0034] Figure 8E schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0035] Figure 8F schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0036] Figure 9A schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0037] Figure 9B schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0038] Figure 10A schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0039] Figure 10B schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0040] Figure 10C schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0041] Figure 10D schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0042] Figure 11A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0043] Figure 11B schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0044] Figure 11C schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0045] Figure 11D schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0046] Figure 12A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0047] Figure 12B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0048] Figure 13A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0049] Figure 13B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0050] Figure 13C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0051] Figure 14A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0052] Figure 14B shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0053] Figure 14C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0054] Figure 14D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0055] Figure 14E shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0056] Figure 15A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0057] Figure 15B shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0058] Figure 15C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0059] Figure 15D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0060] Figure 15E shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0061] Figure 16A shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0062] Figure 16B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0063] Figure 16C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0064] Figure 16D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0065] Figure 17 schematically illustrates a display panel according to an embodiment of the present disclosure.

[0066] Figure 18 schematically illustrates a display device according to an embodiment of the present disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0068] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0069] Furthermore, in the description of embodiments of this disclosure, the term "electrical connection" can refer to a direct connection between two components, or it can refer to a connection between two components via one or more other components. Moreover, these two components can be connected or coupled via wired or wireless means.

[0070] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to its function, one of the source and drain can be called the first terminal, and the other of the source and drain can be called the second terminal.

[0071] It should be noted that, in the description of the embodiments of this disclosure, the symbol VDD can represent either the first power supply or the first power supply voltage provided by the first power supply. Similarly, the symbol CON1 can represent either the first control terminal or the first control signal provided by the first control terminal; the symbol CON2 can represent either the second control terminal or the second control signal provided by the second control terminal; the symbol CON3 can represent either the third control terminal or the third control signal provided by the third control terminal; the symbol CON4 can represent either the fourth control terminal or the fourth control signal provided by the fourth control terminal; the symbol Vdata can represent either the data terminal or the data signal provided by the data terminal, and so on. The following embodiments are the same and will not be described again.

[0072] To achieve display functions such as active privacy protection and dual-view display, one optional approach is to divide the sub-pixels within the deployed unit pixel, thereby forming a unit pixel containing twice the number of sub-pixels. For example, a unit pixel before division might contain three sub-pixels for displaying red, green, and blue, respectively. A unit pixel after division might contain two sub-pixels for displaying red, two for displaying green, and two for displaying blue. Alternatively, the sub-pixels within a unit pixel can be divided into a shared sub-pixel and multiple privacy protection sub-pixels. For example, a unit pixel before division might contain a sub-pixel A for displaying red. This sub-pixel A can be divided into sub-pixels A1, A2, and A3. Sub-pixels A1 can emit light when implementing shared display functionality, while sub-pixels A2 and A3 can emit light when implementing dual-view display, active privacy protection, and shared display functionality. For example, sub-pixel A2 can provide display functions that allow leftward display and rightward privacy protection, while sub-pixel A3 can provide display functions that allow rightward display and leftward privacy protection. When sub-pixels A2 and A3 emit light based on the same image, they can provide shared display functionality. The method for segmenting sub-pixels is not limited here.

[0073] The following example illustrates the relevant technical solutions by dividing a sub-pixel in a unit pixel into two sub-pixels.

[0074] Figure 1A shows a schematic diagram of a unit pixel array arranged in Real-RGB.

[0075] As shown in Figure 1, the unit pixel array may include multiple segmented unit pixels 110. Each segmented unit pixel 110 may include sub-pixels 111, 112, 113, 114, 115, and 116. Sub-pixels 111 and 112 may be used to display the same color, for example, red; sub-pixels 113 and 114 may be used to display the same color, for example, green; and sub-pixels 115 and 116 may be used to display the same color, for example, blue.

[0076] Subpixels 111, 112, 113, 114, 115, and 116 can be privacy subpixels. Specifically, when operating in privacy display mode or dual-view display mode, subpixels 111, 113, and 115 can be used to display screen A in the first direction but not in the second direction, while subpixels 112, 114, and 116 can be used to display screen B in the second direction but not in the first direction.

[0077] Alternatively, subpixels 111, 113, and 115 can be privacy subpixels, while subpixels 112, 114, and 116 can be shared subpixels. In shared display mode, only subpixels 111, 113, and 115 can be enabled, or all subpixels 111, 112, 113, 114, 115, and 116 can be enabled simultaneously. In this case, subpixels 111, 112, 113, 114, 115, and 116 can display the same image. In privacy display mode, only subpixels 112, 114, and 116 can be enabled.

[0078] An occlusion layer can be placed above the sub-pixels, and this occlusion layer can contain black matrices. The number of black matrices in the occlusion layer is not limited here; for example, the number of black matrices can be the same as the number of sub-pixels contained in the segmented unit pixel. For instance, if the segmented unit pixel can include 6 sub-pixels, then the region of the occlusion layer opposite to that unit pixel can contain 6 black matrices. Alternatively, the number of black matrices in the occlusion layer can also be the same as the number of privacy sub-pixels contained in the segmented unit pixel, and so on.

[0079] The orthographic projection of the black matrix onto the pixel array can be located to one side of a sub-pixel, thus preventing light emitted by that sub-pixel from propagating in that direction. For example, if the orthographic projection of black matrix a1 onto the pixel array is located to the left of sub-pixel a2, then black matrix a1 can prevent light emitted by sub-pixel a2 from propagating to the left. The relative positional relationship between the black matrix and the sub-pixels can be set according to the needs of the actual application scenario and is not limited here.

[0080] Optionally, if the sub-pixels obtained by segmenting a unit pixel include shared sub-pixels, the orthographic projection area of ​​the shared sub-pixel on the occlusion layer can be provided with an opening so that the light emitted by the shared sub-pixel can pass freely through the occlusion layer without being blocked by the black matrix.

[0081] Taking the example that the occlusion layer contains six black matrices corresponding to sub-pixels 111, 112, 113, 114, 115, and 116 respectively, Figure 1B shows a schematic diagram of the display of the segmented unit pixels.

[0082] As shown in Figure 1B, the orthographic projections of three of the six black matrices corresponding to each segmented unit pixel 110 in the occlusion layer onto the unit pixel array can be located to the right of sub-pixels 111, 113, and 115, respectively. Therefore, these three black matrices can be used to prevent the light emitted by sub-pixels 111, 113, and 115 from propagating to the right, meaning that sub-pixels 111, 113, and 115 can display image A only from the left perspective. The orthographic projections of the other three black matrices of the six black matrices corresponding to each segmented unit pixel 110 in the occlusion layer onto the unit pixel array can be located to the left of sub-pixels 112, 113, and 116, respectively. Therefore, these other three black matrices can be used to prevent the light emitted by sub-pixels 112, 114, and 116 from propagating to the left, meaning that sub-pixels 112, 114, and 116 can display image B only from the right perspective. By segmenting unit pixels and occluding them with a black matrix in the occlusion layer, a dual-display effect can be achieved. The left side of a sub-pixel can be represented as one side along the row direction of the unit pixel array, and the right side of a sub-pixel can be represented as the other side along the row direction of the unit pixel array. Optionally, in other examples, the orthographic projection of the black matrix onto the unit pixel array can also be located on one or the other side of the sub-pixel along the column direction of the unit pixel array, or it can be located on one or the other side of the sub-pixel in a direction different from the row and column directions of the unit pixel array, which will not be elaborated here.

[0083] In related technologies, a subpixel is typically implemented by a single pixel circuit. However, the number of subpixels in a segmented unit pixel is twice the number in the original unit pixel. Without reducing resolution, it's difficult to deploy more pixel circuits within a single unit pixel. Therefore, to reduce the number of pixel circuits required, a single pixel circuit can be used to implement multiple subpixels for displaying the same color.

[0084] In view of the above, embodiments of this disclosure provide a pixel circuit, which may include: a driving sub-circuit configured to generate a driving current based on a first power supply voltage from a first power supply and a data signal from a data terminal, and provide the driving current to a first node under the control of a first control signal from a first control terminal and a second control signal from a second control terminal; a control sub-circuit configured to provide the driving current to at least one of a second node and a third node under the control of a third control signal from a third control terminal and a fourth control signal from a fourth control terminal; a first light-emitting element, a first end of which is electrically connected to the second node and a second end of which is electrically connected to the second power supply; and a second light-emitting element, a first end of which is electrically connected to the third node and a second end of which is electrically connected to the second power supply.

[0085] Figure 2 schematically illustrates a pixel circuit according to an embodiment of the present disclosure.

[0086] As shown in Figure 2, the pixel circuit 200 may include a driving sub-circuit 10, a control sub-circuit 20, a first light-emitting element 30, and a second light-emitting element 40.

[0087] The driving sub-circuit 10 can be electrically connected to the first power supply VDD, the data terminal Vdata, the first control terminal CON1, and the second control terminal CON2, respectively, and is electrically connected to the control sub-circuit 20 through the first node N1. Under the control of the first control signal CON1 from the first control terminal CON1 and the second control signal CON2 from the second control terminal CON2, the driving sub-circuit 10 can generate a driving current Id based on the first power supply voltage VDD from the first power supply VDD and the data signal Vdata from the data terminal Vdata, and provide the driving current Id to the first node N1.

[0088] The driving sub-circuit 10 may be configured with at least a driving transistor. By providing timing signals to the first control terminal CON1 and the second control terminal CON2, the driving sub-circuit 10 can form a driving current Id between the source and drain of the driving transistor based on the first power supply voltage VDD and the data signal Vdata, and provide the driving current Id to the first node N1.

[0089] The control sub-circuit 20 can be electrically connected to the third control terminal CON3 and the fourth control terminal CON4 respectively, and is electrically connected to the first light-emitting element 30 through the second node N2, and to the second light-emitting element 40 through the third node N3. Under the control of the third control signal CON3 from the third control terminal CON3 and the fourth control signal CON4 from the fourth control terminal CON4, the control sub-circuit 20 can provide a driving current Id to at least one of the second node N2 and the third node N3, thereby providing the driving current Id to at least one of the first light-emitting element 30 and the second light-emitting element 40.

[0090] The selection control logic for the drive current Id in the control sub-circuit 20 is not limited here. For example, the control sub-circuit 20 can provide the drive current Id to the first light-emitting element 30 when the third control signal CON3 is valid, and provide the drive current Id to the second light-emitting element 40 when the fourth control signal CON4 is valid. As another example, the control sub-circuit 20 can provide the drive current Id to the first light-emitting element 30 when the third control signal CON3 is valid, and provide the drive current Id to the second light-emitting element 40 when both the third control signal CON3 and the fourth control signal CON4 are valid.

[0091] The first end of the first light-emitting element 30 can be electrically connected to the second node N2, and the second end can be electrically connected to the second power supply VSS. The first end of the second light-emitting element 40 can be electrically connected to the third node N3, and the second end can be electrically connected to the second power supply VSS.

[0092] Compared to the second power supply voltage VSS provided by the second power supply VSS, the first power supply voltage VDD provided by the first power supply VDD can be a relatively high voltage, and the second power supply voltage VSS can be a relatively low voltage.

[0093] The first light-emitting element 30 and the second light-emitting element 40 can be any current-driven light-emitting device, such as OLED (Organic Light-Emitting Diode), AMOLED (Active-matrix organic light-emitting diode), QLED (Quantum Dot Light-Emitting Diode), etc. Optionally, the first end of the first light-emitting element 30 or the second light-emitting element 40 can be represented as the anode of the first light-emitting element 30 or the second light-emitting element 40, and the second end of the first light-emitting element 30 or the second light-emitting element 40 can be represented as the cathode of the first light-emitting element 30 or the second light-emitting element 40.

[0094] According to embodiments of this disclosure, the driving sub-circuit can generate a driving current based on the timing signals provided in the first control terminal and the second control terminal, and provide the driving current to the control sub-circuit. The control sub-circuit can provide the driving current to at least one of the first light-emitting element and the second light-emitting element based on the different potential states of the third control signal and the fourth control signal, so that the pixel circuit can control the first light-emitting element and the second light-emitting element to emit light synchronously or asynchronously, so that the pixel circuit can realize display functions such as privacy protection and dual-view.

[0095] Optionally, in the embodiments of this disclosure, the pixel circuit including a first light-emitting element 30 and a second light-emitting element 40 is merely an example. Depending on actual needs, by adjusting the control sub-circuit, the control sub-circuit can also control the drive current to be supplied to three or more light-emitting elements, which will not be elaborated here. The following uses the example of a pixel circuit including a first light-emitting element 30 and a second light-emitting element 40 to further illustrate the pixel circuit of the embodiments of this disclosure.

[0096] Figure 3A schematically illustrates the structure of a control sub-circuit according to an embodiment of the present disclosure.

[0097] As shown in Figure 3A, the control sub-circuit 20 may include a first transistor T1 and a second transistor T2. Both the first transistor T1 and the second transistor T2 may be P-type switching transistors.

[0098] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0099] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the third node N3, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0100] When the third control signal CON3 is low and the fourth control signal CON4 is high, the driving current Id can be transmitted from the first node N1 to the third node N3 via the first transistor T1. In other words, the driving current Id can be supplied to the second light-emitting unit 40 to drive it to emit light. At this time, the first light-emitting unit 30 is off, the second light-emitting unit 40 is on, and the pixel circuit can operate in privacy mode.

[0101] When both the third control signal CON3 and the fourth control signal CON4 are low, the driving current Id can still be transmitted from the first node N1 through the first transistor T1 and the second transistor T2 to the second node N2. That is, the driving current Id can be provided to the second light-emitting unit 40 and the first light-emitting unit 30 respectively, so as to drive the second light-emitting unit 40 and the first light-emitting unit 30 to emit light. At this time, both the first light-emitting unit 30 and the second light-emitting unit 40 are turned on, and the pixel circuit can work in a dual-view display mode.

[0102] In the circuit structure of the control sub-circuit 20 shown in Figure 3A, the activation of the first light-emitting unit 30 and the second light-emitting unit 40 both require the first transistor T1 to be turned on, which means that the second light-emitting unit 40 cannot be turned on and off independently. That is, when the first light-emitting unit 30 needs to be turned on, the second light-emitting unit 40 will also be turned on at the same time, which affects the control flexibility of the pixel circuit and makes the pixel circuit suitable for application scenarios dominated by dual-view display mode.

[0103] Figure 3B schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0104] As shown in Figure 3B, the control sub-circuit 20 may include a first transistor T1 and a second transistor T2. Both the first transistor T1 and the second transistor T2 may be P-type switching transistors.

[0105] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0106] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0107] When the third control signal CON3 is low, the driving current Id can be transmitted from the first node N1 to the third node N3 via the first transistor T1. This means the driving current Id can be supplied to the second light-emitting unit 40 to drive it to emit light. When the third control signal CON4 is low, the driving current Id can be transmitted from the first node N1 to the second node N2 via the second transistor T2. This means the driving current Id can be supplied to the first light-emitting unit 30 to drive it to emit light. Therefore, both the first light-emitting unit 30 and the second light-emitting unit 40 can be controlled independently. The pixel circuit can be applied to privacy and dual-display applications, and the corresponding application scenarios can be switched arbitrarily.

[0108] The first light-emitting unit 30 and the second light-emitting unit 40 are typically light-emitting diodes (LEDs). Due to the capacitive effect of diodes, a residual voltage usually remains in the first light-emitting unit 30 and the second light-emitting unit 40 after they stop emitting light. Optionally, to eliminate the residual voltage, a reset structure can be provided in the control sub-circuit 20. Before the pixel circuit controls the first light-emitting unit 30 and / or the second light-emitting unit 40 to emit light, the reset structure can reset the potential at the first light-emitting unit 30 and / or the second light-emitting unit 40.

[0109] Figure 4A schematically illustrates a pixel circuit according to another embodiment of the present disclosure.

[0110] As shown in Figure 4A, based on the pixel circuit 200, the control sub-circuit 20 of the pixel circuit 400 can also be electrically connected to the first reset terminal Vinit1 and the fifth control terminal CON5 respectively.

[0111] Under the control of the fifth control signal CON5 from the fifth control terminal CON5, the potential of at least one of the second node N2 and the third node N3 is reset using the first reset signal Vinit1 from the first reset terminal Vinit1.

[0112] The first reset signal Vinit1 can be a signal with a lower potential level relative to the first power supply voltage VDD.

[0113] Figure 4B schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0114] As shown in Figure 4B, the control sub-circuit shown in Figure 3A may also include a third transistor T3. The third transistor T3 may be a P-type switching transistor.

[0115] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0116] When resetting the first light-emitting element 30, the fifth control signal CON5 is low and controls the third transistor T3 to turn on. The first reset signal Vinit1 is provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30.

[0117] When resetting the second light-emitting element 40, the fifth control signal CON5 is low and controls the third transistor T3 to turn on, the fourth control signal CON4 is low and controls the second transistor T2 to turn on, and the first reset signal Vinit1 can also be provided to the third node N3 via the third transistor T3 and the second transistor T2 to reset the second light-emitting element 40.

[0118] Figure 4C schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0119] As shown in Figure 4C, similarly, the control sub-circuit shown in Figure 3B can also include a third transistor T3. The third transistor T3 can be a P-type switching transistor.

[0120] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0121] When resetting the first light-emitting element 30, the fifth control signal CON5 is low and controls the third transistor T3 to turn on. The first reset signal Vinit1 is provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30.

[0122] When resetting the second light-emitting element 40, the fifth control signal CON5 is low and controls the third transistor T3 to turn on, the fourth control signal CON4 is low and controls the second transistor T2 to turn on, the third control signal CON3 is low and controls the first transistor T1 to turn on, and the first reset signal Vinit1 can also be provided to the third node N3 via the third transistor T3, the second transistor T2 and the first transistor T1 to reset the second light-emitting element 40.

[0123] When resetting the control sub-circuit shown in Figures 4B and 4C, each light-emitting element is usually reset individually. Alternatively, a transistor can be added to the control sub-circuit so that the first light-emitting element 30 and the second light-emitting element 40 can be reset at the same time, thereby reducing the time required for reset, extending the charging time of the device, and thus improving image quality and reducing image retention.

[0124] Figure 4D schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0125] As shown in Figure 4D, the control sub-circuit shown in Figure 4C may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0126] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0127] During the reset process, the fifth control signal CON5 is high, which controls the third transistor T3 and the fourth transistor T4 to turn on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30, and to the third node N3 via the third transistor T3 and the fourth transistor T4 to reset the second light-emitting element 40.

[0128] Figure 4E schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0129] As shown in Figure 4E, the control sub-circuit shown in Figure 4C may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0130] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1.

[0131] During the reset process, the fifth control signal CON5 is high, which controls the third transistor T3 and the fourth transistor T4 to turn on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30. The first reset signal Vinit1 can also be provided to the third node N3 via the fourth transistor T4 to reset the second light-emitting element 40.

[0132] Figure 4F schematically illustrates the structure of a control sub-circuit according to another embodiment of the present disclosure.

[0133] As shown in Figure 4F, the control sub-circuit shown in Figure 4C may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0134] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3. The third reset terminal Vinit3 can provide a third reset signal Vinit3, which is different from the first reset signal Vinit1. That is, the third reset signal Vinit3 and the first reset signal Vinit1 can be provided by two different signal sources.

[0135] During the reset process, the fifth control signal CON5 is high, which controls the third transistor T3 and the fourth transistor T4 to turn on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the first light-emitting element 30. The third reset signal Vinit3 can be provided to the third node N3 via the fourth transistor T4 to reset the second light-emitting element 40.

[0136] Alternatively, the driver sub-circuit can be implemented based on a non-discrete circuit.

[0137] Figure 5A schematically illustrates the structure of a driver sub-circuit according to an embodiment of the present disclosure.

[0138] As shown in Figure 5A, the non-discrete drive sub-circuit may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The fifth transistor T5 through the eighth transistor T8 may all be P-type transistors, and the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 may be switching transistors, while the sixth transistor T6 may be a driving transistor.

[0139] The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata.

[0140] The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0141] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0142] The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4.

[0143] The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0144] When the driver sub-circuit 10 is operating, the first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to turn on. The data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7. After charging the first capacitor C1 is complete, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to turn off. The second control signal is low, controlling the eighth transistor T8 to turn on. The charge stored in the first capacitor C1 can be applied to the gate of the sixth transistor T6, causing the sixth transistor T6 to turn on, thereby forming a drive current Id between the source and drain of the sixth transistor T6.

[0145] Alternatively, similar to the control sub-circuit, the first capacitor C1 usually retains voltage after discharge. In order to eliminate the residual voltage, the drive sub-circuit 10 can be provided with a reset structure. Before the first capacitor C1 is charged again, the reset structure can reset the potential of the first capacitor.

[0146] Figure 5B schematically illustrates a pixel circuit according to another embodiment of the present disclosure.

[0147] As shown in Figure 5B, based on the pixel circuit 400, the driving sub-circuit 10 of the pixel circuit 500 can also be electrically connected to the second reset terminal Vinit2 and the sixth control terminal CON6 respectively.

[0148] Under the control of the sixth control signal CON6 from the sixth control terminal CON6, the drive sub-circuit 10 can use the second reset signal Vinit2 from the second reset terminal Vinit2 to reset the potential of the first capacitor C1.

[0149] The second reset signal Vinit2 can be a signal with a lower potential level relative to the first power supply voltage VDD. The second reset signal Vinit2 and the first reset signal Vinit1 can be the same signal or different signals, which is not limited here.

[0150] Optionally, in some embodiments, the second reset signal Vinit2 can also be used to reset the second light-emitting unit 40 and / or the first light-emitting unit 30.

[0151] Figure 5C schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0152] As shown in Figure 5C, the driving sub-circuit shown in Figure 5A can also include a ninth transistor T9. The ninth transistor T9 can be a P-type switching transistor.

[0153] The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first terminal of the ninth transistor T9 is electrically connected to the fifth node N5, and the second terminal of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2.

[0154] Before the drive sub-circuit 10 operates, the sixth control signal CON6 is low and controls the ninth transistor T9 to turn on. The second reset signal Vinit2 can be provided to the fifth node N5 through the ninth transistor T9 to reset the first capacitor C1.

[0155] Figure 5D schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0156] As shown in Figure 5D, the driving sub-circuit shown in Figure 5A can also include a ninth transistor T9. The ninth transistor T9 can be a P-type switching transistor.

[0157] The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2.

[0158] Before the driving sub-circuit 10 operates, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, and the first control signal CON1 is low, controlling the seventh transistor T7 to turn on. The second reset signal Vinit2 can be provided to the fifth node N5 via the ninth transistor T9 and the seventh transistor T7 to reset the first capacitor C1. The pixel circuit of this embodiment will be further described below with reference to the circuit structures shown in Figures 3A-3B, 4A-4F, and 5A-5D.

[0159] Figure 6A schematically illustrates the structure of a pixel circuit according to an embodiment of the present disclosure.

[0160] As shown in Figure 6A, the pixel circuit 600 may include first transistors T1 to third transistors T3, fifth transistors T5 to ninth transistors T9, a first capacitor C1, a first light-emitting diode LED1, and a second light-emitting diode LED2. Among these, first transistors T1 to third transistor T3, fifth transistor T5, and seventh transistors T7 to ninth transistor T9 can be P-type switching transistors, and sixth transistor T6 can be a P-type driving transistor.

[0161] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the third node N3, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first terminal of the fifth transistor T5 is electrically connected to the fourth node N4, and the second terminal of the fifth transistor T5 is electrically connected to the data terminal Vdata. The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the first node N1. The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4. The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first terminal of the ninth transistor T9 is electrically connected to the fifth node N5, and the second terminal of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2. The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0162] According to embodiments of this disclosure, when the pixel circuit 600 needs to operate in a shared display mode, the first light-emitting diode LED1 and the second light-emitting diode LED2 can be controlled to emit light. When the pixel circuit 600 needs to operate in a privacy display mode, the first light-emitting diode LED1 can be controlled to turn off, while the second light-emitting diode LED2 can be controlled to emit light. The pixel circuit 600 can use fewer transistors to implement functions such as shared display and privacy display, thereby supporting higher image resolution and simplifying the control logic of the reset process, reducing control costs.

[0163] Figure 6B schematically illustrates the timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0164] As shown in Figure 6B, the pixel circuit 600 can operate based on the privacy mode during stages P1 to P3.

[0165] In phase P1, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset using the second reset signal Vinit2; the fifth control signal CON5 is low, controlling the third transistor T3 to turn on, thereby pulling the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset using the first reset signal Vinit1; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on, thereby pulling the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0166] In phase P2, the fourth control signal CON4, the fifth control signal CON5, and the sixth control signal CON6 are all high, controlling the second transistor T2, the third transistor T3, and the ninth transistor T9 to be off. The first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to be on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7. When the voltage across the driving transistor T6 is Vgs = V(Q1) - V(Q2) = V(Q1) - Vdata = Vth, the sixth transistor T6 is off, and the voltage maintained by the first capacitor C1 at this time is V(N5) = Vdata + Vth.

[0167] In stage P3, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to be off; the second control signal CON2 is low, controlling the eighth transistor T8 to be on; and the third control signal CON3 is low, controlling the first transistor T1 to be on. Driven by the first power supply voltage VDD and the voltage V(N5) of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the second light-emitting diode LED2 through the first transistor T1 and the third node N3 to control the second light-emitting diode LED2 to emit light, thereby realizing the privacy display function of the pixel circuit 600.

[0168] Figure 6C schematically illustrates the timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0169] As shown in Figure 6C, the pixel circuit 600 can operate based on dual-view mode during stages P4 to P6.

[0170] In stage P4, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset using the second reset signal Vinit2; the fifth control signal CON5 is low, controlling the third transistor T3 to turn on, thereby pulling the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset using the first reset signal Vinit1; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on, thereby pulling the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0171] In phase P5, the fourth control signal CON4, the fifth control signal CON5, and the sixth control signal CON6 are all high, controlling the second transistor T2, the third transistor T3, and the ninth transistor T9 to be off. The first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to be on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7. When the voltage across the driving transistor T6 is Vgs = V(Q1) - V(Q2) = V(Q1) - Vdata = Vth, the sixth transistor T6 is off, and the voltage maintained by the first capacitor C1 at this time is V(N5) = Vdata + Vth.

[0172] In stage P6, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to be off; the second control signal CON2 is low, controlling the eighth transistor T8 to be on; the third control signal CON3 is low, controlling the first transistor T1 to be on; and the fourth control signal CON4 is low, controlling the second transistor T2 to be on. Driven by the first power supply voltage VDD and the voltage V(N5) of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current I can be supplied to the second light-emitting diode LED2 through the first transistor T1 and the third node N3, and to the first light-emitting diode LED1 through the first transistor T2, the second transistor T2, and the second node N2, thereby controlling the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light, realizing the dual-view display function of the pixel circuit 600.

[0173] Figure 7A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0174] As shown in Figure 7A, the pixel circuit 700 may include first transistors T1 to third transistors T3, fifth transistors T5 to ninth transistors T9, a first capacitor C1, a first light-emitting diode LED1, and a second light-emitting diode LED2. Among them, first transistors T1 to third transistors T3, fifth transistor T5, and seventh transistors T7 to ninth transistors T9 can be P-type switching transistors, and sixth transistor T6 can be a P-type driving transistor.

[0175] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first terminal of the fifth transistor T5 is electrically connected to the fourth node N4, and the second terminal of the fifth transistor T5 is electrically connected to the data terminal Vdata. The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the first node N1. The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4. The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first terminal of the ninth transistor T9 is electrically connected to the fifth node N5, and the second terminal of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2. The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0176] According to embodiments of this disclosure, in addition to the advantages of pixel circuit 600, pixel circuit 700 can also achieve individual control of the first light-emitting diode LED1 and the second light-emitting diode LED2. Therefore, pixel circuit 700 can be applied to active privacy protection and dual-display applications, and the corresponding application scenarios can be switched arbitrarily. For example, the first light-emitting diode LED1 and the second light-emitting diode LED2 can each be used as pixels in privacy protection mode or shared mode independently. At the same time, the privacy protection mode / shared mode can be switched according to the application scenario, time, and brightness, so that the same pixel is not in privacy protection mode or shared mode for its entire life cycle, which would lead to severe device degradation and thus affect the lifespan, image retention, and brightness uniformity of the display panel.

[0177] Figure 7B schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0178] As shown in Figure 7B, during the P1 to P3 stages, the pixel circuit 700 can operate in a privacy mode and control the second light-emitting diode LED2 to emit light independently.

[0179] In phase P1, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset using the second reset signal Vinit2; the fifth control signal CON5 is low, controlling the third transistor T3 to turn on, thereby pulling the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset using the first reset signal Vinit1; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on, and the third control signal CON3 is low, controlling the first transistor T1 to turn on, thereby pulling the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0180] In phase P2, the third control signal CON3, the fourth control signal CON4, the fifth control signal CON5, and the sixth control signal CON6 are all high, controlling the first transistor T1, the second transistor T2, the third transistor T3, and the ninth transistor T9 to be turned off. The first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0181] In stage P3, the first control signal CON1 is high, turning off the fifth transistor T5 and the seventh transistor T7; the second control signal CON2 is low, turning on the eighth transistor T8; and the third control signal CON3 is low, turning on the first transistor T1. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the second light-emitting diode LED2 via the first transistor T1 and the third node N3 to control the second light-emitting diode LED2 to emit light.

[0182] Figure 7C schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0183] As shown in Figure 7C, during stages P4 to P6, the pixel circuit 700 can operate in a privacy mode and control the first light-emitting diode LED1 to emit light individually.

[0184] In stage P4, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset using the second reset signal Vinit2; the fifth control signal CON5 is low, controlling the third transistor T3 to turn on, thereby pulling the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset using the first reset signal Vinit1; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on, and the third control signal CON3 is low, controlling the first transistor T1 to turn on, thereby pulling the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0185] During phase P5, the third control signal CON3, the fourth control signal CON4, the fifth control signal CON5, and the sixth control signal CON6 are all high, controlling the third transistor T3 and the ninth transistor T9 to be turned off. The first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0186] In stage P6, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to be off; the second control signal CON2 is low, controlling the eighth transistor T8 to be on; and the fourth control signal CON4 is low, controlling the second transistor T2 to be on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the first light-emitting diode LED1 via the second transistor T2 and the second node N2 to control the first light-emitting diode LED1 to emit light.

[0187] Figure 7D schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0188] As shown in Figure 7D, during stages P7 to P9, the pixel circuit 700 can operate in a shared state and control the first light-emitting diode LED1 and the second light-emitting transistor LED2 to emit light simultaneously.

[0189] In stage P7, the sixth control signal CON6 is low, controlling the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2, so that the first capacitor C1 can be reset using the second reset signal Vinit2; the fifth control signal CON5 is low, controlling the third transistor T3 to turn on, thereby pulling the potential of the second node N2 down to the first reset signal Vinit1, so that the first light-emitting diode LED1 can be reset using the first reset signal Vinit1; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on, and the third control signal CON3 is low, controlling the first transistor T1 to turn on, thereby pulling the potential of the third node N3 down to the first reset signal Vinit1, so that the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0190] In stage P8, the third control signal CON3, the fourth control signal CON4, the fifth control signal CON5, and the sixth control signal CON6 are all high, controlling the first transistor T1, the second transistor T2, the third transistor T3, and the ninth transistor T9 to be turned off. The first control signal CON1 is low, controlling the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0191] In stage P9, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to be off; the second control signal CON2 is low, controlling the eighth transistor T8 to be on; the third control signal CON3 is low, controlling the first transistor T1 to be on; and the fourth control signal CON4 is low, controlling the second transistor T2 to be on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the second light-emitting diode LED2 through the first transistor T1 and the third node N3, and to the first light-emitting diode LED1 through the second transistor T2 and the second node N2, thereby controlling the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light.

[0192] According to embodiments of this disclosure, the pixel circuit 700 can achieve independent control of two light-emitting diodes, and can switch the working mode, on state and brightness as needed, so that the same light-emitting diode will not be in the privacy mode or shared mode throughout its entire life cycle, thereby improving the uniformity of the brightness of the light-emitting diode and extending the service life of the pixel circuit.

[0193] Figure 8A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0194] As shown in Figure 8A, based on pixel circuit 700, pixel circuit 800A may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0195] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0196] Figure 8B schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0197] As shown in Figure 8B, based on pixel circuit 700, pixel circuit 800B may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0198] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1.

[0199] Alternatively, different reset signals can be used to reset the two LEDs.

[0200] Figure 8C schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0201] As shown in Figure 8C, the control sub-circuit can also be connected to the third reset terminal Vinit3. Based on the pixel circuit 700, the pixel circuit 800C can also include a fourth transistor T4. The fourth transistor T4 can be a P-type switching transistor.

[0202] The third reset terminal Vinit3 can be used to provide a third reset signal Vinit3. This third reset signal Vinit3 can be the same as the first reset signal Vinit1 and the second reset signal Vinit2, or it can be a different signal from the first reset signal Vinit1 or the second reset signal Vinit2. No limitation is made here.

[0203] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3. During the reset process, the fifth control signal CON5 is high, controlling the third transistor T3 and the fourth transistor T4 to conduct. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the anode of the first light-emitting diode LED1; the third reset signal Vinit3 can be provided to the third node N3 via the fourth transistor T4 to reset the anode of the second light-emitting diode LED2.

[0204] According to the embodiments of this disclosure, since the second light-emitting transistor LED2 is initialized simultaneously when the first light-emitting transistor LED1 is initialized, when the second light-emitting transistor LED2 needs to be turned on, it is not necessary to go through the initialization process of the second light-emitting transistor LED2 again, thereby extending the charging time of the second light-emitting transistor LED2, and thus effectively improving the display quality and image retention problem.

[0205] Pixel circuits 800A, 800B, and 800C can achieve individual control of the first light-emitting diode LED1 and the second light-emitting diode LED2 to operate in privacy mode or shared mode.

[0206] Figure 8D schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0207] As shown in Figure 8D, in stages P1 to P3, the pixel circuit 800A can control the first light-emitting diode LED1 to emit light.

[0208] In phase P1, the sixth control signal CON6 is low, which controls the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2. Thus, the first capacitor C1 can be reset using the second reset signal Vinit2. The fifth control signal CON5 is low, which controls the third transistor T3 and the fourth transistor T4 to turn on, thereby pulling the potentials of the second node N2 and the third node N3 down to the first reset signal Vinit1. Thus, the first light-emitting diode LED1 and the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0209] In phase P2, both the fifth control signal CON5 and the sixth control signal CON6 are high to control the third transistor T3, the fourth transistor T4, and the ninth transistor T9 to be turned off. The first control signal CON1 is low to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0210] In stage P3, the first control signal CON1 is high, turning off the fifth transistor T5 and the seventh transistor T7; the second control signal CON2 is low, turning on the eighth transistor T8; and the fourth control signal CON4 is low, turning on the second transistor T2. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the first light-emitting diode LED1 via the second transistor T2 and the second node N2 to control the first light-emitting diode LED1 to emit light.

[0211] Figure 8E schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0212] As shown in Figure 8E, during stages P4 to P6, pixel circuit 800A can control the second light-emitting diode LED2 to emit light.

[0213] In stage P4, the sixth control signal CON6 is low, which controls the ninth transistor T9 to turn on, so as to pull the potential of the fifth node N5 down to the second reset signal Vinit2, thereby resetting the first capacitor C1 using the second reset signal Vinit2; the fifth control signal CON5 is low, which controls the third transistor T3 and the fourth transistor T4 to turn on, so as to pull the potential of the second node N2 and the third node N3 down to the first reset signal Vinit1, thereby resetting the first light-emitting diode LED1 and the second light-emitting diode LED2 using the first reset signal Vinit1.

[0214] In phase P5, both the fifth control signal CON5 and the sixth control signal CON6 are high to control the third transistor T3, the fourth transistor T4, and the ninth transistor T9 to be turned off. The first control signal CON1 is low to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0215] In stage P6, the first control signal CON1 is high, turning off the fifth transistor T5 and the seventh transistor T7; the second control signal CON2 is low, turning on the eighth transistor T8; and the third control signal CON3 is low, turning on the first transistor T1. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the second light-emitting diode LED2 via the first transistor T1 and the third node N3 to control the second light-emitting diode LED2 to emit light.

[0216] Figure 8F schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0217] As shown in Figure 8F, in stages P7 to P9, the pixel circuit 800A can control the first light-emitting diode LED2 and the second light-emitting diode LED2 to emit light simultaneously.

[0218] In stage P7, the sixth control signal CON6 is low, which controls the ninth transistor T9 to turn on, thereby pulling the potential of the fifth node N5 down to the second reset signal Vinit2. Thus, the first capacitor C1 can be reset using the second reset signal Vinit2. The fifth control signal CON5 is low, which controls the third transistor T3 and the fourth transistor T4 to turn on, thereby pulling the potentials of the second node N2 and the third node N3 down to the first reset signal Vinit1. Thus, the first light-emitting diode LED1 and the second light-emitting diode LED2 can be reset using the first reset signal Vinit1.

[0219] In stage P8, both the fifth control signal CON5 and the sixth control signal CON6 are high to control the third transistor T3, the fourth transistor T4, and the ninth transistor T9 to be turned off. The first control signal CON1 is low to control the fifth transistor T5 and the seventh transistor T7 to be turned on, and the data signal Vdata charges the first capacitor C1 through transistors T5, T6, and T7.

[0220] In stage P9, the first control signal CON1 is high, controlling the fifth transistor T5 and the seventh transistor T7 to be off; the second control signal CON2 is low, controlling the eighth transistor T8 to be on; the third control signal CON3 is low, controlling the first transistor T1 to be on; and the fourth control signal CON4 is low, controlling the second transistor T2 to be on. Driven by the first power supply voltage VDD and the voltage of the first capacitor C1, a driving current Id is formed between the source and drain of the sixth transistor T6. This driving current Id can be supplied to the second light-emitting diode LED2 through the first transistor T1 and the third node N3, and to the first light-emitting diode LED1 through the second transistor T2 and the second node N2, so as to control the first light-emitting diode LED1 and the second light-emitting diode LED2 to emit light simultaneously. According to the embodiments of this disclosure, by writing a first reset signal Vinit1 to reset the first light-emitting diode LED1, a first reset signal Vinit1 is also written to reset the second light-emitting diode LED2. Therefore, when the second light-emitting diode LED2 is turned on, there is no need to perform a reset process, thereby reducing the reset process when the second light-emitting diode LED2 is turned on, extending the charging time of the second light-emitting diode LED2, and thus improving image quality and reducing the impact of image retention.

[0221] Since the number of sub-pixels in the segmented unit pixel is twice that in the unit pixel of related technologies, the refresh rate is doubled and the charging time is halved. This affects the charging effect of the device, making it impossible to achieve a high refresh rate, and may cause short-term or medium-term image retention issues, affecting the display effect. Optionally, the driving sub-circuit can be implemented by a separate circuit to separate the Vth compensation process of the driving transistor from the data signal writing process, thereby extending the Vth compensation time and improving the display effect of low grayscale.

[0222] Figure 9A schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0223] As shown in Figure 9A, the discrete driver sub-circuit may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The fifth transistor T5 may be a P-type driver transistor, and the sixth transistor T6 and the seventh transistor T7 may be P-type switching transistors.

[0224] The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.

[0225] The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1.

[0226] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata.

[0227] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0228] The first terminal of the second capacitor C2 is electrically connected to the first power supply VDD, and the second terminal of the second capacitor C2 is electrically connected to the fourth node N4.

[0229] Optionally, the drive sub-circuit can also be electrically connected to the second reset terminal Vinit2 and the sixth control terminal CON6, respectively. Under the control of the sixth control signal CON6 from the sixth control terminal CON6, the drive sub-circuit can use the second reset signal Vinit2 from the second reset terminal Vinit2 to reset the potential of the first capacitor C1.

[0230] Figure 9B schematically illustrates the structure of a driver sub-circuit according to another embodiment of the present disclosure.

[0231] As shown in Figure 9B, the driving sub-circuit shown in Figure 9A may also include an eighth transistor T8. The eighth transistor T8 may be a P-type switching transistor.

[0232] The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5.

[0233] Before the driving sub-circuit operates, the sixth control signal CON6 is low to control the eighth transistor T8 to turn on. The second reset signal Vinit2 can be provided to the fifth node N5 through the eighth transistor T8 to reset the first capacitor C1.

[0234] The pixel circuit of the present disclosure embodiment will be further described below with reference to the circuit structures shown in Figures 3A-3B, 4A-4F, and 9A-9B.

[0235] Figure 10A schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0236] As shown in Figure 10A, the pixel circuit 1000 may include first transistors T1 to third transistors T3, fifth transistors T5 to eighth transistors T8, first capacitor C1, second capacitor C2, first light-emitting diode LED1, and second light-emitting diode LED2. Among these, first transistors T1 to third transistors T3 and sixth transistors T6 to eighth transistors T8 can be P-type switching transistors, and fifth transistor T5 can be a P-type driving transistor.

[0237] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the third node N3, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first terminal of the fifth transistor T5 is electrically connected to the first power supply VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1. The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the data terminal Vdata. The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5. The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5. The first terminal of the second capacitor C2 is electrically connected to the first power supply VDD, and the second terminal of the second capacitor C2 is electrically connected to the fourth node N4. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0238] The following explanation uses the pixel circuit 1000 operating in dual-view mode as an example to illustrate the timing sequence of the pixel circuit 1000.

[0239] Figure 10B schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0240] As shown in Figure 10B, in stage P1, the fifth control signal CON5 is low, controlling the third transistor T3 to conduct, and the first reset signal Vinit1 can reset the first light-emitting diode LED1; the fourth control signal CON4 is low, controlling the second transistor T2 to conduct, and the first reset signal Vinit1 can reset the second light-emitting diode LED2; the sixth control signal CON6 is low, controlling the eighth transistor T8 to conduct, and the second reset signal Vinit2 can reset the first capacitor C1. The second control signal CON2 is low, controlling the sixth transistor T6 to conduct, and the first power supply VDD charges the second capacitor C2 through the fifth transistor T5 and the sixth transistor T6 to begin Vth compensation.

[0241] In phase P2, the sixth control signal CON6 is high, controlling the eighth transistor T8 to turn off; the fifth control signal CON5 is high, controlling the third transistor T3 to turn off; and the fourth control signal CON4 is high, controlling the second transistor T2 to turn off. The first control signal CON1 is low, controlling the seventh transistor T7 to turn on, and the data signal Vdata is written to the fifth node N5. At this time, the second control signal CON2 remains low to continue Vth compensation.

[0242] In stage P3, the first control signal CON1 is high and controls the seventh transistor T7 to be turned off, the second control signal CON2 is high and controls the sixth transistor T6 to be turned off, and the sixth control signal CON6 is low and controls the eighth transistor T8 to be turned on, causing the potential of the first capacitor C1 to jump.

[0243] In stage P4, the sixth control signal CON6 is high, controlling the eighth transistor T8 to be off; the third control signal CON3 is low, controlling the first transistor T1 to be on; and the fourth control signal CON4 is low, controlling the second transistor T2 to be on. A drive current Id is formed between the source and drain of the fifth transistor T5. This drive current Id can be provided to the first LED1 and the second LED2 to drive them to emit light, respectively.

[0244] According to embodiments of this disclosure, the pixel circuit 1000 can independently perform Vth charging and Vdata input through a separate circuit architecture, thereby increasing the Vth charging time and improving the image retention problem that exists in low grayscale display.

[0245] Figure 10C schematically illustrates the operating timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0246] As shown in Figure 10C, in stage P1, the fifth control signal CON5 is low, controlling the third transistor T3 to conduct, and the first reset signal Vinit1 can reset the first light-emitting diode LED1; the fourth control signal CON4 is low, controlling the second transistor T2 to conduct, and the first reset signal Vinit1 can reset the second light-emitting diode LED2; the sixth control signal CON6 is low, controlling the eighth transistor T8 to conduct, and the second reset signal Vinit2 can reset the first capacitor C1. The second control signal CON2 is low, controlling the sixth transistor T6 to conduct, and the first power supply VDD charges the second capacitor C2 through the fifth transistor T5 and the sixth transistor T6 to begin Vth compensation.

[0247] In phase P2, the sixth control signal CON6 is high, controlling the eighth transistor T8 to turn off, and the fourth control signal CON4 is high, controlling the second transistor T2 to turn off. The first control signal CON1 is low, controlling the seventh transistor T7 to turn on, and the data signal Vdata is written to the fifth node N5. At this time, the second control signal CON2 remains low to continue Vth compensation.

[0248] In stage P3, the first control signal CON1 is high and controls the seventh transistor T7 to be turned off, the second control signal CON2 is high and controls the sixth transistor T6 to be turned off, and the sixth control signal CON6 is low and controls the eighth transistor T8 to be turned on, causing the potential of the first capacitor C1 to jump.

[0249] In stage P4, the fifth control signal CON5 is high, controlling the third transistor T3 to turn off; the sixth control signal CON6 is high, controlling the eighth transistor T8 to turn off; the third control signal CON3 is low, controlling the first transistor T1 to turn on; and the fourth control signal CON4 is low, controlling the second transistor T2 to turn on. A drive current Id is formed between the source and drain of the fifth transistor T5. This drive current Id can be provided to the first LED1 and the second LED2 to drive them to emit light, respectively.

[0250] According to embodiments of this disclosure, by extending the turn-on time of the third transistor T3, the initialization time of the first light-emitting diode LED1 can be extended, thereby eliminating the residual charge of the first light-emitting diode LED1 and improving the luminous stability of the first light-emitting diode LED1.

[0251] Figure 10D schematically illustrates the timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0252] As shown in Figure 10D, in stage P1, the fifth control signal CON5 is low, controlling the third transistor T3 to conduct, and the first reset signal Vinit1 can reset the first light-emitting diode LED1; the fourth control signal CON4 is low, controlling the second transistor T2 to conduct, and the first reset signal Vinit1 can reset the second light-emitting diode LED2; the sixth control signal CON6 is low, controlling the eighth transistor T8 to conduct, and the second reset signal Vinit2 can reset the first capacitor C1. The second control signal CON2 is low, controlling the sixth transistor T6 to conduct, and the first power supply VDD charges the second capacitor C2 through the fifth transistor T5 and the sixth transistor T6 to begin Vth compensation.

[0253] In phase P2, the fifth control signal CON5 is high, controlling the third transistor T3 to turn off, and the fourth control signal CON4 is high, controlling the second transistor T2 to turn off. The first control signal CON1 is high, controlling the seventh transistor T7 to turn off. At this time, the second control signal CON2 remains low to continue Vth compensation.

[0254] In the P3 stage, the first control signal CON1 is low and controls the seventh transistor T7 to turn on, the second control signal CON2 is high and controls the sixth transistor T6 to turn off, the sixth control signal CON6 is high and controls the eighth transistor T8 to turn off, the data signal Vdata is written to the fifth node N5, and causes the potential of the first capacitor C1 to jump, so as to complete the input of Vdata.

[0255] In stage P4, the sixth control signal CON6 is high, controlling the eighth transistor T8 to turn off; the third control signal CON3 is low, controlling the first transistor T1 to turn on; the fourth control signal CON4 is low, controlling the second transistor T2 to turn on; and the first control signal CON1 is high, controlling the seventh transistor T7 to turn off. A drive current Id is formed between the source and drain of the fifth transistor T5. This drive current Id can be provided to the first LED1 and the second LED2 to drive them to emit light, respectively.

[0256] According to embodiments of this disclosure, the pixel circuit 1000 can independently perform Vth charging and Vdata input through a separate circuit architecture, thereby increasing the Vth charging time and improving the image retention problem that exists in low grayscale display.

[0257] Figure 11A schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0258] As shown in Figure 11A, the pixel circuit 1100A may include first transistors T1 to third transistors T3, fifth transistors T5 to eighth transistors T8, first capacitor C1, second capacitor C2, first light-emitting diode LED1, and second light-emitting diode LED2. Among these, first transistors T1 to third transistors T3 and sixth transistors T6 to eighth transistors T8 can be P-type switching transistors, and fifth transistor T5 can be a P-type driving transistor.

[0259] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2. The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1. The gate of the fifth transistor T5 is electrically connected to the fourth node N4, the first terminal of the fifth transistor T5 is electrically connected to the first power supply VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first node N1. The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the fourth node N4, and the second terminal of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first terminal of the seventh transistor T7 is electrically connected to the fifth node N5, and the second terminal of the seventh transistor T7 is electrically connected to the data terminal Vdata. The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the second reset terminal Vinit2, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5. The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5. The first terminal of the second capacitor C2 is electrically connected to the first power supply VDD, and the second terminal of the second capacitor C2 is electrically connected to the fourth node N4. The anode of the first light-emitting diode LED1 is electrically connected to the second node N2, and the cathode of the first light-emitting diode LED1 is electrically connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is electrically connected to the third node N3, and the cathode of the second light-emitting diode LED2 is electrically connected to the second power supply VSS.

[0260] The timing diagram of the pixel circuit 1100A can be found in Figure 7B and Figures 10B to 10D, and will not be described in detail here.

[0261] Figure 11B schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0262] As shown in Figure 11B, based on pixel circuit 1100A, pixel circuit 1100B may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0263] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first electrode of the fourth transistor T4 is electrically connected to the third node N3, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2.

[0264] The timing diagram of the pixel circuit 1100B can be found in Figure 7B and Figures 10B to 10D, and will not be described in detail here.

[0265] Figure 11C schematically illustrates a structural diagram of a pixel circuit according to another embodiment of the present disclosure.

[0266] As shown in Figure 11C, based on pixel circuit 1100A, pixel circuit 1100C may also include a fourth transistor T4. The fourth transistor T4 may be a P-type switching transistor.

[0267] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the first reset terminal Vinit1.

[0268] The timing diagram of the pixel circuit 1100C can be found in Figure 7B and Figures 10B to 10D, and will not be described in detail here.

[0269] Alternatively, different reset signals can be used to reset the two LEDs.

[0270] Figure 11D schematically illustrates the structure of a pixel circuit according to another embodiment of the present disclosure.

[0271] As shown in Figure 11D, the control sub-circuit can also be connected to the third reset terminal Vinit3. Based on the pixel circuit 1100A, the pixel circuit 1100D can also include a fourth transistor T4. The fourth transistor T4 can be a P-type switching transistor.

[0272] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0273] During the reset process, the fifth control signal CON5 is high, which controls the third transistor T3 and the fourth transistor T4 to turn on. The first reset signal Vinit1 can be provided to the second node N2 via the third transistor T3 to reset the anode of the first light-emitting diode LED1. The third reset signal Vinit3 can be provided to the third node N3 via the fourth transistor T4 to reset the anode of the second light-emitting diode LED2.

[0274] The timing diagram of the pixel circuit 1100D can be found in Figure 7B and Figures 10B to 10D, and will not be described in detail here.

[0275] The first node can serve as a coupling node between the driving sub-circuit and the control sub-circuit. In some embodiments, some transistors in the driving sub-circuit can be replaced with N-type transistors or oxide transistors. The N-type transistors or oxide transistors can be connected to the coupling node, i.e., connected to the first node, by means of direct connection, indirect connection via thin-film transistors, direct connection via capacitors, etc.

[0276] Optionally, the driving sub-circuit may include at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node.

[0277] Figure 12A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0278] As shown in Figure 12A, in the pixel circuit 1200A, the multiple transistors of the driving sub-circuit 10 may include an oxide transistor Tn, one end of which is connected to the first node N1.

[0279] Figure 12B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0280] As shown in Figure 12B, the pixel circuit 1200B may include first transistors T1 to ninth transistors T9, a first capacitor C1, a first light-emitting diode LED1, and a second light-emitting diode LED1. Specifically, first transistors T1 to sixth transistors T6, eighth transistor T8, and ninth transistor T9 are all P-type switching transistors, and sixth transistor T6 is a P-type driving transistor. Seventh transistor T7 may be an N-type oxide transistor; that is, the oxide transistor included in the driving sub-circuit of pixel circuit 1200B may be the seventh transistor T7.

[0281] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0282] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0283] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0284] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0285] The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata.

[0286] The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0287] The first terminal of the seventh transistor T7 can be electrically connected to the fifth node N5, the second terminal of the seventh transistor T7 can be electrically connected to the first node N1, and the first gate and the second gate of the seventh transistor T7 can both be electrically connected to the first control terminal CON1.

[0288] The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4.

[0289] The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2.

[0290] The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0291] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0292] Optionally, the driving sub-circuit may include at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node via at least one thin-film transistor.

[0293] Figure 13A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0294] As shown in Figure 13A, in the pixel circuit 1300A, the multiple transistors in the driving sub-circuit may include an oxide transistor Tn and a thin film transistor Tm. One end of the oxide transistor Tn is connected to one end of the thin film transistor Tm, and the other end of the thin film transistor can be connected to the first node N1.

[0295] Figure 13B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0296] As shown in Figure 13B, based on pixel circuit 1200B, pixel circuit 1300B may further include a tenth transistor T10. The tenth transistor T10 is a P-type switching transistor and may be a thin-film transistor included in the driving sub-circuit of pixel circuit 1300B. The tenth transistor T10 may be connected in series between the seventh transistor T7 and the first node N1.

[0297] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0298] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0299] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0300] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0301] The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata.

[0302] The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0303] The first terminal of the seventh transistor T7 can be electrically connected to the fifth node N5, the second terminal of the seventh transistor T7 can be electrically connected to the sixth node N6, and the first gate and the second gate of the seventh transistor T7 can both be electrically connected to the first control terminal CON1.

[0304] The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4.

[0305] The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2.

[0306] The first terminal of the tenth transistor T10 can be electrically connected to the sixth node N6, the second terminal of the tenth transistor T10 can be electrically connected to the first node N1, and the gate of the tenth transistor T10 is electrically connected to the first control terminal CON1.

[0307] The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0308] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0309] Figure 13C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0310] As shown in Figure 13C, based on pixel circuit 1200B, pixel circuit 1300C may further include a tenth transistor T10. The tenth transistor T10 is a P-type switching transistor, and it may be a thin-film transistor included in the driving sub-circuit of pixel circuit 1300B. The tenth transistor T10 may be connected in series between the seventh transistor T7 and the first node N1.

[0311] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first electrode of the first transistor T1 is electrically connected to the first node N1, and the second electrode of the first transistor T1 is electrically connected to the third node N3.

[0312] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0313] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0314] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0315] The gate of the fifth transistor T5 is electrically connected to the first control terminal CON1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the data terminal Vdata.

[0316] The gate of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the sixth node N6.

[0317] The first terminal of the seventh transistor T7 can be electrically connected to the fifth node N5, the second terminal of the seventh transistor T7 can be electrically connected to the sixth node N6, and the first gate and the second gate of the seventh transistor T7 can both be electrically connected to the first control terminal CON1.

[0318] The gate of the eighth transistor T8 is electrically connected to the second control terminal CON2, the first terminal of the eighth transistor T8 is electrically connected to the first power supply VDD, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4.

[0319] The gate of the ninth transistor T9 is electrically connected to the sixth control terminal CON6, the first electrode of the ninth transistor T9 is electrically connected to the sixth node N6, and the second electrode of the ninth transistor T9 is electrically connected to the second reset terminal Vinit2.

[0320] The first terminal of the tenth transistor T10 can be electrically connected to the sixth node N6, the second terminal of the tenth transistor T10 can be electrically connected to the first node N1, and the gate of the tenth transistor T10 is electrically connected to the first control terminal CON1.

[0321] The first terminal of the first capacitor C1 is electrically connected to the first power supply VDD, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0322] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0323] Optionally, the driving sub-circuit may include at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node, and at least one capacitor is connected in series between one end of the N-type transistor and the first node.

[0324] Figure 14A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0325] As shown in Figure 14A, in the pixel circuit 1400A, the multiple transistors of the driving sub-circuit 10 may include an oxide transistor Tn. One end of the oxide transistor Tn is connected to the first node N1, and a capacitor Cst1 is connected in series between one end of the oxide transistor Tn and the first node N1.

[0326] Figure 14B shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0327] As shown in Figure 14B, in the pixel circuit 1400B, the multiple transistors of the driving sub-circuit 10 may include an oxide transistor Tn. One end of the oxide transistor Tn is connected to the first node N1, and a capacitor Cst1 and a capacitor Cst2 are connected in series between one end of the oxide transistor Tn and the first node N1.

[0328] Figure 14C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0329] As shown in Figure 14C, the pixel circuit 1400C may include first transistors T1 to eighth transistors T8, a first capacitor C1, a second capacitor C2, a first light-emitting diode LED1, and a second light-emitting diode LED2. First transistors T1 to fourth transistors T4 and sixth transistors T6 to eighth transistors T8 can be P-type switching transistors, and fifth transistor T5 can be an N-type driving transistor, specifically an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of the pixel circuit 1400C can be the fifth transistor T5.

[0330] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0331] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0332] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0333] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0334] The first gate of the fifth transistor T5 is electrically connected to the fifth node N5, the second gate of the fifth transistor T5 is electrically connected to the first node T1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.

[0335] The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4.

[0336] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0337] The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5.

[0338] The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, the second terminal of the first capacitor C1 is electrically connected to the first node N1, the first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the first power supply VDD.

[0339] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0340] Figure 14D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0341] As shown in Figure 14D, the pixel circuit 1400D may include first transistors T1 to T8, a first capacitor C1, a second capacitor C2, a first light-emitting diode LED1, and a second light-emitting diode LED2. First transistors T1 to T4, and sixth transistors T6 to T8 may be P-type switching transistors, and fifth transistor T5 may be an N-type driving transistor, specifically an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of the pixel circuit 1400D may be the fifth transistor T5.

[0342] Unlike pixel circuit 1400C, in pixel circuit 1400D, the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the second node N2.

[0343] Figure 14E shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0344] As shown in Figure 14E, the pixel circuit 1400E may include first transistors T1 to T8, eleventh transistor T11, first capacitor C1, second capacitor C2, first light-emitting diode LED1, and second light-emitting diode LED2. First transistors T1 to T4, sixth transistors T6 to T8, and eleventh transistor T11 can be P-type switching transistors, and fifth transistor T5 can be an N-type driving transistor, specifically an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of the pixel circuit 1400E can be the fifth transistor T5.

[0345] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0346] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0347] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0348] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0349] The first gate of the fifth transistor T5 is electrically connected to the fifth node N5, the second gate of the fifth transistor T5 is electrically connected to the first node N1, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1.

[0350] The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4.

[0351] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata, and the second electrode of the seventh transistor T7 is electrically connected to the seventh node N7.

[0352] The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5.

[0353] The gate of the eleventh transistor T11 is electrically connected to the eighth control terminal CON8, the first terminal of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second terminal of the eleventh transistor T11 is electrically connected to the first power supply VDD.

[0354] The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, the second terminal of the first capacitor C1 is electrically connected to the first node N1, the first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the seventh node N7.

[0355] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0356] In the embodiments of this disclosure, using an oxide transistor as the driving transistor can reduce the off-state leakage current, thereby reducing the power consumption of the pixel circuit, improving signal stability, and reducing screen flicker and grayscale distortion. Simultaneously, by connecting a capacitor at the coupling point, the gate voltage of the driving transistor can be stabilized, preventing the driving transistor from being mis-turned on or off due to instantaneous voltage spikes, thus avoiding screen flicker and ghosting.

[0357] In some embodiments, when using oxide transistors as the driving transistors of pixel circuits, a switching transistor can also be connected in series with the driving transistor. This switching transistor can act as a selection transistor, which can be controlled by the gate driving signal, turning on only when the corresponding row is selected and turning off when it is not selected, thereby blocking signal interference from adjacent rows or columns, ensuring image purity at high resolution, effectively reducing line crosstalk, and reducing grayscale distortion.

[0358] Furthermore, a capacitor can be connected between the driving transistor and the gate transistor to stabilize the gate voltage of the driving transistor, prevent the driving transistor from being mistakenly turned on or off due to instantaneous voltage spikes, and avoid screen flickering and ghosting.

[0359] Optionally, the driving sub-circuit may include at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node via at least one thin-film transistor, and at least one capacitor is connected in series between the N-type transistor or oxide transistor and the thin-film transistor.

[0360] Figure 15A shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0361] As shown in Figure 15A, in the pixel circuit 1500A, the multiple transistors in the driving sub-circuit may include an oxide transistor Tn and a thin film transistor Tm. One end of the oxide transistor Tn is connected to one end of the thin film transistor Tm, and the other end of the thin film transistor Tm can be connected to the first node N1. A capacitor Cst1 is connected in series between the oxide transistor Tn and the thin film transistor Tm.

[0362] Figure 15B shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0363] As shown in Figure 15B, in the pixel circuit 1500B, the multiple transistors in the driving sub-circuit may include an oxide transistor Tn and a thin film transistor Tm. One end of the oxide transistor Tn is connected to one end of the thin film transistor Tm, and the other end of the thin film transistor Tm can be connected to the first node N1. A capacitor Cst1 and a capacitor Cst2 are connected in series between the oxide transistor Tn and the thin film transistor Tm.

[0364] Figure 15C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0365] As shown in Figure 15C, the pixel circuit 1500C may include first transistors T1 to T8, a tenth transistor T10, a first capacitor C1, a second capacitor C2, a first light-emitting diode LED1, and a second light-emitting diode LED2. First transistors T1 to T4, sixth transistors T6 to T8, and tenth transistor T10 can be P-type switching transistors, and fifth transistor T5 can be an N-type driving transistor, specifically an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of the pixel circuit 1500C can be the fifth transistor T5. The thin-film transistor included in the driving sub-circuit of the pixel circuit 1500C can be the tenth transistor T10.

[0366] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0367] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0368] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0369] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0370] The first gate of the fifth transistor T5 is electrically connected to the fifth node N5, the second gate of the fifth transistor T5 is electrically connected to the sixth node T6, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the sixth node N6.

[0371] The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4.

[0372] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0373] The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5.

[0374] The gate of the tenth transistor T10 is electrically connected to the seventh control terminal CON7, the first electrode of the tenth transistor T10 is electrically connected to the sixth node N6, and the second electrode of the tenth transistor T10 is electrically connected to the first node N1.

[0375] The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, the second terminal of the first capacitor C1 is electrically connected to the sixth node N6, the first terminal of the second capacitor C2 is electrically connected to the sixth node N6, and the second terminal of the second capacitor C2 is electrically connected to the first power supply VDD.

[0376] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0377] Figure 15D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0378] As shown in Figure 15D, the pixel circuit 1500D may include first transistors T1 to T8, a tenth transistor T10, a first capacitor C1, a second capacitor C2, a first light-emitting diode LED1, and a second light-emitting diode LED2. First transistors T1 to T4, sixth transistors T6 to T8, and tenth transistor T10 can be P-type switching transistors, and fifth transistor T5 can be an N-type driving transistor, specifically an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of the pixel circuit 1500D can be the fifth transistor T5. The thin-film transistor included in the driving sub-circuit of the pixel circuit 1500D can be the tenth transistor T10.

[0379] Unlike pixel circuit 1500C, in pixel circuit 1500D, the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the second node N2.

[0380] Figure 15E shows a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0381] As shown in Figure 15E, the pixel circuit 1500E may include first transistors T1 to eighth transistors T8, tenth transistor T10, eleventh transistor T11, first capacitor C1, second capacitor C2, first light-emitting diode LED1, and second light-emitting diode LED2. First transistors T1 to fourth transistors T4, sixth transistors T6 to eighth transistors T8, tenth transistor T10, and eleventh transistor T11 can be P-type switching transistors, and fifth transistor T5 can be an N-type driving transistor, and fifth transistor T5 is an oxide transistor. That is, the oxide transistor included in the driving sub-circuit of pixel circuit 1500D can be the fifth transistor T5. The thin-film transistor included in the driving sub-circuit of pixel circuit 1500D can be the tenth transistor T10.

[0382] The gate of the first transistor T1 is electrically connected to the third control terminal CON3, the first terminal of the first transistor T1 is electrically connected to the first node N1, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0383] The gate of the second transistor T2 is electrically connected to the fourth control terminal CON4, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0384] The gate of the third transistor T3 is electrically connected to the fifth control terminal CON5, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the first reset terminal Vinit1.

[0385] The gate of the fourth transistor T4 is electrically connected to the fifth control terminal CON5, the first terminal of the fourth transistor T4 is electrically connected to the third node N3, and the second terminal of the fourth transistor T4 is electrically connected to the third reset terminal Vinit3.

[0386] The first gate of the fifth transistor T5 is electrically connected to the fifth node N5, the second gate of the fifth transistor T5 is electrically connected to the sixth node N6, the first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, and the second electrode of the fifth transistor T5 is electrically connected to the sixth node N6.

[0387] The gate of the sixth transistor T6 is electrically connected to the second control terminal CON2, the first terminal of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4.

[0388] The gate of the seventh transistor T7 is electrically connected to the first control terminal CON1, the first electrode of the seventh transistor T7 is electrically connected to the data terminal Vdata, and the second electrode of the seventh transistor T7 is electrically connected to the seventh node N7.

[0389] The gate of the eighth transistor T8 is electrically connected to the sixth control terminal CON6, the first terminal of the eighth transistor T8 is electrically connected to the reference signal terminal Vref, and the second terminal of the eighth transistor T8 is electrically connected to the fifth node N5.

[0390] The gate of the tenth transistor T10 is electrically connected to the seventh control terminal CON7, the first electrode of the tenth transistor T10 is electrically connected to the sixth node N6, and the second electrode of the tenth transistor T10 is electrically connected to the first node N1.

[0391] The gate of the eleventh transistor T11 is electrically connected to the eighth control terminal CON8, the first terminal of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second terminal of the eleventh transistor T11 is electrically connected to the first power supply VDD.

[0392] The first terminal of the first capacitor C1 is electrically connected to the fifth node N5, the second terminal of the first capacitor C1 is electrically connected to the sixth node N6, the first terminal of the second capacitor C2 is electrically connected to the sixth node N6, and the second terminal of the second capacitor C2 is electrically connected to the seventh node N7.

[0393] The anode of the first light-emitting diode LED1 is connected to the second node N2, and the cathode of the first light-emitting diode LED1 is connected to the second power supply VSS. The anode of the second light-emitting diode LED2 is connected to the third node N3, and the cathode of the second light-emitting diode LED2 is connected to the second power supply VSS.

[0394] In any of the pixel circuits described above, the transistors in the driving sub-circuit are all P-type transistors.

[0395] In some embodiments, some transistors in the driver sub-circuit can be replaced with N-type transistors. That is, the driver sub-circuit includes at least one P-type transistor and at least one N-type transistor among the plurality of transistors.

[0396] Figure 16A shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0397] As shown in Figure 16A, the topology of pixel circuit 1600A is the same as that of pixel circuit 1500E, but the selection of transistors in pixel circuit 1600A differs from that in pixel circuit 1500E. In pixel circuit 1600A, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 can be N-type switching transistors, and the sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 can be oxide transistors.

[0398] The first gate and the second gate of the seventh transistor T7 can be electrically connected to the first control terminal CON1, the first gate and the second gate of the eighth transistor T8 can be electrically connected to the sixth control terminal CON6, and the first gate and the second gate of the eleventh transistor T11 can be electrically connected to the eighth control terminal CON8.

[0399] In some embodiments, the transistors in the driving sub-circuit are all P-type transistors.

[0400] Figure 16B shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0401] As shown in Figure 16B, the topology of pixel circuit 1600B is the same as that of pixel circuit 1500E, but the selection of transistors in pixel circuit 1600B differs from that in pixel circuit 1500E. In pixel circuit 1600B, all transistors in the driving sub-circuit can be N-type transistors; that is, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 can be N-type switching transistors, and the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 can be oxide transistors.

[0402] The first gate and the second gate of the seventh transistor T7 can be electrically connected to the first control terminal CON1, the first gate and the second gate of the eighth transistor T8 can be electrically connected to the sixth control terminal CON6, and the first gate and the second gate of the eleventh transistor T11 can be electrically connected to the eighth control terminal CON8.

[0403] In the pixel circuit described above, all transistors in the control sub-circuit are P-type transistors. Optionally, in some embodiments, at least some transistors in the control sub-circuit can be replaced with N-type transistors; that is, the control sub-circuit includes at least one P-type transistor and at least one N-type transistor, or all transistors in the control sub-circuit can be N-type transistors.

[0404] Figure 16C shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0405] As shown in Figure 16C, the topology of pixel circuit 1600C is the same as that of pixel circuit 1500E, but the selection of transistors in pixel circuit 1600C differs from that in pixel circuit 1500E. In pixel circuit 1600C, the first transistor T1 and the second transistor T2 can be N-type switching transistors.

[0406] Figure 16D shows a schematic diagram of the structure of a pixel circuit according to another embodiment of the present disclosure.

[0407] As shown in Figure 16D, the topology of pixel circuit 1600D is the same as that of pixel circuit 1500E, but the selection of transistors in pixel circuit 1600D differs from that in pixel circuit 1500E. In pixel circuit 1600D, all transistors in the control sub-circuit can be N-type switching transistors; that is, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can all be N-type switching transistors.

[0408] Figure 17 schematically illustrates a display panel according to an embodiment of the present disclosure.

[0409] As shown in Figure 17, the display panel 1700 may include a display area 1710 and a non-display area 1720. The display area 1710 may be provided with a plurality of pixel circuits 1711, which may be the pixel circuits in any of the above embodiments, and are not limited here.

[0410] Figure 18 schematically illustrates a display device according to an embodiment of the present disclosure.

[0411] As shown in Figure 18, the display device 1800 may include a display panel 1810. The display area of ​​the display panel 1810 may be provided with multiple pixel circuits. The pixel circuits may be the pixel circuits in any of the above embodiments, and are not limited here.

[0412] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0413] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

A pixel circuit, comprising: The driving sub-circuit is configured to generate a driving current based on a first power supply voltage from a first power supply and a data signal from a data terminal, under the control of a first control signal from a first control terminal and a second control signal from a second control terminal, and to provide the driving current to the first node. The control sub-circuit is configured to provide the drive current to at least one of the second node and the third node under the control of a third control signal from a third control terminal and a fourth control signal from a fourth control terminal. A first light-emitting element, wherein a first end of the first light-emitting element is electrically connected to the second node, and a second end of the first light-emitting element is electrically connected to a second power supply; as well as The second light-emitting element has its first end electrically connected to the third node and its second end electrically connected to the second power supply. The pixel circuit according to claim 1, wherein, The control sub-circuit includes a first transistor and a second transistor; Wherein, the gate of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; The gate of the second transistor is electrically connected to the fourth control terminal, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the second node. The pixel circuit according to claim 1, wherein, The control sub-circuit includes a first transistor and a second transistor; Wherein, the gate of the first transistor is electrically connected to the third control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; The gate of the second transistor is electrically connected to the fourth control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node. The pixel circuit according to claim 2 or 3, wherein, The control sub-circuit is also electrically connected to the first reset terminal and the fifth control terminal, respectively. The control sub-circuit is further configured to reset the potential of at least one of the second node and the third node using a first reset signal from the first reset terminal, under the control of a fifth control signal from the fifth control terminal. The pixel circuit according to claim 4, wherein, The control sub-circuit also includes a third transistor; The gate of the third transistor is electrically connected to the fifth control terminal, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the first reset terminal. The pixel circuit according to claim 5, wherein, The control sub-circuit also includes a fourth transistor; The gate of the fourth transistor is electrically connected to the fifth control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the second node. [Amended according to Rule 26 07.04.2026] According to the pixel circuit of claim 5, wherein, The control sub-circuit also includes a fourth transistor; The gate of the fourth transistor is electrically connected to the fifth control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first reset terminal. [Amended according to Rule 26 07.04.2026] According to the pixel circuit of claim 5, wherein, The control sub-circuit also includes a fourth transistor; The gate of the fourth transistor is electrically connected to the fifth control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the third reset terminal. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor; Wherein, the gate of the fifth transistor is electrically connected to the fourth node, the first electrode of the fifth transistor is electrically connected to the first power supply, and the second electrode of the fifth transistor is electrically connected to the first node; The gate of the sixth transistor is electrically connected to the second control terminal, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; The gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the data terminal; The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the fifth node; and The first terminal of the second capacitor is electrically connected to the first power source, and the second terminal of the second capacitor is electrically connected to the fourth node. The pixel circuit according to claim 9, wherein, The driving sub-circuit is also electrically connected to the second reset terminal and the sixth control terminal, respectively. The driving sub-circuit is further configured to reset the potential of the first capacitor using a second reset signal from the second reset terminal, under the control of a sixth control signal from the sixth control terminal. The pixel circuit according to claim 10, wherein, The driving sub-circuit also includes an eighth transistor; The gate of the eighth transistor is electrically connected to the sixth control terminal, the first electrode of the eighth transistor is electrically connected to the second reset terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor; The gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the fourth node, and the second electrode of the fifth transistor is electrically connected to the data terminal. The gate of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the first node; The gate of the seventh transistor is electrically connected to the first control terminal, the first electrode of the seventh transistor is electrically connected to the fifth node, and the second electrode of the seventh transistor is electrically connected to the first node; The gate of the eighth transistor is electrically connected to the second control terminal, the first electrode of the eighth transistor is electrically connected to the first power supply, and the second electrode of the eighth transistor is electrically connected to the fourth node; and The first terminal of the first capacitor is electrically connected to the first power source, and the second terminal of the first capacitor is electrically connected to the fifth node. The pixel circuit according to claim 12, wherein, The driving sub-circuit is also electrically connected to the second reset terminal and the sixth control terminal, respectively. The driving sub-circuit is further configured to reset the potential of the first capacitor using a second reset signal from the second reset terminal, under the control of a sixth control signal from the sixth control terminal. The pixel circuit according to claim 13, wherein, The driving sub-circuit also includes a ninth transistor; The gate of the ninth transistor is electrically connected to the sixth control terminal, the first electrode of the ninth transistor is electrically connected to the fifth node, and the second electrode of the ninth transistor is electrically connected to the second reset terminal. The pixel circuit according to claim 13, wherein, The driving sub-circuit also includes a ninth transistor; The gate of the ninth transistor is electrically connected to the sixth control terminal, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second reset terminal. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node, and at least one capacitor is connected in series between one end of the N-type transistor and the first node. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node via at least one thin-film transistor. The pixel circuit according to any one of claims 1 to 8, wherein, The driving sub-circuit includes at least one N-type transistor or oxide transistor, one end of which is electrically connected to the first node via at least one thin-film transistor, and at least one capacitor is connected in series between the N-type transistor or oxide transistor and the thin-film transistor. The pixel circuit according to any one of claims 1 to 18, wherein, The control sub-circuit includes multiple P-type transistors; or The control sub-circuit includes multiple N-type transistors; or The control sub-circuit includes at least one P-type transistor and at least one N-type transistor among the multiple transistors. A display panel includes a display area and a non-display area, wherein, The display area is provided with a plurality of pixel circuits as described in any one of claims 1 to 20. A display device, comprising the display panel as described in claim 21.

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