Display panel and driving method therefor, and display apparatus

Abstract

A display panel and a driving method therefor, and a display apparatus. The display panel (100) comprises a gate drive circuit (00) and a plurality of pixel drive circuits (P0), wherein the gate drive circuit (00) comprises N stages of shift registers (01) cascaded with each other, and N≥2. The shift registers (01) each comprise a stage-transmission module (10) and at least two gating modules (20) connected to the stage-transmission module (10), wherein the gating modules (20) include a first gating module (21) and a second gating module (22), and the stage transmission module (10) is configured to output a stage-transmission signal (NEXT), the first gating module (21) and the second gating module (22) being configured to at least receive a frequency control signal (Ctrl), and output scanning signals (S1N_OUT / S2N_OUT) by means of output terminals of the first gating module (21) and the second gating module (22). In at least some of the shift registers (01), an output terminal of a first gating module (21) and an output terminal of a second gating module (22) are respectively connected to pixel drive circuits (P0) in different rows.

Description

Display panel and its driving method, display device

[0001] This application claims priority to Chinese Patent Application No. 202510238460.6, filed with the Chinese Patent Office on February 28, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel and its driving method, and a display device. Background Technology

[0003] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0004] Normal display of a product typically relies on the combined control of multiple signals. However, when special display techniques are required, such as displaying different areas of a product within a single frame using different refresh rates, display anomalies can easily occur. Therefore, improving the display accuracy of products has become one of the most pressing technical challenges. Summary of the Invention

[0005] This application provides a display panel and its driving method, as well as a display device, which aims to improve the display accuracy of display products.

[0006] In a first aspect, this application provides a display panel, including a gate driving circuit and a plurality of pixel driving circuits, wherein the gate driving circuit includes an N-stage shift register cascaded together, where N≥2;

[0007] One of the shift registers includes a cascading module and at least two gating modules connected to the cascading module, the gating modules including a first gating module and a second gating module;

[0008] The cascading module is configured to output a cascading signal, wherein the cascading signal of the i-th stage shift register is the input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, and i≠j;

[0009] The first gating module and the second gating module are configured to receive at least a frequency control signal and output a scan signal through the output terminals of the first gating module and the second gating module; wherein, in at least a portion of the shift registers, the output terminals of the first gating module and the second gating module are respectively connected to the pixel driving circuits of different rows.

[0010] Secondly, this application provides a driving method for a display panel, used to drive the display panel provided in the first aspect, wherein the first gating module receives a first frequency control signal, the second gating module receives a second frequency control signal, and the driving method includes:

[0011] The first frequency control signal and the second frequency control signal are controlled to maintain the same potential in at least one display frame;

[0012] The first frequency control signal and the second frequency control signal are controlled to undergo potential transitions in at least one display frame. The display frame includes a first stage and a second stage. In the first stage, the first frequency control signal and the second frequency control signal maintain the same potential. In the second stage, the first frequency control signal and the second frequency control signal undergo potential transitions, and the potential transition time of the first frequency control signal is earlier than the potential transition time of the second frequency control signal.

[0013] Thirdly, this application provides a display device including a display panel and a power supply provided in the first aspect of this application, wherein the power supply is electrically connected to the display panel and configured to provide power to the display panel. Attached Figure Description

[0014] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application;

[0015] Figure 2 shows a schematic diagram of a gate driving circuit in a display panel provided in an embodiment of this application.

[0016] Figure 3 shows a schematic diagram of a connection between the shift register and the pixel driving circuit in the gate driving circuit.

[0017] Figure 4 shows another planar structure diagram of the display panel provided in this application;

[0018] Figure 5 shows a schematic diagram of a connection between the shift register and the pixel driving circuit in the gate driving circuit corresponding to Figure 4.

[0019] Figure 6 shows a schematic diagram of a pixel driving circuit provided in an embodiment of this application.

[0020] Figure 7 shows another circuit diagram of the pixel driving circuit provided in the embodiment of this application;

[0021] Figure 8 shows a timing diagram of the pixel driving circuit in Figure 6;

[0022] Figure 9 shows a schematic diagram of a connection between a gate driving circuit and a pixel driving circuit in related technologies.

[0023] Figure 10 shows another connection diagram between the shift register and the pixel driving circuit in the gate driving circuit.

[0024] Figure 11 shows another connection diagram between the shift register and the pixel driving circuit in the gate driving circuit;

[0025] Figure 12 shows a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0026] Figure 13 shows another structural schematic diagram of the gate driving circuit provided in the embodiment of this application;

[0027] Figure 14 shows a driving timing diagram of the cascading module of the shift register in Figure 13;

[0028] Figure 15 shows a schematic diagram of a first gating module and a second gating module provided in an embodiment of this application.

[0029] Figure 16 shows a timing diagram of one of the gating modules in Figure 15.

[0030] Figure 17 shows another timing diagram of the gating module in Figure 15;

[0031] Figure 18 shows a timing diagram of a pixel driving circuit driven by a gate driving circuit provided in an embodiment of this application.

[0032] Figure 19 shows another structural schematic diagram of the gate driving circuit provided in the embodiment of this application;

[0033] Figure 20 shows a schematic diagram of a gating module corresponding to the embodiment in Figure 19;

[0034] Figure 21 is a flowchart of a display panel driving method provided in an embodiment of this application;

[0035] Figure 22 shows a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0036] The solution of this application will be described below. Unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0037] Many details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0038] Figure 1 shows a structural schematic diagram of a display panel 100 provided in an embodiment of this application. Figure 2 shows a structural schematic diagram of a gate driving circuit 00 in the display panel 100 provided in an embodiment of this application. Figure 3 shows a connection schematic diagram of a shift register 01 and a pixel driving circuit P0 in the gate driving circuit 00.

[0039] Please refer to Figures 1 to 3. This application embodiment provides a display panel 100, including a gate driving circuit 00 and multiple pixel driving circuits P0. The gate driving circuit 00 includes N-stage shift registers 01 cascaded together, where N≥2. Each shift register 01 includes a cascade module 10 and at least two gating modules 20 connected to the cascade module 10. Each gating module 20 includes a first gating module 21 and a second gating module 22. The cascade module 10 is configured to output a cascade signal NEXT, where the cascade signal of the i-th stage shift register is the input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, and i≠j. The first gating module 21 and the second gating module 22 are configured to receive at least a frequency control signal Ctrl and output scan signals S1N_OUT / S2N_OUT through the output terminals of the first gating module 21 and the second gating module 22. In at least some of the shift registers 01, the output terminals of the first gating module 21 and the second gating module 22 are respectively connected to pixel driving circuits P0 in different rows.

[0040] Figure 1 illustrates a rectangular display panel as an example only and does not limit the actual shape of the display panel. In some other embodiments of this application, the display panel can also be any other feasible shape such as a circle or a rounded rectangle. Optionally, the display panel provided in this embodiment can be an organic light-emitting display panel, and the corresponding light-emitting element is an organic light-emitting element. Of course, in some other embodiments of this application, the display panel can also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc. This application does not limit this.

[0041] To clearly illustrate the relative positional relationship between the gate driving circuit and the pixel driving circuit, Figure 1 does not show other structures of the display panel such as light-emitting elements, and only illustrates the pixel driving circuit with a rectangular structure. The number and arrangement of the pixel driving circuits are not limited. Furthermore, the position of the gate driving circuit in the display area in Figure 1 is only illustrative, and the example given is the introduction of one set of gate driving circuits 00 into the display panel and the placement of the gate driving circuits 00 in a non-display area on one side of the display area. However, this application is not limited to this. In some other embodiments of this application, two sets of gate driving circuits can be provided in the display panel. For example, please refer to Figures 4 and 5. Figure 4 shows another planar structure schematic diagram of the display panel provided in this application, and Figure 5 shows a connection schematic diagram of the shift register and the pixel driving circuit in the gate driving circuit corresponding to Figure 4. This embodiment uses the introduction of two sets of gate driving circuits 00 into the display panel and the placement of the two sets of gate driving circuits 00 in the left and right border areas of the display panel as an example. Driving the pixel driving circuit P0 with two sets of gate driving circuits 00 is beneficial to improving the transmission efficiency and reliability of the scanning signal.

[0042] Optionally, referring to Figures 1 to 5, the gate driving circuit 00 includes multiple cascaded shift registers 01. The output of the shift register 01 is connected to the scan line S, which is electrically connected to the pixel driving circuit P0. The shift register 01 provides scan signals to the pixel driving circuit P0 through the scan line S. The scan signals include, for example, reset control signals, data write control signals, light emission control signals, etc., to control the operation of the pixel driving circuit P0. Optionally, at least two different control signals correspond to different gate driving circuits. For example, the gate driving circuit that sends the reset control signal and the gate driving circuit that sends the light emission control signal are two independent gate driving circuits. Figure 6 shows a schematic diagram of a pixel driving circuit provided in an embodiment of this application. Taking Figure 6 as an example, the pixel driving circuit P0 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a capacitor C. The third transistor M3 is a driving transistor configured to provide driving current to the light-emitting element D0. The gate, first terminal, and second terminal of the third driving transistor M3 are respectively connected to the first sub-node N01, the third sub-node N03, and the second sub-node N02. The first terminal and second terminal of the fifth transistor M5 are respectively connected to the first reset signal terminal Vref1 and the first sub-node N01. The gate is connected to the first control signal terminal S1N and is configured to receive a reset control signal. The fifth transistor M5 is configured to provide the first reset signal Vref1 to the first sub-node N01. The first terminal and second terminal of the second transistor M2 are respectively connected to the data voltage signal terminal Vdata and the second sub-node N02. The gate receives the control signal SP. The second transistor M2 is configured to transmit the data voltage signal Vdata to the second sub-node N02. In this embodiment, the signal terminals and the signals transmitted by the signal terminals are represented by the same reference numerals. The first and second terminals of the fourth transistor M4 are connected to the third sub-node N03 and the first sub-node N01, respectively, and its gate is connected to the second control signal terminal S2N. It is configured to receive the control signal S2N, and the fourth transistor M4 is configured to perform threshold compensation on the third transistor M3. The first and second terminals of the seventh transistor M7 are connected to the second reset signal terminal Vref2 and the first terminal of the light-emitting element D0, respectively, and its gate is connected to the control signal terminal SPX. The seventh transistor M7 is configured to reset the first terminal of the light-emitting element D0. The first and second terminals of the eighth transistor M8 are connected to the bias adjustment signal terminal DVH and the second sub-node N02, respectively, and its gate is connected to the control signal terminal SPX. The first and second terminals of the first transistor M1 are connected to the first power supply signal terminal PVDD and the second sub-node N02, respectively, and its gate is connected to the light-emitting control signal terminal Emit.The first and second terminals of the sixth transistor M6 are respectively connected to the first terminal of the third sub-node N03 and the first terminal of the light-emitting element D0. Its gate is connected to the light-emitting control signal terminal Emit and is configured to transmit driving current to the light-emitting element D0. The second terminal of the light-emitting element D0 is connected to the second power supply signal PVEE. This embodiment only illustrates the example where the gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the control signal terminal SPX, but this application is not limited thereto. The pixel driving circuit in Figure 6 is only schematic, and this application does not limit the structure of the pixel driving circuit. In the embodiment of Figure 6, the fourth transistor M4 and the fifth transistor M5 connected to the first sub-node N01 are N-type transistors. N-type transistors can be oxide transistors. The signal controlling the conduction of the fourth transistor M4 and the fifth transistor M5 is a high-level signal. The other transistors are all P-type transistors. In this embodiment, the fourth transistor M4 and the fifth transistor M5 are N-type transistors. When the N-type transistors are oxide transistors, it is beneficial to reduce the leakage current from the fourth transistor M4 and the fifth transistor M5 to the first sub-node N01, thereby helping to maintain the stability of the potential of the gate of the driving transistor connected to the first sub-node N01. In other embodiments, the pixel driving circuit may also be embodied in other structures. For example, please refer to Figure 7. Figure 7 shows another circuit diagram of the pixel driving circuit provided in the embodiment of this application. The connection relationship and working principle are the same as those in Figure 6. The only difference from Figure 6 is that the fourth transistor M4 and the fifth transistor M5 are P-type transistors. The P-type transistors are turned on under the control of a low-level signal. When all transistors in the embodiment shown in Figure 7 are P-type transistors, it is beneficial to simplify the manufacturing process of the pixel driving circuit.

[0043] In the pixel driving circuits shown in Figures 6 and 7, the first control signal terminal S1N, the second control signal terminal S2N, the light emission control signal terminal Emit, and the control signal terminals SP and SPX are all connected to the gate driving circuit. The first control signal terminal S1N and the second control signal terminal S2N can correspond to the same group of gate driving circuits, while the light emission control signal terminal Emit, and the control signal terminals SP and SPX can correspond to other different gate driving circuits. In this embodiment, only the structure of the gate driving circuits corresponding to the first control signal terminal S1N and the second control signal terminal S2N is described, and the structure of other gate driving circuits in the display panel is not limited.

[0044] The working principle of Figure 6 will be explained below with reference to Figure 8. The working principle of the pixel driving circuit in Figure 7 can be referred to this embodiment. Figure 8 shows a timing diagram of the pixel driving circuit in Figure 6. Referring to Figures 6 and 8, the workflow of the pixel driving circuit P0 includes an initialization stage t1, a data writing and threshold compensation stage t2, a bias stage t3, and an emission stage t4.

[0045] During the initialization phase t1, the high-level signal of the first control signal S1N controls the fifth transistor M5 to conduct, transmitting the first reset signal Vref1 to the control terminal of the third transistor M3 for initialization. This eliminates residual charge from the previous frame, improving the display effect of the display panel. In this application, during a portion of the initialization phase t1, the effective levels of the first control signal S1N and the second control signal S2N overlap, which helps to mitigate the hysteresis problem of the driving transistors during the initialization process.

[0046] During the data writing and threshold compensation stage t2, the fifth transistor M5 is turned off, the control signal SP controls the second transistor M2 to turn on, and the second control signal S2N controls the fourth transistor M4 to turn on. The data voltage signal Vdata is written to the third transistor M3 through the second transistor M2. The fourth transistor M4 is connected between the gate and the first electrode of the third transistor M3, and can capture the threshold voltage of the third transistor M3 to the gate of the third transistor M3 to achieve threshold voltage compensation and self-compensate the deviation of the threshold voltage of the driving transistor.

[0047] During the bias phase t3, the control signal SPX turns on the eighth transistor M8, and the bias adjustment signal DVH is transmitted through the eighth transistor M8 to the second terminal (i.e., the second sub-node N02) of the driving transistor to adjust the bias state of the driving transistor. At the same time, the control signal SPX turns on the seventh transistor M7, and the second reset signal Vref2 is transmitted through the seventh transistor M7 to the anode of the light-emitting element D0 to reset the light-emitting element D0.

[0048] During the light-emitting stage t4, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are all off, while the first transistor M1, the third transistor M3, and the sixth transistor M6 are all on. The driving current is transmitted to the first electrode of the light-emitting element D0, causing D0 to emit light. The timing diagram in Figure 8 is for illustrative purposes only and is not intended to be limiting. In some other embodiments of this application, pixel driving circuits with different structures may correspond to different timing sequences.

[0049] Figure 9 shows a schematic diagram of the connection between the gate driving circuit 00' and the pixel driving circuit in the related technology. To simplify the panel design, the shift register that transmits the aforementioned reset control signal S1N and the shift register that transmits the aforementioned control signal S2N are usually multiplexed. That is, the same shift register is used to transmit the aforementioned reset control signal S1N and control signal S2N. Referring to Figure 6 and Figure 9, in this gate driving circuit, the output of the shift register 01' of this stage can provide the control signal S2N for the nth row pixel driving circuit and the reset control signal S1N for the mth row pixel driving circuit. This allows the fourth transistor M4 in the nth row pixel driving circuit to be turned on to achieve threshold compensation, while controlling the fifth transistor in the mth row to be turned on to achieve the reset of the gate of the driving transistor, where m > n. For display panels using this type of gate drive circuit, the reset control signal S1N and control signal S2N corresponding to the two rows of pixel drive circuits are multiplexed. When the display panel needs to implement partitioned refresh, for example, in two adjacent display areas, the pixel drive circuit in one display area needs to be refreshed (both the first control signal terminal S1N and the second control signal terminal S2N need to receive the valid level signal in the scan signal), while the pixel drive circuit in the other display area does not need to be refreshed (both the first control signal terminal S1N and the second control signal terminal S2N need to receive the invalid level signal in the scan signal). Assuming that the first row of pixel drive circuits needs to be refreshed and the second row of pixel drive circuits does not need to be refreshed, considering that the second-stage shift register 01 is simultaneously connected to the first row of pixel drive circuits... The second control signal terminal S2N and the first control signal terminal S1N in the second row pixel driving circuit require the second-stage shift register to output a valid level signal of the control signal S2N to ensure the normal refresh of the first row pixel driving circuit. However, to ensure that the second row pixel driving circuit does not refresh, the corresponding shift register needs to output an invalid level signal of the reset control signal S1N. It can be seen that the signals required by the first and second row pixel driving circuits are different. However, since the first and second row pixel driving circuits are connected to the output terminal of the same shift register, the two control signals mentioned above are multiplexed and the output signals are consistent. Therefore, it cannot meet the different refresh requirements of the two row pixel driving circuits, resulting in display abnormalities when the display panel has a requirement for partitioned refresh.

[0050] To address the aforementioned issues, this application embodiment improves the structure of the shift register. Referring to Figures 2 to 5, in the N-stage shift registers included in the gate drive circuit, each shift register includes a stage transfer module 10 and a first gating module 21 and a second gating module 22 connected to the stage transfer module 10. The stage transfer module 10 is configured to transmit stage transfer signals, with the stage transfer signal of the i-th stage shift register serving as the input signal of the j-th stage shift register. The first gating module 21 and the second gating module 22 output scan signals at least according to the received frequency control signal Ctrl. That is, the same shift register 01 can output two different scan signals through the first gating module 21 and the second gating module 22 respectively. In at least some shift registers, the output of the first gating module 21 and the output of the second gating module 22 are respectively connected to pixel driving circuits in different rows. Assuming that in the same shift register, the first gating module 21 is connected to the pixel driving circuit in row a and the second gating module 22 is connected to the pixel driving circuit in row b, when the refresh requirements of different display areas are different, for example, when the pixel driving circuit in row a needs to be refreshed but the pixel driving circuit in row b does not need to be refreshed, the first gating module 21 can output an effective level signal of the scan signal to the pixel driving circuit in row a to refresh the pixel driving circuit in row a, and the second gating module 22 can output an invalid level signal of the scan signal to the pixel driving circuit in row b, so that the pixel driving circuit in row b does not need to be refreshed. This allows the pixel driving circuits with different refresh requirements to receive the correct scan signal, which is beneficial to improving the display accuracy of the display panel when refreshing in zones.

[0051] Please refer to Figures 2 to 5. In one optional embodiment of this application, in at least one display frame, the first gating module 21 and the second gating module 22 in at least one shift register are configured to receive different frequency control signals respectively. The frequency control signal mentioned in the embodiments of this application can be regarded as one of the control signals that controls whether the gating module outputs a valid level signal. For example, when the frequency control signal is a level signal, the scanning signal output by the corresponding gating module may include a valid level signal, which can realize the normal refresh of the corresponding row pixel driving circuit; while when the frequency control signal is another level signal, the scanning signal output by the corresponding gating module may only include an invalid level signal, and the corresponding row pixel driving circuit is not refreshed. Therefore, in at least one display frame, if the first gating module 21 and the second gating module 22 in the shift register receive different frequency control signals, the different refresh requirements of the pixel driving circuits of different rows connected to the first gating module 21 and the second gating module 22 of the shift register can be realized, so as to meet the partition refresh requirements of the display panel and help ensure that the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improving the display accuracy during partition refresh. Subsequent embodiments will illustrate the different frequency control signals in conjunction with timing.

[0052] Please refer to Figures 2 and 3. In one optional embodiment of this application, the first gating module 21 and the second gating module 22 are configured to receive different frequency control signals respectively. This can be manifested in that, in at least one display frame, in at least one shift register, one of the frequency control signals received by the first gating module 21 and the other by the second gating module 22 is a high-level signal and the other is a low-level signal. For example, the first gating module 21 receives a first frequency signal Ctrl_1, and the second gating module 22 receives a second frequency signal Ctrl_2. Correspondingly, in a shift register, the potentials of the first frequency signal Ctrl_1 and the second frequency signal Ctrl_2 are opposite. Optionally, when the frequency control signal received by the gating module is a low-level signal, the scan signal output by the gating module may include a valid level signal to refresh the pixel driving circuit; when the frequency control signal received by the gating module is a high-level signal, the scan signal output by the gating module does not include a valid level signal and does not refresh the pixel driving circuit. Of course, in some other embodiments of this application, when the frequency control signal received by the gating module is high, the scanning signal output by the gating module can be controlled to not include a valid level signal; conversely, when the received frequency control signal is low, the scanning signal output by the gating module can be controlled to include a valid level signal. This application is not limited thereto. By controlling the output of the gating module by setting the frequency control signal high or low, and thus achieving different refresh requirements for different areas, the signal control of the panel can be simplified.

[0053] Please continue to refer to Figures 2 and 3. In one optional embodiment of this application, in at least one display frame, in at least one shift register, the scanning signal transmitted by the first gating module 21 to the corresponding pixel driving circuit includes a valid level signal. At this time, the pixel driving circuit connected to the first gating module 21 can be refreshed normally. The scanning signal output by the second gating module 22 to the corresponding pixel driving circuit does not include a valid level signal. At this time, the pixel driving circuit connected to the first gating module 21 does not need to be refreshed. The above embodiments are only illustrated by the example of the pixel driving circuit connected to the first gating module 21 being refreshed normally and the pixel driving circuit connected to the second gating module 22 not needing to be refreshed. In some other embodiments of this application, the pixel driving circuit connected to the first gating module 21 can be kept refreshed and the pixel driving circuit connected to the second gating module 22 can be refreshed normally by controlling the output signals of the first gating module 21 and the second gating module 22. For example, if the scan signal transmitted by the first gating module 21 to the corresponding pixel driving circuit does not include a valid level signal, then the pixel driving circuit connected to the first gating module 21 will not be refreshed. If the scan signal output by the second gating module 22 to the corresponding pixel driving circuit includes a valid level signal, then the pixel driving circuit corresponding to the second gating module 22 will be refreshed normally.

[0054] In this way, by controlling the output signals of the first gating module 21 and the second gating module 22 in the shift register, the different refresh requirements of different pixel driving circuits connected to the same shift register can be met. There is no need to introduce different shift registers for pixel driving circuits with different refresh requirements, which helps to reduce the number of shift registers actually contained in the gate driving circuit, simplify the panel structure, and realize the narrow bezel design.

[0055] In one optional embodiment of this application, in at least one display frame, the two gating modules in the shift register are configured to receive the same frequency control signal. For example, the frequency control signals received by the first gating module 21 and the second gating module 22 are both high-level signals or both low-level signals. Assuming the received frequency control signal is a low-level signal, the scan signal output by the corresponding gating module includes a valid level signal, and the corresponding pixel driving circuit can be refreshed normally; when the received frequency control signal is a high-level signal, the scan signal output by the corresponding gating module only includes an invalid level signal, and the corresponding pixel driving circuit is not refreshed. Therefore, when both gating modules receive low-level signals, the pixel driving circuits corresponding to both gating modules can be refreshed normally; when both gating modules receive high-level signals, the pixel driving circuits corresponding to both gating modules do not need to be refreshed. In this embodiment, the pixel driving circuits connected to the two gating modules in the same shift register do not need to perform differentiated refresh. Therefore, the scheme of introducing at least two gating modules in the same shift register in this application embodiment can meet both the differentiated refresh requirements of different display areas and the same refresh requirements of different display areas, thereby helping to meet the different display requirements of the display panel.

[0056] In one optional embodiment of this application, in at least one display frame, the scan signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit in at least one shift register may or may not include valid level signals. When the scan signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit both include valid signals, the pixel driving circuits corresponding to the first gating module 21 and the second gating module 22 can be refreshed normally; when the scan signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit neither include valid level signals, i.e., both are invalid level signals, the pixel driving circuits corresponding to the first gating module 21 and the second gating module 22 do not need to be refreshed. That is to say, the pixel driving circuits corresponding to the first gating module 21 and the second gating module 22 can also be refreshed using the same refresh requirements. By simultaneously introducing the first gating module 21 and the second gating module 22 in the same shift register, both the differentiated refresh requirements of different display areas and the same refresh requirements of different display areas can be met, thereby satisfying the different display requirements of the display panel.

[0057] Referring to Figures 6, 3, and 5, in one optional embodiment of this application, the pixel driving circuit P0 includes a first control signal terminal S1N and a second control signal terminal S2N. The first control signal terminal S1N and the second control signal terminal S2N are configured to receive scan signals output by different shift registers O1. For simplicity, in this embodiment, the signal terminal and the signal transmitted through it are represented by the same reference numerals. The first control signal terminal S1N in the pixel driving circuit P0 can be considered as a signal terminal connected to the gate of the fifth transistor M5. The signal of the first control signal terminal S1N is used to control the conduction state of the fifth transistor M5. When the fifth transistor M5 is turned on, the gate of the driving transistor can be reset. The second control signal terminal S2N can be considered as a signal terminal connected to the gate of the fourth transistor M4 in the pixel driving circuit. The signal of the second control signal terminal S2N is used to control the conduction state of the fourth transistor M4. When the signal of the second control signal terminal S2N controls the fourth transistor M4 to conduct and the signal of the control signal terminal SP controls the second transistor M2 to conduct, data writing and threshold compensation of the driving transistor can be realized. When the pixel driving circuit is working, during normal refresh, the fifth transistor M5 turns on earlier than the fourth transistor M4. This means that the gate of the fifth transistor M5 receives a valid voltage level signal earlier than the gate of the fourth transistor M4. This resets the gate of the driving transistor before the data writing and threshold compensation stages. Therefore, in the same pixel driving circuit, the gates of the fifth transistor M5 (corresponding to the first control signal terminal S1N) and the fourth transistor M4 (corresponding to the second control signal terminal S2N) are connected to different shift registers, which provide the scan signals.

[0058] In the same shift register 01, the first gating module 21 and the second gating module 22 are respectively configured to connect to different control signal terminals in the pixel driving circuit. For example, the first gating module 21 is configured to connect to the first control signal terminal S1N to control whether to reset the gate of the driving transistor in the pixel driving circuit, and the second gating module 22 is configured to connect to the second control signal terminal S2N to control the conduction state of the fourth transistor M4. In this embodiment, when the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit are configured to receive scan signals output from different shift registers 01, the output of the corresponding gating module can be controlled by the frequency control signal, so that both the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit can receive the valid level signal in the scan signal to achieve refresh, or both can receive the invalid level signal in the scan signal to avoid refresh.

[0059] The embodiments in Figures 3 and 5 above illustrate a method where one gating module in the shift register is electrically connected to only one row of pixel driving circuits, i.e., one gating module drives one row of pixel driving circuits. In this method, the load on the gating module is small, which is beneficial to improving the driving capability. Referring to Figures 3 and 5, when one gating module drives one row of pixel driving circuits, the shift register of the (n+1)th stage can be set on one side or both sides of the pixel driving circuit of the nth row. The first control signal terminal S1N corresponding to the pixel driving circuit of the nth row is connected to the output terminal of the first gating module 21 in the shift register of the nth stage, and the second control signal terminal S2N of the pixel driving circuit of the nth row is connected to the output terminal of the second gating module 22 in the (n+1)th stage shift register.

[0060] In some other embodiments of this application, a gating module in the shift register can also be connected to at least two rows of pixel driving circuits. For example, please refer to Figure 10, which shows another connection diagram between the shift register and the pixel driving circuit in the gate driving circuit. In the pixel driving circuits of the s-th and p-th rows, the second control signal terminal S2N is connected to the output terminal of the second gating module 22 in the m-th stage shift register, and the first control signal terminal S1N is connected to the output terminal of the first gating module 21 in the n-th stage shift register, where s≥1, p≥1, s≠p, and m>n≥1. For example, in Figure 10, the first control signal terminal S1N of the first row pixel driving circuit and the second row pixel driving circuit are both connected to the output terminal of the first gating module 21 in the first stage shift register, and the second control signal terminal S2N of the first row pixel driving circuit and the second row pixel driving circuit are both connected to the output terminal of the second gating module 22 in the second stage shift register.

[0061] In this embodiment, the pixel driving circuits in row s and row p can be any two rows of pixel driving circuits in the display panel. These two rows of pixel driving circuits can be adjacent or not adjacent. Figure 10 only illustrates the case where the two are adjacent, but it is not limited to this. The second control signal terminal S2N in the two rows of pixel driving circuits is connected to the same shift register, and the first control signal terminal S1N in the two rows of pixel driving circuits is connected to another shift register. This allows the gate reset process of the driving transistors in the two rows of pixel driving circuits to be performed simultaneously, as well as the threshold compensation and data writing processes. By using the same shift register to drive the two rows of pixel driving circuits, it is not necessary to introduce different shift registers for the pixel driving circuits in different rows. Therefore, it is beneficial to simplify the number of shift registers actually included in the gate driving circuit and reduce the space actually occupied by the gate driving circuit in the display panel. This is beneficial to realizing the narrow bezel design of the display panel.

[0062] In the pixel driving circuits of rows s and p, the shift registers connected to the first control signal terminal S1N are different from those connected to the second control signal terminal S2N. The first control signal terminal S1N is connected to the output of the first gating module 21 in the nth-stage shift register, and the second control signal terminal S2N is connected to the output of the second gating module 22 in the mth-stage shift register, where n < m. That is, the nth-stage shift register outputs the scan signal first, and the mth-stage shift register outputs the scan signal later. Thus, during actual refresh, the valid level signal in the scan signal can be sent to the first control signal terminal S1N first to reset the gates of the driving transistors in the two rows of pixel driving circuits, and then the valid level signal in the scan signal can be sent to the second control signal terminal S2N to complete the threshold voltage compensation. Of course, when refresh is not required, the nth-stage shift register also sends the invalid level signal in the scan signal to the first control signal terminal S1N first, and the mth-stage shift register then sends the invalid level signal in the scan signal to the second control signal terminal S2N. In actual display panels, the pixel driving circuits of the s-th row and the p-th row have the same refresh requirements, for example, both need to be refreshed, or neither needs to be refreshed.

[0063] Optionally, in the above embodiments, p = s + 1, mn = 1. That is, when using the same shift register to drive two rows of pixel driving circuits, these two rows of pixel driving circuits can be, for example, two adjacent rows. In the actual panel, for example, the pixel driving circuits of the first and second rows are treated as a whole, the pixel driving circuits of the third and fourth rows are treated as a whole, and so on. This simplifies the connection between the pixel driving circuits of different rows and the shift register. When mn = 1, it means that the shift register of the nth stage and the shift register of the mth stage are adjacent. That is, the two shift registers that provide scan signals to the first control signal terminal S1N and the second control signal terminal S2N of the adjacent two rows of pixel driving circuits are adjacent shift registers. This helps to reduce the interval between the gate reset stage of the driving transistor and the data writing and threshold compensation stage in the pixel driving circuit, and helps to improve the working efficiency of the pixel driving circuit.

[0064] Please continue to refer to Figure 10. The above embodiment describes the connection relationship between the pixel driving circuit and the shift register in adjacent rows s and p. For the connection relationship of the pixel driving circuit after row p, you can refer to the connection relationship of the pixel driving circuit in rows s and p. For example, in an optional embodiment of this application, in the pixel driving circuit of row p+1 and row p+2 (the pixel driving circuit of row 3 and row 4 can be used as an example), the second control signal terminal S2N is connected to the output terminal of the second gating module 22 in the shift register of stage m+1, and the first control signal terminal S1N is connected to the output terminal of the first gating module 21 in the shift register of stage m. In other words, the pixel driving circuits in rows p+1 and p+2 are treated as a whole. The first control signal terminal S1N of the pixel driving circuits in rows p+1 and p+2 receives the scan signal output by the first gating module 21 in the shift register of the m-th stage to determine whether to reset the gate of the driving transistor. The second control signal terminal S2N of the pixel driving circuits in rows p+1 and p+2 receives the scan signal output by the second gating module 22 in the shift register of the m+1-th stage to determine whether to turn on the fourth transistor M4 in the pixel driving circuit shown in Figure 6 or Figure 7.

[0065] When the pixel driving circuits of rows s and p are considered as one unit, and the pixel driving circuits of rows p+1 and p+2 are considered as another unit, it is possible to achieve normal refresh of the pixel driving circuits of rows s and p, while the pixel driving circuits of rows p+1 and p+2 do not refresh; or, it is possible to achieve no refresh of the pixel driving circuits of rows s and p, while the pixel driving circuits of rows p+1 and p+2 refresh normally. Taking the normal refresh of the pixel driving circuits of rows s and p, and no refresh of the pixel driving circuits of rows p+1 and p+2 as an example, the scan signal output by the first gating module 21 in the nth stage shift register to the first control signal terminal S1N of the pixel driving circuits of rows s and p includes a valid level signal, realizing the reset of the gate of the driving transistor; the scan signal output by the second gating module 22 in the mth stage shift register to the second control signal terminal S2N of the pixel driving circuits of rows s and p includes a valid level signal, realizing the compensation of the threshold voltage, thereby realizing the refresh of the pixel driving circuits of rows s and p. The scanning signals output by the first gating module 21 of the first shift register in the m-th stage to the pixel driving circuits of rows p+1 and p+2 do not include valid level signals, and the scanning signals output by the second gating module 22 of the shift register in the m+1-th stage to the pixel driving circuits of rows p+1 and p+2 also do not include valid level signals, thus preventing the pixel driving circuits of rows p+1 and p+2 from refreshing. When the pixel driving circuits of rows s and p are refreshed, and the pixel driving circuits of rows p+1 and p+2 are not refreshed, the first control signal terminal S1N and the second control signal terminal S2N of the corresponding pixel driving circuits can both receive the correct scanning signals, thereby avoiding the problem of abnormal display on the display panel during the partition refresh stage.

[0066] Please refer to Figure 10. In one optional embodiment of this application, in at least one display frame, the scan signals received by the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit of the same row both include valid level signals. That is, when a row of pixel driving circuits needs to be refreshed normally, the first control signal terminal S1N and the second control signal terminal S2N of that row of pixel driving circuits can receive signals that normally control their refresh, without the problem in related technologies where one of the first control line signal terminal and the second control signal terminal S2N receives an incorrect refresh signal. Similarly, when a row of pixel driving circuits does not need to be refreshed, the scan signals received by the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit of the same row do not include valid level signals, without the problem in related technologies where one of the first control signal terminal S1N and the second control signal terminal S2N receives a valid level signal, leading to display errors.

[0067] Referring to Figures 3 and 10, the display panel includes C circuit groups Z0, where C ≥ 1. Each circuit group Z0 includes multiple pixel driving circuits, and each circuit group Z0 includes at least one row of pixel driving circuits. In the embodiment shown in Figure 3, one circuit group Z0 includes one row of pixel driving circuits, and in the embodiment shown in Figure 10, one circuit group Z0 includes two adjacent rows of pixel driving circuits. Each pixel driving circuit includes a first control signal terminal S1N and a second control signal terminal S2N, which are configured to receive scan signals output from different shift registers. In one circuit group Z0, the first control signal terminal S1N of the pixel driving circuit is connected to the output of the first gating module 21 in one shift register 01, and the second control signal terminal S2N of the pixel driving circuit is connected to the output of the second gating module 22 in another shift register 01. The number of shift registers included in a group of gate driving circuits is N ≥ C + 1. In other words, when the number of circuit groups in the display panel is C, the number N of shift registers contained in a group of gate driving circuits is at least C+1. This application uses N=C+1 as an example for explanation, but it is not limited to this. In some other embodiments of this application, the number N of shift registers contained in a group of gate driving circuits can also be greater than C+1. It is understood that a shift register needs to provide corresponding scan signals to pixel circuits in different rows through the first gating module 21 and the second gating module 22. Simultaneously, the first control signal terminal S1N and the second control signal terminal S2N of the pixel driving circuit in a circuit group are also provided with scan signals by different shift registers. This may result in some circuit groups not having corresponding shift registers to provide scan signals for their first signal control terminal S1N or second signal control terminal S2N. In this embodiment, setting the number of shift registers to be greater than the number of circuit groups ensures that the first control signal terminal S1N and the second control signal terminal S2N of multiple pixel driving circuits have corresponding scan signals provided, ensuring that the display panel can display normally.

[0068] When the number of shift registers in a set of gate drive circuits is set to be at least one more than the number of circuit groups, the extra shift register can act as a buffer to ensure that the signal has enough time to stabilize during transmission, avoiding data errors caused by timing deviations. Moreover, in high-speed refresh operations, the extra shift register can provide additional clock cycles to compensate for signal delays, so that the scan signals output by shift registers at different levels can be generated and processed in the same way, reducing circuit complexity.

[0069] Taking Figure 10 as an example, when N=C+1, the first control signal terminal S1N of the pixel driving circuit in the first and second rows is connected to the output terminal of the first gating module 21 of the first-stage shift register, and the second control signal terminal S2N of the pixel driving circuit in the first and second rows is connected to the output terminal of the second gating module 22 of the second-stage shift register. At this time, the output terminal of the second gating module 22 of the first-stage shift register is not connected to the pixel driving circuit. Optionally, in the gate driving circuit, at least the output terminal of the second gating module 22 located in the first-stage shift register is floating or connected to the first signal line X1, and the first signal line X1 is not connected to the pixel driving circuit. In other words, the output of the second gating module 22 in the first-stage shift register can be unconnected to any other signal, or a first signal line X1 can be introduced into the display panel and connected to the output of the second gating module 22. The first signal line X1 can be regarded as a dummy signal line that is not connected to the pixel driving circuit. The first signal line X1 can receive fixed level signals in the display panel, such as high level signals or low level signals, or other fixed potential signals in the display panel. This helps to prevent static electricity from affecting the normal operation of the shift register through the output of the second gating module 22.

[0070] For the shift register located in the last stage, the output of its second gating module 22 is electrically connected to the second control signal terminal S2N of the last two rows of pixel driving circuits in the display panel. The output of the first gating module 21 in the last stage shift register is not connected to the pixel driving circuit. At this time, the output of the first gating module 21 in at least the last stage shift register is either floating or connected to the second signal line X2. The second signal line X2 is not connected to the pixel driving circuit. When the first gating module 21 is floating, its output can be unconnected to any other signal. When the output of the first gating module 21 is connected to the second signal line X2, the second signal line X2 can be regarded as a dummy signal line that is not connected to the pixel driving circuit. The second signal line X2 can receive fixed-level signals in the display panel, such as high-level signals or low-level signals. This helps to prevent static electricity from affecting the normal operation of the shift register through the output of the first gating module 21. Optionally, the first signal line X1 and the second signal line X2 can be the same signal line, for example, both can be high-level signal lines that receive high-level signals, or both can be low-level signal lines that receive low-level signals. Optionally, the first signal line X1 and the second signal line X2 can be different signal lines, for example, one can be a high-level signal line that receives high-level signals, and the other can be a low-level signal line that receives low-level signals. Here, the high-level signal can be the high-level signal VGH, which will be introduced later, and the low-level signal can be the low-level signal VGL, which will be introduced later.

[0071] When the output of the second gating module 22 of the first-stage shift register is floating, the output of the first gating module 21 in the last-stage shift register can also be floating or connected to the second signal line X2 that receives a fixed-potential signal. When the output of the second gating module 22 of the first-stage shift register is connected to the first signal line X1 that receives a fixed-potential signal, the output of the first gating module 21 in the last-stage shift register can also be floating or connected to the second signal line X2 that receives a fixed-potential signal; this application does not impose any limitations on this.

[0072] In this application embodiment, a first gating module 21 and a second gating module 22 are introduced for different shift registers. These modules are configured to be electrically connected to the first control signal terminal S1N and the second control signal terminal S2N of pixel driving circuits in different rows, respectively, and to output scan signals to the corresponding first control signal terminal S1N and second control signal terminal S2N. In an optional embodiment of this application, the first gating module 21 and the second gating module 22 in the shift register have the same circuit structure. This "same circuit structure" can mean, for example, that the first gating module 21 and the second gating module 22 contain the same number of transistors and have the same connection relationship between the transistors. Considering that the first gating module 21 and the second gating module 22 have the same function but different connected signal terminals, using the same circuit structure for the first gating module 21 and the second gating module 22 eliminates the need to introduce different circuits for each module, thus simplifying the overall circuit structure of the shift register. In the actual circuit layout, the circuit layout of the first gating module 21 and the second gating module 22 can be the same or different according to actual needs. This application does not limit this. In the subsequent embodiments, feasible circuit structures of the transmission module 10, the first gating module 21 and the second gating module 22 will be illustrated with examples.

[0073] Figure 10 illustrates an embodiment where the first control signal terminal S1N and the second control signal terminal S2N in the same row of pixel driving circuits are provided with scanning signals by a set of gate driving circuits. In some other embodiments of this application, the first control signal terminal S1N and the second control signal terminal S2N in the same row of pixel driving circuits can also be driven by two sets of gate driving circuits. For example, please refer to Figure 11, which shows another connection diagram between the shift register and the pixel driving circuit in the gate driving circuit. In an optional embodiment of this application, the display panel includes two sets of gate driving circuits 00, and the pixel driving circuit includes a first control signal terminal S1N and a second control signal terminal S2N. The first control signal terminal S1N of the same row of pixel driving circuits is electrically connected to the shift register 01 located at the same level in the two sets of gate driving circuits 00, and the second control signal terminal S2N of the same row of pixel driving circuits is electrically connected to the shift register 01 located at the same level in the two sets of gate driving circuits 00. The two shift registers 01 connected to the same row of pixel driving circuits are located on both sides of the row of pixel driving circuits.

[0074] This embodiment illustrates a scheme in which two sets of gate driving circuits 00 are introduced on both sides of an array composed of pixel driving circuits, and the pixel driving circuits are driven by these two sets of gate driving circuits. Taking the first row of pixel driving circuits as an example, the first control signal terminals S1N on both sides of the pixel driving circuit are respectively connected to the first gating module 21 in the shift register 01 located in the first stage of the two sets of gate driving circuits 00. The two first gating modules 21 jointly provide scanning signals to the first control signal terminals S1N on both sides of the first row of pixel driving circuits. This is beneficial to improving the overall driving capability of the panel and improving the scanning efficiency and scanning effect of the pixel driving circuits. In particular, for the scheme of driving two rows of pixel driving circuits with a single shift register 01, since the number of pixel driving circuits loaded by a single shift register 01 is large, there may be a problem of weak driving capability. In this case, introducing two sets of gate driving circuits 00 to drive the pixel driving circuits is beneficial to improving the overall driving capability of the gate driving circuits for the pixel driving circuits and meeting the driving requirements of the display panel.

[0075] Referring to Figures 6 and 11, in one optional embodiment of this application, the pixel driving circuit includes a driving transistor (the third transistor M3 is used as an example in the figures), a reset module 71 (the fifth transistor M5 is used as an example in the figures), and a threshold compensation module 72 (the fourth transistor M4 is used as an example in the figures). The reset module 71 is connected between the reset signal terminal Vref1 and the gate of the driving transistor M3, and the threshold compensation module 72 is connected between the gate of the driving transistor M3 and the first terminal of the driving transistor M3. The control terminal of the reset module 71 is connected to the first control signal terminal S1N, and the control terminal of the threshold compensation module 72 is connected to the second control signal terminal S2N. In one pixel driving circuit, the first control signal terminal S1N receives the scan signal output by the first gating module 21 of a shift register, and the second control signal terminal S2N receives the scan signal output by the second gating module 22 of another shift register.

[0076] In this embodiment of the application, the shift registers of the transmission module 10, the first gating module 21, and the second gating module 22 refer to shift registers that output scan signals to the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit. The gate driving circuit mentioned in this embodiment of the application refers to the gate driving circuit that outputs scan signals to the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit.

[0077] Figure 12 shows a schematic diagram of a gate drive circuit provided in an embodiment of this application. Referring to Figure 12, the cascading module 10 includes a control unit 80 and a first output unit 91 and a second output unit 92 electrically connected to the control unit 80. The first output unit 91 is connected to the control unit 80 at a first node N1, and the second output unit 92 is connected to the control unit 80 at a second node N2. The first output unit 91 and the second output unit 92 output a cascading signal NEXT based on the signals from the first node N1 and the second node N2. In this embodiment, the gating module 20 is configured to output a scan signal based on the frequency control signal Ctrl, the signal from the first node N1, the signal from the second node N2, and the cascading signal NEXT. In this embodiment, the gating module 20 also receives the cascading signal NEXT.

[0078] Figure 13 shows another structural schematic diagram of the gate drive circuit provided in this embodiment. Referring to Figures 12 and 13, this embodiment refines the structure of the cascade module 10. Optionally, the control unit 80 in the cascade module 10 includes a first control module 81 and a second control module 82. The first control module 81 is configured to receive an input signal IN and control the signals of the third node N3 and the fourth node N4 in response to a first clock signal CK. The signal of the third node N3 is connected to the second node N2. The second control module 82 is configured to receive voltage signals VGH and VGL and control the signal of the first node N1 in response to the signals of the third node N3, the fourth node N4, the first clock signal CK, and the second clock signal XCK.

[0079] For example, the first control module 81 includes transistor T13 and transistor T14. The first terminal of transistor T13 is connected to the input signal terminal IN, the second terminal is connected to the fourth node N4, and the gate is connected to the first clock signal CK. The first terminal of transistor T14 is connected to the input signal terminal IN, the second terminal is connected to the third node N3, and the gate is connected to the first clock signal CK.

[0080] For example, the second control module 82 includes transistors T15 to T25, capacitor C4, and capacitor C5. Transistor T15 receives a low-level signal VGL at its first terminal, receives a first clock signal CK at its gate, and its second terminal is connected to node N0. Transistor T16 has its gate connected to a third node N3, receives the first clock signal CK at its first terminal, and its second terminal is connected to node N0. Transistor T17 has its first terminal connected to node N0, receives a low-level signal VGL at its gate, and its second terminal is connected to the first plate of capacitor C4. The second plate of capacitor C4 is connected to the first terminal of transistor T19. Transistor T18 receives a second clock signal XCK at its first terminal, receives a low-level signal XCK at its gate, and its second terminal is connected to the first terminal of transistor T19. Transistor T19 has its second terminal connected to a first node N1, and its gate receives the second clock signal XCK. Transistor T20 receives a high-level signal VGH at its first terminal, and its second terminal is connected to… Connect the first node N1, and the gate is connected to the third node N3; the first terminal of transistor T21 is connected to the third node N12, the second terminal is connected to the second node N2, and the gate receives a low-level signal VGL; the first terminal of transistor T22 is connected to the fourth node N4, the second terminal is connected to the first terminal of transistor T23, and the gate receives a low-level signal VGL; the first terminal and gate of transistor T23 are connected to the second terminal of transistor T22, and the second terminal of transistor T23 is connected to the second node N2; the first plate of capacitor C5 is connected to the gate of transistor T23, and the second plate is connected to the second terminals of transistors T24 and T25; the first terminal of transistor T24 receives a low-level signal VGL, and the gate is connected to node N0; the first terminal of T25 receives the second clock signal XCK, and the gate is connected to the first terminal of transistor M23.

[0081] For example, the first output section 91 includes a transistor T11 and a capacitor C3, and the second output section 92 includes a transistor T12. The gate of transistor T11 is connected to the first node N1, the first electrode receives a high-level signal VGH, and the second electrode outputs the signal NEXT. The first plate of capacitor C3 receives the high-level signal VGH, and the second plate is connected to the gate of transistor T11. The gate of transistor T12 is connected to the second node N2, the first electrode receives a low-level signal VGL, and the second electrode outputs the signal NEXT.

[0082] The circuit structure of the cascade module shown in Figure 13 is for illustrative purposes only and does not limit the structure of the cascade module. In some other embodiments of this application, the cascade module may also adopt other feasible circuit structures.

[0083] Figure 14 shows a driving timing diagram of the shift register cascade module 10 in Figure 13. The working principle and working process of the cascade module 10 in this implementation will be introduced below with reference to Figures 13 and 14:

[0084] During the Ta phase, the input signal IN is high and the first clock signal CK is low. At this time, transistors T13, T14, and T15 are turned on, and the input signal IN is transmitted to the third node N3 and the fourth node N4 through transistors T13 and T14 respectively, making the third node N3 and the fourth node N4 both high. Transistors T16 and T20 are turned off. At the same time, the low-level signal VGL is transmitted to node N0 through transistor T15. Node N0 is low and transistor T17 is normally open, so node N5 is low. Transistor T18 is turned on, the second clock signal XCK is high, node N6 remains high, transistor T19 is turned off, the first node N1 remains low, transistor T11 is turned on, and the high-level signal VGH is transmitted to the output terminal, making the stage transmission signal NEXT high.

[0085] During the Tb stage, the input signal IN is high, the first clock signal CK is high, transistors T13, T14, and T15 are off, the third node N3 and the fourth node N4 remain high, transistors T16 and T20 are off, node N0 remains low, transistor T18 is on, the second clock signal XCK is low, and it is transmitted to node N6 through transistor T18, making node N6 low. Transistor T19 is on, and the signal from node N6 is transmitted to the first node N1. Transistor T11 is on, and the high-level signal VGH is transmitted to the output, making the stage transmission signal NEXT high.

[0086] During the Tc phase, the input signal IN is high and the first clock signal CK is low. At this time, transistors T13, T14, and T15 are turned on, and the input signal IN is transmitted to the third node N3 and the fourth node N4 through transistors T13 and T14 respectively, making the third node N3 and the fourth node N4 both high. Transistors T16 and T20 are turned off. At the same time, the low-level signal VGL is transmitted to node N0 through transistor T15. Node N0 is low and transistor T17 is normally open, so node N5 is low. Transistor T18 is turned on, the second clock signal XCK is high, node N6 remains high, transistor T19 is turned off, the first node N1 remains low, transistor T11 is turned on, and the high-level signal VGH is transmitted to the output terminal, making the stage transmission signal NEXT high.

[0087] During the Td phase, the input signal IN is low, the first clock signal CK is high, transistors T13, T14, and T15 are all off, the third node N3 and the fourth node N4 are both high, and transistors T16 and T20 are both off. Node N0 is low, and transistor T17 is normally on, so node N5 is low, transistor T18 is on, the second clock signal XCK is low, and the second clock signal XCK is transmitted to node N6 through transistor T18, making node N6 low. At the same time, transistor T19 is on, the signal from node N6 is transmitted to the first node N1 and is low, transistor T11 is on, and the high-level signal VGH is transmitted to the output, making the stage transmission signal NEXT high.

[0088] During the Te phase, the input signal IN is low, the first clock signal CK is low, and transistors T13, T14, and T15 are turned on. The input signal IN is transmitted to the third node N3 and the fourth node N4 through transistors T13 and T14 respectively, making both the third node N3 and the fourth node N4 low. Transistors T16 and T20 are turned on. Simultaneously, transistor T15 is turned on, and the low-level signal VGL is transmitted to node N0 through transistor T15. Node N0 is low, and transistor T17 is normally open, so node N5 is low. When the voltage level is high, transistor T18 is turned on, the second clock signal XCK is high, node N6 remains high, and transistor T19 is turned off; transistor T20 is turned on, and the high-level signal VGH is transmitted to the first node N1 through transistor T20, making the first node N1 high, and transistor T11 is turned off; at the same time, transistors T21 and T22 are normally open, the signal of the third node N3 is transmitted to the second node N2, making the second node N2 low, transistor T12 is turned on, and the low-level signal VGL is transmitted to the output terminal, making the stage transmission signal NEXT low.

[0089] As can be seen, during the Ta~Td stage, when the NEXT output signal is high, one of the first node N1 and the second node N2 is low and the other is high. This embodiment of the application will be described with the first node N1 being low and the second node being high as an example.

[0090] Please continue referring to Figures 12 and 13. In this embodiment, the first gating module 21 and the second gating module 22 are electrically connected to the first node N1 and the second node N2 in the cascade module 10, respectively. They also receive the cascade signal NEXT and the frequency control signals Ctrl_1 / Ctrl_2, respectively. The first gating module 21 and the second gating module 22 can output scanning signals according to the frequency control signals Ctrl_1 / Ctrl_2, the signal of the first node N1, the signal of the second node N2, and the cascade signal NEXT, respectively. The following will describe the structure of the gating module.

[0091] Please refer to Figure 15, which shows a schematic diagram of the structure of the first gating module 21 and the second gating module 22 provided in an embodiment of this application. Referring to Figures 13 and 15, in an optional embodiment of this application, the gating module includes a first output unit 31, a second output unit 32, an isolation protection unit 33, and an output control unit 34. The control terminal of the isolation protection unit 33 receives the transmission signal NEXT, and the input terminal of the isolation protection unit 33 receives the frequency control signals Ctrl_1 / Ctrl_2. The output terminal of the isolation protection unit 33 is connected to the control terminal of the output control unit 34. The input terminal of the output control unit 34 receives the signal from the first node N1, and the output terminal is connected to the control terminal of the first output unit 31. The input terminal of the first output unit 31 receives the first level signal VGH, and the output terminal is connected to the output terminals S1N_OUT / S2N_OUT of the gating module. The control terminal of the second output unit 32 receives the signal from the second node N2, the input terminal receives the second level signal VGL, and the output terminal is connected to the output terminals S1N_OUT / S2N_OUT of the gating module. Optionally, the selection module further includes a node control module 35. The control terminal of the node control module 35 receives the signal from the first node N1, the input terminal receives the first level signal VGH, and the output terminal is connected to the control terminal of the first output unit 31. It is configured to control the signal of the control terminal of the first output unit 31. Optionally, a capacitor can also be introduced between the control terminal of the first output unit 31 and the first level signal terminal VGH, which can also serve to maintain the signal of the control terminal of the first output unit 31.

[0092] For example, the isolation protection unit 33 includes a transistor T3 and a capacitor, the output control unit 34 includes a transistor T4, the first output unit 31 includes a transistor T1, and the second output unit 32 includes a transistor T2. The gate of transistor T3 receives a transmission signal, its first terminal receives frequency control signals Ctrl_1 / Ctrl_2, and its second terminal is connected to the gate of transistor T4. The first terminal of transistor T4 is connected to the first node N1 in the transmission module 10, and its second terminal is connected to the gate of transistor T1. The first terminal of transistor T1 receives a first-level signal VGH, and its second terminal is connected to the output terminal of the gating module. The gate of transistor T2 is connected to the first node in the transmission module 10, its first terminal receives a second-level signal VGL, and its second terminal is connected to the output terminals S1N_OUT / S2N_OUT of the gating module.

[0093] Figure 16 shows a timing diagram of the gating module in Figure 15, illustrating the operation of the gating module when the frequency control signals Ctrl_1 / Ctrl_2 are low. Referring to Figures 15 and 16, when the output of the transmission signal is low, transistor T3 is turned on, and the low-level signal of the frequency control signal is transmitted to the gate of transistor T4 through transistor T3, controlling transistor T4 to turn on. The high-level signal of the first node N1 is transmitted to transistor T1 through transistor T4, causing transistor T1 to turn off. The low-level signal of the second node N2 is transmitted to transistor T2, and transistor T2 turns on. The second-level signal VGL is transmitted to the output of the gating module through transistor T2, and the output of the gating module outputs a low-level signal. When the output of the cascade signal is high, the second node N2 is high, the first node N1 is low, transistor T2 and T3 are off, and transistor T4 remains on. The low-level signal from the first node N1 is transmitted to the gate of transistor T1, turning T1 on. The first-level signal VGH is transmitted through transistor T1 to the output of the gating module, and the outputs S1N_OUT / S2N_OUT of the gating module output high-level signals. Therefore, when the frequency control signal is low, the output signal of the gating module is not affected by the frequency control signal, and the gating module can output the scanning signal normally.

[0094] Figure 17 shows another timing diagram of the gating module in Figure 15, illustrating the operation of the gating module when the frequency control signal is high. Referring to Figures 15 and 17, when the stage transmission signal output is low, transistor T3 is turned on, and the high-level signal of the frequency control signal is transmitted to transistor T4, causing transistor T4 to turn off. The signal from the first node N1 cannot be transmitted to the gate of transistor T1. At this time, the potential of the second node N2 is low, controlling transistor T2 to turn on. The second-level signal VGL is transmitted to the output of the gating module through transistor T2, and the output of the gating module outputs a low-level signal. When the stage transmission signal jumps to a high-level signal, transistor T3 is turned off, and transistor T4 remains off. The signal from the first node N1 still cannot be transmitted to the gate of transistor T1, and transistor T1 remains off. The high level of the second node N2 controls transistor T2 to turn off, and the output of the gating module remains at the low level of the previous stage. Therefore, when the frequency control signal is high, the scan signal output by the gating module only includes invalid level signals.

[0095] Therefore, when the frequency control signal is low, the gating module can output a scanning signal normally. When the frequency control signal changes from low to high, the gating module can only output an invalid signal.

[0096] The function of transistor T3 in isolation protection unit 33 is to cut off when the transmission signal output is high. If the frequency control signal changes, it will be unable to write the frequency control signal to the gate of transistor T4 until the transmission signal changes to low, at which point the changed frequency control signal will be written to the gate of transistor T4. This helps to avoid the problem of incomplete output signal of the gating module caused by the change of the frequency control signal when the transmission signal is halfway through transmission.

[0097] The following description, in conjunction with Figure 18, illustrates the operation of the display panel in this embodiment when implementing partitioned refresh. Figure 18 shows a timing diagram of the gate driving circuit driving the pixel driving circuit provided in this embodiment. Taking the architecture shown in Figure 11 as an example, the first row pixel driving circuit and the second row pixel driving circuit are integrated. The first control signal terminal S1N of the first row pixel driving circuit and the second row pixel driving circuit is connected to the output terminal of the first gating module 21 in the first-stage shift register, and the second control signal terminal S2N of the first row pixel driving circuit and the second row pixel driving circuit is connected to the output terminal of the second gating module 22 in the second-stage shift register. The third row pixel driving circuit and the fourth row pixel driving circuit are integrated. The first control signal terminal S1N of the third row pixel driving circuit and the fourth row pixel driving circuit is connected to the output terminal of the first gating module 21 in the second-stage shift register, and the second control signal terminal S2N of the third row pixel driving circuit and the fourth row pixel driving circuit is connected to the output terminal of the second gating module 22 in the third-stage shift register. The fifth and sixth row pixel driving circuits are integrated as a whole. The first control signal terminal S1N of the fifth and sixth row pixel driving circuits is connected to the output terminal of the first gating module 21 in the third-level shift register, and the second control signal terminal S2N of the fifth and sixth row pixel driving circuits is connected to the output terminal of the second gating module 22 in the fourth-level shift register.

[0098] In Figure 18, NEXT(1) to NEXT(4) represent the stage transmission signals output by the first-stage shift register to the fourth-stage shift register, respectively; S1N_OUT(1) to S1N_OUT(4) represent the scan signals output by the first gating module 21 in the first-stage shift register to the fourth-stage shift register, respectively; S2N_OUT(1) to S2N_OUT(4) represent the scan signals output by the second gating module 22 in the first-stage shift register to the fourth-stage shift register, respectively. The first control signal terminal S1N of the pixel driving circuit in rows 1 and 2 receives signal S1N_OUT (1), and the second control signal terminal S2N receives signal S2N_OUT (2); the first control signal terminal S1N of the pixel driving circuit in rows 3 and 4 receives signal S1N_OUT (2), and the second control signal terminal S2N receives signal S2N_OUT (3); the first control signal terminal S1N of the pixel driving circuit in rows 5 and 6 receives signal S1N_OUT (3), and the second control signal terminal S2N receives signal S2N_OUT (4). Ctrl_1 represents the frequency control signal received by the first gating module 21 in the first to fourth level shift registers; Ctrl_2 represents the frequency control signal received by the second gating module 22 in the first to fourth level shift registers.

[0099] When both frequency control signals Ctrl_1 and Ctrl_2 are low, the pixel driving circuits of rows 1 and 2, as well as rows 3 and 4, receive valid level signals from the scan signals. When the output stage of the third-stage shift register outputs a valid level signal, the first frequency control signal Ctrl_1 has already changed from a low level signal to a high level signal, while the second frequency control signal Ctrl_2 remains low. Therefore, the second gating module 22 in the third-stage shift register can still output scan signals containing valid level signals to the pixel driving circuits of rows 3 and 4, while the first gating module 21 outputs scan signals containing only invalid level signals to the pixel driving circuits of rows 5 and 6, without resetting the gates of the driving transistors in the pixel driving circuits of rows 5 and 6. When the fourth-stage shift register outputs a valid level signal, the second frequency control signal has already transitioned from a low level to a high level, while the first frequency control signal remains high. Therefore, the scan signals output by the first gating module 21 and the second gating module 22 of the fourth-stage shift register both contain only invalid level signals. Starting from the 5th and 6th row pixel driving circuits, subsequent pixel driving circuits do not refresh. This achieves a partitioned refresh effect, where the pixel driving circuits in rows 1-4 refresh normally, while the pixel driving circuits starting from row 5 do not refresh.

[0100] Because the first gating module 21 and the second gating module 22 are introduced into the shift register in this embodiment, the first gating module 21 and the second gating module 22 in the same shift register can output different scanning signals. For example, one contains a valid level signal, while the other does not contain a valid level signal. Therefore, the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improving the display accuracy during partition refresh.

[0101] Figure 19 shows another schematic diagram of the gate drive circuit provided in an embodiment of this application. Compared with Figure 12, in this embodiment, in the same shift register 00, the first gating module 21 and the second gating module 22 are not connected to the cascading signal NEXT output by the cascading module 10. Referring to Figure 19, in an optional embodiment of this application, the cascading module 10 includes a control unit 80 and a first output unit 91 and a second output unit 92 electrically connected to the control unit 80. The first output unit 91 is connected to the control unit 80 at a first node N1, and the second output unit 92 is connected to the control unit 80 at a second node N2. The first output unit 91 and the second output unit 92 output the cascading signal NEXT according to the signal of the first node N1 and the signal of the second node N2. The gating module 20 is configured to output a scan signal according to the frequency control signal Ctrl_1 / Ctr_2, the signal of the first node N1, and the signal of the second node N2.

[0102] The structure, circuit, and working principle of the cascading module 10 in this embodiment can be referred to the embodiments shown in Figures 13 and 14, and will not be repeated here. As can be seen from the embodiments shown in Figures 13 and 14, during the Ta~Td stage, when the cascading signal NEXT is output at a high level, one of the first node N1 and the second node N2 is at a low level, and the other is at a high level. This embodiment of the application will be described using the example of the first node N1 being at a low level and the second node being at a high level.

[0103] Figure 20 shows a schematic diagram of a gating module corresponding to the embodiment in Figure 19. Referring to Figures 19 and 20, in an optional embodiment of this application, the first gating module 21 and the second gating module 22 in the gating module 20 respectively include a first output unit s1 and a second output unit s2. The control terminal of the first output unit s1 receives the signal from the first node N1, the input terminal receives the frequency control signal Ctrl_1 / Ctrl_2, and the output terminal is connected to the output terminal S1N_OUT / S2N_OUT of the gating module. The control terminal of the second output unit s2 receives the signal from the second node N2, the input terminal receives the second level signal VGL, and the output terminal is connected to the output terminal S1N_OUT / S2N_OUT of the gating module. Optionally, the frequency control signal received by the first gating module 21 is the first frequency control signal Ctrl_1, and the frequency control signal received by the second gating module 22 is the second frequency control signal Ctrl_2.

[0104] In this embodiment, the first gating module 21 and the second gating module 22 are electrically connected to the first node N1 and the second node N2 in the transmission module 10, respectively, and also receive frequency control signals Ctrl_1 / Ctrl_2. The first gating module 21 and the second gating module 22 can output scanning signals according to the frequency control signals Ctrl_1 / Ctrl_2, the signal of the first node N1, and the signal of the second node N2, respectively.

[0105] Referring to Figure 20, for example, the first output unit s1 in the first gating module 21 includes transistor T26, and the second output unit 32 includes transistor T27. The first output unit s1 in the second gating module 22 includes transistor T28, and the second output unit 32 includes transistor T29. When the signal control transistor T26 of the first node N1 is turned on, the first frequency control signal Ctrl_1 is output as a scan signal from the output terminal S1N_OUT of the first gating module 21. Similarly, when the signal control transistor T28 of the first node N1 is turned on, the second frequency control signal Ctrl_2 is output as a scan signal from the output terminal S2N_OUT of the second gating module 22. Thus, during the scanning phase, when the gating module needs to output a valid level signal for the scan signal, the first output unit 31 can output a frequency control signal containing a valid level as the scan signal. When the gating module needs to output an invalid level signal for the scan signal, the first output unit 31 can also output a frequency control signal without a valid level as the scan signal. By adjusting the frequency control signal, different output requirements of the gating module can be met.

[0106] When the first gating module 21 and the second gating module 22 are respectively embodied in the structure shown in Figure 20, the first gating module 21 and the second gating module 22 each include two transistors. The gates of the two transistors are respectively connected to the first node N1 and the second node N2 in the transmission module 10. The conduction of the transistors is controlled by the potential of the first node N1 and the second node N2. At this time, the gating module can output a scanning signal according to the frequency control signal, the signal of the first node and the signal of the second node. In addition, the first gating module 21 and the second gating module 22 in this application are each composed of two transistors, which is relatively simple in structure. It is beneficial to simplify the overall structure of the gate driving circuit and reduce the space occupied by the gate driving circuit in the display panel. Therefore, it is beneficial to realize the narrow bezel design of the display panel.

[0107] Based on the same inventive concept, this application also provides a driving method for a display panel. Figure 21 shows a flowchart of a driving method for a display panel provided in an embodiment of this application. This driving method is used to drive the display panel in the aforementioned embodiment. Referring to Figures 21, 11, and 16 to 18, the first gating module 21 receives a first frequency control signal Ctrl_1, and the second gating module 22 receives a second frequency control signal Ctrl_2. The driving method includes:

[0108] S01, control the first frequency control signal and the second frequency control signal to maintain the same potential in at least one display frame.

[0109] S02. Control the first frequency control signal and the second frequency control signal to perform potential transitions in at least one display frame. The display frame includes a first stage T01 and a second stage T02. In the first stage T01, the first frequency control signal Ctrl_1 and the second frequency control signal Ctrl_2 maintain the same potential. In the second stage T02, the first frequency control signal Ctrl_1 and the second frequency control signal Ctrl_2 undergo potential transitions, and the potential transition time of the first frequency control signal is earlier than the potential transition time of the second frequency control signal.

[0110] The two steps S01 and S02 mentioned in this method are not in any particular order.

[0111] When the first frequency control signal and the second frequency control signal maintain the same potential in a display frame, for example, both the first and second frequency control signals can be represented as low-level signals (see Figure 16), then multiple shift registers can normally output valid level signals in the scan signals, and each row of pixel driving circuits is refreshed. In a display frame, when both the first and second frequency control signals are represented as high-level signals (see Figure 17), the scan signals output by multiple shift registers only include invalid level signals, and multiple rows of pixel driving circuits will not be refreshed.

[0112] When the first frequency control signal and the second frequency control signal undergo a potential transition within a display frame, some pixel circuit rows can be refreshed while others remain unrefreshed. For example, referring to Figures 11 and 18, in the first stage T01, assuming both the first and second frequency control signals are low-level signals, the shift registers located in the first to third stages can output scan signals containing valid level signals, thus refreshing the pixel driving circuits in rows 1 to 4. In the second stage T02, when the shift register in the third stage outputs a valid level signal in the stage transmission signal, the first frequency control signal Ctrl_1 first transitions from low to high level, while the second frequency control signal Ctrl_2 remains low. Therefore, the second gating module 22 in the third-stage shift register can still output scan signals containing valid level signals to the pixel driving circuits in rows 3 and 4, while the first gating module 21 outputs scan signals containing only invalid level signals to the pixel driving circuits in rows 5 and 6, without resetting the gates of the driving transistors in the pixel driving circuits in rows 5 and 6. When the fourth-stage shift register outputs a valid level signal, the second frequency control signal Ctrl_2 has already changed from a low level to a high level, while the first frequency control signal Ctrl_1 remains high. Therefore, the scan signals output by the first gating module 21 and the second gating module 22 of the fourth-stage shift register both contain only invalid level signals. Starting from the 5th and 6th row pixel driving circuits, subsequent pixel driving circuits do not refresh. This achieves a partitioned refresh effect, where the pixel driving circuits in rows 1-4 refresh normally, while the pixel driving circuits starting from row 5 do not refresh.

[0113] Because the first gating module 21 and the second gating module 22 are introduced into the shift register in this embodiment, the first gating module 21 and the second gating module 22 in the same shift register can output different scanning signals. For example, one contains a valid level signal, while the other does not contain a valid level signal. Therefore, the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improving the display accuracy during partition refresh.

[0114] Based on the same inventive concept, this application also provides a display device. Figure 22 shows a schematic diagram of a display device 200 provided in an embodiment of this application. Referring to Figure 22, the display device 200 includes a display panel 100 as described in any of the above embodiments and a power supply. The power supply is electrically connected to the display panel 100 and is configured to provide power to the display panel 100. The display device 200 provided in this application embodiment can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 200 provided in this application embodiment has the function of the display panel provided in the embodiments of this application. The description of the display panel in the above embodiments can be referred to, and will not be repeated here.

[0115] Figure 22 illustrates one shape of the display device 200 using only a rounded rectangle structure as an example. In some other embodiments of this application, the display device 200 may also be circular, elliptical, or any other feasible shape, which is not limited in this application.

[0116] In summary, the technical solution provided in this application has the following advantages:

[0117] In the display panel and its driving method and display device provided in the embodiments of this application, the same shift register can output two kinds of scanning signals through a first gating module and a second gating module respectively. In at least some shift registers, the output terminals of the first gating module and the second gating module are respectively connected to pixel driving circuits in different rows. Assuming that in the same shift register, the first gating module is connected to the pixel driving circuit in row a, and the second gating module is connected to the pixel driving circuit in row b, when the refresh requirements for different display areas are different—for example, when the pixel driving circuit in row a needs to be refreshed, but the pixel driving circuit in row b does not—the first gating module can output an effective level signal of the scanning signal to the pixel driving circuit in row a to refresh it, and the second gating module can output an invalid level signal of the scanning signal to the pixel driving circuit in row b, eliminating the need to refresh it. This ensures that pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial for improving the display accuracy during partitioned refresh.

[0118] In this document, relational terms such as “first” and “second” are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0119] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display panel, comprising a gate driving circuit and a plurality of pixel driving circuits, wherein the gate driving circuit comprises N-stage shift registers cascaded together, where N≥2; One of the shift registers includes a cascading module and at least two gating modules connected to the cascading module, the gating modules including a first gating module and a second gating module; The cascading module is configured to output a cascading signal, wherein the cascading signal of the i-th stage shift register is the input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, and i≠j; The first gating module and the second gating module are configured to receive at least a frequency control signal and output a scanning signal through their respective output terminals; wherein, In at least a portion of the shift registers, the outputs of the first gating module and the second gating module are respectively connected to the pixel driving circuits in different rows.

2. The display panel according to claim 1, wherein, In at least one display frame, the first gating module and the second gating module in at least one of the shift registers are configured to receive different frequency control signals, respectively.

3. The display panel according to claim 2, wherein, In the at least one display frame, in at least one of the shift registers, one of the frequency control signals received by the first gating module and the second gating module is a high-level signal and the other is a low-level signal.

4. The display panel according to claim 2, wherein, In the at least one display frame, in at least one of the shift registers, the scan signal transmitted by the first gating module to the corresponding pixel driving circuit includes a valid level signal, and the scan signal output by the second gating module to the corresponding pixel driving circuit does not include a valid level signal; or, the scan signal transmitted by the first gating module to the corresponding pixel driving circuit does not include a valid level signal, and the scan signal output by the second gating module to the corresponding pixel driving circuit includes a valid level signal.

5. The display panel according to claim 1, wherein, In at least one display frame, the two gating modules in the shift register are configured to receive the same frequency control signal.

6. The display panel according to claim 5, wherein, In the at least one display frame, in at least one of the shift registers, the scan signals transmitted by the first gating module and the second gating module to the corresponding pixel driving circuit both include valid level signals, or neither includes valid level signals.

7. The display panel according to claim 1, wherein, The pixel driving circuit includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal and the second control signal terminal are configured to receive different scan signals output by the shift register; In the pixel driving circuits of the s-th and p-th rows, the second control signal terminal is connected to the output terminal of the second gating module in the shift register of the m-th stage, and the first control signal terminal is connected to the output terminal of the first gating module in the shift register of the n-th stage, where s≥1, p≥1, s≠p, and m>n≥1.

8. The display panel according to claim 7, wherein, In at least one display frame, the scan signals received by the first control signal terminal and the second control signal terminal in the pixel driving circuit of the same row both include valid level signals; or, the scan signals received by the first control signal terminal and the second control signal terminal in the pixel driving circuit of the same row neither include valid level signals.

9. The display panel according to claim 7, wherein, p = s + 1, mn = 1.

10. The display panel according to claim 9, wherein, In the pixel driving circuits of the (p+1)th and (p+2)th rows, the second control signal terminal is connected to the output terminal of the second gating module in the (m+1)th stage shift register, and the first control signal terminal is connected to the output terminal of the first gating module in the (m)th stage shift register.

11. The display panel according to claim 1, wherein the display panel comprises C circuit groups, and one circuit group comprises at least one row of pixel driving circuits; wherein, C≥1, N≥C+1; The pixel driving circuit includes a first control signal terminal and a second control signal terminal, which are configured to receive scan signals output by different shift registers. In one circuit group, the first control signal terminal of the pixel driving circuit is connected to the output terminal of the first gating module in one shift register, and the second control signal terminal of the pixel driving circuit is connected to the output terminal of the second gating module in another shift register.

12. The display panel according to claim 11, wherein, In the gate driving circuit, at least the output terminal of the second gating module in the shift register of the first stage is floating or connected to the first signal line, and the first signal line is not connected to the pixel driving circuit; Alternatively, the output of the first gating module in at least the last stage of the shift register may be floating or connected to a second signal line, which is not connected to the pixel driving circuit. Alternatively, in the gate driving circuit, the output terminal of the second gating module in the shift register at least in the first stage is floating or connected to the first signal line, and the first signal line is not connected to the pixel driving circuit; the output terminal of the first gating module in the shift register at least in the last stage is floating or connected to the second signal line, and the second signal line is not connected to the pixel driving circuit.

13. The display panel according to claim 1, wherein, In the shift register, the first gating module and the second gating module have the same circuit structure.

14. The display panel according to claim 1, wherein the display panel includes two sets of gate driving circuits, and the pixel driving circuit includes a first control signal terminal and a second control signal terminal; the first control signal terminal of the pixel driving circuit in the same row is electrically connected to the shift registers located at the same level in the two sets of gate driving circuits, and the second control signal terminal of the pixel driving circuit in the same row is electrically connected to the shift registers located at the same level in the two sets of gate driving circuits; the two shift registers connected to the pixel driving circuit in the same row are located on both sides of the pixel driving circuit in that row.

15. The display panel according to claim 1, wherein, The pixel driving circuit includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal and the second control signal terminal are configured to receive different scan signals output by the shift register; The pixel driving circuit includes a driving transistor, a reset module, and a threshold compensation module. The reset module is connected between a reset signal terminal and the gate of the driving transistor, and the threshold compensation module is connected between the gate of the driving transistor and the first terminal of the driving transistor. The control terminal of the reset module is connected to the first control signal terminal, and the control terminal of the threshold compensation module is connected to the second control signal terminal. In one of the pixel driving circuits, the first control signal terminal receives a scan signal output by the first gating module of one of the shift registers, and the second control signal terminal receives a scan signal output by the second gating module of another of the shift registers.

16. The display panel according to claim 1, wherein, The cascade module includes a control unit and a first output unit and a second output unit electrically connected to the control unit. The first output unit is connected to the control unit at a first node, and the second output unit is connected to the control unit at a second node. The first output unit and the second output unit output the cascade signal according to the signal from the first node and the signal from the second node. The gating module is configured to output the scanning signal based at least on the frequency control signal, the signal of the first node, and the signal of the second node.

17. The display panel according to claim 16, wherein, The gating module is configured to also output the scanning signal based on the cascade signal.

18. The display panel according to claim 17, wherein, The gating module includes a first output unit, a second output unit, an isolation protection unit, and an output control unit. The control terminal of the isolation protection unit receives the transmission signal, the input terminal of the isolation protection unit receives the frequency control signal, and the output terminal of the isolation protection unit is connected to the control terminal of the output control unit. The input terminal of the output control unit receives the signal from the first node, and the output terminal is connected to the control terminal of the first output unit. The input terminal of the first output unit receives a first level signal, and the output terminal is connected to the output terminal of the gating module; The control terminal of the second output unit receives the signal from the second node, the input terminal receives the second level signal, and the output terminal is connected to the output terminal of the gating module.

19. The display panel according to claim 16, wherein, The gating module includes a first output unit and a second output unit. The control terminal of the first output unit receives the signal from the first node, the input terminal receives the frequency control signal, and the output terminal is connected to the output terminal of the gating module. The control terminal of the second output unit receives the signal from the second node, the input terminal receives a second level signal, and the output terminal is connected to the output terminal of the gating module.

20. A method for driving a display panel, used to drive the display panel according to any one of claims 1 to 19, wherein, The first gating module receives a first frequency control signal, the second gating module receives a second frequency control signal, and the driving method includes: The first frequency control signal and the second frequency control signal are controlled to maintain the same potential in at least one display frame; The first frequency control signal and the second frequency control signal are controlled to undergo potential transitions in at least one display frame. The display frame includes a first stage and a second stage. In the first stage, the first frequency control signal and the second frequency control signal maintain the same potential. In the second stage, the first frequency control signal and the second frequency control signal undergo potential transitions, and the potential transition time of the first frequency control signal is earlier than the potential transition time of the second frequency control signal.

21. A display device comprising a display panel as described in any one of claims 1 to 19 and a power supply, the power supply being electrically connected to the display panel and configured to provide power to the display panel.

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