Task scheduling method and processor

Abstract

The present application provides a task scheduling method and a processor. The method comprises: a processor receives first information, the first information being used for indicating M groups, each of the M groups comprising at least one task block divided from a first task, a data correlation being present between different task blocks comprised in each group, and M being a positive integer; and the processor separately schedules the task block of each of the M groups to at least one group of dies having idle processing cores among N groups of dies of the processor, wherein each group of dies among the N groups of dies comprises at least one die, each die comprises at least one processing core, and the task block of each group is executed by the at least one idle processing core on the at least one group of dies. The method can be used to improve the overall performance of a multi-die architecture and the usability and universality of a task scheduling scheme.

Description

Task scheduling method and processor

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202510213965.7, filed on February 25, 2025, and entitled "A task scheduling method and processor", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of communication technology, and in particular to a task scheduling method and processor. BACKGROUND

[0004] A die is a small piece cut from a silicon wafer, and the die is the core part of a chip and contains all functional circuits of the chip. In a processor, the die is a carrier of a processing core, i.e., the processing core is located on the die. The processing core on the die can be used to perform all computing, accept / store commands, process data, and other tasks. One die can include one or more processing cores, and the multiple processing cores can be connected through a bus, and the multiple processing cores can share the cache and other resources of the die, thereby reducing communication delay and overall performance.

[0005] With the increasing demand for single-chip high computing power, some current processors (such as graphics processing units (GPUs), neural network processing units (NPUs), etc.) gradually apply multi-die architecture. The multi-die architecture refers to that the processor can include multiple dies inside, and the processing cores on the multiple dies can process tasks scheduled to the die in parallel. Currently, how to reasonably schedule tasks in the multi-die architecture to improve overall performance and the universality and ease of use of the scheme is a problem to be solved. SUMMARY

[0006] The present application provides a task scheduling method and processor to improve the overall performance of the multi-die architecture and the ease of use and universality of the task scheduling scheme.

[0007] In a first aspect, this application provides a task scheduling method, which can be executed by a processor. The method includes: the processor receiving first information, the first information indicating M groups, each of the M groups including at least one task block divided from a first task, the different task blocks included in each group having data correlation, and M being a positive integer; the processor scheduling the task blocks of each of the M groups to at least one group of N groups of die dies in which there are idle processing cores; wherein each of the N groups of dies includes at least one die, and each die includes at least one processing core; the task blocks of each group are executed by the at least one idle processing core on the at least one group of dies.

[0008] Based on the above method, during task scheduling, task blocks belonging to the same group based on task partitioning can be centrally scheduled to one or more dies. Therefore, task scheduling in this method is carried out at the die level. Currently, since caches of different dies can access each other through cache coherency mechanisms, unified memory access across multiple dies can be achieved. Combining this with the above-mentioned method of task scheduling at the die level, the unified memory access mechanism across multiple dies can be fully utilized to improve cache access efficiency on dies and enhance the overall effect of unified memory access across multiple dies. Furthermore, since task scheduling is carried out at the die level, there is no need to be aware of the number, distribution, or status of processing cores on the die during the task scheduling process; that is, there is no need to explicitly perceive the die size. Therefore, the above method is applicable to various die models and has high versatility and ease of use in different products. The grouping method in the above method can schedule related task blocks to the same group or multiple dies, allowing related services to be executed through the same dies as much as possible, thereby further improving cache access efficiency on each die. Based on the above method, as long as there are idle processing cores in each die group, the task blocks scheduled to this die group can be executed through those idle cores. Therefore, the response speed and processing efficiency of task scheduling and execution are both high, improving the success rate and efficiency of task scheduling and execution. It also avoids the strong constraints of simultaneous scheduling and preemption of large amounts of resources on the die, thus effectively preventing wasted computing power and overhead. In summary, the above method can improve the overall performance of multi-die architectures and the ease of use and versatility of task scheduling schemes.

[0009] In a possible design, the processor schedules the task blocks of each of the M groups to at least one of the N groups of the Die in which there are idle processing cores, including: the processor schedules the task blocks of a first group of the M groups to one of the N groups of the Die in which there are idle processing cores; and / or, the processor schedules the task blocks of a second group of the M groups to the N groups of the Die in which there are idle processing cores.

[0010] In the method, scheduling the task blocks of one group to one group of the Die can improve the cache access efficiency of the group of the Die as much as possible. Scheduling the task blocks of one group to multiple groups of the Die can help to schedule all the Die, and thus help to improve the task execution efficiency. Based on the method, the task can be scheduled in different manners flexibly, and thus the overall performance can be improved.

[0011] In a possible design, the first group belongs to at least one of the groups that are scheduled first among the M groups, and the second group belongs to at least one of the groups that are scheduled last among the M groups; where the number of the at least one of the groups that are scheduled first is divisible by the N.

[0012] In the method, scheduling the task blocks of each of the groups that are scheduled first to one group of the Die can help to execute the task blocks of the same group by a smaller number of the Die, and thus improve the cache access efficiency of each group of the Die. Scheduling the task blocks of each of the groups that are scheduled last to multiple groups of the Die can help to start as many available Die as possible, and thus improve the overall processing efficiency.

[0013] In a possible design, after the processor schedules the task blocks of a first group of the M groups to one of the N groups of the Die in which there are idle processing cores, the method further includes: when there are still idle processing cores in the one group of the Die, the processor schedules the task blocks of a third group of the M groups to the one group of the Die.

[0014] Based on the method, when the processing cores of one group of the Die can execute the task blocks of multiple groups, the task blocks of different groups can be scheduled to one group of the Die in sequence, and thus the processing cores of one group of the Die can be fully utilized to execute tasks. In addition, based on the method, in a multi-Die scenario, the task can be scheduled flexibly and reasonably in combination with the capabilities of the processing cores of each group of the Die, and thus the overall performance can be improved.

[0015] In one possible design, the method further includes: the processor dividing the processor's plurality of dies into the N groups of dies; wherein, when M equals 1, N equals 1; or, when M is greater than 1 and less than the number of the plurality of dies, N equals the maximum value that divides the number of the plurality of dies and is less than or equal to M; or, when M is greater than or equal to the number of the plurality of dies, N equals the number of the plurality of dies.

[0016] Based on this method, multiple dies can be grouped more reasonably and flexibly by combining the actual grouping of task blocks and the actual situation of dies. In different scenarios, scheduling tasks based on the above grouping method helps to schedule all dies, thereby making full use of available dies to execute tasks and improving task execution efficiency.

[0017] In one possible design, the first information includes an identifier for each group, and the identifier for each group is associated with an identifier for a task block included in each group. In this method, the group identifier clearly and easily indicates the group to which a task block belongs, which helps improve processing efficiency.

[0018] Secondly, this application provides a processor comprising a plurality of dies and a scheduler; wherein each of the plurality of dies includes at least one processing core; the scheduler is configured to receive first information indicating M groups, each of the M groups including at least one task block divided from a first task, the different task blocks included in each group having data correlation, and M being a positive integer; the scheduler is further configured to schedule the task blocks of each of the M groups to at least one group of dies among N groups of dies that have idle processing cores; wherein each group of dies includes at least one of the plurality of dies, and the task blocks of each group are executed by at least one idle processing core on the at least one group of dies.

[0019] In one possible design, when the scheduler schedules the task blocks of each of the M groups to at least one group of N dies with idle processing cores, it is specifically used to: schedule the task blocks of the first group of the M groups to one group of N dies with idle processing cores; and / or, schedule the task blocks of the second group of the M groups to the N groups of dies with idle processing cores.

[0020] In one possible design, the first group belongs to at least one group that is scheduled first among the M groups, and the second group belongs to at least one group that is scheduled later among the M groups; wherein the number of the at least one group that is scheduled first is divisible by N.

[0021] In one possible design, after scheduling the task blocks of the first group among the M groups to a group of dies with idle processing cores among the N groups of dies, the scheduler is further configured to: when there are still idle processing cores on the group of dies, schedule the task blocks of the third group among the M groups to the group of dies.

[0022] In one possible design, the first information includes an identifier for each group, the identifier of each group being associated with an identifier for a task block included in each group.

[0023] In one possible design, the scheduler is further configured to: divide the plurality of dies into the N groups of dies; wherein, when M equals 1, N equals 1; or, when M is greater than 1 and less than the number of the plurality of dies, N equals the maximum value that divides the number of the plurality of dies and is less than or equal to M; or, when M is greater than or equal to the number of the plurality of dies, N equals the number of the plurality of dies.

[0024] Thirdly, this application provides a task scheduling device, which includes a module or unit for executing the first aspect or any one of the methods described above.

[0025] Fourthly, this application provides a computer-readable storage medium storing a computer-readable program that, when run on a task scheduling device, causes the task scheduling device to perform the method described in the first aspect or any possible design of the first aspect.

[0026] Fifthly, this application provides a computer program product comprising a computer program or instructions that, when executed on a task scheduling device, cause the task scheduling device to perform the method described in the first aspect or any possible design of the first aspect.

[0027] In a sixth aspect, this application provides a chip for reading a computer program stored in a memory and executing the method described in the first aspect or any possible design of the first aspect.

[0028] In a seventh aspect, embodiments of this application provide a chip system including a processor for implementing the methods described in the first aspect or any possible design of the first aspect.

[0029] In one possible design, the chip system also includes a memory for storing programs and data necessary for the processor.

[0030] In one possible design, the chip system consists of chips, or includes chips and other discrete devices.

[0031] For the beneficial effects described in aspects two through seven above, please refer to the description of the beneficial effects in aspect one above, which will not be repeated here. Attached Figure Description

[0032] Figure 1 is a schematic diagram of a task scheduling method;

[0033] Figure 2 is a schematic diagram of the architecture of a possible task scheduling system provided in an embodiment of this application;

[0034] Figure 3 is a schematic diagram of a single-die UMA mechanism provided in an embodiment of this application;

[0035] Figure 4 is a schematic diagram of a two-die UMA mechanism provided in an embodiment of this application;

[0036] Figure 5 is a schematic diagram of a 4Die UMA mechanism provided in an embodiment of this application;

[0037] Figure 6 is a schematic diagram of a task scheduling method provided in an embodiment of this application;

[0038] Figure 7 is a schematic diagram of a task block grouping and scheduling method provided in an embodiment of this application;

[0039] Figure 8 is a schematic diagram of a task scheduling method in a single-group double-die scenario provided by an embodiment of this application;

[0040] Figure 9 is a schematic diagram of a task scheduling method in a single-group 4Die scenario provided by an embodiment of this application;

[0041] Figure 10 is a schematic diagram of a task scheduling method in a dual-group dual-die scenario provided by an embodiment of this application;

[0042] Figure 11 is a schematic diagram of a task scheduling method in a 3-group double-die scenario provided by an embodiment of this application;

[0043] Figure 12 is a schematic diagram of a task scheduling method in a 4-group double-die scenario provided by an embodiment of this application;

[0044] Figure 13 is a schematic diagram of a task scheduling method in a 3-group double-die scenario provided by an embodiment of this application;

[0045] Figure 14 is a schematic diagram of a task scheduling method in a 5-group double-die scenario provided by an embodiment of this application;

[0046] Figure 15 is a schematic diagram of a task scheduling method in a 14-group 4Die scenario provided by an embodiment of this application;

[0047] Figure 16 is a schematic diagram of a task scheduling device provided in an embodiment of this application;

[0048] Figure 17 is a schematic diagram of the structure of a task scheduling device provided in an embodiment of this application. Detailed Implementation

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0050] The methods and equipment are based on the same technical concept. Since the methods and equipment solve problems in similar ways, the implementation of the equipment and methods can refer to each other, and the repeated parts will not be described again.

[0051] The following explanations of some terms used in this application are provided to help those skilled in the art to understand them.

[0052] 1) Dynamic random access memory (DRAM) is a type of semiconductor memory that stores data in the form of electrical cores. DRAM, also known as main memory or RAM, is an internal memory that directly exchanges data with the central processing unit (CPU).

[0053] 2) A cache is a high-speed memory designed to provide fast access to stored data or computation results. When the processor processes data, it first looks for the required data in the cache. If found, it executes the data directly; otherwise, it looks for the data in main memory. Because the cache operates much faster than main memory, it can significantly improve data access speed and application response time.

[0054] Processors typically contain multiple levels of cache, each level offering faster access speeds than the next. The last level cache (LLC) is usually located between the processor and main memory; its capacity is larger than the preceding cache levels but smaller than main memory. The primary function of the LLC is to reduce access to main memory, thereby improving overall system performance. LLCs can also function as memory-side caches for DRAM.

[0055] It should be noted that in this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Multiple" in this application refers to two or more. "At least one" refers to one or more. Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0056] Single-die architecture and multi-die architecture refer to two different architectures in chip design, mainly differing in the number of dies contained within the chip. A single-die architecture means the chip contains only one independent die. This architecture is typically suitable for applications with low performance requirements or cost sensitivity. In a single-die architecture, all computational tasks are completed within a single die, reducing communication latency between dies and improving overall performance. A multi-die architecture, on the other hand, contains multiple dies. Multi-die architecture is typically suitable for high-performance computing or large-scale data processing applications. By distributing different computational tasks to different dies, multi-die architecture leverages parallel processing to improve overall performance, but it also increases communication latency and complexity between dies.

[0057] Current multi-die architectures typically employ a cluster-based task scheduling scheme. In this scheme, tasks to be executed can be divided into multiple clusters (i.e., task block clusters), where each cluster contains a certain number of task blocks, and each task block contains a subset of tasks to be executed. For example, as shown in Figure 1, if the tasks to be executed can be divided into 8 task blocks (i.e., task blocks 0-7), then every 4 task blocks can be grouped into a cluster. The code description of each task block includes the identifier of the cluster it belongs to. During task scheduling, task blocks from each cluster can be scheduled to a set of processing cores on a die (i.e., the processing cores of a cluster) and executed in parallel by the scheduled set of processing cores. A processing core (core) can be simply referred to as a core. In the above method, a set of cores must all be in an idle state and located in the same physical region. Each core in a set of processing cores is used to execute one task block in the cluster. For example, as shown in Figure 1, taking a scenario where Die 0 contains 8 cores as an example, every 4 cores located in the same physical region can be grouped into a core cluster. During task scheduling, for one cluster among the eight task blocks mentioned above, when all cores in a group on Die0 are idle, the four task blocks in that cluster can be executed on the four cores in the idle group. For example, as shown in Figure 1, when cores 0-4 belonging to the same group are all idle, task blocks 0-4 belonging to the same cluster can be scheduled to cores 0-4 for execution. In the above method, since the code description of each task block includes the identifier of the cluster to which the task block belongs, and task blocks in the same cluster need to be scheduled to the same group of cores and each core executes one task block, the above method requires that when scheduling task blocks in the same cluster, the number of cores in a group called by each cluster's task block must be the same as the number of task blocks in each cluster, and the called group of cores must all be in an idle state before the call. If this requirement is not met, scheduling will fail. For example, if not all cores in each group in Die0 are idle, or if each group of cores in Die0 only includes two cores, then task blocks 0-4 belonging to the same cluster cannot be scheduled to Die0 for execution. Therefore, in the above method, each cluster has a strong constraint on the simultaneous scheduling and preemption of a set of cores on the die (i.e., a set of cores must be idle before scheduling), which leads to a waste of computing resources on the die and overhead at the beginning and end. Furthermore, during task scheduling, it is necessary to determine how many cores each cluster needs to call, thus requiring explicit awareness of the size of the core clusters on the die; that is, programming must be based on the size of the core clusters on the die during the programming phase. However, the size of the core clusters on the die varies depending on the die model, therefore the above solution has low universality across different products.Furthermore, the task scheduling methods described above are performed at the cluster level, which limits their effectiveness in improving data reuse on dies and their benefits for unified memory access (UMA) across multiple dies. In summary, the overall performance, ease of use, and versatility of the above-described task scheduling schemes are poor.

[0058] To address the above issues and improve the overall performance of multi-die architectures, as well as the ease of use and versatility of task scheduling schemes, this application provides a task scheduling method and processor. This method can be applied to any system, chip (e.g., system-on-chip (SoC)), device, or apparatus (e.g., communication equipment, terminal equipment) containing multiple processors. For ease of description and understanding, the following embodiments use the application of this method to a system composed of the first and second processors shown in Figure 2 as an example. Methods for scenarios with more processors can be implemented with reference to the following methods, which will not be detailed in this application embodiment.

[0059] In this embodiment, the first processor can be used to divide and group the task to be executed into task blocks at the software layer and instruct the second processor on relevant information. The specific execution process can be referred to the description in the embodiments below, and will not be detailed here. For example, the first processor can be a CPU.

[0060] As shown in Figure 2, the second processor may include multiple dies. Each die includes at least one processing core. For ease of description, in the following embodiments of this application, the processing core on the die is simply referred to as a core, and an idle processing core is simply referred to as an idle core or idle core. In some embodiments of this application, the second processor may include a scheduler, which may be located on one die of the second processor or may be distributed across multiple dies of the second processor. The scheduler may be used to receive relevant information from the first processor regarding task block partitioning and grouping, and based on the relevant information, to group and schedule the task blocks partitioned for the task to be executed to multiple dies for execution. The specific execution process can be referred to the description in the embodiments below, which will not be detailed here. For example, the second processor may be a GPU, NPU, or other processor mainly used for performing complex computing tasks; such processors may be collectively referred to as XPUs.

[0061] In some embodiments of this application, multiple dies in the second processor can implement UMA based on cache coherence, thereby improving the performance and ease of use of the multi-die architecture. UMA refers to treating the DRAM of a single chip as a single unit, without further intra-chip segmentation of DRAM memory allocation. Specifically, each die can have a private cache (i.e., a cache dedicated to its own die). Cores on each die can only directly access data in their own private cache, and mutual access between private caches of different dies relies on consistency. Optionally, each die's private cache can be an LLC. When a core on a die accesses its own private cache, if the private cache does not contain matching data, the private cache can first check if matching data exists in the private caches of other dies. If matching data exists in the private caches of other dies, the data is retrieved from those private caches; otherwise, the data is retrieved from the DRAM. The following examples illustrate the single-die scene shown in Figure 3, the two-die scene shown in Figure 4, and the four-die scene shown in Figure 5.

[0062] For example, as shown in Figure 3, in a single-die scenario, taking a die containing core 0 and core 1 as an example, the LLC can be used as a memory-side cache for DRAM. All data is cached only once in the LLC, and all cores on the die (e.g., core 0 and core 1) can directly access the data in the LLC. Similarly, in an example, as shown in Figure 4, taking a two-die scenario including Die 0 and Die 1 as an example, P0 and P1 are LLCs respectively. P0 can be used as a private cache for Die 0, and P1 can be used as a private cache for Die 1. P0 and P1 can communicate with each other based on consistency (called cache communication UMA mode). DRAM is used as main memory (or RAM). Die 0 and Die 1 each contain at least one core. Cores on Die 0 can only directly access P0, and cores on Die 1 can only directly access P1. When Die0 accesses P0, if P0 does not contain the required data, P0 retrieves the data from P1. If P1 also does not contain the required data, P0 retrieves the data from DRAM. Similarly, when Die1 accesses P1, if P1 does not contain the required data, P1 retrieves the data from P0. If P0 also does not contain the required data, P1 retrieves the data from DRAM. Based on this access mechanism, two-die UMA can be implemented, improving system performance in two-die scenarios. In another example, as shown in Figure 5, taking a 4-die scenario including Die0, Die1, Die2, and Die3 as an example, P0-P3 are LLCs, and P0-P3 can be used as private caches for Die0-Die3 respectively. P0-P3 can rely on consistency to complete mutual access. DRAM is the main memory. The access mechanism in the 4-die scenario shown in Figure 5 can be referred to the corresponding access mechanism in Figure 4, and will not be repeated here. Based on the access mechanism shown in Figure 5 for the 4-Die scenario, 4-Die UMA can be implemented, improving system performance in the 4-Die scenario. Other multi-Die scenarios (such as 3-Die or more-Die scenarios) can be implemented by referring to the two-Die or 4-Die scenario implementations, and will not be listed here.

[0063] It should be understood that the system architecture shown in Figure 2 is merely an example. In practical applications, the system may include more or fewer components than those shown in Figure 2, and this application embodiment does not limit the scope of the invention. The system shown in Figure 2 is only an example, and the system may have more or fewer components than those shown in Figure 2, may combine two or more components, or may have different component configurations. The various components shown in Figure 2 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0064] Taking the system architecture shown in Figure 2 as an example, a possible task scheduling method provided by this application embodiment can be seen with reference to Figure 6. As shown in Figure 6, the method may include:

[0065] S601: The first processor sends first information to the second processor; wherein the first information is used to indicate M groups, each of the M groups including at least one task block divided from the first task, and M is a positive integer.

[0066] Each task block in at least one of the task blocks includes a portion of the tasks in the first task. For example, the first information may be a task descriptor for the first task.

[0067] In some embodiments of this application, each task can be represented by a kernel function. The kernel function defines the algorithm to be executed on the second processor. The kernel function can be called on the first processor and started and run on the second processor. The first task can be any task in a task stream. The task stream can contain multiple kernel function calls, each kernel function call representing a task, and each kernel function call is executed in the order it is added to the stream. In embodiments of this application, the code description (or function code) of each task block does not include an identifier of the group to which the task block belongs.

[0068] In some embodiments of this application, before sending the first information to the second processor, the first processor may generate the first information in response to a first instruction. The first instruction is used to indicate that the first task is divided into M groups. Optionally, the first instruction may originate from programming instructions. For example, a user can use a programming model to generate programming code related to the first instruction. A programming model is a software development method or framework. A programming model defines a model of a software system through the structure and syntax of a programming language and converts these models into executable code. In embodiments of this application, the programming model may define logical layers such as task flows, kernel functions (tasks), groups, and task blocks. The programming code generated by the user based on the programming model may include code related to the first instruction. During the execution of the programming code, the first processor can obtain the first instruction and respond to it based on the above method.

[0069] In one possible approach, the first instruction can also be used to indicate the partitioning method (or partitioning rule) for dividing the first task into M groups. For example, a user can simultaneously write code in their programming code related to the partitioning method for dividing the first task into M groups. Based on this approach, the user can manually create the groups under the task. In another possible approach, the first processor can automatically divide the first task into M groups. Based on this approach, the system can automatically create the groups under the task, which helps improve efficiency.

[0070] In the above method, dividing the first task into M groups can include grouping related task blocks from the multiple task blocks obtained from the first task into the same group. Related task blocks can be task blocks with data correlation. Data correlation can include correlation between upstream and downstream tasks and / or correlation within the same task. Data correlation can also be understood as data reuse, data reuse, or data dependency, etc.

[0071] In some embodiments of this application, the first information may include an identifier for each of the M groups, wherein the identifier of each group is associated with an identifier for a task block included in each group, or the identifier of each group is associated with a task block included in each group. Optionally, the identifier of each group may be indicated by a first instruction or may be automatically generated by a first processor.

[0072] S602: Based on the first information, the second processor schedules the task blocks of each of the M groups to at least one group of N groups of dies with idle processing cores; wherein, each group of N groups of dies includes at least one die, and each die includes at least one processing core.

[0073] Optionally, step S602 can be executed by the scheduler in the second processor. The specific implementation method of step S602 is described in detail below.

[0074] In some embodiments of this application, after receiving the first information, the scheduler in the second processor can divide the multiple dies used for task execution in the second processor into N groups of dies based on the number of M groups indicated by the first information, i.e., the value of M. Then, based on the grouping of the task blocks indicated by the first information and in conjunction with the grouping of the dies, schedule the M groups of task blocks. The multiple dies used for task execution may include some or all of the dies in the second processor. For example, the multiple dies used for task execution may include multiple dies in the second processor other than the dies where the scheduler is deployed.

[0075] For example, as shown in Figure 7, taking a scenario where the first task can be divided into eight task blocks (0-7) and the second processor includes two sets of dies, task blocks 0-3 can be assigned to group 0, and task blocks 4-7 can be assigned to group 1. Task blocks in group 0 can be scheduled to a set of dies, and task blocks in group 1 can also be scheduled to a set of dies. Each die can execute the task blocks scheduled to it as long as there are idle cores available. The number of dies in each group and the scheduling method of each group of task blocks shown in Figure 7 are only for illustrative purposes.

[0076] The following sections will provide detailed explanations of scenarios 1-3.

[0077] Scenario 1, M=1.

[0078] In this scenario, there is only one group. The scheduler in the second processor can group multiple dies together, meaning N can equal 1. This means that task blocks from a single group can be centrally scheduled across multiple dies. In this method, each of the multiple dies can include at least one core. After centrally scheduling the task blocks from a single group across multiple dies, each die can begin executing the task blocks scheduled to that die as long as it has idle cores (which can be one or more). Idle cores refer to cores that have no tasks (or task blocks) executing.

[0079] For example, taking a scenario with a single group (Group 0) and multiple dies (Die 0 and Die 1) as shown in Figure 8, in the scenario of a single group with two dies, based on the above method, the scheduler can schedule task blocks in Group 0 to Die 0 and Die 1. As long as there are idle cores in Die 0 and Die 1, the task blocks scheduled to this die can be executed through the idle cores.

[0080] For example, taking a scenario with a single group (Group 0) and multiple dies (Die 0, Die 1, Die 2, and Die 3) as shown in Figure 9, in a single-group four-die scenario, based on the above method, the scheduler can schedule task blocks in Group 0 to Die 0, Die 1, Die 2, and Die 3. As long as there are idle cores in Die 0, Die 1, Die 2, and Die 3, the task blocks scheduled to this die can be executed using those idle cores.

[0081] Scenario 2, M > 1.

[0082] In this scenario, the scheduler in the second processor can divide multiple dies into one or more groups, i.e., N≥1 and N is less than or equal to the number of dies.

[0083] In the first possible case, when M is less than the number of dies, N can be a positive integer less than or equal to M. The scheduler can group the dies evenly or unevenly. In evenly grouped dies, all N groups have the same number of dies. In unevenly grouped dies, all N groups may have different numbers of dies or some may have the same number of dies.

[0084] In one example, N can equal M. In this scenario, when N is divisible by M, the grouping of multiple dies can be considered uniform. When N is not divisible by M, the grouping of multiple dies is considered uneven. For example, in a scenario with 2 groups and 4 dies, the 4 dies can be divided into two groups, each containing 2 dies. As another example, in a scenario with 2 groups and 5 dies, the 5 dies can be divided into two groups, one containing 2 dies and the other containing 3 dies. Alternatively, in a scenario with 2 groups and 5 dies, the 5 dies can be grouped into one group.

[0085] In another example, N can be equal to the maximum value of M that is divisible by the number of dies. Based on this method, multiple dies can be evenly grouped. For example, in a scenario with 2 groups and 4 dies, the 4 dies can be divided into two groups, each containing 2 dies. Similarly, in a scenario with 5 groups and 4 dies, the 4 dies can be divided into two groups, each containing 2 dies. And again, in a scenario with 5 groups and 6 dies, the 6 dies can be divided into three groups, each containing 2 dies.

[0086] In the second possible scenario, when M is greater than or equal to the number of dies, N can be equal to the number of dies. In this scenario, the scheduler in the second processor groups the dies into uniform groups, resulting in each group containing one die; that is, each die forms a group.

[0087] For example, in a scenario with more than 2 groups and 2 dies, the 2 dies can be divided into two groups, with each group containing 1 die. In a scenario with more than 4 groups and 4 dies, the 4 dies can be divided into four groups, with each group containing 1 die.

[0088] In either the first or second possible scenario described above, the scheduler in the second processor can schedule the M grouped task blocks to N groups of dies based on any of the following methods 1-3. Each of the N groups of dies can execute the task blocks scheduled to its own die using any available core.

[0089] Method 1: Following the order of the M groups, process each of the M groups in turn as follows: schedule the task block of the group to one of the N groups of dies.

[0090] In the first possible approach, the set of dies can be selected sequentially from multiple sets of dies. That is, each time a task block of a group is scheduled, a set of dies is selected sequentially from multiple sets of dies. This method can also be understood as: using the remainder value of the sorting number of the currently scheduled group among the M groups divided by N as the set of dies for executing the task block of the currently scheduled group. Each of the N sets of dies corresponds to a remainder value, and different sets of dies correspond to different remainder values.

[0091] In the second possible scheme, the group of dies can be a group of dies with idle cores, where an idle core refers to a core with no tasks being executed. Optionally, the group of dies with idle cores can be a group of dies that has not executed any task blocks of any of the M groups, or a group of dies that has previously executed or is currently executing task blocks of at least one of the M groups. No specific restrictions are imposed in the embodiments of this application.

[0092] Optionally, in scenarios where M is divisible by N, method 1 can be used for task scheduling.

[0093] The following examples 1 to 3 illustrate method 1.

[0094] Example 1: In an example scenario where M=2, M groups including group 0 and group 1, and multiple dies including die0 and die1, as shown in Figure 10, based on the aforementioned grouping method, the scheduler can divide the multiple dies into two groups: die0 and die1. The scheduler can schedule task blocks of group 0 and task blocks of group 1 sequentially. As an optional implementation, based on the first possible scheme in method 1 above, as shown in Figure 10, the scheduler can first schedule the task blocks of group 0 to die0, and then schedule the task blocks of group 1 to die1. The dashed box in Figure 10 represents a die group. As another optional implementation, based on the second possible scheme in method 1 above, the scheduler can first schedule the task blocks of group 0 to die0. When scheduling task blocks of group 1, if there are idle cores in both die0 and die1, the scheduler can schedule the task blocks of group 1 to either die0 or die1.

[0095] Example 2: In an example, taking a scenario where M=3, M groups including group 0, group 1, and group 2, and multiple dies including die0 and die1 as shown in Figure 11, based on the aforementioned grouping method, the scheduler can divide the multiple dies into two groups: die0 and die1. The scheduler can schedule task blocks of group 0, task blocks of group 1, and task blocks of group 2 sequentially. As an optional implementation, based on the second possible scheme in method 1 above, the scheduler can first schedule the task blocks of group 0 to die0. After the task blocks of group 0 are scheduled, if the only die with available cores is die1, the scheduler can schedule the task blocks of group 1 to die1. After the task blocks of group 1 are scheduled, if there are available cores in die0 but not in die1, the scheduler can schedule the task blocks of group 2 to die0. The dashed boxes in Figure 11 represent a die group.

[0096] Example 3: In an example, taking a scenario where M=4, M groups including group 0, group 1, group 2, and group 3, and multiple dies including Die 0 and Die 1 as shown in Figure 12, based on the aforementioned grouping method, the second processor can divide the multiple dies into two groups: Die 0 and Die 1. The scheduler can schedule the task blocks of group 0, group 1, group 2, and group 3 sequentially. As an optional implementation, based on the first possible scheme in Method 1 above, the second processor can schedule the task blocks of group 0 to Die 0, the task blocks of group 1 to Die 1, the task blocks of group 2 to Die 0, and the task blocks of group 3 to Die 1. The dashed boxes in Figure 12 represent a Die group.

[0097] Method 2: Following the order of the M groups, process each of the first K groups in the M groups as follows: schedule the task blocks of that group to one of the N groups of dies; following the order of the M groups, process each of the last L groups in the M groups as follows: schedule the task blocks of that group to the N groups of dies. Where K and L are positive integers, and the sum of K and L is M.

[0098] In the first possible solution, the group of dies can be a group of dies selected in the order of multiple groups of dies. For details on this solution, please refer to the relevant description in the first possible solution of Method 1 above; it will not be repeated here. In the second possible solution, the group of dies can be a group of dies with available cores. For details on this solution, please refer to the relevant description in the second possible solution of Method 1 above; it will not be repeated here.

[0099] The method for scheduling a group of task blocks to an idle group of N groups of dies can be found in the relevant method described in Method 1, and will not be repeated here.

[0100] Optionally, K can be equal to the maximum value that is divisible by N and less than M, and L can be equal to the value of M modulo N.

[0101] Optionally, in scenarios where M is not divisible by N, method 2 can be used for task scheduling.

[0102] The following examples 4 to 6 illustrate method 2.

[0103] Example 4: In an example, taking a scenario where M=3, M groups including group 0, group 1, and group 2, and multiple dies including die0 and die1 as shown in Figure 13, based on the aforementioned grouping method, the scheduler can divide the multiple dies into two groups: die0 and die1. The scheduler can schedule the task blocks of group 0, group 1, and group 2 sequentially. As an optional implementation, based on the first possible scheme in method 2 above, as shown in Figure 13, the scheduler can first schedule the task blocks of group 0 to die0, then schedule the task blocks of group 1 to die1, and finally schedule the task blocks of group 2 to both die0 and die1. The dashed boxes in Figure 13 represent a die group.

[0104] Example 4: In an example scenario where M=5, M groups (including groups 0-4), and multiple dies (including dies 0 and dies 1) are used, as shown in Figure 14, based on the aforementioned grouping method, the scheduler can divide the multiple dies into two groups: dies 0 and dies 1. The scheduler can then schedule task blocks from groups 0 to 4 sequentially. As an optional implementation, based on the second possible scheme in method 2 above, as shown in Figure 14, the scheduler can first schedule task blocks from group 0 to dies 0 where there are idle cores. When scheduling task blocks from group 1, if only dies 1 have idle cores, the scheduler can schedule task blocks from group 1 to dies 1. When scheduling task blocks from group 2, if only dies 1 have idle cores, the scheduler can schedule task blocks from group 2 to dies 1. When scheduling task blocks from group 3, if only dies 0 have idle cores, the scheduler can schedule task blocks from group 3 to dies 0. When scheduling task blocks for group 4, the scheduler can schedule task blocks for group 4 to Die0 and Die1. The dashed boxes in Figure 14 represent a Die group.

[0105] Example 6: In an example scenario where M=14, M groups include group 0-group 13, and multiple dies include Die0, Die1, Die2, and Die3, as shown in Figure 15, based on the aforementioned grouping method, the scheduler can divide the multiple dies into a group of Die0, a group of Die1, a group of Die2, and a group of Die3. The scheduler can then schedule the task blocks of groups 0-13 sequentially. As an optional implementation, based on the first possible scheme in Method 2 above, as shown in Figure 15, during the scheduling process, the scheduler can schedule the task blocks of groups 0, 4, and 8 to Die 0, the task blocks of groups 1, 5, and 9 to Die 1, the task blocks of groups 2, 6, and 10 to Die 2, the task blocks of groups 3, 7, and 11 to Die 3, and the task blocks of groups 12 and 13 to Die 0-Die 3. That is, group 12 can be centrally scheduled across the four Dies (Die 0-Die 3), and group 13 can also be centrally scheduled across the four Dies (Die 0-Die 3). The dashed boxes in Figure 15 represent a single Die group.

[0106] In the method provided in the above embodiments, the scheduler in the second processor can efficiently and reasonably schedule tasks based on the grouping of task blocks and the actual situation of multiple dies in the second processor, with task block grouping and die grouping as the granularity. This helps to improve the system memory access effect during task execution and improve overall performance.

[0107] It should be understood that the implementation process provided in the above embodiments is merely an example illustrating the applicable method flow of the embodiments of this application. The execution order of each step can be adjusted according to actual needs, and other steps can be added or some steps can be removed. The execution order between steps that are not temporally related can be arbitrary, and this embodiment of the application does not impose any restrictions on this.

[0108] It should be noted that the application scenarios or various examples provided in the above embodiments are merely illustrative examples of the applicable scenarios of the embodiments of this application, and do not limit the applicable scenarios of the solutions of this application. Some methods or the same technical concepts provided in any of the above embodiments or scenarios can also be applied in other embodiments or other scenarios, or can be combined with methods provided in other embodiments or other scenarios. Specifically, they can be applied in combination with specific embodiments or specific scenarios, and will not be listed and described one by one in this application.

[0109] Based on the above embodiments and the same technical concept, this application also provides a task scheduling device, which is used to implement the method applied to the scheduler provided in the above embodiments. Optionally, the task scheduling device can be a scheduler. Referring to FIG16, the task scheduling device 1600 may include a transceiver unit 1601 and a scheduling unit 1602.

[0110] In one example, the transceiver unit 1601 can be used to receive first information indicating M packets, each of the M packets including at least one task block divided from a first task, with data correlation between different task blocks included in each packet, where M is a positive integer; the scheduling unit 1602 can be used to schedule the task blocks of each of the M packets to at least one set of dies with idle processing cores in the N sets of die dies of the processor; wherein each set of dies includes at least one die, and each die includes at least one processing core; the task blocks of each packet are executed by at least one idle processing core on the at least one set of dies.

[0111] In one possible design, when the scheduling unit 1602 schedules the task blocks of each of the M groups to at least one group of the N groups of dies in the processor that has idle processing cores, it is specifically used to: schedule the task blocks of the first group of the M groups to one group of dies in the N groups of dies that has idle processing cores; and / or, schedule the task blocks of the second group of the M groups to the N groups of dies that have idle processing cores.

[0112] In one possible design, the first group belongs to at least one group that is scheduled first among the M groups, and the second group belongs to at least one group that is scheduled later among the M groups; wherein the number of the at least one group that is scheduled first is divisible by N.

[0113] In one possible design, after scheduling the task blocks of the first group among the M groups to a group of dies with idle processing cores among the N groups of dies, the scheduling unit 1602 is further configured to: when there are still idle processing cores on the group of dies, schedule the task blocks of the third group among the M groups to the group of dies.

[0114] In one possible design, the first information includes an identifier for each group, the identifier of each group being associated with an identifier for a task block included in each group.

[0115] In one possible design, the scheduling unit 1602 is further configured to: divide the processor's multiple dies into the N groups of dies; wherein, when M equals 1, N equals 1; or, when M is greater than 1 and less than the number of the multiple dies, N equals the maximum value that divides the number of the multiple dies and is less than or equal to M; or, when M is greater than or equal to the number of the multiple dies, N equals the number of the multiple dies.

[0116] Based on the above embodiments and the same technical concept, this application also provides a task scheduling device for implementing the method provided in the above embodiments applied to a first processor and / or a second processor. Referring to FIG17, the task scheduling device 1700 may include one or more processors 1701. Optionally, the task scheduling device 1700 further includes a memory 1702 and / or a communication interface 1703. The memory may be located inside or outside the task scheduling device, and this application does not limit this. The communication interface 1703, the processor 1701, and the memory 1702 are interconnected. Exemplarily, one or more processors 1701 may include the first processor and / or the second processor described in the above embodiments of this application.

[0117] Optionally, the communication interface 1703, the processor 1701, and the memory 1702 are interconnected via a bus 1704. The bus 1704 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in Figure 17, but this does not indicate that there is only one bus or one type of bus.

[0118] The communication interface 1703 is used to receive and / or send signals and data to enable communication with other devices besides the task scheduling device.

[0119] The processor 1701 can be used to execute the methods applied to the first processor or the second processor provided in the foregoing embodiments, as specifically described in the above embodiments, and will not be elaborated here. The processor 1701 can be a combination of one or more processors such as a CPU, GPU, or NPU. The processor 1701 may further include a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. When implementing the above functions, the processor 1701 can be implemented in hardware, or it can be implemented by hardware executing corresponding software.

[0120] The memory 1702 is used to store program instructions, etc. Specifically, the program instructions may include program code, which includes computer operation instructions. The memory 1702 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The processor 1701 can execute the program instructions stored in the memory 1702 to implement the method provided in the above embodiments.

[0121] Based on the above embodiments and the same technical concept, this application also provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the method provided in the above embodiments.

[0122] Based on the above embodiments and the same technical concept, this application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer performs the method provided in the above embodiments.

[0123] Based on the above embodiments and the same technical concept, this application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer performs the method provided in the above embodiments.

[0124] The methods provided in this application can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. A computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs), or semiconductor media (e.g., SSDs), etc.

[0125] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A task scheduling method, characterized in that, The method includes: The processor receives first information, which indicates M groups, each of the M groups including at least one task block divided from the first task, and there is data correlation between different task blocks included in each group, where M is a positive integer; The processor schedules the task blocks of each of the M groups to at least one group of dies in the processor's N groups of die dies where there are idle processing cores; wherein, each of the N groups of dies includes at least one die, and each die includes at least one processing core; the task blocks of each group are executed by at least one idle processing core on the at least one group of dies.

2. The method as described in claim 1, characterized in that, The processor schedules the task blocks of each of the M groups to at least one group of the processor's N groups of dies that have idle processing cores, including: The processor schedules the task blocks of the first group out of the M groups to a group of dies with available processing cores among the N groups of dies; and / or The processor schedules the task blocks of the second group out of the M groups to the N groups of dies where there are idle processing cores.

3. The method as described in claim 2, characterized in that, The first group belongs to at least one group that is scheduled first among the M groups, and the second group belongs to at least one group that is scheduled later among the M groups; wherein the number of the at least one group that is scheduled first is divisible by N.

4. The method as described in claim 2 or 3, characterized in that, After the processor schedules the task blocks of the first group out of the M groups to a group of dies with idle processing cores among the N groups of dies, the method further includes: When there are still idle processing cores on the group of dies, the processor schedules the task block of the third group among the M groups to the group of dies.

5. The method according to any one of claims 1 to 4, characterized in that, The first information includes an identifier for each group, and the identifier for each group is associated with the identifier of the task block included in each group.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: the processor dividing the processor's multiple dies into the N groups of dies; wherein, When M equals 1, N equals 1; or When M is greater than 1 and less than the number of dies, N is equal to the maximum value that divides the number of dies and is less than or equal to M; or When M is greater than or equal to the number of the plurality of dies, N is equal to the number of the plurality of dies.

7. A processor, characterized in that, The processor includes multiple dies and a scheduler; wherein each of the multiple dies includes at least one processing core; The scheduler is configured to receive first information, which indicates M groups, each of the M groups including at least one task block divided from the first task, and there is data correlation between different task blocks included in each group, where M is a positive integer; The scheduler is further configured to schedule the task blocks of each of the M groups to at least one group of dies in the N groups of dies where there are idle processing cores; wherein, each of the N groups of dies includes at least one of the plurality of dies, and the task blocks of each group are executed by at least one idle processing core on the at least one group of dies.

8. The processor as described in claim 7, characterized in that, When the scheduler schedules the task blocks of each of the M groups to at least one group of dies with idle processing cores in the N groups of dies, it is specifically used for: Schedule the task blocks of the first group among the M groups to a group of dies among the N groups of dies that have idle processing cores; and / or The task blocks of the second group among the M groups are scheduled to the N groups of Dies where there are idle processing cores.

9. The processor as described in claim 8, characterized in that, The first group belongs to at least one group that is scheduled first among the M groups, and the second group belongs to at least one group that is scheduled later among the M groups; wherein the number of the at least one group that is scheduled first is divisible by N.

10. The processor as claimed in claim 8 or 9, characterized in that, After scheduling the task blocks of the first group out of the M groups to a group of dies with idle processing cores among the N groups of dies, the scheduler is further configured to: When there are still idle processing cores on the group of dies, the task blocks of the third group among the M groups are scheduled to the group of dies.

11. The processor according to any one of claims 8 to 10, characterized in that, The first information includes an identifier for each group, and the identifier for each group is associated with the identifier of the task block included in each group.

12. The processor according to any one of claims 8 to 11, characterized in that, The scheduler is further configured to: divide the plurality of dies into the N groups of dies; wherein... When M equals 1, N equals 1; or When M is greater than 1 and less than the number of dies, N is equal to the maximum value that divides the number of dies and is less than or equal to M; or When M is greater than or equal to the number of the plurality of dies, N is equal to the number of the plurality of dies.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on the device, causes the device to perform the method as described in any one of claims 1 to 6.

14. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when executed on a device, cause the device to perform the method as described in any one of claims 1 to 6.

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