Panel assembly and electronic device

Abstract

The present application belongs to the technical field of electronic devices. Disclosed are a panel assembly and an electronic device. The panel assembly comprises: a display panel, wherein the display panel is provided with traces, and the display panel comprises a bonding region, the traces being located outside the bonding region; at least one support pad, which is arranged in the bonding region; and crack arrest pads, which are arranged on the display panel, wherein the crack arrest pads are configured to prevent cracks from extending to the traces.

Description

Panel components and electronic devices

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202510207286.9, filed on February 25, 2025, entitled "Pattern Assembly and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of electronic equipment technology, specifically relating to a panel assembly and an electronic device. Background Technology

[0004] With the rapid development of the display industry, many electronic devices are gradually adopting low-cost solutions to reduce costs while meeting performance requirements.

[0005] In related technologies, an increasing number of display chips are choosing to use display integrated circuits (Ramless ICs) that do not contain built-in random access memory. Display integrated circuits without built-in random access memory have the advantages of smaller size and lower cost.

[0006] Because the display integrated circuits in related technologies are small in size and the bonding area of ​​the display integrated circuits is not well supported, there is a problem that the traces outside the bonding chip area of ​​the display panel are prone to breakage. Summary of the Invention

[0007] This application provides a panel assembly and an electronic device that solves the problem that traces outside the bonding chip area of ​​a display panel are prone to breakage.

[0008] In a first aspect, embodiments of this application provide a panel assembly, including: a display panel, on which traces are disposed, and the display panel includes a bonding area, the traces being located outside the bonding area; at least one support pad disposed in the bonding area; and a crack-stop pad disposed in the display panel, wherein the crack-stop pad is used to prevent cracks from extending to the traces.

[0009] Secondly, embodiments of this application provide an electronic device, including: a panel assembly as described in any of the above technical solutions; and a chip disposed within the bonding area of ​​the display panel in the panel assembly.

[0010] In this embodiment, support pads and crack-stop pads are provided on the display panel. The crack-stop pads can improve the support performance between the display panel and the chip, reduce the deformation of the traces at the chip edge, and reduce the possibility of cracks between the display panel and the chip. Furthermore, the crack-stop pads are located on the crack propagation path, so even if cracks occur between the panel and the chip, the crack-stop pads can block the cracks. This solves the problem of easy breakage of traces outside the bonding area of ​​the display panel and improves the structural stability of the panel assembly after bonding. Attached Figure Description

[0011] Figure 1 shows a schematic diagram of one of the panel components provided in some embodiments of this application;

[0012] Figure 2 shows a second schematic diagram of the structure of the panel assembly provided in some embodiments of this application;

[0013] Figure 3 shows a third schematic diagram of the structure of the panel assembly provided in some embodiments of this application;

[0014] Figure 4 shows a fourth schematic diagram of the structure of the panel assembly provided in some embodiments of this application;

[0015] Figure 5 shows a fifth schematic diagram of the structure of the panel assembly provided in some embodiments of this application;

[0016] Figure 6 shows a sixth schematic diagram of the structure of the panel assembly provided in some embodiments of this application;

[0017] Figure 7 shows a schematic diagram of the structure of the chip and display panel provided in some embodiments of this application;

[0018] Figure 8 shows one of the structural schematic diagrams of the anti-crack pads provided in some embodiments of this application;

[0019] Figure 9 shows a second schematic diagram of the structure of the anti-crack pad provided in some embodiments of this application;

[0020] Figure 10 shows a third schematic diagram of the structure of the anti-crack pad provided in some embodiments of this application;

[0021] Figure 11 shows a schematic diagram of the structure of an electronic device provided in some embodiments of this application.

[0022] The attached figures are labeled as follows:

[0023] 10 Panel assembly, 100 Display panel, 110 Bonding area, 120 Trace, 130 Support pad, 140 Crack-stop pad, 1401 First pad, 1402 Second pad, 1403 Opening, 1404 Gap, 1405 Pixel circuit gate layer, 1406 Pixel signal line layer, 1407 First signal line layer, 1408 Second signal line layer, 1409 Touch trace layer, 1410 Barrier layer, 1411 First insulating layer, 1412 Metal layer, 1413 Second insulating layer, 200 Electronic device, 201 Chip, 300 Crack. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0025] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0026] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] The panel components and electronic devices provided in this application will be described in detail below with reference to Figures 1 to 11, through specific embodiments and application scenarios.

[0029] In some embodiments of this application, a panel assembly is provided. Figure 1 shows one structural schematic diagram of the panel assembly provided in some embodiments of this application, Figure 2 shows another structural schematic diagram of the panel assembly provided in some embodiments of this application, Figure 3 shows a third structural schematic diagram of the panel assembly provided in some embodiments of this application, Figure 4 shows a fourth structural schematic diagram of the panel assembly provided in some embodiments of this application, Figure 5 shows a fifth structural schematic diagram of the panel assembly provided in some embodiments of this application, and Figure 6 shows a sixth structural schematic diagram of the panel assembly provided in some embodiments of this application. As shown in Figures 1, 2, 3, 4, 5, and 6, the panel assembly 10 includes: a display panel 100, on which traces 120 are provided, and the display panel 100 includes a bonding area 110, with the traces 120 located outside the bonding area 110; at least one support pad 130 disposed in the bonding area 110; and a crack-stop pad 140 disposed in the display panel 100, wherein the crack-stop pad 140 is used to prevent cracks from extending to the traces 120.

[0030] In this embodiment, the panel assembly 10 includes a display panel 100, on which a trace 120 is provided. The trace 120 is a Gate-On-Array (GOA) trace integrated on an array substrate, and the trace 120 is located outside the bonding region 110. The bonding region 110 in the display panel 100 is used for bonding chips. The support pad 130 on the bonding region 110 is a pad on the display panel 100. The support pad 130 can be disposed opposite to the chip pad on the chip. When the chip and the display panel 100 are packaged together, the support pad 130 and the chip pad of the chip together play a supporting role between the display panel 100 and the chip.

[0031] For example, both the support pad 130 and the chip pad on the chip are dummy pads. The dummy pads only serve a supporting function and are not used to connect the traces 120. When bonding the chip to the display panel 100, the support pad 130 and the chip pad on the chip are set opposite to each other so that the support pad 130 and the chip pad together support the display panel 100 and the chip.

[0032] It should be noted that when the chip is bonded to the display panel 100, insufficient support in the bonding area 110 where the chip is located may cause cracks in the bonding area 110, and the cracks in the bonding area 110 will extend to the trace 120.

[0033] Table 1 shows the pressure table for a single pad, as shown in Table 1:

[0034] Table 1

[0035] Figure 7 shows a schematic diagram of the chip and display panel provided in some embodiments of this application. As shown in Figure 7, the integrated circuit without built-in random access memory (RAM) has a reduced number of output pins and dummy pads at the edges. That is, the number of support pads 130 between chip 201 and display panel 100 is reduced, and the input and output pins are farther from the left and right edges, resulting in excessive deformation of the edge traces 120 of display panel 100. When a crack 300 occurs between chip 201 and display panel 100 without support pads 130, the crack 300 can extend to the trace 120, causing the trace to break.

[0036] In this embodiment, the crack-stop pad 140 is a dummy pad disposed on the display panel 100. The crack-stop pad 140 can block the occurrence of cracks, preventing the cracks from extending to the trace 120 and causing the trace 120 to break. Specifically, the crack-stop pad 140 can be located within or outside the bonding area 110. The crack-stop pad 140 is disposed on the path of crack extension, thereby blocking the extension of cracks.

[0037] In this embodiment, the number of dummy pads used for support is reduced because the chip is selected as an integrated circuit (Ramless IC) without built-in random access memory. That is, the number of chip pads corresponding to the support pad 130 is reduced. Therefore, the support performance of the support pad 130 and the chip pads between the chip and the display panel 100 is reduced. When the chip and the display panel 100 are bonded, the traces 120 at the edge of the display panel 100 deform too much. By setting the anti-crack pad 140 on the display panel 100, the anti-crack pad 140 can work together with the support pad 130 to provide support, thereby improving the strength between the display panel 100 and the chip. In this embodiment, a support pad 130 and a crack-stopping pad 140 are provided on the display panel 100. The support pad 130 is located within the bonding area 110, and the crack-stopping pad 140 is located on the extension path of the crack generated when the display panel 100 is bonded to the chip. When a crack is generated between the display panel 100 and the chip, the crack-stopping pad 140 can block the generated crack.

[0038] In this embodiment, a support pad 130 and a crack-stopping pad 140 are provided on the display panel 100. The crack-stopping pad 140 can improve the support performance between the display panel 100 and the chip, reduce the deformation of the trace 120 at the edge of the chip, and reduce the possibility of cracks between the display panel 100 and the chip. Furthermore, the crack-stopping pad 140 is located on the crack propagation path, so even if cracks occur between the panel and the chip, the crack-stopping pad 140 can block the cracks. This solves the problem that the traces 120 outside the bonding area 110 of the display panel 100 are prone to breakage, and improves the structural stability of the panel assembly 10 after bonding.

[0039] As shown in Figures 1 to 6, in some embodiments of this application, the crack-stop pad 140 includes at least one first pad 1401, which is located within the bonding region 110, wherein the first pad 1401 is located between the support pad 130 and the trace 120.

[0040] In this application, the crack-prevention pad 140 includes a first pad 1401 disposed within the bonding region 110. The first pad 1401, located within the bonding region 110, together with the support pad 130, provides support for the chip bonded within the bonding region 110. Specifically, the first pad 1401 is disposed around the support pad 130. The first pad 1401 enhances the support performance between the display panel 100 and the chip. Furthermore, the first pad 1401 is located between the support pad 130 and the trace 120. Even if a crack occurs between the display panel 100 and the chip, the crack will pass through the first pad 1401 located around the support pad 130 as it extends towards the trace 120. The first pad 1401 can thus prevent the crack from extending.

[0041] For example, the number of first pads 1401 can be one, and the first pads 1401 are distributed around the support pads 130. The shape of the first pads 1401 can be a rectangular pad or an annular pad.

[0042] For example, there may be multiple first pads 1401, which may be distributed around the support pad 130, or the first pads 1401 may be distributed on both sides of the support pad 130, and at least one first pad 1401 may be provided between the support pad 130 and the trace 120.

[0043] In this embodiment, a support pad 130 and a first pad 1401 are provided in the bonding area 110 of the display panel 100. The first pad 1401 is disposed around the support pad 130 and can also serve as a support between the chip and the display panel 100, reducing the deformation of the trace 120 at the edge of the chip. Furthermore, the first pad 1401 is located between the support pad 130 and the trace 120. When a crack occurs between the display panel 100 and the chip, the first pad 1401 can block the crack, preventing the crack from extending to the trace 120 and causing the trace 120 to break. This avoids the display panel 100 from displaying abnormalities due to the breakage of the trace 120.

[0044] As shown in Figures 1 to 5, in some embodiments of this application, the first pad 1401 and the support pad 130 are arranged side by side, and the first pad 1401 is located on both sides of the support pad 130.

[0045] In this embodiment, the first pad 1401 and the support pad 130 are arranged side by side in the bonding region 110. When there are at least two first pads 1401, at least two first pads 1401 are located on both sides of the support pad 130, that is, the support pad 130 is located between at least two first pads 1401. The first pads 1401 are located between the support pad 130 and the trace 120, which plays a role in blocking the extension of cracks generated in the bonding region 110, preventing cracks in the bonding region 110 from extending to the trace 120 outside the bonding region 110, thereby avoiding the problem of trace 120 breaking.

[0046] As shown in Figure 1, there are 4 first pads 1401, and 2 first pads 1401 are distributed on both sides of the support pad 130.

[0047] As shown in Figure 6, there are two first pads 1401, with one first pad 1401 distributed on each side of the support pad 130.

[0048] It should be noted that the number of support pads 130 and the number of chip pads on the chip can both be one or more. When there are multiple support pads 130, all of the multiple support pads 130 are located between at least two first pads 1401.

[0049] In this embodiment of the application, by setting at least two first pads 1401, the support of the first pads 1401 for the chip and the display panel 100 can be further improved. Furthermore, by arranging the first pads 1401 side by side on both sides of the support pad 130, the crack can be further prevented from extending to the trace 120 outside the bonding area 110, thus avoiding the occurrence of trace 120 breakage.

[0050] As shown in FIG. 6, in some embodiments of the present application, the first pad 1401 is provided with an opening 1403, and the opening 1403 faces the support pad 130.

[0051] In the embodiment of the present application, the first pad 1401 is provided with the opening 1403 facing the support pad 130, and the first pad 1401 can partially enclose the support pad 130 through the opening 1403, so that the first pad 1401 has better coverage on the support pad 130, thereby blocking cracks generated in multiple directions, and further improving the crack blocking performance of the first pad 1401 for cracks generated near the support pad 130.

[0052] It should be noted that when there are a plurality of first pads 1401 and the support pad 130 is located between the plurality of first pads 1401, the opening 1403 directions of the first pads 1401 located on both sides of the support pad 130 are oppositely arranged, so as to achieve a certain surrounding enclosing effect on the support pad 130 located in the middle.

[0053] For example, the shape of the first pad 1401 can be C-shaped, V-shaped or 匚-shaped, and the direction of the opening 1403 of the first pad 1401 all faces the support pad 130.

[0054] As shown in FIG. 1 to FIG. 5, in some embodiments of the present application, the extending direction of the first pad 1401 is the same as that of the support pad 130. Arrow C in FIG. 4 shows the extending direction of the first pad 1401 and the support pad 130.

[0055] In the embodiment of the present application, the first pad 1401 can be configured as a pad extending in the same direction as the support pad 130, and the shape of the first pad 1401 is the same as that of the support pad 130. When the support pad 130 is arranged on the bonding area 110 of the display panel 100, the first pad 1401 can be arranged synchronously, which further simplifies the manufacturing process of the display panel 100.

[0056] For example, both the support pad 130 and the first pad 1401 are strip-shaped pads, and the extending direction of the support pad 130 is the same as that of the first pad 1401, that is, the support pad 130 and the first pad 1401 are arranged in parallel.

[0057] As shown in FIG. 1 to FIG. 4, in some embodiments of the present application, the crack stopping pad 140 comprises: at least one second pad 1402, the second pad 1402 is arranged on the display panel 100, the second pad 1402 is located outside the bonding area 110, and the second pad 1402 is distributed along the circumferential direction of the bonding area 110.

[0058] In this embodiment, the second pad 1402 is disposed outside the bonding area 110. Since the bonding area 110 is used to bond the chip, after the chip is bonded to the display panel 100, the second pad 1402 is located on the periphery of the chip. The second pad 1402 is spaced apart from the bonding area 110 to avoid interference with the chip packaging.

[0059] Arrow A in Figure 4 indicates the circumference of the bonding region 110.

[0060] For example, if there is one second pad 1402, the second pad 1402 is disposed around the periphery of the bonding area 110, and the second pad 1402 is provided with a clearance groove, and the trace 120 extends out of the bonding area 110 through the clearance groove.

[0061] It should be noted that the second pad 1402 is located outside the bonding area 110, and the second pad 1402 is located outside the first pad 1401, which can further block the extension of cracks outside the first pad 1401.

[0062] In this embodiment, when bonding a chip to the display panel 100, the chip is subjected to pressure and extends towards the edge of the chip, causing excessive deformation of the trace 120 at the chip edge, which may lead to breakage of the trace 120 corresponding to the display panel 100. By providing a second pad 1402 around the bonding area 110 of the packaged chip, the second pad 1402 is located circumferentially in the bonding area 110, which can effectively prevent the chip edge from extending to both sides when bonding the packaged chip, thus preventing cracks from forming between the chip and the display panel 100.

[0063] As shown in Figure 4, in some embodiments of this application, a gap 1404 is provided between two adjacent second pads 1402 in the circumferential direction of the bonding region 110, and the trace 120 extends from the gap 1404 to the bonding region 110.

[0064] In this embodiment, the trace 120 is used to connect the chip within the bonding region 110 to an external circuit outside the bonding region. The number of second pads 1402 can be at least two, and the at least two second pads 1402 are spaced apart. A gap 1404 is provided between two adjacent second pads 1402. The gap 1404 is used to avoid the trace 120 of the display panel 100, so that the trace 120 can extend from the outside of the bonding region 110 to the inside of the bonding region 110 through the gap 1404, thereby avoiding interference between the second pads 1402 and the trace 120 between the display panel 100 and the chip.

[0065] It should be noted that since the second pad 1402 is located outside the bonding area 110, and the trace 120 enters the bonding area 110 through the gap 1404 between the second pads 1402, the inner and outer sides of the second pad 1402 are both covered by the trace 120. Therefore, the second pad 1402 can prevent cracks from extending to the outside of the second pad 1402, further improving the crack-stopping performance of the crack-stopping pad 140.

[0066] As shown in Figure 4, for example, there are two second pads 1402, and the second pads 1402 are distributed on both sides of the bonding area 110. A gap 1404 is provided between the two second pads 1402, and the trace 120 extends from inside the bonding area 110 to outside the bonding area 110 through the gap 1404.

[0067] As shown in Figures 1 to 3, in some embodiments of this application, the bonding region 110 is a polygon; at least two second pads 1402 are located at opposite corners of the bonding region.

[0068] In this embodiment, the bonding region 110 can be a polygon, and the bonding region 110 is used to bond the chip. When the number of second pads 1402 is at least two, the second pads 1402 are located at the diagonal positions of the polygonal bonding region 110. It should be noted that the shape of the chip is the same as the shape of the bonding region 110. When the chip is bonded to the bonding region 110, the diagonal position of the chip matches the diagonal position of the bonding region 110. Therefore, when a crack occurs in the bonding region 110, it usually extends outward from the diagonal position of the bonding region 110. By setting the second pads 1402 at the diagonal positions of the bonding region 110, the blocking area of ​​the second pads 1402 in blocking crack propagation can be increased, thereby improving the crack blocking performance of the second pads 1402.

[0069] In this embodiment, the bonding region 110 can also be pentagonal, hexagonal, or other shapes. The number of second pads 1402 is the same as the number of diagonals of the bonding region 110, and each second pad 1402 is located at a corresponding diagonal position, thereby preventing cracks generated in each diagonal position of the bonding region 110 from extending outward and further reducing the possibility of cracks extending to the trace 120 position.

[0070] As shown in Figures 1 to 3, for example, the bonding area 110 is rectangular, and the rectangular bonding area 110 has four diagonals, with the second pad 1402 located at the four diagonal positions.

[0071] The second pads 1402 shown in FIGS. 1 to 3 are rectangular. The rectangular second pads 1402 in FIG. 2 extend along the long side of the bonding area 110, and the rectangular second pads 1402 in FIG. 3 form an included angle with both the long side and the short side of the bonding area 110, and each second pad 1402 is oppositely disposed at a corresponding diagonal position.

[0072] The second pad 1402 shown in FIG. 1 is in a "corner" shape, and two sides of the "corner"-shaped second pad 1402 respectively extend along the long side and the short side of the rectangular bonding area 110.

[0073] As shown in FIG. 4, in some embodiments of the present application, the bonding area 110 is an axisymmetric graphic area; at least two second pads 1402 are located on two sides of the bonding area 110, and the at least two second pads 1402 are axisymmetrically distributed along the axis of the bonding area 110.

[0074] In the embodiments of the present application, the bonding area 110 may be an axisymmetric graphic area, at least two second pads 1402 are disposed on two sides of the bonding area 110, and the second pads 1402 distributed on two sides of the bonding area 110 are axisymmetrically distributed along the axis of the bonding area 110. Since the second pads 1402 are distributed on two sides of the bonding area 110, the second pads 1402 can block the propagation of cracks on two sides of the bonding area 110, and the coverage of the second pads 1402 to the bonding area 110 is relatively large, which can play a role in blocking cracks for traces in a larger range, further improving the crack blocking performance of the second pads 1402.

[0075] The dashed line B in FIG. 4 shows the axis of the bonding area 110.

[0076] As shown in FIG. 4, exemplarily, the bonding area 110 is rectangular, and two second pads 1402 are located on two sides of the rectangular bonding area 110, that is, the two second pads 1402 are respectively located at two short side positions of the rectangular bonding area 110. Herein, the two second pads 1402 are in a "匚" shape, and the "匚"-shaped second pad 1402 can partially surround the bonding area 110. The second pad 1402 can also be in a "C" shape, a "V" shape or the like, so as to surround and cover the bonding area 110 on two sides of the bonding area 110, and can also be in a linear shape such as a rectangle.

[0077] FIG. 8 is one of the structural schematic diagrams of a crack-stopping pad provided in some embodiments of the present application. As shown in FIG. 8, in some embodiments of the present application, the crack-stopping pad 140 comprises: a pixel circuit gate layer 1405, the pixel circuit gate layer 1405 is disposed in the bonding area 110; and a pixel signal line layer 1406, the pixel signal line layer 1406 is disposed on the pixel circuit gate layer 1405.

[0078] In this embodiment, the crack-stop pad 140 includes a pixel circuit gate layer 1405 disposed on the bonding area 110 of the display panel 100, and a pixel signal line layer 1406 disposed on the pixel circuit gate layer 1405. The crack-stop pad 140 is an exposed pad, disposed around the support pad 130 corresponding to the dummy pad of the chip. The shape of the crack-stop pad 140 is the same as the wiring pad on the display panel 100 for connecting the trace 120, except that it is not connected to the trace 120. It prevents cracks from extending to the trace 120 while providing effective support for the chip. Under the same pressure, the pressure-bearing area increases and the pressure decreases, which not only reduces the pressure and deformation, but also prevents crack extension.

[0079] Specifically, the pixel circuit gate layer 1405 is made of a material with good thermal stability and serves as the gate of the pixel circuit. The pixel signal line layer 1406 is made of a metal material with good conductivity and is not easily oxidized and serves as the drain of the pixel circuit. The pixel circuit gate layer 1405 and the pixel signal line layer 1406 together form a discharge circuit.

[0080] Figure 9 shows a second schematic diagram of the structure of the anti-crack pad provided in some embodiments of this application. As shown in Figure 9, in some embodiments of this application, the pixel signal line layer 1406 includes: a first signal line layer 1407, which is disposed on the pixel circuit gate layer 1405; and a second signal line layer 1408, which is disposed on the first signal line layer 1407. The anti-crack pad 140 also includes: a touch trace layer 1409, which is disposed on the second signal line layer 1408.

[0081] In this embodiment, the pixel signal line layer 1406 comprises two stacked layers, specifically a first signal line layer 1407 and a second signal line layer 1408. The first signal line layer 1407 is stacked on the pixel circuit gate layer 1405, and the second signal line layer 1408 is stacked on the first signal line layer 1407, meaning the first signal line layer 1407 is located between the second signal line layer 1408 and the pixel circuit gate layer 1405. The crack-resistant pad 140 also includes a touch trace layer 1409 stacked on the pixel signal line layer 1406. Specifically, the touch trace layer 1409 is stacked on the second signal line layer 1408. By setting the pixel signal line layer 1406 as a dual-layer structure including the first signal line layer 1407 and the second signal line layer 1408, and setting the touch trace layer 1409 on the pixel signal line layer 1406, the height of the anti-crack pad 140 can be made consistent with the height of the wiring pad of the connecting trace 120, thereby improving the support performance of the anti-crack pad 140 between the chip and the display panel 100.

[0082] It should be noted that the first signal line layer 1407, the second signal line layer 1408 and the touch trace layer 1409 are made of the same material, which is metal layer 1412 with good conductivity and certain oxidation resistance.

[0083] In some embodiments of this application, optionally, the pixel circuit gate layer 1405 includes a molybdenum layer; and / or the pixel signal line layer 1406 and the touch trace layer 1409 include a titanium-aluminum alloy layer.

[0084] In this embodiment, the pixel circuit gate layer 1405 is made of molybdenum, which has good thermal stability, further improving the support stability of the crack-resistant pad 140. The pixel signal line layer 1406 and the touch trace layer 1409 are both made of titanium-aluminum alloy. Specifically, both the pixel signal line layer 1406 and the touch trace layer 1409 are titanium-aluminum-titanium metal layers 1412, with the aluminum layer disposed between the two titanium layers. The inner aluminum layer has good conductivity, and the outer titanium layer has good oxidation resistance, thereby improving the oxidation resistance of the pixel signal line layer and the touch trace layer 1409.

[0085] It should be noted that the hierarchical stacking structure of the first pad 1401 and the second pad 1402 in the crack-stop pad 140 can be selected as the hierarchical stacking structure shown in Figures 8 to 9.

[0086] Figure 10 shows a third schematic diagram of the structure of the anti-crack pad provided in some embodiments of this application. As shown in Figure 10, in some embodiments of this application, the anti-crack pad 140 includes: a barrier layer 1410 disposed on the display panel 100; a first insulating layer 1411 disposed on the barrier layer 1410; a metal layer 1412 disposed on the first insulating layer 1411; and a second insulating layer 1413 disposed on the metal layer 1412.

[0087] In this embodiment, the crack-stop pad 140 includes a barrier layer 1410, a first insulating layer 1411, a metal layer 1412, and a second insulating layer 1413 stacked sequentially. The barrier layer 1410 is disposed outside the bonding area 110 of the display panel 100 and is used to block water and oxygen from the crack-stop pad 140. The first insulating layer 1411 and the second insulating layer 1413 are located on both sides of the metal layer 1412 and are used to insulate both sides of the metal layer 1412 so that the metal layer 1412 is not exposed.

[0088] Specifically, the crack-stop pad 140 is designed to not expose the trace 120. The trace 120 is partially routed on the trace 120 layer of the display panel 100, and the crack-stop pad 140 does not connect to the pixel point. That is, the crack-stop pad 140 is a redundant trace 120 solution, which can effectively prevent the extension of the left and right edges of the chip and play a good role in preventing cracks.

[0089] In some embodiments of this application, the metal layer 1412 includes a molybdenum layer; and / or the first insulating layer 1411 and the second insulating layer 1413 include at least one of the following: a silicon nitride layer, a silicon suboxide layer, and a silicon dioxide layer.

[0090] In this embodiment, the metal layer 1412 is made of molybdenum, which has good thermal stability, further improving the support stability of the crack-arresting pad 140. The first insulating layer 1411 and the second insulating layer 1413 can be selected from at least one of silicon nitride, silicon suboxide, and silicon dioxide, which can improve the insulation performance of the crack-arresting pad 140.

[0091] For example, the second insulating layer 1413 includes four insulator layers. The first insulator layer is disposed on the metal layer 1412 and is selected as a silicon nitride layer. The second insulator layer is disposed on the first insulator layer and is selected as a silicon dioxide layer or a silicon nitride layer. The third insulator layer is disposed on the second insulator layer and is selected as a silicon suboxide layer or a silicon nitride layer. The fourth insulator layer is disposed on the third insulator layer and is selected as a silicon nitride layer. By providing a stacked four-layer structure for the second insulating layer 1413, the insulation performance of the crack-resistant pad 140 can be further improved.

[0092] For example, the first insulating layer 1411 is selected as a silicon dioxide layer.

[0093] It should be noted that the layer stacking structure of the second pad 1402 in the crack arrest pad 140 can be selected as the layer stacking structure in Figure 10.

[0094] In some embodiments of this application, an electronic device is provided. FIG11 shows a schematic diagram of the structure of the electronic device provided in some embodiments of this application. As shown in FIG11, the electronic device 200 includes: a panel assembly 10 and a chip 201. The chip 201 is disposed in the bonding area of ​​the panel assembly 10. The panel assembly 10 is the panel assembly 10 in any of the above embodiments, and thus has all the technical effects of the panel assembly 10 in any of the above embodiments, which will not be elaborated here.

[0095] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0096] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A panel assembly, comprising: The display panel has traces provided on it, and the display panel includes a bonding area, with the traces located outside the bonding area; At least one support pad is disposed in the bonding area; Crack-prevention pads are provided on the display panel, wherein the crack-prevention pads are used to prevent cracks from extending to the traces.

2. The panel assembly according to claim 1, wherein, The crack-resistant pad includes: At least one first pad, the first pad being located within the bonding area, wherein the first pad is located between the support pad and the trace.

3. The panel assembly according to claim 2, wherein, The first pad is arranged side by side with the support pad, and the first pad is located on both sides of the support pad.

4. The panel assembly according to claim 2, wherein, The first pad has an opening facing the support pad.

5. The panel assembly according to claim 2, wherein, The first pad extends in the same direction as the supporting pad.

6. The panel assembly according to claim 1, wherein, The crack-resistant pad includes: At least one second pad is disposed on the display panel and located outside the bonding area, and the second pad is distributed circumferentially along the bonding area.

7. The panel assembly according to claim 6, wherein, In the circumferential direction of the bonding area, a gap is provided between two adjacent second pads, and the trace extends from the gap to the bonding area.

8. The panel assembly according to claim 6, wherein, The bonding region is a polygonal region; At least two of the second pads are located diagonally opposite each other in the bonding region.

9. The panel assembly according to claim 6, wherein, The bonding region is an axisymmetric graphic region; At least two of the second pads are located on both sides of the bonding region, and at least two of the second pads are axially symmetrically distributed along the axis of the bonding region.

10. The panel assembly according to any one of claims 1 to 9, wherein, The crack-resistant pad includes: A pixel circuit gate layer, wherein the pixel circuit gate layer is disposed in the bonding region; A pixel signal line layer is disposed on the pixel circuit gate layer.

11. The panel assembly of claim 10, wherein, The pixel signal line layer includes: A first signal line layer is disposed on the pixel circuit gate layer; The second signal line layer is disposed on the first signal line layer; The crack-resistant pad includes: A touch routing layer is disposed on the second signal line layer.

12. The panel assembly of claim 11, wherein, The pixel circuit gate layer includes a molybdenum layer; and / or The pixel signal line layer and the touch trace layer include a titanium-aluminum alloy layer.

13. The panel assembly according to any one of claims 6 to 9, wherein, The crack-resistant pad includes: A barrier layer is disposed on the display panel; A first insulating layer is disposed on the barrier layer; A metal layer disposed on the first insulating layer; A second insulating layer is disposed on the metal layer.

14. The panel assembly of claim 13, wherein, The metal layer includes a molybdenum layer; and / or The first insulating layer and the second insulating layer include at least one of the following: a silicon nitride layer, a silicon suboxide layer, and a silicon dioxide layer.

15. An electronic device, further comprising: The panel assembly as claimed in any one of claims 1 to 14; The chip is disposed within the bonding area of ​​the display panel in the panel assembly.

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