Three-dimensional sensing-memory-computing integrated chip and preparation method and computing method therefor

Abstract

The present application discloses a three-dimensional sensing-memory-computing integrated chip and a preparation method and computing method therefor. The three-dimensional sensing-memory-computing integrated chip comprises a plurality of sensing-memory-computing units, each sensing-memory-computing unit comprising a stacked resistive random access memory device group, a sensing device and a gating device, wherein the stacked resistive random access memory device group comprises at least two resistive random access memory devices stacked in the thickness direction; the sensing device is configured to receive an external signal and convert the external signal into an input signal, and an output terminal of the sensing device is coupled to a top electrode of the stacked resistive random access memory device group; the gating device is configured to receive a control signal and switch between on and off states on the basis of the control signal, and the gating device is coupled to the top electrode of the stacked resistive random access memory device group; and the stacked resistive random access memory device group is arranged between the sensing device and the gating device in the width direction, and at least two resistive random access memory devices share one top electrode, such that the at least two resistive random access memory devices synchronously receive the input signal or are synchronously turned on and off.

Description

Integrated 3D chip for sensing, storage, and computing, and its fabrication and computation methods

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510230953.5, filed on February 27, 2025, entitled “Integrated 3D Chip for Sensing, Storage and Computing and its Fabrication Method and Computation Method,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of microelectronic device technology, and in particular to a three-dimensional integrated chip that integrates sensing, storage, and computing, as well as its fabrication and computation methods. Background Technology

[0004] In traditional chips, sensing, storage, and computing functions are typically designed as independent modules. However, this architecture results in high power consumption and high latency, making it difficult to meet the increasingly demanding performance requirements of terminal devices.

[0005] In response, some studies have proposed integrating sensing, storage, and computing functions into a single chip to optimize power consumption and latency. However, such chips still suffer from drawbacks such as high parasitic capacitance and large dynamic power consumption, which require further optimization. Summary of the Invention

[0006] This application provides a three-dimensional integrated chip for sensing, storage, and computing, as well as its fabrication and calculation methods. One of the objectives is to achieve the writing of multiple weight values ​​within the sensing, storage, and computing unit by stacking multiple resistive random access memory devices in the thickness direction, and to achieve synchronous storage or synchronous calculation by sharing the top electrodes of multiple resistive random access memory devices, thereby improving chip performance.

[0007] In a first aspect, embodiments of this application provide a three-dimensional integrated chip for sensing, memory, and computing, integrating an array of sensing, memory, and computing units, each of which includes a stacked resistive random access memory (RRAM) device group, a sensing device, and a gating device. The stacked RRAM device group includes at least two RRAM devices stacked along the thickness direction of the three-dimensional integrated chip. The sensing device is configured to receive external signals and convert them into input signals, and its output terminal is coupled to the top electrode of the stacked RRAM device group. The gating device is configured to receive control signals and switch on / off according to the control signals, and is coupled to the top electrode of the stacked RRAM device group. The stacked RRAM device group is disposed between the sensing device and the gating device along the width direction of the three-dimensional integrated chip, and at least two RRAM devices share a single top electrode to enable at least two RRAM devices to simultaneously receive input signals or simultaneously switch on / off.

[0008] In some alternative embodiments, the stacked resistive switching memory device group includes a top electrode, a resistive switching layer, and at least two bottom electrodes. The top electrode is coupled to the at least two bottom electrodes through the resistive switching layer, and the resistive switching layer is configured to change its resistance value under the control of voltage signals applied to the top and bottom electrodes.

[0009] In some optional embodiments, at least two bottom electrodes are stacked along the thickness direction and an insulating dielectric layer is provided between any two bottom electrodes, a top electrode extends at least along the thickness direction to connect each bottom electrode, and a resistive switching layer extends at least along the thickness direction to space the top electrode from each bottom electrode.

[0010] In some optional embodiments, the gate device includes a substrate, an active region disposed on one side of the substrate, and a drain, a source, and a gate. The drain and the source are disposed on the side of the active region away from the substrate and are electrically isolated by a gate dielectric layer. The gate is disposed between the drain and the source along the width direction and is spaced apart from the active region by the gate dielectric layer. The source is electrically connected to the top electrode of the memory device.

[0011] In some optional embodiments, the integrated sensing, memory, and computing 3D chip further includes:

[0012] The drive module is configured to output control signals to the gating device;

[0013] Bit lines extend along the row direction and connect the drive module to the drain of each gating device;

[0014] Word lines extend along the column direction and connect the driver module to the gate of each gating device.

[0015] In some optional embodiments, the integrated sensing, memory, and computing 3D chip further includes:

[0016] The first output line is electrically connected to the stacked resistive random access memory device group in each inductive memory unit.

[0017] The second output line is electrically connected to the sensing devices in each sensing and storage unit.

[0018] In some alternative embodiments, the sensing device includes a photosensitive layer disposed on the side of the active region away from the substrate, and the photosensitive layer and the top electrode of the stacked resistive switching memory device group are coupled to the active region through the source electrode.

[0019] Secondly, embodiments of this application provide a method for fabricating a three-dimensional integrated chip that combines sensing, storage, and computing. The fabrication method includes:

[0020] Provide gating devices and sensing devices;

[0021] An insulating dielectric layer and a bottom electrode layer are deposited sequentially above the gating device;

[0022] Repeatedly deposit insulating dielectric layers and bottom electrode layers to obtain N bottom electrode layers, with insulating dielectric layers formed above and below each bottom electrode layer;

[0023] Etching the stacked structure of the insulating dielectric layer and the bottom electrode layer forms vias to expose the gating device;

[0024] A resistive switching layer is grown at the interface of the stacked structure on the inner wall of the through hole;

[0025] A top electrode layer is deposited inside the resistive switching layer to complete the fabrication of the stacked resistive switching memory device assembly.

[0026] In some alternative embodiments, the thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm.

[0027] In some optional embodiments, the resistive switching layer is made of at least one of oxides, nitrides, sulfides, and organic materials, and the thickness of the resistive switching layer is greater than or equal to 4 nm and less than or equal to 30 nm.

[0028] In some alternative embodiments, the material of the top electrode layer includes an active metal.

[0029] In some alternative embodiments, the bottom electrode layer is made of an inert material.

[0030] Thirdly, embodiments of this application provide a calculation method for a sensor-memory-computing integrated 3D chip, applied to the sensor-memory-computing integrated 3D chip provided in any embodiment of the first aspect. The calculation method includes:

[0031] Connect the gating device and the sensing device, and the sensing device receives the sample signal and generates the first output current;

[0032] Disconnect the sensing device, connect the gating device and the stacked resistive switching memory device group, and write weights to each memory device respectively;

[0033] Disconnect the gating device and connect the stacked resistive switching memory device group to the sensing device. The sensing device receives the sample signal and calculates and generates the second output current according to the weight of the memory device.

[0034] By comparing the first output current with the second output current, it is determined whether the target image is a sample image, thus completing image recognition.

[0035] The integrated 3D chip for sensing, memory, and computing provided in this application integrates multiple memory devices within a sensing, memory, and computing unit by stacking them in the thickness direction. The memory devices are resistive switching memory (RSM) devices to enable in-memory computation and shorten signal transmission time. Multiple RSM devices share a single top electrode to achieve synchronous storage or computation. This integrated 3D chip significantly improves storage density by stacking memory devices, achieving enhanced chip performance within the same area. Simultaneously, the stacked memory devices reduce the length of interconnect lines, thereby lowering parasitic capacitance and dynamic power consumption within the sensing, memory, and computing unit. Attached Figure Description

[0036] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0037] Figure 1 is a schematic diagram of an array of three-dimensional integrated chips that integrate sensing, storage, and computing according to some embodiments of this application;

[0038] Figure 2 is a schematic diagram of the structure of a sensing and memory computing unit in some embodiments of this application;

[0039] Figure 3 is a flowchart illustrating the fabrication method of a three-dimensional integrated chip for sensing, storage, and computing according to some embodiments of this application;

[0040] Figures 4a to 4g are schematic diagrams of the process structure of the preparation method shown in Figure 3;

[0041] Figure 5 is a flowchart illustrating the calculation method of a three-dimensional integrated chip for sensing, storage, and computing according to some embodiments of this application.

[0042] Figure 6 is a schematic diagram of the sub-processes of the calculation method of some embodiments of this application.

[0043] The reference numerals in the detailed embodiments are as follows: 01, sensing and memory unit; 100, gating device; 110, substrate; 121, epitaxial layer; 1221, first sub-region; 1222, second sub-region; 131, drain; 132, gate; 133, source; 140, gate dielectric layer; 150, isolation structure; 200, sensing device; 210, photosensitive layer; 300, stacked resistive switching memory device group; 301, resistive switching memory device; 310, top electrode; 320, resistive switching layer; 331, bottom electrode; 332, insulating dielectric layer; thickness direction Z; width direction X; length direction Y; word line WL; bit line BL; first output line C1; second output line C2. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are configured to distinguish different objects, rather than to describe a particular order or hierarchy.

[0046] In this application, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] In the embodiments of this application, the same reference numerals denote the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width, and other dimensions of various components in the embodiments of this application shown in the accompanying drawings, as well as the overall thickness, length, width, and other dimensions of the integrated device, are merely illustrative and should not constitute any limitation on this application.

[0049] In this application, "multiple" means two or more (including two).

[0050] With the rapid development of IoT and AI technologies, the demand for real-time data processing from terminal devices is constantly increasing. The traditional von Neumann architecture, which separates storage and computing, suffers from low data transfer efficiency and high power consumption, making it difficult to meet the urgent needs of new scenarios such as edge computing for low latency and high energy efficiency.

[0051] In recent years, with the development of in-memory computing technology, some studies have integrated sensing, storage and computing functions into a single chip to form an integrated sensing-memory-computing chip, which effectively reduces power consumption and latency and improves the overall system performance.

[0052] However, due to the limited single-chip area, two-dimensional integrated sensing-memory-computing chips cannot provide sufficient storage capacity and computing power when handling complex real-time tasks. Traditional static random access memory (SRAM) and dynamic random access memory (DRAM) occupy a large area, limiting storage density. At the same time, the increasing interconnect length and density in the two-dimensional integrated structure leads to an increase in parasitic capacitance and resistive load, negatively impacting signal transmission speed and limiting the chip's energy efficiency ratio.

[0053] In response, related research has proposed 3D NAND technology, which improves computing power by introducing multiple memory devices into a memory chip through vertical stacking. However, the direct stacking of memory devices with the insulating structure results in excessive chip thickness, making it prone to defects such as warping. At the same time, the increased production costs due to the complexity of its manufacturing process also hinder large-scale production.

[0054] To address the related technical issues, this application provides a three-dimensional integrated chip for sensing, memory, and computing, along with its fabrication and computation methods. This chip achieves the writing of multiple weight values ​​within a single sensing, memory, and computing unit by stacking multiple resistive random access memory (RESM) devices along the thickness direction. Furthermore, the top electrodes of the multiple RSM devices are shared to achieve synchronous storage or computation, thereby improving chip performance. The three-dimensional integrated chip for sensing, memory, and computing provided in this application is described below.

[0055] In a first aspect, referring to Figures 1 and 2, embodiments of this application provide a three-dimensional integrated chip for sensing, memory, and computing, integrating an array of sensing, memory, and computing units 01. Each sensing, memory, and computing unit 01 includes a stacked resistive random access memory (RRAM) device group 300, a sensing device 200, and a gating device 100. The stacked RRAM device group 300 includes at least two RRAM devices 301 stacked along the thickness direction of the three-dimensional integrated chip. The sensing device 200 is configured to receive external signals and convert them into input signals. The output of the sensing device 200... The terminal is coupled to the top electrode 310 of the stacked resistive random access memory device group 300; the gating device 100 is configured to receive a control signal and switch on and off according to the control signal, and the gating device 100 is coupled to the top electrode 310 of the stacked resistive random access memory device group 300; wherein, the stacked resistive random access memory device group 300 is disposed between the sensing device 200 and the gating device 100 along the width direction of the sensing, storage and computing integrated three-dimensional integrated chip, and at least two resistive random access memory devices 301 share a top electrode 310 so that at least two resistive random access memory devices 301 synchronously receive input signals or synchronously switch on and off.

[0056] As a non-volatile memory device, the resistive switching memory device 301 can switch between two conduction modes—high configuration and low resistance—in response to voltage excitation, thereby integrating storage and computing functions. Optionally, the resistive switching memory device 301 is selected from one of the following: metal oxide resistive switching memory device 301, organic resistive switching memory device 301, two-dimensional material resistive switching memory device 301, ferroresistive switching memory device 301, spin resistive switching memory device 301, and electrolyte resistive switching memory device 301.

[0057] Sensing device 200 refers to a component capable of directly sensing external physical signals on a chip and converting them into electrical signals. These external physical signals include temperature, light, sound, pressure, etc. Optionally, the external signal is an optical signal, and the input signal is a photocurrent. Sensing device 200 includes a photodiode configured to sense the optical signal and convert it into an electrical signal. Exemplarily, the photodiode is one of a PIN photodiode, a PN junction photodiode, or a Schottky photodiode.

[0058] The gating device 100 is a component that activates the selected inductive-memory unit 01 by controlling the current path through its own on / off switching. Optionally, the gating device 100 is selected from one of a metal-semiconductor field-effect transistor, a magnetoresistive tunnel junction, a diode, a threshold switch, and a two-terminal gating device 100. Exemplarily, the gating device 100 is selected from a metal-semiconductor field-effect transistor. In some embodiments, to reduce system power consumption, the metal-semiconductor field-effect transistor is designed with a low threshold voltage for driving, for example, a threshold voltage not exceeding 5V.

[0059] Therefore, the integrated 3D chip for sensing, memory, and computing achieves monolithic integration of multiple memory chips through stacking in the thickness direction, thereby enabling the writing of multiple weight values ​​and increasing the storage density of the integrated 3D chip for sensing, memory, and computing. The integrated 3D chip for sensing, memory, and computing uses resistive random access memory (RRAM) devices 301 for in-memory computation, reducing signal transmission time and increasing signal transmission speed. The design of multiple RRAM devices 301 sharing a top electrode 310 allows multiple RRAM devices 301 to perform weight writing or computation operations synchronously, further improving the chip's real-time data processing capability within the same area. Compared to direct stacking, this significantly reduces the chip thickness, achieving process simplification and cost optimization, and has greater potential for mass production. Furthermore, compared to planar chips with the same computing power, the stacking structure of the integrated 3D chip for sensing, memory, and computing reduces the length of interconnects within the chip, thereby reducing dynamic power consumption and parasitic capacitance, thus optimizing performance.

[0060] According to some embodiments of this application, the stacked resistive switching memory device group 300 includes a top electrode 310, a resistive switching layer 320, and at least two bottom electrodes 331. The top electrode 310 is coupled to the at least two bottom electrodes 331 through the resistive switching layer 320. The resistive switching layer 320 is configured to realize a change in resistance value under the control of the voltage signal applied to the top electrode 310 and the bottom electrodes 331.

[0061] It is understandable that at least two bottom electrodes 331 can be individually voltage-excited, thereby enabling independent weight writing and subsequent calculation operations while sharing the top electrode 310.

[0062] Optionally, the thickness of the resistive switching layer 320 is greater than or equal to 4 nm. It is understood that the thickness direction of the resistive switching layer 320 differs from the thickness direction of the integrated sensing, storage, and computing 3D chip. Specifically, the thickness direction of the resistive switching layer 320 refers to the direction that is simultaneously perpendicular to both the contact surface between the top electrode 310 and the resistive switching layer 320, and the contact surface between the bottom electrode 331 and the resistive switching layer 320.

[0063] Alternatively, the thickness of the resistive switching layer 320 may be less than or equal to 30 nm.

[0064] Optionally, the resistive switching layer 320 is selected from at least one of metal oxides, chalcogenides, perovskite materials, organic materials, and nitrides. Among them, metal oxides include hafnium oxide, tantalum pentoxide, titanium dioxide, bismuth ferrite, etc. For example, the resistive switching layer 320 is made of hafnium oxide.

[0065] Therefore, when the sensing and storage unit 01 performs a weight writing or calculation operation, the top electrode 310 responds to the control signal of the gating device 100 or the input signal of the sensing device 200, so that multiple resistive switching storage devices 301 synchronously receive the voltage signal excitation of the top electrode 310 and respectively perform weight writing or calculation operations to realize the storage function or the calculation function.

[0066] According to some embodiments of this application, at least two bottom electrodes 331 are stacked along the thickness direction, and an insulating dielectric layer 332 is provided between any two bottom electrodes 331. A top electrode 310 extends at least along the thickness direction to connect each bottom electrode 331, and a resistive switching layer 320 extends at least along the thickness direction to space the top electrode 310 from each bottom electrode 331. Optionally, the resistive switching layer 320 is inclined relative to the thickness direction, which facilitates processing on the inner wall of the etched via and provides a more easily adhered foundation for the subsequent fabrication of the top electrode 310.

[0067] Optionally, the top electrode 310 is inclined relative to the thickness direction, which facilitates its fabrication by means of deposition or other methods and its simultaneous coupling with each bottom electrode 331.

[0068] Understandably, the insulating dielectric layer 332 is configured to block lateral leakage current between two adjacent bottom electrodes 331 along the thickness direction. The insulating dielectric layer 332 can form device isolation between each resistive switching memory device 301 so that each resistive switching memory device 301 can be independently controlled to switch on and off by adjusting the voltage of the bottom electrode 331.

[0069] Optionally, the thickness of the insulating dielectric layer 332 is greater than or equal to 100 nm. The thickness of the insulating dielectric layer 332 refers to its minimum length in the thickness direction of the integrated sensing, storage, and computing 3D chip.

[0070] Alternatively, the thickness of the insulating dielectric layer 332 may be less than or equal to 300 nm.

[0071] Optionally, the top electrode 310 is made of an active metal material, and the bottom electrode 331 is made of an inert material.

[0072] Therefore, multiple bottom electrodes 331 stacked along the thickness direction can form multiple resistive switching memory devices 301 by sharing a resistive switching layer 320 and a top electrode 310, which improves the storage density of the sensing and memory units 01 while controlling the thickness of the chip, reduces parasitic capacitance and helps with the thermal management of the chip.

[0073] According to some embodiments of this application, the gate device 100 includes a substrate 110, an active region disposed on one side of the substrate 110, a drain 131, a source 133, and a gate 132. The drain 131 and the source 133 are disposed on the side of the active region away from the substrate 110 and are electrically isolated by a gate dielectric layer 140. The gate 132 is disposed along the width direction between the drain 131 and the source 133 and is spaced apart from the active region by the gate dielectric layer 140. The source 133 is electrically connected to the top electrode 310 of the memory device.

[0074] Optionally, the drain 131 and gate 132 of the gating device 100 are respectively connected to the row gating signal and the column gating signal, and the chip can select the target sensing and computing unit 01 according to the row gating signal and the column gating signal and perform operations such as weight writing, calculation or image acquisition.

[0075] Specifically, the active region includes an epitaxial layer 121 doped with ions of a first conductivity type and a well region disposed within the epitaxial layer 121 and doped with ions of a second conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type.

[0076] Optionally, the well region includes a first sub-region 1221 coupled to the drain 131 and a second sub-region 1222 coupled to the source 133. Exemplarily, the orthographic projection of the drain 131 onto the substrate 110 falls within the orthographic projection range of the first sub-region 1221 onto the substrate 110, and the orthographic projection of the source 133 onto the substrate 110 falls within the orthographic projection range of the second sub-region 1222 onto the substrate 110.

[0077] Further optionally, the doping concentration of the second sub-region 1222 is greater than the doping concentration of the first sub-region 1221, or the doping concentration of the second sub-region 1222 is equal to the doping concentration of the first sub-region 1221.

[0078] Alternatively, the orthogonal projection of the top electrode 310 onto the substrate 110 falls within the orthogonal projection range of the source electrode 133 onto the substrate 110.

[0079] Alternatively, the orthographic projection of the stacked resistive switching memory device group 300 onto the substrate 110 falls within the orthographic projection range of the source 133 onto the substrate 110.

[0080] It is understandable that an insulating dielectric layer 332 is provided between the stacked resistive switching memory device group 300 and the source 133 to achieve electrical isolation between the bottom electrode 331 of the resistive switching memory region and the source 133 of the gating device 100.

[0081] It is understood that the selection device 100 also includes an isolation structure 150, which is disposed on the outer periphery of the horizontal plane to achieve electrical isolation between different sensing and memory computing units 01, thereby enabling the selection or shutdown of the target sensing and memory computing unit 01. Specifically, the isolation structure 150 is disposed on both sides of the active region along the width direction of the integrated sensing and memory computing chip, and the isolation structure 150 is also disposed on both sides of the active region along the length direction of the integrated sensing and memory computing chip.

[0082] Therefore, the gating device 100 uses a transistor. When the drain 131 and gate 132 of the transistor sense a control signal, the sensing, storage and computing unit 01 where the transistor is located is turned on to perform operations such as image acquisition, weight writing or calculation. The sensing, storage and computing integrated 3D chip realizes the calling of different sensing, storage and computing units 01 through the gating device 100.

[0083] According to some embodiments of this application, the integrated 3D sensing, storage, and computing chip further includes:

[0084] The drive module is configured to output control signals to the gating device 100;

[0085] Bit lines extend along the row direction and connect the drive module to the drain 131 of each gating device 100;

[0086] Word lines extend along the column direction and connect the drive module to the gate 132 of each gating device 100.

[0087] Optionally, the driving module includes a word line driving unit and a bit line driving unit. The word line driving unit is connected to the gate 132 of each gating device 100 via word lines, and the bit line driving unit is connected to the drain 131 of each gating device 100 via bit lines.

[0088] Optionally, the width direction of the integrated sensing, storage, and computing 3D chip is the row direction, the length direction of the integrated sensing, storage, and computing 3D chip is the column direction, and multiple sensing, storage, and computing units 01 are arranged in a matrix array.

[0089] For example, xy memory computing units 01 are provided and distributed in x rows and y columns. x bit lines are provided and electrically connected to x rows of memory computing units 01 respectively. y word lines are provided and electrically connected to y columns of memory computing units 01 respectively. The bit lines are configured to control the conduction state of the drain 131 of the y memory computing units 01 in the same row, and the word lines are configured to control the switching state of the gate 132 of the x memory computing units 01 in the same column.

[0090] Optionally, the gate device 100 includes a passivation layer covering the drain 131 and the gate 132. The passivation layer above the drain 131 has a first via, in which a first conductive metal is deposited to form a bit line. The passivation layer above the gate 132 has a second via, in which a second conductive metal is deposited to form a word line. Along the thickness direction of the integrated sensor-memory-computing 3D chip, the word line and the bit line are insulated and isolated by the passivation layer.

[0091] Therefore, the driving module can transmit control signals through word lines and bit lines and select the corresponding sensing and computing unit 01 to make it conduct, thereby realizing operations such as image acquisition, weight writing or calculation.

[0092] According to some embodiments of this application, the integrated 3D sensing, storage, and computing chip further includes:

[0093] The first output line is electrically connected to the stacked resistive random access memory device group 300 in each inductive and memory computing unit 01.

[0094] The second output line is electrically connected to the sensing device 200 in each sensing and storage unit 01.

[0095] Optionally, the first output line includes at least two write sub-lines, which are connected one-to-one with the bottom electrodes 331 of at least two resistive random access memory devices 301 in each inductive computing unit 01 to perform weighted write operations to each resistive random access memory device 301 in the same inductive computing unit 01.

[0096] For example, the stacked resistive switching memory device group 300 includes two resistive switching memory devices 301. The first output line includes two write sub-lines, one of which is electrically connected to the bottom electrode 331 of each inductive memory unit 01 near the active region, and the other write word line is electrically connected to the bottom electrode 331 of each inductive memory unit 01 away from the active region.

[0097] Optionally, the integrated 3D chip for sensing, storage, and computing also includes a first inverting amplifier, which is connected to the output terminal of the first output line and configured to generate a first output voltage as the calculation result.

[0098] Optionally, the integrated 3D chip for sensing, storage, and computing also includes a second inverting amplifier. The second inverting amplifier is connected to the output terminal of the second output line and is configured to generate a second output voltage as the image acquisition result. By comparing the first output voltage with the second output voltage, the integrated 3D chip for sensing, storage, and computing can complete the image recognition task.

[0099] Therefore, the integrated 3D chip capable of sensing, storing, and computing can output the total current as the acquisition result and the calculation result respectively in acquisition mode and calculation mode, and complete the recognition task by comparing the calculation result and the acquisition result. It can be understood that the recognition task can be image recognition, speech recognition, or similar tasks.

[0100] According to some embodiments of this application, the sensing device 200 includes a photosensitive layer 210, which is disposed on the side of the active region away from the substrate 110. The photosensitive layer 210 and the top electrode 310 of the stacked resistive switching memory device group 300 are coupled to the active region through the source electrode 133.

[0101] Optionally, at least a portion of the photosensitive layer 210's orthogonal projection onto the substrate 110 falls within the orthogonal projection range of the second sub-region 1222 onto the substrate 110.

[0102] Alternatively, the orthographic projection of the photosensitive layer 210 onto the substrate 110 falls within the orthographic projection range of the second sub-region 1222 onto the substrate 110.

[0103] Optionally, the photosensitive layer 210 and the source 133 of the gating device 100 are adjacent along the width direction of the integrated three-dimensional chip for sensing, memory, and computing; or, the photosensitive layer 210 and the source 133 of the gating device 100 are spaced apart along the width direction of the integrated three-dimensional chip for sensing, memory, and computing and are isolated by the gate dielectric layer 140.

[0104] Optionally, the photosensitive layer 210 is selected from at least one of silicon, gallium arsenide, indium phosphide, mercury cadmium telluride (HgCdTe, MCT) and organic semiconductor materials.

[0105] Thus, the sensing device 200 can receive external light signals and generate photocurrent. The photocurrent can directly output the image acquisition results through the second output line, or the photocurrent can be transmitted through the second sub-region 1222 and the source 133 to the top electrode 310 of the stacked resistive switching memory device group 300 and output the calculation results through each resistive switching memory device 301 and the first output line.

[0106] Secondly, referring to Figures 3 and 4a to 4g, embodiments of this application provide a method for fabricating a three-dimensional integrated chip that combines sensing, storage, and computing. The fabrication method includes:

[0107] S110, provides gating devices and sensing devices;

[0108] S120. An insulating dielectric layer and a bottom electrode layer are deposited sequentially above the gating device;

[0109] S130, Repeatedly deposit insulating dielectric layer and bottom electrode layer to obtain N bottom electrode layers, with insulating dielectric layer formed above and below each bottom electrode layer;

[0110] S140: Etching the stacked structure of the insulating dielectric layer and the bottom electrode layer forms a via to expose the gating device;

[0111] S150, A resistive switching layer is grown at the interface of the stacked structure on the inner wall of the through hole;

[0112] S160. Deposit a top electrode layer inside the resistive switching layer to complete the fabrication of the stacked resistive switching memory device group.

[0113] Therefore, compared with traditional three-dimensional integrated chips formed by stacked memory devices, this application significantly reduces the number of stacked layers, thereby improving chip fabrication feasibility. For example, taking the fabrication of a two-layer resistive switching memory as an example, related technologies require the fabrication of three insulating layers, two top electrode layers, two bottom electrode layers, and two resistive switching layers, while the fabrication method provided by this application only requires the fabrication of three insulating layers, two bottom electrode layers, one top electrode layer, and one resistive switching layer. Furthermore, the top electrode layer and the resistive switching layer do not occupy space in the chip thickness direction, and this advantage becomes more prominent as the number of stacked resistive switching memory devices increases.

[0114] According to some embodiments of this application, step S110 includes:

[0115] S111, Provide a substrate and grow an epitaxial layer on one side of the substrate;

[0116] S112, Implanting ions of the first conductivity type into the epitaxial layer;

[0117] S113. Implanting ions of a second conductivity type onto the surface of the epitaxial layer away from the substrate to form a well region located within the epitaxial layer;

[0118] S114. The source and drain electrodes are formed on the surface of the epitaxial layer away from the substrate;

[0119] S115. A gate dielectric layer is formed on the surface of the epitaxial layer away from the substrate;

[0120] S116. A gate is formed on the surface of the gate dielectric layer away from the substrate.

[0121] Optionally, step S110 further includes:

[0122] S117. Etch the gate dielectric layer to expose the second sub-region;

[0123] S118, A photosensitive layer is deposited above the second sub-region.

[0124] Optionally, in step S114, the source and drain are prepared by a deposition process.

[0125] Alternatively, in step S114, a mask is placed on the surface of the epitaxial layer away from the substrate, and the source and drain are directly deposited.

[0126] Optionally, in step S116, the gate is fabricated by a deposition process.

[0127] Alternatively, in step S116, a mask is set on the surface of the gate dielectric layer away from the substrate and the gate is directly deposited.

[0128] According to some embodiments of this application, in step S120, the same mask is used to form the insulating dielectric layer and the bottom electrode layer.

[0129] According to some embodiments of this application, in steps S120 and S130, the thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm.

[0130] Optionally, the material of the insulating dielectric layer includes at least one of silicon dioxide, silicon nitride, and polymer insulating materials.

[0131] According to some embodiments of this application, in steps S120 and S130, the material of the bottom electrode layer includes an inert material.

[0132] For example, the material of the bottom electrode layer includes at least one of gold, platinum, and titanium nitride.

[0133] According to some embodiments of this application, in step S140, the etched via has an inverted conical structure. Specifically, referring to FIG4e, in the width direction of the integrated 3D chip for sensing, storage, and computing, the opening size of the via on the side away from the substrate is larger than the opening size on the side closer to the substrate, so as to facilitate the subsequent process of growing a resistive switching layer and depositing a top electrode layer on the inner wall of the via.

[0134] Optionally, in step S140, a mask is set and the stacked structure of the insulating dielectric layer and the bottom electrode layer is etched to form a via and expose the source electrode.

[0135] Alternatively, the via is formed at the center of the stacked structure of the insulating dielectric layer and the bottom electrode layer.

[0136] According to some embodiments of this application, in step S150, the material of the resistive switching layer includes at least one of oxides, nitrides, sulfides, and organic compounds.

[0137] Optionally, the thickness of the resistive switching layer is greater than or equal to 4 nm and less than or equal to 30 nm.

[0138] For example, the resistive switching layer is a hafnium dioxide layer.

[0139] It is understandable that the resistive switching layer between two adjacent bottom electrodes can be set as one or more layers. When the resistive switching layer is set as multiple layers, the materials of the two directly adjacent resistive switching layers are set differently.

[0140] According to some embodiments of this application, in step S160, the material of the top electrode layer includes an active metal.

[0141] For example, the material of the top electrode layer includes one of copper, silver, and lead.

[0142] According to some embodiments of this application, the preparation method further includes:

[0143] S171. Prepare a passivation layer above the gate;

[0144] S172. The passivation layer is etched to form a first via to expose the drain, and a first conductive metal is deposited in the first via to obtain a bit line;

[0145] S173. The passivation layer is etched to form a second via to expose the gate, and a second conductive metal is deposited in the second via to obtain the word line.

[0146] Thirdly, referring to Figure 5, this application provides a calculation method for a sensor-memory-computing integrated 3D chip, applied to the sensor-memory-computing integrated 3D chip provided in any embodiment of the first aspect. The calculation method includes:

[0147] S210, connect the gating device and the sensing device, the sensing device receives the sample signal and generates the first output current;

[0148] S220: Disconnect the sensing device, connect the gating device and the stacked resistive switching memory device group, and write weights to each memory device respectively.

[0149] S230: Disconnect the gating device and connect the stacked resistive variable storage device group with the sensing device. The sensing device receives the sample signal and calculates and generates the second output current according to the weight of the storage device.

[0150] S240. Compare the first output current with the second output current to determine whether the target image is a sample image, and complete the image recognition.

[0151] According to some embodiments of this application, step S210 includes:

[0152] S211. Provide a first voltage to the j-th column word line and a second voltage or ground to the i-th row word line, wherein the second voltage is lower than the first voltage;

[0153] S212, Provide a read signal to the second output line.

[0154] This enables the selection and reading of a single sensor unit in the i-th row and j-th column.

[0155] According to some embodiments of this application, step S220 includes:

[0156] S221. Voltage is supplied to the bottom electrode of each resistive switching memory device through the write sub-line;

[0157] S222, Provide a third voltage to the j-th column word line and provide a write signal or rewrite signal to the i-th row bit line;

[0158] S223, Provide a read signal to the first output line.

[0159] This enables the selection and weight writing of a single inductive computing unit in the i-th row and j-th column. Each bottom electrode, which has been subjected to voltage excitation, is simultaneously turned on after the inductive computing unit is selected, thus allowing for simultaneous weight writing operations.

[0160] Optionally, in step S221, the driving module divides the system clock into N sub-cycles through a time-slice allocation circuit. Each sub-cycle corresponds to the weight writing of a layer of resistive random access memory devices, and the writing voltage is sequentially applied to each bottom electrode through the writing sub-line.

[0161] According to some embodiments of this application, referring to FIG6, step S230 includes:

[0162] S231. The system clock generates a high-precision clock signal and divides it into time slices equal to the number of layers of the resistive random access memory device 301 by a frequency divider. Each time slice corresponds to one layer of resistive random access memory device.

[0163] S232, The logic control unit generates a hierarchical gating signal sequence according to the time slice number, and the signal switching module dynamically allocates the gating signal to the row gating circuit of the target layer;

[0164] S233: Cyclicly switch the resistive variable storage devices in each layer to complete feature extraction or inference operations and generate the second output current.

[0165] Specifically, in step S233, the second output current is the cumulative value of the output currents of each sensing and computing unit in the array, wherein the output current of each sensing and computing unit is the cumulative value of the output currents of each layer of resistive switching memory within the unit. The output current of a single resistive switching memory is the product of its own weight and the photocurrent. Thus, the second output current is calculated by the coupling between the sensing and computing units and the photocurrent and can be configured to characterize the target image.

[0166] According to some embodiments of this application, step S240 includes:

[0167] S241. Obtain the first output voltage and the second output voltage based on the first output current and the second output current;

[0168] S242. Normalize the first output voltage and the second output voltage to obtain the calculation result. Compare the calculation result with the preset threshold to determine whether the target image is a sample image.

[0169] Optionally, in step S241, the first output current and the second output current are amplified by an operational amplifier to obtain the first output voltage and the second output voltage.

[0170] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A three-dimensional integrated chip for sensing, storage, and computing, wherein, Includes an array of in-memory computing units having multiple in-memory computing units, wherein the in-memory computing units include: A stacked resistive switching memory device group includes at least two resistive switching memory devices stacked along the thickness direction of the integrated sensing, memory, and computing 3D chip; A sensing device is configured to receive an external signal and convert the external signal into an input signal, and the output of the sensing device is coupled to the top electrode of the stacked resistive switching memory device group. A gating device is configured to receive a control signal and switch on / off according to the control signal, the gating device being coupled to the top electrode of the stacked resistive switching memory device group; The stacked resistive random access memory (RRAM) device group is disposed between the sensing device and the gating device along the width direction of the integrated sensing, storage, and computing 3D chip. At least two RRAM devices share a top electrode so that at least two RRAM devices can synchronously receive input signals or synchronously switch on and off.

2. The integrated 3D sensing, storage, and computing chip according to claim 1, wherein, The stacked resistive switching memory device group includes a top electrode, a resistive switching layer, and at least two bottom electrodes. The top electrode is coupled to the at least two bottom electrodes through the resistive switching layer. The resistive switching layer is configured to change its resistance value under the control of voltage signals applied to the top electrode and the bottom electrodes.

3. The integrated 3D sensing, storage, and computing chip according to claim 2, wherein, At least two bottom electrodes are stacked along the thickness direction and an insulating dielectric layer is provided between any two bottom electrodes. The top electrode extends at least along the thickness direction to connect each bottom electrode, and the resistive switching layer extends at least along the thickness direction to space the top electrode from each bottom electrode.

4. The integrated 3D sensing, storage, and computing chip according to claim 1, wherein, The gating device includes a substrate, an active region disposed on one side of the substrate, a drain, a source, and a gate. The drain and the source are disposed on the side of the active region away from the substrate and are electrically isolated by a gate dielectric layer. The gate is disposed along the width direction between the drain and the source and is spaced apart from the active region by the gate dielectric layer. The source is electrically connected to the top electrode of the memory device.

5. The integrated 3D sensing, storage, and computing chip according to claim 4, wherein, The integrated 3D chip for sensing, storage, and computing also includes: The driving module is configured to output a control signal to the gating device; Bit lines extend along the row direction and are connected between the driving module and the drain of each of the gating devices; Word lines extend along the column direction and connect the driving module to the gate of each of the selected devices.

6. The integrated 3D sensing, storage, and computing chip according to claim 5, wherein, The integrated 3D chip for sensing, storage, and computing also includes: The first output line is electrically connected to the stacked resistive random access memory device group in each of the aforementioned inductive computing units; The second output line is electrically connected to the sensing device in each of the aforementioned sensing, storage, and computing units.

7. The integrated 3D sensing, storage, and computing chip according to claim 4, wherein, The sensing device includes a photosensitive layer disposed on the side of the active region away from the substrate, and the photosensitive layer and the top electrode of the stacked resistive switching memory device group are coupled to the active region through the source electrode.

8. A method for fabricating a three-dimensional integrated chip that combines sensing, storage, and computing, wherein, Preparation methods include: Provide gating devices and sensing devices; An insulating dielectric layer and a bottom electrode layer are deposited sequentially above the gating device; Repeatedly deposit insulating dielectric layers and bottom electrode layers to obtain N bottom electrode layers, with insulating dielectric layers formed above and below each bottom electrode layer; Etching the stacked structure of the insulating dielectric layer and the bottom electrode layer forms vias to expose the gating device; A resistive switching layer is grown at the interface of the stacked structure on the inner wall of the through hole; A top electrode layer is deposited inside the resistive switching layer to complete the fabrication of the stacked resistive switching memory device assembly.

9. The method for fabricating a three-dimensional integrated chip combining sensing, storage, and computing according to claim 8, wherein, The thickness of the insulating dielectric layer is greater than or equal to 100 nm and less than or equal to 300 nm; and / or, The resistive switching layer is made of at least one of oxides, nitrides, sulfides, and organic compounds, and the thickness of the resistive switching layer is greater than or equal to 4 nm and less than or equal to 30 nm; and / or, The material of the top electrode layer includes an active metal; and / or, The bottom electrode layer is made of an inert material.

10. A computing method for a sensor-memory-computing integrated 3D chip, applied to the sensor-memory-computing integrated 3D chip as described in any one of claims 1 to 7, wherein, The calculation methods include: Connect the gating device and the sensing device, and the sensing device receives the sample signal and generates the first output current; Disconnect the sensing device, connect the gating device and the stacked resistive switching memory device group, and write weights to each memory device respectively; Disconnect the gating device and connect the stacked resistive switching memory device group to the sensing device. The sensing device receives the sample signal and calculates and generates the second output current according to the weight of the memory device. By comparing the first output current with the second output current, it is determined whether the target image is a sample image, thus completing image recognition.

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